Ring oscillator and chip

Abstract

The embodiment of the invention discloses a ring oscillator and a chip. The ring oscillator comprises a loop formed by M delay units and a current generating circuit, wherein M is an odd number greater than or equal to 3. The delay unit comprises a second transistor and a first capacitor. The control end of the second transistor serves as the input end of the delay unit, and the first end of the second transistor serves as the output end of the delay unit. The current generating circuit includes a first transistor. The current generating circuit generates a control current proportional to a voltage difference between a control terminal voltage and a second terminal voltage of the first transistor and supplies the control current to the delay unit. The first transistor and the second transistor are both P-type or N-type. The frequency of the clock signal of the ring oscillator is in direct proportion to the voltage difference between the control end voltage of the first transistor and the second end voltage, and is in inverse proportion to the voltage difference between the control end voltage of the second transistor and the second end voltage, so that the frequency of the clock signal has a zero temperature drift characteristic.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a ring oscillator and a chip including the ring oscillator. Background Art

[0002] An oscillator is an important component of a chip, providing a clock signal for the chip. The frequency stability of the clock signal affects the performance, power consumption, and reliability of the chip. The frequency of the clock signal is affected by factors such as process, voltage, and temperature (PVT). Therefore, there is a need in the art for an oscillator with low temperature drift and simple trimming. Summary of the Invention

[0003] Embodiments of the present application provide a ring oscillator and a chip including the ring oscillator. The ring oscillator has a zero temperature drift characteristic, improving the performance and reliability of the ring oscillator and the chip.

[0004] According to one aspect of the embodiments of the present application, a ring oscillator is provided. The ring oscillator includes: M delay units and a current generation circuit. The M delay units are cascaded in sequence to form a loop. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first terminal of the second transistor serves as the output terminal of the delay unit. M is an odd number greater than or equal to 3. The current generation circuit includes a first transistor. The current generation circuit is configured to generate a control current proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor, and supply the control current to the M delay units. Wherein, one end of the first capacitor is connected to the first terminal of the second transistor, and the other end of the first capacitor is connected to ground or a power supply terminal. Both the first transistor and the second transistor are P-type or N-type.

[0005] In some embodiments, both the first transistor and the second transistor are NMOS transistors, and the first capacitor is connected between the first terminal of the second transistor and ground; or, both the first transistor and the second transistor are PMOS transistors, and the first capacitor is connected between the first terminal of the second transistor and the power supply terminal.

[0006] In some embodiments, the current generation circuit further includes: a current source, a first resistor, and a current mirror module. Wherein, the current source is connected in series with the first transistor, the voltage difference across the two ends of the first resistor is clamped to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor, and the current mirror module generates the control current based on the current flowing through the first resistor.

[0007] In some embodiments, the current generating circuit further includes a voltage clamping circuit, which clamps the voltage at the first end of the first resistor to the control terminal voltage of the first transistor. The second end of the first resistor is connected to the second end of the first transistor, and the current source is a bandgap reference current source.

[0008] In some embodiments, the current generating circuit further includes a third transistor, which is connected in series with the first resistor. The current mirror module includes a first current mirror, which includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, and the second ends of the plurality of fourth transistors are connected together. The voltage clamping circuit includes an operational amplifier. The first input terminal of the operational amplifier is connected to the control terminal of the first transistor, the second input terminal is connected to the first end of the first resistor, and the output terminal is connected to the control terminal of the third transistor. The control terminal of the first transistor is connected to the first end of the first transistor.

[0009] In some embodiments, when the first transistor and the second transistor are NMOS transistors, the third transistor is a PMOS transistor, and the fourth transistors are PMOS transistors; when the first transistor and the second transistor are PMOS transistors, the third transistor is an NMOS transistor, and the fourth transistors are NMOS transistors.

[0010] In some embodiments, the current mirror module further includes a second current mirror, which includes a plurality of fifth transistors. One of the fourth transistors and the fifth transistors is N-type, and the other is P-type. The second current mirror generates an intermediate current based on the current flowing through the first resistor, and the first current mirror generates the control current based on the intermediate current.

[0011] In some embodiments, the first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

[0012] In some embodiments, the m trimming capacitors have different capacitance values.

[0013] In some embodiments, the first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch, where n is a positive integer greater than 1.

[0014] In some embodiments, the n trimming resistors have different resistance values.

[0015] In some embodiments, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor, and the change in the frequency of the clock signal caused by the conduction of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the conduction of one or more of the n second switches.

[0016] In some embodiments, the current mirror module includes a first current mirror, the first current mirror includes a plurality of fourth transistors, the control terminals of the plurality of fourth transistors are connected together, the second terminals of the plurality of fourth transistors are connected together, the fourth transistors include n trimming transistors and n second switches, the n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1.

[0017] In some embodiments, the n trimming transistors have different aspect ratios.

[0018] In some embodiments, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current, and the change in the frequency of the clock signal caused by the conduction of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the conduction of one or more of the n second switches.

[0019] In some embodiments, the first transistor and the second transistor have the same type and temperature drift characteristics, and the frequency of the clock signal generated by the ring oscillator has zero temperature drift characteristics.

[0020] According to another aspect of the embodiments of the present application, a chip is provided. The chip includes a ring oscillator that generates a clock signal. The ring oscillator includes M delay units and a current generation circuit.

[0021] The M delay units are cascaded in sequence to form a loop. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first terminal of the second transistor serves as the output terminal of the delay unit. M is an odd number greater than or equal to 3. The current generation circuit includes a first transistor. The current generation circuit is configured to generate a control current proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor and supply the control current to the M delay units. Wherein, one end of the first capacitor is connected to the first terminal of the second transistor, the other end of the first capacitor is connected to ground or a power supply terminal, and both the first transistor and the second transistor are P-type or N-type.

[0022] In some embodiments, both the first transistor and the second transistor are NMOS transistors, and the first capacitor is connected between the first end of the second transistor and the ground; alternatively, both the first transistor and the second transistor are PMOS transistors, and the first capacitor is connected between the first end of the second transistor and the power supply terminal.

[0023] In some embodiments, the current generation circuit further includes: a current source, a first resistor, and a current mirror module. Among them, the current source and the first transistor are connected in series, the voltage difference across the two ends of the first resistor is clamped to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor, and the current mirror module generates the control current based on the current flowing through the first resistor.

[0024] In some embodiments, the current generation circuit further includes a voltage clamping circuit. The voltage clamping circuit clamps the voltage at the first end of the first resistor to the control terminal voltage of the first transistor. The second end of the first resistor is connected to the second end of the first transistor, and the current source is a bandgap reference current source.

[0025] In some embodiments, the current generation circuit further includes a third transistor. The third transistor and the first resistor are connected in series. The current mirror module includes a first current mirror. The first current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, and the second terminals of the plurality of fourth transistors are connected together. The voltage clamping circuit includes an operational amplifier. The first input terminal of the operational amplifier is connected to the control terminal of the first transistor, the second input terminal is connected to the first end of the first resistor, and the output terminal is connected to the control terminal of the third transistor. The control terminal of the first transistor is connected to the first end of the first transistor.

[0026] In some embodiments, when the first transistor and the second transistor are NMOS transistors, the third transistor is a PMOS transistor, and the fourth transistors are PMOS transistors; when the first transistor and the second transistor are PMOS transistors, the third transistor is an NMOS transistor, and the fourth transistors are NMOS transistors.

[0027] In some embodiments, the current mirror module further includes a second current mirror. The second current mirror includes a plurality of fifth transistors. One of the fourth transistors and the fifth transistors is N-type, and the other is P-type. The second current mirror generates an intermediate current based on the current flowing through the first resistor, and the first current mirror generates the control current based on the intermediate current.

[0028] In some embodiments, the first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

[0029] In some embodiments, the first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch, where n is a positive integer greater than 1. The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor. The change in the frequency of the clock signal caused by the conduction of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the conduction of one or more of the n second switches.

[0030] In some embodiments, the current mirror module includes a first current mirror. The first current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, and the second terminals of the plurality of fourth transistors are connected together. The fourth transistor includes n trimming transistors and n second switches. The n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1. The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current. The change in the frequency of the clock signal caused by the conduction of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the conduction of one or more of the n second switches.

[0031] In some embodiments, the chip further includes a memory that stores an (m + n)-bit binary number. The m first switches and the n second switches are set to be conductive or non-conductive according to the (m + n)-bit binary number.

[0032] In some embodiments, the first transistor and the second transistor have the same type and temperature drift characteristics, and the clock signal generated by the ring oscillator has zero temperature drift characteristics.

[0033] According to the ring oscillator of the present application, the magnitude of the control current of the oscillation loop depends on the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor. The frequency of the clock signal generated by the ring oscillator is proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor and inversely proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the second transistor. The first transistor and the second transistor are both N-type transistors or both P-type transistors. Therefore, the frequency of the clock signal has low temperature drift or zero temperature drift characteristics, improving the performance of the ring oscillator.

[0034] In addition, the frequency of the clock signal is adjusted by adjusting the resistance value of the first resistor and the capacitance value of the first capacitor, or by adjusting the effective width-to-length ratio of the third transistor and the capacitance value of the first capacitor. Among them, adjusting the capacitance value of the first capacitor realizes the coarse adjustment of the frequency, and adjusting the resistance value of the first resistor or the effective width-to-length ratio of the third transistor realizes the fine adjustment of the frequency. Adjusting the capacitance value of the first capacitor does not change the magnitude of the control current and does not affect the low temperature drift characteristic of the ring oscillator. Adjusting the resistance value of the first resistor or the effective width-to-length ratio of the third transistor can save the area and power consumption of the adjustment circuit. Description of the Drawings

[0035] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0036] Figure 1 is a schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0037] Figure 2 is a schematic circuit diagram of the shaping circuit according to an embodiment of the present application;

[0038] Figure 3 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0039] Figure 4 is a schematic circuit diagram of the low dropout linear regulator according to an embodiment of the present application;

[0040] Figure 5 is another schematic circuit diagram of the low dropout linear regulator according to an embodiment of the present application;

[0041] Figure 6 is a schematic circuit diagram of the first resistor according to an embodiment of the present application;

[0042] Figure 7 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0043] Figure 8 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0044] Figure 9 is a schematic circuit diagram of the second current mirror according to an embodiment of the present application;

[0045] Figure 10 is another schematic circuit diagram of the second current mirror according to an embodiment of the present application;

[0046] Figure 11 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0047] Figure 12 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application;

[0048] Figure 13 is a schematic diagram of a chip according to an embodiment of the present application;

[0049] Figure 14 is a schematic circuit diagram of the first capacitor according to an embodiment of the present application;

[0050] Figure 15 is a schematic circuit diagram of the first resistor according to an embodiment of the present application;

[0051] Figure 16 is a schematic circuit diagram of the fourth transistor according to an embodiment of the present application;

[0052] Figure 17 is another schematic circuit diagram of the first resistor according to an embodiment of the present application;

[0053] Figure 18 is another schematic circuit diagram of the first capacitor according to an embodiment of the present application;

[0054] Figure 19 is another schematic circuit diagram of the fourth transistor according to an embodiment of the present application;

[0055] Figure 20 is another schematic circuit diagram of the first resistor according to an embodiment of the present application;

[0056] Figure 21 is another schematic circuit diagram of the first capacitor according to an embodiment of the present application. Detailed implementation manners

[0057] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. To avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0058] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0059] Unless the context clearly requires otherwise, the words "including", "comprising", and the like in the entire application document should be interpreted as including rather than exclusive or exhaustive meanings, that is, the meaning of "including but not limited to".

[0060] In the description of this application, it should be understood that terms such as "first" and "second" are only for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0061] Figure 1 FIG. 4 is a schematic circuit diagram of a ring oscillator provided by an embodiment of the present application. The ring oscillator is used to generate a clock signal CLK. The ring oscillator includes an oscillation loop 100, a current generation circuit 200, and a shaping circuit 300.

[0062] The oscillation loop 100 includes M delay units, where M is an odd number greater than or equal to 3. The M delay units are cascaded in sequence to form a loop. Specifically, the output terminal of the previous-stage delay unit is connected to the input terminal of the next-stage delay unit, and the output terminal of the last-stage delay unit is connected to the input terminal of the first-stage delay unit. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first terminal of the second transistor serves as the output terminal of the delay unit. One end of the first capacitor is connected to the first terminal of the second transistor, and the other end of the first capacitor is connected to ground or a power supply terminal.

[0063] In Figure 1 the illustrated exemplary embodiment, M = 3, and the oscillation loop 100 includes a delay unit 101, a delay unit 102, and a delay unit 103. The delay unit 101 includes a second transistor N21 and a first capacitor C21. The delay unit 102 includes a second transistor N22 and a first capacitor C22. The delay unit 103 includes a second transistor N23 and a first capacitor C23. The first capacitor C21, the first capacitor C22, and the first capacitor C23 have the same capacitance value.

[0064] The current generation circuit 200 includes a first transistor N1. The current generation circuit 200 is used to generate a control current I OSC and provide the control current I OSC to M delay units respectively. The magnitude of the control current I OSC is proportional to the gate-source voltage Vgs1 of the first transistor N1. For example, the current generation circuit 200 is connected to the drain of the second transistor of the delay unit and provides the control current I OSC to the output terminal of the delay unit. In Figure 1 the illustrated embodiment, the current generation circuit 200 includes 3 output terminals, which are respectively connected to the drains of the second transistors N21, N22, and N23, that is, respectively connected to the gates of the second transistors N22, N23, and N21.

[0065] Both the first transistor and the second transistor are P-type transistors or N-type transistors. For example, both the first transistor and the second transistor are N-type MOSFETs (NMOS), or both the first transistor and the second transistor are P-type MOSFETs (PMOS). The control terminal is the gate of the MOS transistor, the first terminal is the drain of the MOS transistor, and the second terminal is the source of the MOS transistor. The voltage at the control terminal of the transistor is the gate voltage, the voltage at the first terminal is the drain voltage, and the voltage at the second terminal is the source voltage. For another example, both the first transistor and the second transistor are PNP bipolar junction transistors (BJTs), or both the first transistor and the second transistor are NPN bipolar junction transistors. The control terminal is the base of the bipolar junction transistor, the first terminal is the emitter of the bipolar junction transistor, and the second terminal is the collector of the bipolar junction transistor. In Figure 1 In the corresponding embodiment, both the first transistor and the second transistor are NMOS transistors, and the first capacitor is connected between the drain of the second transistor and the ground. The first capacitor is, for example, a zero-temperature-drift metal-metal capacitor.

[0066] The input terminal of the shaping circuit 300 is connected to the output terminal OUT of the oscillation loop 100, and the output terminal of the shaping circuit 300 outputs a clock signal CLK. The shaping circuit is used to shape the oscillation signal generated by the oscillation loop 100 to obtain the clock signal CLK. Figure 2 is a circuit diagram of an exemplary shaping circuit 300. The shaping circuit 300 includes a PMOS transistor 301, an NMOS transistor 302, and one or more cascaded inverters 303. The PMOS transistor 301 and the NMOS transistor 302 are connected in series between the power supply terminal and the ground. The source of the PMOS transistor 301 is connected to the power supply terminal, the source of the NMOS transistor 302 is grounded, the drains of the PMOS transistor 301 and the NMOS transistor 302 are connected, and the gates of the PMOS transistor 301 and the NMOS transistor 302 are connected. The gates of the PMOS transistor 301 and the NMOS transistor 302 are connected to the output terminal OUT of the oscillation loop 100, the drains of the PMOS transistor 301 and the NMOS transistor 302 are connected to the input terminal of the inverter 303, and the output terminal of the inverter 303 outputs the clock signal CLK. By adjusting the width-to-length ratio of the PMOS transistor 301, the pull-up ability of the PMOS transistor 301 can be adjusted, and by adjusting the width-to-length ratio of the NMOS transistor 302, the pull-down ability of the NMOS transistor 302 can be adjusted. By adjusting the pull-up ability and the pull-down ability, the duty cycle of the clock signal CLK can be adjusted. One or more cascaded inverters 303 are used to filter out glitches, making the waveform of the clock signal CLK more ideal.

[0067] In the present application, the power supply terminal can be the first power supply terminal VDD1 or the second power supply terminal VDD2. The first power supply terminal VDD1 is an external power supply, such as a battery. The voltage provided by the second power supply terminal VDD2 is the voltage generated after the voltage of the first power supply terminal VDD1 is processed by a Low Dropout Regulator (LDO). The voltage after LDO processing has a good Power Supply Rejection Ratio (PSRR). The source terminal of the PMOS transistor 301 is connected to the second power supply terminal VDD2, and the clock signal CLK is hardly affected by the jitter of the power supply voltage, thus improving the stability of the oscillator output frequency.

[0068] The frequency f of the clock signal CLK generated by the ring oscillator and the control current I OSC are directly proportional, inversely proportional to the capacitance value C of the first capacitor, and inversely proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the second transistor. For Figure 1 the embodiment shown, the voltage difference between the control terminal voltage and the second terminal voltage of the second transistor is the gate-source voltage Vgs2 of the second transistor.

[0069]

[0070] The amplitudes of the gate-source voltages Vgs2 of the second transistor N21, the gate-source voltages Vgs3 of the second transistor N22, and the gate-source voltages Vgs4 of the second transistor N23 are the same, but the phases are different. In the above formula, Vgs2 refers to the amplitude of the gate-source voltage of the second transistor N21.

[0071] In the present application, both the first transistor and the second transistor are N-type transistors or both are P-type transistors. Therefore, the first transistor and the second transistor have the same temperature drift characteristics. For example, both the first transistor and the second transistor have a positive temperature coefficient or both have a negative temperature coefficient. Therefore, the frequency f of the clock signal CLK generated by the ring oscillator has a low temperature drift characteristic or a zero temperature drift characteristic.

[0072] Figure 3 is another schematic circuit diagram of the ring oscillator according to an embodiment of the present application. Figure 3 The shaping circuit is not shown. As Figure 3 shown, the current generation circuit 200 further includes: a current source 230, a first resistor R0, a third transistor P10, a current mirror module, and a voltage clamping circuit 220. The ring oscillator further includes a low dropout regulator 400.

[0073] Figure 4 is the circuit diagram of the exemplary low dropout regulator 400 of the present application. As Figure 4As shown, the low dropout linear regulator 400 includes: an operational amplifier OP2, a Bandgap circuit, a PMOS transistor P401, voltage dividing resistors R3 and R4. The Bandgap circuit is used to generate a reference voltage V Ref . The source of the PMOS transistor P401 is connected to the first power supply terminal VDD1, and the drain serves as the output terminal of the low dropout linear regulator 400. The voltage dividing resistors R3 and R4 are connected in series between the drain of the PMOS transistor P401 and the ground. The first input terminal of the operational amplifier OP2 is connected to the Bandgap circuit to receive the reference voltage V Ref . The second input terminal of the operational amplifier OP2 is connected to the node between the voltage dividing resistors R3 and R4 to receive the feedback voltage V FB . The output terminal of the operational amplifier OP2 is connected to the gate of the PMOS transistor P401. Optionally, the first input terminal is the Inverting input terminal, and the second input terminal is the Non-inverting input terminal. Through the action of negative feedback, the drain voltage VDD2 of the PMOS transistor P401 is stabilized at V Ref *(R3 + R4) / R4. The low dropout linear regulator 400 further includes a resistor R2 and a capacitor C2. The resistor R2 and the capacitor C2 are connected in series between the output terminal of the operational amplifier OP2 and the drain of the PMOS transistor P401.

[0074] Figure 5 is the circuit diagram of another exemplary low dropout linear regulator 400. As Figure 5 shown, the low dropout linear regulator 400 includes: an operational amplifier OP2, a Bandgap circuit, an NMOS transistor N401, voltage dividing resistors R3 and R4. The Bandgap circuit is used to generate a reference voltage V Ref . The drain of the NMOS transistor N401 is connected to the first power supply terminal VDD1, and the source serves as the output terminal of the low dropout linear regulator 400. The voltage dividing resistors R3 and R4 are connected in series between the source of the NMOS transistor N401 and the ground. The second input terminal of the operational amplifier OP2 is connected to the Bandgap circuit to receive the reference voltage V Ref . The first input terminal of the operational amplifier OP2 is connected to the node between the voltage dividing resistors R3 and R4 to receive the feedback voltage V FB . The output terminal of the operational amplifier OP2 is connected to the gate of the NMOS transistor N401. Through the action of negative feedback, the source voltage VDD2 of the NMOS transistor N401 is stabilized at V Ref *(R3 + R4) / R4. The low dropout linear regulator 400 further includes a resistor R2 and a capacitor C2. The resistor R2 and the capacitor C2 are connected in series between the output terminal of the operational amplifier OP2 and the drain of the NMOS transistor N401.

[0075] The output terminal of the low dropout linear regulator 400 serves as the second power supply terminal VDD2, providing a power supply voltage with better power supply rejection ratio (PSRR) and less ripple.

[0076] The current source 230 is used to supply the bias current Iref to the first transistor N1. The bias current Iref has the characteristic of zero temperature drift. The current source 230 is, for example, a bandgap reference current source. The bandgap reference current source includes a sub-circuit that generates a positive temperature coefficient (PTAT) current and a sub-circuit that generates a negative temperature coefficient (CTAT) current. By superimposing the positive temperature coefficient current and the negative temperature coefficient current, a bias current Iref with zero temperature coefficient is obtained. As Figure 3 shown, the current source 230 and the first transistor N1 are connected in series between the second power supply terminal VDD2 and the ground GND. The bias current Iref determines the gate-source voltage Vgs1 of the first transistor N1. The temperature drift characteristic of the gate-source voltage Vgs1 of the first transistor N1 is determined by the temperature drift characteristic of the first transistor. More specifically, as Figure 3 shown, the drain of the first transistor N1 is connected to the current source 230, the gate and the drain of the first transistor N1 are connected together, and the source of the first transistor N1 is grounded. That is, the first transistor N1 is in a diode-connected state.

[0077] The voltage clamping circuit 220 is connected to the gate of the first transistor N1 and the first end N of the first resistor R0. The second end of the first resistor R0 is grounded. The voltage clamping circuit 220 clamps the voltage of the first end N of the first resistor R0 to the gate voltage of the first transistor N1, so that the voltage across the first resistor R0 is the gate-source voltage Vgs1 of the first transistor N1. The voltage clamping circuit 220 is, for example, a voltage follower or other voltage clamping circuit based on an operational amplifier. The first resistor R0 is, for example, a resistor with zero temperature drift. Figure 6 is a circuit diagram of an exemplary first resistor R0. As Figure 6 shown, the first resistor R0 includes a sub-resistor R0+ and a sub-resistor R0-. The sub-resistor R0+ and the sub-resistor R0- are connected in series. The sub-resistor R0+ has a positive temperature coefficient, and the sub-resistor R0- has a negative temperature coefficient, so that the first resistor R0 is realized as a resistor with zero temperature drift.

[0078] As described above, the voltage clamping circuit 220 clamps the voltage of the first end N of the first resistor R0 to the gate voltage of the first transistor N1. The second end of the first resistor R0 is connected to the source of the first transistor N1, and the voltage across the first resistor R0 is the gate-source voltage Vgs1 of the first transistor N1. Therefore, the current I 0 flowing through the first resistor R0 has a magnitude of Vgs1 / R0, and the temperature drift characteristic of this current depends on the temperature drift characteristic of the gate-source voltage Vgs1 of the first transistor N1.

[0079] The third transistor P10 and the first resistor R0 are connected in series between the second power supply terminal VDD2 and the ground GND. The current mirror module includes a first current mirror 210. The first current mirror 210 generates a control current I 0 based on the current I OSC flowing through the first resistor R0. As Figure 3 shown, the first current mirror 210 includes a plurality of fourth transistors P11 - P13. The gates of the fourth transistors P11 - P13 and the gate of the third transistor P10 are commonly connected to a bias node B. The bias node B is used to provide a bias voltage V B . The sources of the fourth transistors P11 - P13 and the source of the third transistor P10 are connected to the second power supply terminal VDD2. The drain of the third transistor P10 is connected to the first end N of the first resistor R0. The drains of the fourth transistors P11 - P13 are connected to the drain ends of the second transistors of the corresponding delay units. The control current I OSC is proportional to the current I 0 flowing through the first resistor R0, and the ratio of the control current I OSC to the current I 0 is determined by the aspect ratios of the fourth transistors P11 - P13 and the aspect ratio of the third transistor P10.

[0080] In Figure 3 the corresponding embodiment, the first transistor N1 and the second transistors N21 - N23 are NMOS transistors, and the third transistor P10 and the fourth transistors P11 - P13 are PMOS transistors. In Figure 3 the corresponding embodiment, when the aspect ratios of the fourth transistors P11 - P13 are the same as the aspect ratio of the third transistor P10, the control current I OSC = Vgs1 / R0. The frequency f of the clock signal CLK generated by the ring oscillator has a low temperature drift characteristic or a zero temperature drift characteristic.

[0081] Figure 7 is another schematic circuit diagram of a ring oscillator according to an embodiment of the present application. Figure 7 The shaping circuit is not shown in Figure 7As shown, the voltage clamping circuit 220 includes an operational amplifier OP1. The first input terminal of the operational amplifier OP1 is connected to the gate of the first transistor N1, the second input terminal is connected to the first end N of the first resistor R0, and the output terminal is connected to the gates of the third transistor P10 and the fourth transistors P11 - P13. That is, the output terminal of the operational amplifier OP1 serves as the bias node B. The sources of the third transistor P10 and the fourth transistors P11 - P13 are both connected to the first power supply terminal VDD1 or the second power supply terminal VDD2. Optionally, the first input terminal of the operational amplifier OP1 is the inverting input terminal, and the second input terminal is the non-inverting input terminal. The operational amplifier OP1 clamps the voltage at the first end N of the first resistor R0 to the gate voltage of the first transistor N1 through negative feedback. The second end of the first resistor R0 and the source of the first transistor N1 are grounded together. Therefore, the voltage across the first resistor R0 is the gate-source voltage Vgs1 of the first transistor N1.

[0082] As Figure 7 shown, the voltage clamping circuit 220 further includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier OP1 and the first end N of the first resistor R0, and the resistor R1 and the capacitor C1 are used for Miller compensation.

[0083] According to Figure 7 the ring oscillator shown, the current I 0 flowing through the first resistor R0 has a magnitude of Vgs1 / R0. The control current I OSC is proportional to the current I 0 flowing through the first resistor R0. The first current mirror 210 mirrors the current I 0 . The temperature drift characteristics of the third transistor P10 and the fourth transistors P11 - P13 do not affect the temperature drift characteristics of the control current I osc . The temperature drift characteristics of the control current I OSC are determined by the temperature drift characteristics of the gate-source voltage Vgs1 of the first transistor N1. Taking I OSC = I 0 and M = 3 as an example, Figure 7 the expression of the frequency f of the clock signal generated by the ring oscillator shown is as follows.

[0084]

[0085] Since the first transistor and the second transistor have the same temperature drift characteristics, Vgs1 and Vgs2 also have the same temperature drift characteristics. Therefore, the frequency f of the clock signal generated by the ring oscillator has low temperature drift or zero temperature drift characteristics. When designing the oscillator, by adjusting the ratio of Vgs1 and Vgs2, temperature compensation is performed to achieve low temperature drift or zero temperature drift characteristics of the frequency at -40 to 150 degrees Celsius.

[0086] Figure 8 This is the circuit diagram of another exemplary ring oscillator of the present application. As Figure 8 shown, the ring oscillator includes: an oscillation loop 100, a current generation circuit 200, a shaping circuit (not shown), and a low dropout linear regulator 400. The oscillation loop 100 includes three delay units, and the three delay units include: second transistors N21 - N23 and first capacitors C21 - C23.

[0087] The current generation circuit includes: a current mirror module, a first transistor N1, a first resistor R0, a current source 230, a voltage clamping circuit 220, and a third transistor P10. The current source 230 and the first transistor N1 are connected in series between the first power supply terminal VDD1 and the ground, and the first transistor N1 is in a diode - connected state. The third transistor P10 and the first resistor R0 are connected in series between the first power supply terminal VDD1 and the ground. The first end N of the first resistor R0 is connected to the drain of the third transistor P10. The second end of the first resistor R0 and the source of the first transistor N1 are grounded.

[0088] The voltage clamping circuit 220 is used to clamp the voltage of the first end N of the first resistor R0 to the gate voltage of the first transistor N1. Specifically, the voltage clamping circuit 220 includes an operational amplifier OP1. The first input terminal of the operational amplifier OP1 is connected to the gate of the first transistor N1, the second input terminal is connected to the first end N of the first resistor R0, and the output terminal is connected to the gate of the third transistor P10. The operational amplifier OP1, the third transistor P10, and the first resistor R0 form negative feedback. Through the negative feedback, the voltage of the first end N of the first resistor R0 is clamped to the gate voltage of the first transistor N1. The current I flowing through the first resistor R0 0 = Vgs1 / R0. The voltage clamping circuit 220 further includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier OP1 and the first end N of the first resistor R0, and the resistor R1 and the capacitor C1 are used for Miller compensation.

[0089] The current mirror module generates a control current I 0 based on the current I OSC . The current mirror includes: a sixth transistor P14, a first current mirror 210, and a second current mirror 250. The source of the sixth transistor P14 is connected to the first power supply terminal VDD1, and the gate of the sixth transistor P14 is connected to the gate of the third transistor P10. Therefore, the current flowing through the sixth transistor P14 is proportional to the current flowing through the third transistor P10. For example, when the aspect ratios of the sixth transistor P14 and the third transistor P10 are the same, the current flowing through the sixth transistor P14 is also I 0The input terminal of the second current mirror 250 is connected to the drain of the sixth transistor P14, and the output terminal is connected to the input terminal of the first current mirror 210. The second current mirror 250 generates an intermediate current based on the current I 0 to generate an intermediate current, and the first current mirror 210 generates a control current I based on the intermediate current OSC . Specifically, the second current mirror 250 copies the current flowing through the sixth transistor P14, and the first current mirror 210 copies the current output by the second current mirror 250.

[0090] The first current mirror 210 includes fourth transistors P11, P12, P13, and P15. The sources of the fourth transistors P11, P12, P13, and P15 are connected to the second power supply terminal VDD2, and the gates of the fourth transistors P11, P12, P13, and P15 are connected together. Specifically, the gates of the fourth transistors P11, P12, P13, and P15 are connected to the bias node B. The gate and drain of the fourth transistor P15 are connected together as the input terminal of the first current mirror 210. The drains of the fourth transistors P11, P12, and P13 serve as the output terminals to provide the control current I OSC .

[0091] Figure 9 is the circuit diagram of the exemplary second current mirror 250 of the present application. The second current mirror 250 includes fifth transistors N251 and N252. The gates of the fifth transistors N251 and N252 are connected together, and the sources of the fifth transistors N251 and N252 are both grounded. The fifth transistor N251 and the sixth transistor P14 are connected in series. The drain of the fifth transistor N251 is connected to the drain of the sixth transistor P14, and the drain of the fifth transistor N251 is also connected to the gate of the fifth transistor N251. The fifth transistor N252 and the fourth transistor P15 are connected in series. The drain of the fifth transistor N252 is connected to the drain of the fourth transistor P15. The drain of the fifth transistor N251 serves as the input terminal of the second current mirror 250, and the drain of the fifth transistor N252 serves as the output terminal of the second current mirror 250. The fifth transistors N251 and N252 copy the current I 0 to the fourth transistor P15, and the fourth transistors P11, P12, and P13 generate the control circuit I based on the current I 0 . OSC .

[0092] Figure 10It is a circuit diagram of another exemplary second current mirror 250 of the present application. The second current mirror 250 includes fifth transistors N253 - N256. A sixth transistor P14, a fifth transistor N255, and a fifth transistor N253 are connected in series. The drain of the sixth transistor P14 is connected to the drain of the fifth transistor N255, the source of the fifth transistor N255 is connected to the drain of the fifth transistor N253, and the source of the fifth transistor N255 is grounded. The drain of the sixth transistor P14 is also connected to the gate of the fifth transistor N253.

[0093] A fourth transistor P15, a fifth transistor N256, and a fifth transistor N254 are connected in series. The drain of the fourth transistor P15 is connected to the drain of the fifth transistor N256, the source of the fifth transistor N256 is connected to the drain of the fifth transistor N254, and the source of the fifth transistor N254 is grounded. The gates of the fifth transistors N255 and N256 are connected together, and the gates of the fifth transistors N253 and N254 are connected together. The drain of the fifth transistor N255 serves as the input terminal of the second current mirror 250, and the drain of the fifth transistor N256 serves as the output terminal of the second current mirror 250.

[0094] The fifth transistors N253 - N256 form a cascode current mirror. Compared with Figure 9 the current mirror formed by the fifth transistors N251 and N252 in

[0095] In Figure 8 the corresponding embodiment, the first transistor N1, the second transistors N21 - N23, and the fifth transistors N251 - N256 are NMOS transistors, and the third transistor P10, the sixth transistor P14, and the fourth transistors P11 - P13 and P15 are PMOS transistors. That is, the first transistor N1 and the second transistors N21 - N23 are transistors of the same type.

[0096] In this embodiment, the control current I OSC is proportional to the current I 0 and the current I 0 = Vgs1 / R0. The frequency f of the clock signal CLK generated by the oscillator has low or zero temperature drift characteristics.

[0097] Figure 11 It is a circuit diagram of another exemplary ring oscillator of the present application. As Figure 11As shown, the ring oscillator includes: an oscillation loop 100, a current generation circuit 200, a shaping circuit 300, and a low-dropout linear regulator 400. The low-dropout linear regulator 400 generates the voltage of the second power supply terminal VDD2 based on the voltage provided by the first power supply terminal VDD1. The shaping circuit 300 and the low-dropout linear regulator 400 can refer to the previous embodiments.

[0098] The oscillation loop 100 includes M delay units, where M is an odd number greater than or equal to 3. The M delay units are cascaded in sequence to form a loop. Specifically, the output terminal of the previous-stage delay unit is connected to the input terminal of the next-stage delay unit, and the output terminal of the last-stage delay unit is connected to the input terminal of the first-stage delay unit. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first terminal of the second transistor serves as the output terminal of the delay unit. In Figure 11 the corresponding embodiment, the second transistor is a PMOS transistor, and the first capacitor is connected between the drain of the second transistor and the second power supply terminal VDD2. The first capacitor is, for example, a zero-temperature-drift metal-metal capacitor.

[0099] In Figure 11 the shown exemplary embodiment, M = 3, and the oscillation loop 100 includes a delay unit 101, a delay unit 102, and a delay unit 103. The delay unit 101 includes a second transistor P21 and a first capacitor C21. The delay unit 102 includes a second transistor P22 and a first capacitor C22. The delay unit 103 includes a second transistor P23 and a first capacitor C23. The first capacitor C21, the first capacitor C22, and the first capacitor C23 have the same capacitance value.

[0100] The current generation circuit 200 includes a first transistor P1. In Figure 11 the corresponding embodiment, the first transistor P1 is a PMOS transistor. The current generation circuit 200 is used to generate a control current I OSC , and provide the control current I OSC to the M delay units. The magnitude of the control current I OSC is proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor P1 (i.e., the gate-source voltage Vgs1). For example, the current generation circuit 200 is connected to the drain of the second transistor of the delay unit, and provides the control current I OSC to the drain of the second transistor. In Figure 11 the shown embodiment, the current generation circuit 200 includes 3 output terminals, which are respectively connected to the drains of the second transistors P21, P22, and P23, that is, respectively connected to the gates of the second transistors P22, P23, and P21.

[0101] The frequency f of the clock signal CLK generated by the ring oscillator and the control current I OSCis directly proportional to, inversely proportional to the capacitance value C of the first capacitor, and inversely proportional to the voltage difference between the control terminal voltage and the second terminal voltage of the second transistor (i.e., the gate-source voltage Vgs2). The first capacitor has a zero temperature coefficient. The frequency f of the clock signal CLK has a low temperature drift or zero temperature drift.

[0102] Figure 12 is a circuit diagram of another exemplary ring oscillator of the present application. As Figure 12 shown, the ring oscillator includes: an oscillation loop 100, a current generation circuit 200, a shaping circuit 300, and a low dropout linear regulator 400. The shaping circuit 300 and the low dropout linear regulator 400 can refer to the previous embodiments. The oscillation loop 100 includes three delay units, and the three delay units respectively include a second transistor P21 and a first capacitor C21, a second transistor P22 and a first capacitor C22, and a second transistor P23 and a first capacitor C23. The sources of the second transistors P21, P22, and P23 are connected to the second power supply terminal VDD2. The first capacitor C21 is connected between the drain of the second transistor P21 and the second power supply terminal VDD2. The first capacitor C22 is connected between the drain of the second transistor P22 and the second power supply terminal VDD2. The first capacitor C23 is connected between the drain of the second transistor P23 and the second power supply terminal VDD2.

[0103] The current generation circuit 200 includes a current mirror module, a first transistor P1, a third transistor N10, a first resistor R0, a current source 230, and a voltage clamping circuit 220.

[0104] The first transistor P1 and the current source 230 are connected in series between the second power supply terminal VDD2 and the ground. The source of the first transistor P1 is connected to the second power supply terminal VDD2, and the drain is connected to the current source 230. The current source 230 is used to generate a bias current Iref with zero temperature drift. The drain and the gate of the first transistor P1 are connected together, and the first transistor P1 is in diode-connected state.

[0105] The third transistor N10 and the first resistor R0 are connected in series between the second power supply terminal VDD2 and the ground. The source of the third transistor N10 is grounded, and the drain is connected to the first end N of the first resistor R0. The second end of the first resistor R0 is connected to the second power supply terminal VDD2. That is, the second end of the first resistor R0 and the source of the first transistor P1 are connected together.

[0106] The voltage clamping circuit 220 includes an operational amplifier OP1. The first input terminal of the operational amplifier OP1 is connected to the gate of the first transistor P1, the second input terminal is connected to the first end N of the first resistor R0, and the output terminal is connected to the gate of the third transistor N10. Optionally, the first input terminal is an inverting input terminal, and the second input terminal is a non-inverting input terminal. The operational amplifier OP1 clamps the voltage at the first end N of the first resistor R0 to the gate voltage of the first transistor P1. In this way, the voltage across the first resistor R0 is equal to the gate-source voltage Vgs1 of the first transistor P1, and the current I flowing through the first resistor R0 0 is equal to Vgs1 / R0. For Miller compensation, a resistor R1 and a capacitor C1 are connected in series between the output terminal of the operational amplifier OP1 and the first end N of the first resistor R0.

[0107] The current mirror module includes a first current mirror 210. The first current mirror 210 includes fourth transistors N11, N12, and N13. The drains of the fourth transistors N11, N12, and N13 are respectively connected to the drains of the second transistors P21, P22, and P23. The sources of the fourth transistors N11, N12, and N13 are grounded. The gates of the fourth transistors N11, N12, and N13 are connected to the gate of the third transistor N10. The gate of the third transistor N10 serves as a bias node B, and the bias node B provides a bias voltage V B . The control current I flowing through the fourth transistors N11, N12, and N13 OSC is proportional to the current I of the third transistor N10 0 . For example, when the aspect ratios of the fourth transistors N11, N12, and N13 are equal to the aspect ratio of the third transistor N1, the control current I OSC is equal to the current I 0 = Vgs1 / R0. The frequency f of the clock signal CLK generated by the oscillator has a low temperature drift or zero temperature drift characteristic.

[0108] In Figure 12 the shown ring oscillator, the first transistor P1 and the second transistors P21-P23 are PMOS transistors, and the third transistor N10 and the fourth transistors N11-N13 are NMOS transistors.

[0109] Figure 12 The shown ring oscillator includes a low dropout linear regulator 400, and the sources of the second transistors P21-P23 are connected to the second power supply terminal VDD2. It can be understood that the ring oscillator may not include the low dropout linear regulator 400, and the sources of the second transistors P21-P23 are connected to the first power supply terminal VDD1.

[0110] The present application also provides a chip. The chip includes the ring oscillator of the above embodiment. The chip is, for example, a microprocessor MCU. Figure 13 It is a structural diagram of an exemplary chip. The chip includes: a memory and the ring oscillator of the above embodiment.

[0111] Due to the influence of factors such as PVT, the actual frequency of the ring oscillator may deviate from the target frequency. Therefore, it is necessary to trim the frequency of the ring oscillator. According to the expression of the frequency f of the clock signal, trimming the control current I OSC , the resistance value of the first resistor R0, and the capacitance value of the first capacitor can achieve trimming of the frequency f. Taking Figure 3 , Figure 7 and Figure 8 's ring oscillator as an example, the present application provides the following several frequency trimming methods.

[0112] Exemplary Frequency Tuning Method 1

[0113] In some embodiments, the frequency f of the clock signal CLK of the ring oscillator is trimmed by trimming the first resistor R0 and the first capacitor. Each of the first capacitors C21, C22, C23 includes m trimming capacitors and m first switches, where m is a positive integer greater than 1. Each trimming capacitor and the corresponding first switch are connected in series to form a trimming branch. In Figure 3 , Figure 7 and Figure 8 's ring oscillator, the second transistor is an NMOS, and m trimming branches are connected in parallel between the drain terminal of the corresponding second transistor and the ground. In Figure 11 and 12 's ring oscillator, the second transistor is a PMOS, and m trimming branches are connected in parallel between the drain terminal of the corresponding second transistor and the power supply terminal. The m trimming capacitors, for example, have different capacitance values. The effective capacitance value of the first capacitor depends on which first switches are in the conducting state. The first resistor R0 includes n trimming resistors and n second switches, where n is a positive integer greater than 1. The n trimming resistors are connected in series, and each trimming resistor and the corresponding second switch are connected in parallel. When the second switch is conducting, the corresponding trimming resistor is short-circuited. The n trimming resistors, for example, have different resistance values. The effective resistance value of the first resistor depends on which second switches are in the off state.

[0114] Figure 14 is a schematic circuit diagram of the first capacitor according to an embodiment of the present application, Figure 15 is a schematic circuit diagram of the first resistor according to an embodiment of the present application. In Figure 14 and Figure 15 's corresponding embodiment, m = 8 and n = 2. The first capacitor includes 8 trimming capacitors C 30 , C 40, C 50 , C 60 , C 70 , C 80 , C 90 , C 100 , and eight first switches K 3 , K 4 , K 5 , K 6 , K 7 , K 8 , K 9 , K 10 . In some embodiments, the capacitance values of the trimming capacitors C 30 , C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 are C 0 , 2C 0 , 4C 0 , 8C 0 , 16C 0 , 32C 0 , 64C 0 , 128C 0 . Optionally, the eight first switches are respectively controlled by binary signals Bit<2>-Bit<9>.

[0115] The first resistor includes two trimming resistors R 10 and R 20 , and two second switches K 1 and K 2 . The trimming resistors R 10 and R 20 both include a positive temperature coefficient sub-resistor and a negative temperature coefficient sub-resistor connected in series. Therefore, the trimming resistors R 10 and R 20 are zero temperature coefficient resistors. In some embodiments, the resistance values of the trimming resistors R 10 and R 20 are R 00 and 2R 00 . Optionally, the two second switches are respectively controlled by binary signals Bit<0> and Bit<1>.

[0116] Two candidate frequency values can be achieved through the adjustable first capacitor and the first resistor, and the candidate frequency value closest to the target frequency value is selected. 10

[0117] The first switch and the second switch can be a Zener diode, a fuse, a MOSFET switch, etc. Exemplarily, the first switch and the second switch are MOSFET switches, and binary signals Bit<0>-Bit<9> are stored in the memory of the chip. When the chip is powered on, the first switch and the second switch are controlled to be turned on or off according to the binary signals Bit<0>-Bit<9>.

[0118] As described above, the frequency f of the clock signal CLK generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the control current I OSC The magnitude of the control current I OSC depends on the effective resistance value of the first resistor. In this embodiment, the change in the frequency f of the clock signal CLK caused by the conduction of one or more of the m first switches is greater than the change in the frequency f of the clock signal CLK caused by the conduction of one or more of the n second switches. That is, the first switch is used for coarse-tuning the frequency f, and the second switch is used for fine-tuning the frequency f. For example, the change in the frequency f of the clock signal caused by the conduction of any one of the first switches is greater than the change in the frequency f of the clock signal caused by the conduction of any one of the second switches. For example, the change in the frequency f of the clock signal caused by the conduction of the first switch K 30 corresponding to the trimming capacitor C 3 is greater than the change in the frequency f of the clock signal caused by the conduction of all two second switches K 1 and K 2 The binary signals Bit<0> to Bit<9> form a 10-bit binary number. The high 8 bits of the 10-bit binary number are used to control the first switch, and the low 2 bits are used to control the second switch. As the value of the 10-bit binary number gradually increases, the frequency f gradually increases or gradually decreases.

[0119] Exemplary Frequency Tuning Method 2

[0120] In some embodiments, the frequency f of the clock signal CLK generated by the ring oscillator is trimmed by trimming the fourth transistor and the first capacitor. Each of the first capacitors C21, C22, and C23 includes m trimming capacitors and m first switches, where m is a positive integer greater than 1. Each trimming capacitor and the corresponding first switch are connected in series to form a trimming branch. When the second transistor is an NMOS, the m trimming branches are connected in parallel between the drain terminal of the corresponding second transistor and the ground. When the second transistor is a PMOS, the m trimming branches are connected in parallel between the drain terminal of the corresponding second transistor and the power supply terminal. The m trimming capacitors have different capacitance values, for example. The effective capacitance value of the first capacitor depends on which first switches are in the on state. The fourth transistor includes n trimming transistors and n second switches. The n trimming transistors are connected in parallel, and the gate of each trimming transistor is connected to the bias node B through the corresponding second switch, where n is a positive integer greater than 1. When the second switch is on, the trimming transistor provides a control current to the delay unit. When the second switch is off, the trimming transistor does not provide a control current to the delay unit. Optionally, the n trimming transistors have different aspect ratios, for example. The magnitude of the control current provided to the delay unit depends on which second switches are in the off state.

[0121] Figure 14 is a schematic circuit diagram of the first capacitor according to an embodiment of the present application, Figure 16 is a schematic circuit diagram of the fourth transistor according to an embodiment of the present application. In Figure 14 and Figure 16 the corresponding embodiments, m = 8 and n = 2. The first capacitor includes eight trimming capacitors C 30 、C 40 、C 50 、C 60 、C 70 、C 80 、C 90 、C 100 , and eight first switches K 3 、K 4 、K 5 、K 6 、K 7 、K 8 、K 9 、K 10 . In some embodiments, the capacitance values of the trimming capacitors C 30 、C 40 、C 50 、C 60 、C 70 、C 80 、C 90 、C 100 are C 0 、2C 0 、4C 0,8C 0 , 16C 0 , 32C 0 , 64C 0 , 128C 0 Optionally, the eight first switches are respectively subjected to the binary signal Bit <2> ~Bit <9> control.

[0122] Each of the fourth transistors P11-P13 includes two trimming transistors P 100 and P 200 , and 2 second switches K 1 and K 2 In some embodiments, the trimming transistor P 100 and P 200 Can provide I 0 and 2I 0 Optionally, the two second switches are respectively subjected to the binary signal Bit <0> and Bit <1> control.

[0123] The adjustable first capacitor and the fourth transistor can realize 2 10 candidate frequency values, and the candidate frequency value closest to the target frequency value is selected. Exemplarily, the first switch and the second switch are MOSFET switches, and the binary signal Bit <0> -Bit <9> Stored in the chip's memory. When the chip is powered on, the binary signal Bit <0> -Bit <9> The first switch and the second switch are controlled to be turned on or off.

[0124] As mentioned above, the frequency f of the clock signal CLK generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the control current I OSC In this embodiment, the change in the frequency f of the clock signal CLK caused by the conduction of one or more of the m first switches is greater than the change in the frequency f of the clock signal CLK caused by the conduction of one or more of the n second switches. That is, the first switch is used to coarsely adjust the frequency f, and the second switch is used to finely adjust the frequency f. For example, the change in the frequency f of the clock signal CLK caused by the conduction of any first switch is greater than the change in the frequency f of the clock signal CLK caused by the conduction of any second switch. Binary signal Bit <0> ~Bit <9> A 10-bit binary number is formed, the upper 8 bits of the 10-bit binary number are used to control the first switch, and the lower 2 bits are used to control the second switch. The value of the 10-bit binary number gradually increases, and the frequency f gradually increases or decreases.

[0125] Exemplary Frequency Tuning Method 3

[0126] In some embodiments, the frequency of the ring oscillator is trimmed by trimming the first resistor R0 and the first capacitor. In this embodiment, m = 7 and n = 3. Figure 17 is a schematic circuit diagram of the first resistor in this embodiment, Figure 18 and is a schematic circuit diagram of the first capacitor in this embodiment. The first capacitor includes seven trimming capacitors C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 , and seven first switches K 4 , K 5 , K 6 , K 7 , K 8 , K 9 , K 10 . The first resistor includes three trimming resistors R 10 , R 20 , and R 30 , and three second switches K 1 , K 2 , and K 3 . The first switches and the second switches are controlled by binary signals Bit<0> to Bit<9>.

[0127] Exemplary Frequency Tuning Method 4

[0128] In some embodiments, the magnitude of the control current is trimmed by trimming the fourth transistor, and then the frequency f of the clock signal CLK of the ring oscillator is trimmed. Figure 19 is a schematic circuit diagram of the fourth transistor in this embodiment. Each of the fourth transistors P11 - P13 includes ten trimming transistors and ten second switches K 1 to K 10 . The ten trimming transistors are connected in parallel, and the gate of each trimming transistor is connected to the bias node B through the corresponding second switch. In some embodiments, the currents that the ten trimming transistors can respectively provide are I 0 , 2I 0 ... 2 8 * I 0 , 2 9 * I 0 . The ten second switches are respectively controlled by binary signals Bit<0> to Bit<9>. The adjustable fourth transistor can provide 2 10 candidate control current magnitudes, and thus provide 2 10 frequency values.

[0129] Exemplary Frequency Tuning Method 5

[0130] In some embodiments, the magnitude of the control current is trimmed by trimming the first resistor, and then the frequency f of the clock signal CLK of the ring oscillator is trimmed. Figure 20 is a schematic circuit diagram of the first resistor. The first resistor includes 10 trimming resistors and 10 second switches K 1 ~K 10 . In some embodiments, the resistance values of the 10 trimming resistors are R 0 , 2R 0 , …, 9R 0 , 10R 0 respectively. The 10 second switches are respectively controlled by binary signals Bit<0> to Bit<9>. Multiple candidate frequency values can be achieved through the tunable first resistor, and the candidate frequency value closest to the target frequency value is selected.

[0131] Exemplary Frequency Tuning Method 6

[0132] In some embodiments, the frequency f of the clock signal CLK of the ring oscillator is trimmed by trimming the first capacitor. Figure 21 is a schematic circuit diagram of the first capacitor. The first capacitor includes 10 trimming capacitors C 10 ~C 100 , and 10 first switches K 1 ~K 10 . The 10 first switches are respectively controlled by binary signals Bit<0> to Bit<9>. Multiple candidate frequency values can be achieved through the tunable first resistor, and the candidate frequency value closest to the target frequency value is selected.

[0133] In exemplary method 4, the control current I OSC is changed by trimming the fourth transistor, and then the frequency f of the clock signal CLK is trimmed. In exemplary method 5, the control current I OSC is changed by trimming the first resistor, and then the frequency f of the clock signal CLK is trimmed. However, both of these trimming methods will change the gate-source voltage of the second transistor. If the control current I OSCThe variation is large. The variation of the gate-source voltage of the second transistor is large, and the temperature drift characteristic of the second transistor will also change greatly, which will cause the oscillator to deviate seriously from the optimal temperature compensation point set under the "TT" process corner, resulting in a poor overall temperature drift characteristic of the oscillator. In the exemplary frequency trimming methods 1-3, a method combining trimming the control current and trimming the first capacitor is adopted. Moreover, the frequency f of the clock signal CLK is finely tuned by trimming the control current, and the frequency f of the clock signal CLK is coarsely tuned by trimming the first capacitor. In this way, the frequency deviation caused by factors such as PVT can be trimmed, and the offset of the temperature compensation point is minimized as much as possible, ensuring the low temperature drift characteristic of the oscillator.

[0134] In the exemplary method 6, the frequency of the ring oscillator is trimmed by trimming the first capacitor. Trimming the first capacitor does not change the gate-source voltage of the second transistor and maintains the optimal temperature drift compensation point of the design. However, since the minimum trimming capacitor designed cannot be close to the parasitic capacitance of the oscillator circuit, the capacitance value of the minimum trimming capacitor in the first capacitor cannot be made very small. If the capacitance value of the minimum trimming capacitor is designed to be large, the capacitance values of other trimming capacitors will also increase, resulting in an increase in the area and power consumption of the trimming circuit. In the exemplary frequency trimming methods 1-3, a method combining trimming the control current and trimming the first capacitor is adopted. Moreover, the frequency of the clock signal is finely tuned by trimming the control current, and the frequency of the clock signal is coarsely tuned by trimming the first capacitor. In this way, the power consumption and area are greatly optimized, and a good temperature drift characteristic can still be maintained. For example, if the exemplary frequency trimming method 6 is used, the first capacitor includes 10 trimming capacitors, the minimum trimming capacitor is 10 fF, and the maximum trimming capacitor is 10240 fF. If the exemplary frequency trimming method 1 is used, the lower 2 bits correspond to the trimming of the first resistor, and the higher 8 bits correspond to the trimming of the first capacitor. The maximum trimming capacitor only needs 2560 fF, and the capacitor area is greatly reduced. When the oscillator circuit is working, the first capacitor is charged and discharged, the capacitor area is reduced, and the power consumption is also reduced.

[0135] Taking the design frequency of 262 KHz and the operating temperature range of -40 to 125 °C as an example, the ring oscillators adopting the exemplary trimming methods 1 and 3-6 are each subjected to 100 Monte Carlo simulations, and the simulation results are shown in Table 1.

[0136]

[0137]

[0138] Table 1

[0139] As shown in Table 1, when using trimming methods 4 and 5 and only trimming the control current, a large temperature drift will be caused. When using trimming method 6 and only trimming the first capacitor, a large capacitor area and power consumption will be caused. When using trimming methods 1 and 3, by trimming the first capacitor to coarsely adjust the clock signal frequency and trimming the control current to finely adjust the clock signal frequency, good temperature drift characteristics and low power consumption can be achieved.

[0140] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A ring oscillator, characterized in that: include: M delay units, the M delay units are sequentially cascaded into a loop, the delay unit comprises a second transistor and a first capacitor, the control end of the second transistor serves as an input end of the delay unit, the first end of the second transistor serves as an output end of the delay unit, and M is an odd number greater than or equal to 3; and a current generating circuit, the current generating circuit comprising a first transistor, the current generating circuit being used to generate a control current proportional to a voltage difference between a control terminal voltage and a second terminal voltage of the first transistor, and providing the control current to the M delay units, One end of the first capacitor is connected to the first end of the second transistor, the other end of the first capacitor is connected to the ground or the power supply end, and the first transistor and the second transistor are both P-type or N-type.

2. The ring oscillator according to claim 1, characterized in that The first transistor and the second transistor are both NMOS transistors, and the first capacitor is connected between the first end of the second transistor and ground; or, the first transistor and the second transistor are both PMOS transistors, and the first capacitor is connected between the first end of the second transistor and a power supply terminal.

3. The ring oscillator according to claim 1, characterized in that: The current generating circuit also includes: a current source, a first resistor and a current mirror module, wherein the current source and the first transistor are connected in series, the voltage difference between the two ends of the first resistor is clamped to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor, and the current mirror module generates the control current based on the current flowing through the first resistor.

4. The ring oscillator according to claim 3, characterized in that: The current generating circuit also includes a voltage clamping circuit, which clamps the voltage of the first end of the first resistor to the control terminal voltage of the first transistor. The second end of the first resistor is connected to the second end of the first transistor. The current source is a bandgap reference current source.

5. The ring oscillator according to claim 4, characterized in that: The current generating circuit further includes a third transistor, and the third transistor is connected in series with the first resistor. The current mirror module includes a first current mirror, the first current mirror includes a plurality of fourth transistors, the control ends of the plurality of fourth transistors are connected together, the second ends of the plurality of fourth transistors are connected together, The voltage clamp circuit comprises an operational amplifier, a first input terminal of the operational amplifier is connected to the control terminal of the first transistor, a second input terminal is connected to the first terminal of the first resistor, and an output terminal is connected to the control terminal of the third transistor. The control end of the first transistor is connected to the first end of the first transistor.

6. The ring oscillator according to claim 5, characterized in that: When the first transistor and the second transistor are NMOS transistors, the third transistor is a PMOS transistor, and the fourth transistor is a PMOS transistor; When the first transistor and the second transistor are PMOS transistors, the third transistor is an NMOS transistor, and the fourth transistor is an NMOS transistor.

7. The ring oscillator according to claim 5, characterized in that: The current mirror module further includes a second current mirror, the second current mirror includes a plurality of fifth transistors, one of the fourth transistor and the fifth transistor is of N type, and the other is of P type, The second current mirror generates an intermediate current based on the current flowing through the first resistor, and the first current mirror generates the control current based on the intermediate current.

8. The ring oscillator according to claim 3, characterized in that: The first capacitor includes m trimming capacitors and m first switches, each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, wherein m is a positive integer greater than 1.

9. The ring oscillator according to claim 8, characterized in that: The m trimming capacitors have different capacitance values.

10. The ring oscillator according to claim 8, characterized in that The first resistor includes n trimming resistors and n second switches, the n trimming resistors are connected in series, and each trimming resistor is connected in parallel with a corresponding second switch, wherein n is a positive integer greater than 1.

11. The ring oscillator according to claim 10, characterized in that: The n trimming resistors have different resistance values.

12. The ring oscillator according to claim 10, characterized in that The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor, and the frequency change of the clock signal caused when one or more first switches among the m first switches are turned on is greater than the frequency change of the clock signal caused when one or more second switches among the n second switches are turned on.

13. The ring oscillator according to claim 8, characterized in that The current mirror module includes a first current mirror, the first current mirror includes a plurality of fourth transistors, the control ends of the plurality of fourth transistors are connected together, the second ends of the plurality of fourth transistors are connected together, the fourth transistors include n trimming transistors and n second switches, the n trimming transistors are connected in parallel, and the control end of each trimming transistor is connected to a bias node through the corresponding second switch, wherein n is a positive integer greater than 1.

14. The ring oscillator according to claim 13, characterized in that The n trimming transistors have different width-to-length ratios.

15. The ring oscillator according to claim 13, characterized in that The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the size of the control current, and the frequency change of the clock signal caused when one or more first switches among the m first switches are turned on is greater than the frequency change of the clock signal caused when one or more second switches among the n second switches are turned on.

16. The ring oscillator according to claim 1, characterized in that The first transistor and the second transistor have the same type and temperature drift characteristics, and the frequency of the clock signal generated by the ring oscillator has a zero temperature drift characteristic.

17. A chip, characterized in that: comprising a ring oscillator, the ring oscillator generating a clock signal, The ring oscillator comprises: M delay units, the M delay units are sequentially cascaded into a loop, the delay unit comprises a second transistor and a first capacitor, the control end of the second transistor serves as an input end of the delay unit, the first end of the second transistor serves as an output end of the delay unit, and M is an odd number greater than or equal to 3; and a current generating circuit, the current generating circuit comprising a first transistor, the current generating circuit being used to generate a control current proportional to a voltage difference between a control terminal voltage and a second terminal voltage of the first transistor, and providing the control current to the M delay units, One end of the first capacitor is connected to the first end of the second transistor, the other end of the first capacitor is connected to the ground or the power supply end, and the first transistor and the second transistor are both P-type or N-type.

18. The chip according to claim 17, characterized in that: The first transistor and the second transistor are both NMOS transistors, and the first capacitor is connected between the first end of the second transistor and ground; or, the first transistor and the second transistor are both PMOS transistors, and the first capacitor is connected between the first end of the second transistor and a power supply terminal.

19. The chip according to claim 17, characterized in that: The current generating circuit also includes: a current source, a first resistor and a current mirror module, wherein the current source and the first transistor are connected in series, the voltage difference between the two ends of the first resistor is clamped to the voltage difference between the control terminal voltage and the second terminal voltage of the first transistor, and the current mirror module generates the control current based on the current flowing through the first resistor.

20. The chip according to claim 19, characterized in that The current generating circuit also includes a voltage clamping circuit, which clamps the voltage of the first end of the first resistor to the control terminal voltage of the first transistor. The second end of the first resistor is connected to the second end of the first transistor. The current source is a bandgap reference current source.

21. The chip according to claim 20, characterized in that: The current generating circuit further includes a third transistor, and the third transistor is connected in series with the first resistor. The current mirror module includes a first current mirror, the first current mirror includes a plurality of fourth transistors, the control ends of the plurality of fourth transistors are connected together, the second ends of the plurality of fourth transistors are connected together, The voltage clamp circuit comprises an operational amplifier, a first input terminal of the operational amplifier is connected to the control terminal of the first transistor, a second input terminal is connected to the first terminal of the first resistor, and an output terminal is connected to the control terminal of the third transistor. The control terminal of the first transistor is connected to the first terminal of the first transistor.

22. The chip according to claim 21, characterized in that: When the first transistor and the second transistor are NMOS transistors, the third transistor is a PMOS transistor, and the fourth transistor is a PMOS transistor; When the first transistor and the second transistor are PMOS transistors, the third transistor is an NMOS transistor, and the fourth transistor is an NMOS transistor.

23. The chip according to claim 21, characterized in that: The current mirror module further includes a second current mirror, the second current mirror includes a plurality of fifth transistors, one of the fourth transistor and the fifth transistor is of N type, and the other is of P type, The second current mirror generates an intermediate current based on the current flowing through the first resistor, and the first current mirror generates the control current based on the intermediate current.

24. The chip according to claim 19, characterized in that The first capacitor includes m trimming capacitors and m first switches, each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, wherein m is a positive integer greater than 1.

25. The chip according to claim 24, characterized in that: The first resistor includes n trimming resistors and n second switches, the n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch, wherein n is a positive integer greater than 1. The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor, and the frequency change of the clock signal caused when one or more first switches among the m first switches are turned on is greater than the frequency change of the clock signal caused when one or more second switches among the n second switches are turned on.

26. The chip according to claim 24, characterized in that: The current mirror module includes a first current mirror, the first current mirror includes a plurality of fourth transistors, the control ends of the plurality of fourth transistors are connected together, the second ends of the plurality of fourth transistors are connected together, the fourth transistors include n trimming transistors and n second switches, the n trimming transistors are connected in parallel, and the control end of each trimming transistor is connected to a bias node through the corresponding second switch, wherein n is a positive integer greater than 1, The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the size of the control current, and the frequency change of the clock signal caused when one or more first switches among the m first switches are turned on is greater than the frequency change of the clock signal caused when one or more second switches among the n second switches are turned on.

27. The chip according to claim 25 or 26, characterized in that: The chip further includes a memory storing an (m+n)-bit binary number, and the m first switches and the n second switches are set to be turned on or off according to the (m+n)-bit binary number.

28. The chip according to claim 17, characterized in that: The first transistor and the second transistor have the same type and temperature drift characteristics, and the frequency of the clock signal generated by the ring oscillator has a zero temperature drift characteristic.

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