FPGA lookup table circuit and implementation method

Abstract

The invention relates to the technical field of integrated circuits, and discloses a field programmable gate array (FPGA) lookup table circuit and an implementation method, the lookup table circuit comprises a first decoder used for acquiring a first address input signal of a lookup table and decoding the first address input signal to obtain first decoded data; the first selector is used for acquiring RAM multi-bit data, and performing selection processing on the RAM multi-bit data by utilizing the first decoding data to obtain output multi-bit data; the second decoder is used for acquiring a second address input signal of the lookup table and decoding the second address input signal to obtain second decoded data; and the second selector is used for performing selection processing on the output multi-bit data by using the second decoding data to obtain single-bit output data of the lookup table. According to the method, the number of consumed devices is smaller, logic resources and area occupied by the LUT in the FPGA are saved, and the effect of universality enhancement is achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an FPGA look-up table circuit and an implementation method thereof. Background Art

[0002] A LUT (Lookup Table) is an important component unit of an FPGA (Field-Programmable Gate Array). The LUT can be regarded as a RAM (Random Access Memory) with multiple address lines. By inputting an address signal to look up a table and outputting the content pre-written in the RAM at this address, a logical operation on a signal can be realized once.

[0003] The related look-up table adopts an architecture composed of a RAM and its supporting multi-stage selectors. Each stage of the selector is controlled by a 1-bit input terminal; however, with the increase in the scale of programmable logic devices and the improvement of functional requirements, the related look-up table has problems such as insufficient working speed, increased power consumption, and increased on-chip area. These problems have become key factors restricting the overall performance of FPGA chips. Summary of the Invention

[0004] In view of this, the present invention provides an FPGA look-up table circuit and an implementation method thereof to solve problems such as insufficient working speed, increased power consumption, and increased on-chip area of the related look-up table.

[0005] In a first aspect, the present invention provides an FPGA look-up table circuit. The look-up table circuit includes a first decoder, a second decoder, a first selector, and a second selector; wherein, the output terminal of the first decoder is connected to the input terminal of the first selector, the output terminal of the second decoder is connected to the input terminal of the second selector, and the output terminal of the first selector is connected to the input terminal of the second selector;

[0006] The first decoder is configured to obtain a first address input signal of the look-up table, perform decoding processing on the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector;

[0007] The first selector is configured to obtain multi-bit data of the RAM, perform selection processing on the multi-bit data of the RAM by using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector;

[0008] The second decoder is configured to obtain a second address input signal of the look-up table, perform decoding processing on the second address input signal to obtain second decoded data, and transmit the second decoded data to the second selector;

[0009] A second selector for performing a selection process on the output multi-bit data using the second decoded data to obtain the single-bit output data of the lookup table.

[0010] The FPGA lookup table circuit provided by the embodiments of the present invention constitutes a LUT addressing structure with a dual decoder by setting a first decoder, a second decoder, a first selector, and a second selector in the lookup table circuit. Compared with the LUT with a multi-stage selector structure, the LUT addressing structure with a dual decoder consumes fewer device numbers, saving area resources and overall power consumption. At the same time, the LUT addressing structure with a dual decoder has better symmetry and can be arranged in an orderly and regular manner, saving the logic resources and area occupied by the LUT in the FPGA, thereby facilitating the optimization of the layout space on the FPGA chip. And by using the dual decoder as the control unit of the two-stage selector, each stage of the selector is controlled by a multi-bit input terminal, which can shorten the difference between the fastest and slowest signal delays to the delay size of one selector, curbing the attenuation of the delay performance of each port and having the effect of enhanced versatility, which is flexible and friendly for chip hardware wiring, software interaction, etc.

[0011] In an optional embodiment, the first decoder is specifically configured to perform an inversion operation on the first address input signal to obtain an inverted signal, and perform permutation and combination on the first address input signal and the inverted signal to obtain the first decoded data.

[0012] The FPGA lookup table circuit provided by the embodiments of the present invention uses the first decoder to perform decoding processing on the divided first address input signal. Since the input bit number of the divided first address input signal is relatively small, the decoding complexity of the first decoder is effectively reduced, and the addressing speed of the FPGA lookup table circuit is improved.

[0013] In an optional embodiment, the first selector is specifically configured to select the RAM multi-bit data corresponding to the input port based on the first decoded data to obtain the output multi-bit data, and transmit the output multi-bit data to the second selector;

[0014] The FPGA lookup table circuit provided by the embodiments of the present invention controls the selection control logic of the first selector through the first decoded data, improves the flexibility of the selection control, can effectively improve the working performance of the selector, and reduces the overall power consumption and area of the FPGA.

[0015] In an optional embodiment, when one-bit data in the second decoded data is low-level data and the remaining bit data are all high-level data, the second selector is specifically configured to select the output multi-bit data corresponding to the input port based on the low-level data to obtain the single-bit output data of the lookup table; wherein, the single-bit data in the output multi-bit data corresponds to the input port of the second selector one by one.

[0016] In the FPGA lookup table circuit provided by the embodiment of the present invention, the selection control logic of the second selector is controlled by the second decoded data, and then the second selector is controlled to output single-bit output data, realizing the addressing function of the lookup table and accelerating the comprehensive transmission rate of the addressing signal in the lookup table.

[0017] In an alternative embodiment, both the first decoder and the second decoder adopt 3-8 decoders.

[0018] In the FPGA lookup table circuit provided by the embodiment of the present invention, both the first decoder and the second decoder adopt 3-8 decoders, using a dual 3-8 decoder as the addressing configuration, and the total logic levels of the 6 input-output paths are less, thus shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output paths.

[0019] In an alternative embodiment, both the first selector and the second selector adopt one-hot code multiplexers, reducing the decoding delay and improving the selection speed.

[0020] In the FPGA lookup table circuit provided by the embodiment of the present invention, by adopting one-hot code multiplexers as the first selector and the second selector, the first selector and the second selector are controlled by multi-bit input terminals, improving the flexibility of use, effectively improving the working performance, reducing the overall power consumption and area.

[0021] In an alternative embodiment, it further includes:

[0022] A first buffer, connected to the input terminal of the first selector, for acquiring multi-bit data of the RAM and inputting the multi-bit data of the RAM into the first selector.

[0023] In the FPGA lookup table circuit provided by the embodiment of the present invention, by using the first buffer to acquire multi-bit data of the RAM and inputting the multi-bit data of the RAM into the first selector, the caching of the multi-bit data of the RAM is realized, ensuring that the FPGA lookup table circuit will not lose important data due to external interrupts, and at the same time ensuring the integrity of the lookup table task.

[0024] In an alternative embodiment, it further includes:

[0025] A second buffer, connected to the output terminal of the second selector, for acquiring the single-bit output data of the lookup table and transmitting the single-bit output data of the lookup table to the lookup table exit.

[0026] The FPGA lookup table circuit provided by the embodiment of the present invention uses a second buffer to obtain the single-bit output data of the lookup table, and transmits the single-bit output data of the lookup table to the lookup table exit, so that the single-bit output data of the lookup table arrives at the receiving device synchronously, ensuring the accuracy and consistency of data reception.

[0027] In a second aspect, the present invention provides an FPGA, including: the FPGA lookup table circuit according to the first aspect or any corresponding embodiment thereof.

[0028] In a third aspect, the present invention provides a method for implementing an FPGA lookup table circuit, which is applied to the FPGA lookup table circuit according to the first aspect or any corresponding embodiment thereof. The method includes:

[0029] The first decoder obtains the first address input signal of the lookup table, decodes the first address input signal to obtain the first decoded data, and transmits the first decoded data to the first selector;

[0030] The first selector obtains the RAM multi-bit data, uses the first decoded data to perform a selection process on the RAM multi-bit data to obtain the output multi-bit data, and transmits the output multi-bit data to the second selector;

[0031] The second decoder obtains the second address input signal of the lookup table, decodes the second address input signal to obtain the second decoded data, and transmits the second decoded data to the second selector;

[0032] The second selector uses the second decoded data to perform a selection process on the output multi-bit data to obtain the single-bit output data of the lookup table. Description of the Drawings

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 is a structural block diagram of an FPGA lookup table circuit according to an embodiment of the present invention;

[0035] Figure 2 is a structural schematic diagram of an FPGA lookup table circuit according to an embodiment of the present invention;

[0036] Figure 3 is a flow schematic diagram of a method for implementing an FPGA lookup table circuit according to an embodiment of the present invention. Detailed Embodiments

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0038] In this embodiment, an FPGA look-up table circuit is provided. As Figure 1 shown, the look-up table circuit includes a first decoder 101, a second decoder 102, a first selector 103, and a second selector 104. Among them, the output terminal of the first decoder 101 is connected to the input terminal of the first selector 103, the output terminal of the second decoder 102 is connected to the input terminal of the second selector 104, and the output terminal of the first selector 103 is connected to the input terminal of the second selector 104.

[0039] The first decoder 101 is configured to obtain a first address input signal of the look-up table, perform decoding processing on the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector 103.

[0040] Specifically, the FPGA look-up table is a storage unit array composed of an address signal and RAM multi-bit data corresponding to the address signal.

[0041] Further, an address input signal of the look-up table is obtained, and the address input signal of the look-up table is divided to obtain a first address input signal and a second address input signal. Among them, the total number of bits of the address of the look-up table is n bits. According to the actual situation, the n-bit address is reasonably divided into two parts. For example, the high m bits are allocated to the first decoder 101, and the low k bits (where n = m + k) are allocated to the second decoder 102. For example, if the look-up table address has 8 bits, the high 4 bits can be used as the first address input signal and divided to the first decoder 101, and the low 4 bits can be used as the second address input signal and divided to the second decoder 102.

[0042] The first selector 103 is configured to obtain RAM multi-bit data, perform selection processing on the RAM multi-bit data by using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector 104.

[0043] The second decoder 102 is configured to obtain a second address input signal of the look-up table, perform decoding processing on the second address input signal to obtain second decoded data, and transmit the second decoded data to the second selector 104.

[0044] Specifically, the first decoder 101 and the second decoder 102 are respectively used as the control units of the two-stage selector, and each stage of the selector is controlled by the multi-bit input terminal (i.e., the output data of the first decoder 101 and the second decoder 102).

[0045] The second selector 104 is used to perform a selection process on the output multi-bit data by using the second decoded data to obtain the single-bit output data of the look-up table.

[0046] An FPGA look-up table circuit provided in this embodiment constitutes a LUT addressing structure with a dual decoder by setting a first decoder, a second decoder, a first selector, and a second selector in the look-up table circuit. Compared with the LUT with a multi-stage selector structure, the LUT addressing structure with a dual decoder consumes fewer device numbers, saving area resources and overall power consumption; at the same time, the LUT addressing structure with a dual decoder has better symmetry and can be arranged in an orderly and regular manner, saving the logic resources and area occupied by the LUT in the FPGA, thus being beneficial to the optimization of the layout space on the FPGA chip; and by using the dual decoder as the control unit of the two-stage selector, each stage of the selector is controlled by the multi-bit input terminal, the difference between the fastest and slowest signal delays can be shortened to the delay size of one selector, curbing the delay performance attenuation of each port, and having the effect of enhanced versatility, being flexible and friendly for chip hardware wiring, software interaction, etc.

[0047] In some optional embodiments, the first decoder 101 is specifically configured to perform an inversion operation on the first address input signal to obtain an inverted signal, and perform permutation and combination on the first address input signal and the inverted signal to obtain the first decoded data.

[0048] For example, the first decoder 101 performs permutation and combination on three input signals (i.e., the first address input signal) and their inverted signals, and each three signals serve as the input terminals of a NAND gate device, and a total of eight outputs (i.e., the first decoded data) can be generated.

[0049] Among them, the first decoder 101 decodes the m-bit first address input signal through the internal combinational logic circuit; taking a 4-bit address input signal as an example, 4-bit binary numbers can represent 16 different states, so the first decoder 101 can generate 16 different strobe signals, and its internal decoding logic can be constructed by multiple basic logic gates such as AND gates and OR gates; among them, the strobe signals can be transmitted to the first selector 103 as the first decoded data to control the selection logic of the first selector 103. By adjusting the level state of the input signals of the first decoder 101 or the second decoder 102, it can be determined which path the first selector 103 or the second selector 104 selects to conduct, so as to achieve the directional selection function.

[0050] Furthermore, the function of the second decoder 102 is the same as that of the first decoder 101.

[0051] An FPGA look-up table circuit provided in this embodiment uses a first decoder to perform decoding processing on the divided first address input signal. Since the input bit number of the divided first address input signal is relatively small, the decoding complexity of the first decoder is effectively reduced, and the addressing speed of the FPGA look-up table circuit is improved.

[0052] In some optional embodiments, the first selector 103 is specifically configured to select the RAM multi-bit data corresponding to the input port based on the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector 104.

[0053] Specifically, the first selector 103 includes an input, an output port, and a selection control circuit composed of logic gate circuits; among them, the input port receives the RAM multi-bit data in the look-up table and the first decoded data sent from the output end of the first decoder 101, and the selection control port in the selection control circuit controls the on / off of the input port according to the level state of the first decoded data, that is, when the first decoded data is at a low level, the data of the input port corresponding to the first decoded data is used as the output, otherwise, the data is cut off; the first selector 103 includes multiple output ports, and the selection control circuit is used to control the output ports to send output multi-bit data to the second selector 104.

[0054] Furthermore, the internal of the selection control circuit uses logic gates such as AND gates and OR gates to implement the selection function.

[0055] For example, when the first selector 103 uses a mux8, there are eight parallel switches, and each switch is connected to one bit of data. If the first decoded data is at a low level, the path corresponding to the switch is selected for RAM single-bit data transmission; if the first decoded data is at a high level, the path corresponding to the switch is disconnected and the data transmission is stopped.

[0056] An FPGA look-up table circuit provided in this embodiment controls the selection control logic of the first selector through the first decoded data, improves the flexibility of the selection control, can effectively improve the working performance of the selector, and reduces the overall power consumption and area of the FPGA.

[0057] In some optional embodiments, the second selector 104 is specifically configured to, when one bit of data in the second decoded data is low-level data and the remaining bits of data are all high-level data, select the output multi-bit data corresponding to the input port based on the low-level data to obtain the single-bit output data of the look-up table; among them, the single-bit data in the output multi-bit data corresponds to the input port of the second selector 104 one by one.

[0058] Specifically, the second selector 104 includes an input, an output port, and a selection control circuit composed of logic gate circuits. Its input port is the same as that of the selection control circuit of the first selector 103, and the second selector 104 includes one output port.

[0059] Furthermore, the output multi-bit data (i.e., control bits) generated by the second decoder 102 reach the second selector 104, and only one bit is at a low level, such that only one path of the second selector 104 is gated.

[0060] An FPGA look-up table circuit provided in this embodiment controls the selection control logic of the second selector through the second decoded data, and further controls the second selector to output single-bit output data, realizing the addressing function of the look-up table and accelerating the comprehensive transmission rate of the addressing signal in the look-up table.

[0061] In some alternative embodiments, both the first decoder 101 and the second decoder 102 employ 3-to-8 decoders.

[0062] Specifically, in the actual usage scenario of the FPGA, the path delays of all fast and slow ports need to be considered. Therefore, comprehensively improving the signal transmission rate from the address input end to the LUT output end and reducing the propagation delay are the keys to enhancing the LUT performance and thus improving the chip operating speed. Taking a six-input look-up table (LUT6) as an example, using a dual 3-to-8 decoder as the addressing configuration, the total logic levels of the 6 input-output paths are fewer, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output paths.

[0063] Furthermore, a 3-to-8 decoder is a digital logic circuit. A 3-to-8 decoder has 3 input terminals and 8 output terminals. The input terminals receive 3-bit binary codes, and the data conversion process of the 3-to-8 decoder is implemented through internal logic gate circuits. When the 3-bit binary number input changes, the high-level signals at the output terminals will also correspondingly switch among the 8 output lines to ensure that each input combination has a unique output correspondence.

[0064] Furthermore, the first decoder 101 and the second decoder 102 can also employ decoders of types such as 2-to-4 decoders and 4-to-7 decoders, and different types of decoders can be selected according to the number of bits of the input signal.

[0065] An FPGA look-up table circuit provided in this embodiment, where both the first decoder and the second decoder employ 3-to-8 decoders, uses a dual 3-to-8 decoder as the addressing configuration, and the total logic levels of the 6 input-output paths are fewer, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output paths.

[0066] In some alternative embodiments, both the first selector 103 and the second selector 104 employ one-hot encoded multiplexers.

[0067] Specifically, an one-hot encoded multiplexer is a unique multiplexer that uses one-hot encoding as the selection signal to control the data transmission path; one-hot encoding, as a binary encoding method, is characterized in that only one bit in the encoding is 1 and the remaining bits are all 0; in the one-hot encoded multiplexer, each bit of the one-hot encoding corresponds to an input channel; when a certain bit in the one-hot encoding is set to 1, the input channel corresponding to that bit is selected, and the data it carries will be transmitted to the output end through the input channel, enabling the one-hot encoded multiplexer to efficiently and accurately implement the selection of the data transmission path.

[0068] An FPGA look-up table circuit provided in this embodiment, by using one-hot encoded multiplexers as the first selector and the second selector, which are controlled by multi-bit input terminals, improves the flexibility of use, effectively improves the working performance, and reduces the overall power consumption and area of the look-up table.

[0069] In some alternative embodiments, it further includes:

[0070] A first buffer 105, connected to the input terminal of the first selector 103, for obtaining multi-bit RAM data and inputting the multi-bit RAM data into the first selector 103.

[0071] Specifically, a buffer is a logic gate circuit used to amplify and transmit signals, usually used to connect different logic circuits to achieve signal transmission between modules and level adaptation. The buffer can enhance the driving ability of the signal, enabling the signal to stably drive more logic gates or transmit over a longer distance.

[0072] An FPGA look-up table circuit provided in this embodiment, by using the first buffer to obtain multi-bit RAM data and inputting the multi-bit RAM data into the first selector, realizes the caching of multi-bit RAM data, ensures that the FPGA look-up table circuit will not lose important data due to external interrupts, and also guarantees the integrity of the look-up table task.

[0073] In some alternative embodiments, it further includes:

[0074] A second buffer 106, connected to the output terminal of the second selector 104, for obtaining single-bit output data of the look-up table and transmitting the single-bit output data of the look-up table to the look-up table exit.

[0075] The FPGA lookup table circuit provided by the embodiment of the present invention uses a second buffer to obtain the single-bit output data of the lookup table, and transmits the single-bit output data of the lookup table to the lookup table exit, so that the single-bit output data of the lookup table arrives at the receiving device synchronously, ensuring the accuracy and consistency of data reception.

[0076] The working process of the FPGA lookup table circuit is described below through an embodiment.

[0077] Embodiment 1:

[0078] As Figure 2 shown, the first decoder and the second decoder adopt decoder3_8 (3-8 decoder), and both the first selector and the second selector adopt mux8 (a kind of multiplexer). Then the working process of doubledecoder3_8LUT6 (LUT6 adopting a dual 3-8 decoder) includes:

[0079] Divide the addresses in LUT6 to obtain the address input signals inb_0, inb_1, and inb_2 of the first decoder, and the address input signals inb_3, inb_4, and inb_5 of the second decoder;

[0080] The first decoder decoder3_8 decodes inb_0, inb_1, and inb_2 to obtain the decoded data ctrl1_38[7:0], and inputs the decoded data into the first selector mux8;

[0081] Input the RAM multi-bit data tb[0:56] in LUT6 into the first selector mux8;

[0082] The first selector uses the decoded data ctrl1_38[7:0] to perform selection logic control on tb[0:56] to obtain the output multi-bit data and send it to the second selector mux8;

[0083] The second decoder decoder3_8 decodes inb_3, inb_4, and inb_5 to obtain the decoded data ctrl2_38[7:0], and inputs the decoded data into the second selector mux8;

[0084] The second selector uses the decoded data ctrl2_38[7:0] to perform selection logic control on the output multi-bit data to obtain the single-bit output data f.

[0085] The beneficial effects of the above Embodiment 1 are:

[0086] 1) For the problems faced by the LUT, a dual decoder is used to control the addressing function of the lookup table; the first decoder and the second decoder are used as the control units of the two-stage selector, and the one-hot code selector is used as the first selector and the second selector. Each stage of the selector is controlled by a multi-bit input terminal, which improves the flexibility of use and can effectively improve the working performance, reduce the overall power consumption and area.

[0087] 2) In the actual use scenario of the FPGA, the path delays of all fast and slow ports need to be considered. Therefore, comprehensively improving the signal transmission rate from the address input terminal to the LUT output terminal and reducing the propagation delay are the keys to improving the LUT performance and thus the chip working speed; taking LUT6 as an example, using a dual 3-8 decoder as the addressing configuration, the total number of logic levels of the 6 input-output paths is less, thus shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output path.

[0088] 3) Each LUT has multiple address input terminals. Due to the limitation of the device structure combination, the propagation delays of signals from each address input terminal to the LUT output terminal are not the same. The LUT addressing structure of the dual decoder can shorten the gap between the fastest and slowest signal delays to the delay size of one selector, curbing the decay of the delay performance of each port, and having the effect of enhanced versatility, which is flexible and friendly for chip hardware wiring, software interaction, etc.

[0089] 4) The logic resources occupied by each LUT in the FPGA are determined by the number of components of each part of the LUT and the regularity of the arrangement; compared with the LUT with a multi-stage selector structure, the LUT addressing structure of the dual decoder consumes fewer devices, saving area resources and overall power consumption; at the same time, the LUT addressing structure of the dual decoder has better physical symmetry and can be arranged in an orderly and regular manner, thus being conducive to the optimization of the on-chip layout space.

[0090] In this embodiment, an FPGA is further provided, including: an FPGA lookup table circuit as in Figure 1 the embodiment shown.

[0091] In this embodiment, a method for implementing an FPGA lookup table circuit is further provided, which is applied to the FPGA lookup table circuit, as in Figure 3 shown, including:

[0092] Step S301, the first decoder obtains the first address input signal of the lookup table, decodes the first address input signal to obtain the first decoded data, and transmits the first decoded data to the first selector.

[0093] In step S302, the first selector obtains multi-bit data of the RAM, performs selection processing on the multi-bit data of the RAM by using the first decoded data to obtain output multi-bit data, and transmits the output multi-bit data to the second selector.

[0094] In step S303, the second decoder obtains the second address input signal of the look-up table, performs decoding processing on the second address input signal to obtain second decoded data, and transmits the second decoded data to the second selector.

[0095] In step S304, the second selector performs selection processing on the output multi-bit data by using the second decoded data to obtain single-bit output data of the look-up table.

[0096] The implementation method of an FPGA look-up table circuit in this embodiment is applied to an FPGA look-up table circuit in the embodiment shown in Figure 1 Therefore, the specific implementation manners of steps S301 to S304 can refer to the corresponding descriptions in the embodiment part shown above, and will not be elaborated here. Figure 1

[0097] It can be understood that the functions and beneficial effects of the method in this embodiment correspond to those of an FPGA look-up table circuit in the embodiment shown in Figure 1 and will not be elaborated here.

[0098] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0099] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated here.

[0100] ​In several embodiments provided by the embodiments of the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0101] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] In addition, in each embodiment of the embodiments of the present application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0103] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0104] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. An FPGA lookup table circuit, characterized in that: The lookup table circuit comprises a first decoder, a second decoder, a first selector and a second selector; wherein the output end of the first decoder is connected to the input end of the first selector, the output end of the second decoder is connected to the input end of the second selector, and the output end of the first selector is connected to the input end of the second selector; The first decoder is used to obtain a first address input signal of the lookup table, decode the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector; The first selector is used to obtain RAM multi-bit data, select and process the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector; The second decoder is used to obtain a second address input signal of the lookup table, decode the second address input signal to obtain second decoded data, and transmit the second decoded data to the second selector; The second selector is used to select and process the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

2. The FPGA lookup table circuit according to claim 1, characterized in that: The first decoder is specifically configured to perform an inversion operation on the first address input signal to obtain an inversion signal, and to arrange and combine the first address input signal and the inversion signal to obtain the first decoded data.

3. The FPGA lookup table circuit according to claim 1, characterized in that: The first selector is specifically configured to select the RAM multi-bit data corresponding to the input port based on the first decoded data, obtain the output multi-bit data, and transmit the output multi-bit data to the second selector.

4. The FPGA lookup table circuit according to claim 1, characterized in that: The second selector is specifically used to select the output multi-bit data corresponding to the input port based on the low-level data when one bit of the second decoded data is low-level data and the remaining bit data are all high-level data, so as to obtain the single-bit output data of the lookup table; wherein the single-bit data in the output multi-bit data corresponds one-to-one to the input port of the second selector.

5. The FPGA lookup table circuit according to claim 1, characterized in that: The first decoder and the second decoder both adopt 3-8 decoders.

6. The FPGA lookup table circuit according to claim 1, characterized in that: The first selector and the second selector both adopt one-hot code multiplexer.

7. The FPGA lookup table circuit according to claim 1, characterized in that: Also includes: The first buffer is connected to the input end of the first selector and is used for acquiring the RAM multi-bit data and inputting the RAM multi-bit data into the first selector.

8. The FPGA lookup table circuit according to claim 1, characterized in that: Also includes: The second buffer is connected to the output end of the second selector, and is used to obtain the single-bit output data of the lookup table and transmit the single-bit output data of the lookup table to the lookup table exit.

9. An FPGA, characterized in that: include: The FPGA lookup table circuit according to any one of claims 1 to 8.

10. A method for implementing an FPGA lookup table circuit, characterized in that: Applied to the FPGA lookup table circuit according to any one of claims 1 to 8, the method comprising: The first decoder obtains a first address input signal from the lookup table, decodes the first address input signal to obtain first decoded data, and transmits the first decoded data to the first selector; The first selector obtains RAM multi-bit data, selects and processes the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmits the output multi-bit data to the second selector; The second decoder obtains a second address input signal from the lookup table, decodes the second address input signal to obtain second decoded data, and transmits the second decoded data to the second selector; The second selector selects and processes the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

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