Time voltage conversion circuit with common-mode feedback function

Abstract

The invention discloses a time voltage conversion circuit with a common-mode feedback function. The time voltage conversion circuit comprises a time voltage conversion circuit part and a common-mode detection and control circuit part. And the time-voltage conversion circuit converts the input time margin into voltage margin and completes the whole circuit conversion work. After multiple times of conversion, the common-mode voltage approaches the reference common-mode voltage, and finally the functions of time-voltage conversion and output common-mode matching are achieved. Firstly, a first part time-voltage conversion circuit converts a time signal into a voltage signal, and the circuit controls the discharge time of an output capacitor through the input time signal; and in the second part, after the output voltage is generated, the common-mode detection and control circuit adjusts the delay of the delay unit according to the current output voltage common mode, and after multiple times of conversion, the output common-mode voltage converted by the time voltage approaches the reference common-mode voltage. Therefore, the conversion from the time domain signal to the voltage domain signal is completed, and the purpose that the output common-mode voltage is matched with the next-stage voltage domain ADC is achieved.

Description

Technical Field

[0001] The present invention relates to a time-to-voltage conversion circuit with a common-mode feedback function, belonging to the field of data converters. Background Art

[0002] With the progress of integrated circuit technology, digital signal processing has gradually replaced analog signal processing and become the mainstream means of signal processing. In nature, the signals that people can sense are often continuously changing analog signals. Therefore, an analog-to-digital converter (ADC) is needed as a bridge between analog signals and digital signals to achieve the efficient processing of analog signals by a digital signal processing system. In recent years, with the improvement of various indicators and requirements, high-speed, medium-high-precision, and low-power analog-to-digital converters have gradually become a research hotspot. As the feature size and supply voltage decrease, the circuit delay becomes shorter, which is beneficial to the improvement of the time-domain quantization resolution and conversion speed. In addition, the time-domain quantization circuit is basically composed of digital circuits, so it can achieve lower power consumption and a compact area. Given the above advantages, the time-domain quantization technology is integrated into the traditional voltage-domain ADC. For time signals, there is a lower limit for the edge jitter caused by noise, which limits the time-domain quantization accuracy. Therefore, in the hybrid quantization technology, to further improve the quantization accuracy of time signals, a time-to-voltage converter is used as a key module to convert and amplify the time margin into a voltage margin and continue quantization in the voltage domain. In the hybrid quantization structure, the time-to-voltage conversion circuit, which plays an intermediate conversion role, is particularly important and needs to balance linearity and speed to ensure the mutual matching of time and voltage.

[0003] Currently, the basic working principle of the time-to-voltage conversion circuit is as follows: for a time signal, the time information therein is represented as the time difference between two rising edges. First, a fully charged capacitor is discharged by a constant current source, and at this time, a ramp voltage is obtained on the upper plate of the capacitor. When the rising edge of the time signal arrives, the two signals respectively control their respective capacitors to terminate the discharge. Since the stopping discharge times are different, the voltages on the upper plates of the two capacitors are also different, thus completing the conversion from time to voltage. By controlling the capacitance value of the capacitor and the magnitude of the discharge current, different conversion gains can be achieved, and the output common-mode voltage is determined by the time difference between the starting time point of the discharge and the rising edge of the input time signal.

[0004] For traditional structures, in order to match the input common-mode voltage of the subsequent-stage voltage-domain ADC, it is necessary to use a delay unit to control the time difference between the rising edge of the discharge start signal and the rising edge of the time signal to avoid incorrect quantization by the subsequent-stage ADC. However, due to process manufacturing, supply voltage, and temperature deviations, the delay of the delay unit in each chip is inconsistent. Therefore, it is necessary to manually adjust the delay to match the common-mode voltage, which not only increases the difficulty of circuit use but also deteriorates the stability of the time-voltage conversion circuit in practical applications. The present invention can overcome the deficiencies of the prior art and further improve the performance of the time-voltage conversion circuit. Summary of the Invention

[0005] The present invention proposes a new output common-mode voltage regulation method for the time-voltage converter, and completes the regulation of the output common-mode voltage in a simpler and more stable manner. The overall circuit of the present invention is divided into two parts. First, the first part, the time-voltage conversion circuit, converts the time signal into a voltage signal. This circuit controls the discharge time of the output capacitor through the input time signal, thereby generating a corresponding voltage signal on the upper plate of the output capacitor. The second part is that after the output voltage is generated, the common-mode detection and control circuit adjusts the delay of the delay unit according to the current output voltage common-mode. After multiple conversions, the output common-mode voltage of the time-voltage conversion approaches the reference common-mode voltage, that is, the input common-mode voltage of the subsequent-stage voltage-domain ADC. In this way, the conversion from the time-domain signal to the voltage-domain signal is completed, and the purpose of matching the output common-mode voltage with the subsequent-stage voltage-domain ADC is achieved.

[0006] The above object is achieved by the following technical solutions:

[0007] A time-voltage conversion circuit with a common-mode feedback function includes two parts: a time-voltage conversion circuit and a common-mode detection and control circuit. It involves the conversion from the time domain to the voltage domain. The overall working process of the circuit is as follows: The time-voltage conversion circuit converts the input time margin into a voltage margin and completes the overall circuit conversion work; then the common-mode detection and control circuit controls the common-mode voltage of the next time-voltage conversion output through the current common-mode voltage position. After multiple conversions, the common-mode voltage will approach the reference common-mode voltage, and finally the functions of time-voltage conversion and output common-mode matching are realized.

[0008] The described time-voltage conversion circuit includes adjustable delay units DELAY1 and DELAY2, inverters INV1 and INV2, current sources Ib1 and Ib2, switches S1, S2, S3, S4, S5, S6, and capacitors C1 and C2. The input terminals of the adjustable delay units DELAY1 and DELAY2 are respectively connected to the time signals Tp and Tn, and the output terminals are respectively connected to the input terminals of the inverters INV1 and INV2; the output terminals of the inverters INV1 and INV2 are respectively connected to the control terminals of the switches S3 and S4; one ends of the switches S3 and S4 are respectively connected to the current inflow terminals of the current sources Ib1 and Ib2, and the other ends are respectively connected to one ends of the switches S2 and S5; one ends of the switches S2 and S5 are respectively connected to one ends of the switches S3 and S4, and the other ends are respectively connected to the upper plates of the capacitors C1 and C2, and are controlled by the time signals Tp and Tn; one ends of the switches S1 and S6 are respectively connected to the upper plates of the capacitors C1 and C2, and the other ends are both connected to the power supply, and are controlled by CLK; the lower plates of the capacitors C1 and C2 are both connected to the ground; the current outflow terminals of the current sources Ib1 and Ib2 are both connected to the ground.

[0009] The described common-mode detection and control circuit is composed of a common-mode detector, a feedback control circuit, a NOR gate NOR1, and a delay unit DELAY3. Among them, the enabling of the common-mode detector and the feedback control circuit is controlled by the signal CMFB_EN. The input terminal of the common-mode detector is connected to the upper plates of the capacitors C1 and C2, and the output is connected to the positive input terminal of the feedback control circuit; the negative input terminal of the feedback control circuit is connected to the reference common-mode voltage signal Vcm_ref, the clock input terminal of the feedback control circuit is connected to the output terminal of the delay unit DELAY3, and the output of the feedback control circuit is connected to the delay control terminals of the adjustable delay units DELAY1 and DELAY2; the inputs of the NOR gate NOR1 are respectively connected to the output terminals of the inverters INV1 and INV2, and the output is connected to the input terminal of the delay unit DELAY3. For the described time-voltage conversion circuit, the output terminals are respectively the upper plates Vop and Von of the capacitors C1 and C2.

[0010] Compared with the traditional structure, the present invention introduces a negative feedback technology in the time-voltage conversion circuit, which can automatically match the common-mode voltage of the time-voltage conversion circuit and the subsequent-stage voltage-domain ADC, reduce the circuit usage difficulty, improve the stability of the circuit operation, and ultimately improve the performance of the overall analog-to-digital conversion circuit. The present invention adds an enabling control to the common-mode feedback, and can turn off the common-mode feedback function after calibration, avoiding additional power consumption waste caused by the common-mode detection and control circuit. Description of the Drawings

[0011] Figure 1 is the circuit structure block diagram of the present invention.

[0012] Figure 2 It is the circuit principle block diagram of the present invention. Specific embodiments

[0013] A time-voltage conversion circuit with a common-mode feedback function. During a single clock cycle, there should be a certain correlation between the control clock CLK and the phases of the time signal inputs Tp and Tn. When CLK is at a high level, the rising edges of Tp and Tn appear and both lag behind the rising edge of CLK; when CLK is at a low level, Tp and Tn are also at a low level. In addition, in the said circuit, DELAY1 and DELAY2 are exactly the same, INV1 and INV2 are exactly the same, Ib1 and Ib2 are exactly the same, and C1 and C2 are exactly the same. For DELAY1 and DELAY2, their delay increases as the control code of the delay control terminal increases, and also decreases as the control code of the delay control terminal decreases.

[0014] The basic working principle of the present invention is as follows:

[0015] When CLK is at a low level, the circuit is in the reset stage. The switches S1 and S6 are turned on, and the switches S2 and S5 are turned off. At this time, the upper plates of the capacitors C1 and C2 are connected to the power supply, and the output voltages Vop and Von are reset to the power supply voltage. When CLK is at a high level, the circuit is in the time-voltage conversion stage. At this time, the switches S1 and S6 are turned off, and the switches S2, S3, S4, and S5 control the discharge of the capacitors C1 and C2 under the control of Tp, Tn, and Tp_B and Tn_B, and the discharge occurs. When the rising edges of Tp and Tn appear, the capacitors C2 and C1 start to discharge respectively; when the falling edges of Tp_B and Tn_B appear, the capacitors C1 and C2 stop discharging respectively. Let the time difference between the rising edges of Tp and Tn be tin, and the total delay of DELAY1 and INV1 be td. Then the discharge time of C1 is td - tin, and the discharge time of C2 is td + tin. Therefore, the discharge time difference between C1 and C2 is 2·tin. Since the discharge process is linear, the corresponding relationship between the output voltage difference and the discharge time difference is also linear. Finally, the circuit realizes the linear conversion from time to output voltage difference.

[0016] When CMFB_EN is at a low level, the feedback control circuit holds the output at the current code value, and at the same time the common-mode detector stops working, turning off the common-mode feedback function. When CMFB_EN is at a high level, the common-mode feedback function is enabled. Let the power supply voltage value be VDD, the current values of current sources Ib1 and Ib2 be I, and the capacitance values of capacitors C1 and C2 be C. It can be derived that the output common-mode voltage is VDD - I·td / C. Therefore, the output common-mode voltage can be changed by changing the delays of DELAY1 and DELAY2. Within a single clock cycle, when CLK is at a high level and the time-voltage conversion has been completed, the common-mode detector generates the output common-mode voltage Vcm_out of this conversion based on Von and Vop. Then the feedback control circuit compares Vcm_out with the reference common-mode voltage Vcm_ref (i.e., the common-mode voltage of the subsequent voltage-domain ADC). If Vcm_out is less than Vcm_ref, at the rising edge of CLK_CNT, the feedback control circuit decrements the output delay control code Ddly by 1, reducing the delays of DELAY1 and DELAY2 and increasing the output common-mode voltage of the next conversion. If Vcm_out is greater than Vcm_ref, at the rising edge of CLK_CNT, the feedback control circuit increments the output delay control code Ddly by 1, increasing the delays of DELAY1 and DELAY2 and decreasing the output common-mode voltage of the next conversion. After multiple conversion cycles, the output common-mode voltage will gradually stabilize around Vcm_ref, automatically matching the output common-mode voltage with the subsequent voltage-domain ADC, avoiding manual adjustment and improving the robustness of the circuit.

[0017] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those skilled in the art within the scope of the essence of the present invention should also fall within the protection scope of the present invention.

Claims

1. A time-to-voltage conversion circuit with common-mode feedback function, characterized in that: include: The circuit consists of two parts: a time voltage conversion circuit and a common mode detection and control circuit. The time voltage conversion circuit converts the input time margin into a voltage margin and completes the overall circuit conversion. Then the common mode detection and control circuit controls the common mode voltage output by the next time voltage conversion through the current common mode voltage position. After multiple conversions, the common mode voltage will approach the reference common mode voltage, and finally realize the function of time voltage conversion and output common mode matching.

2. The time-to-voltage conversion circuit with common-mode feedback function according to claim 1, characterized in that: The time-to-voltage conversion circuit comprises adjustable delay units DELAY1 and DELAY2, inverters INV1 and INV2, current sources Ib1 and Ib2, switches S1, S2, S3, S4, S5, S6, and capacitors C1 and C2; the input ends of the adjustable delay units DELAY1 and DELAY2 are respectively connected to the time signals Tp and Tn, and the output ends are respectively connected to the input ends of the inverters INV1 and INV2; the output ends of the inverters INV1 and INV2 are respectively connected to the control ends of the switches S3 and S4; the control ends of the switches S3 and S4 are respectively connected to the control ends of the switches S3 and S4. One end of each of the switches is connected to the current inflow end of the current sources Ib1 and Ib2, and the other end is connected to one end of each of the switches S2 and S5. One end of each of the switches S2 and S5 is connected to one end of each of the switches S3 and S4, and the other end is connected to the upper plates of the capacitors C1 and C2, respectively, and is controlled by the time signals Tp and Tn. One end of each of the switches S1 and S6 is connected to the upper plates of the capacitors C1 and C2, and the other end is connected to the power supply, and is controlled by CLK. The lower plates of the capacitors C1 and C2 are connected to the ground. The current outflow ends of the current sources Ib1 and Ib2 are connected to the ground.

3. The time-to-voltage conversion circuit with common-mode feedback function according to claim 1, characterized in that: The common mode detection and control circuit is composed of a common mode detector, a feedback control circuit, a NOR gate NOR1 and a delay unit DELAY3, wherein the enable of the common mode detector and the feedback control circuit is controlled by a signal CMFB_EN; the input end of the common mode detector is connected to the upper plates of capacitors C1 and C2, and the output is connected to the positive input end of the feedback control circuit; the negative input end of the feedback control circuit is connected to a reference common mode voltage signal Vcm_ref, the clock input end of the feedback control circuit is connected to the output end of the delay unit DELAY3, and the output of the feedback control circuit is connected to the delay control end of the adjustable delay units DELAY1 and DELAY2; the input of the NOR gate NOR1 is respectively connected to the output ends of inverters INV1 and INV2, and the output is connected to the input of the delay unit DELAY3; for the time voltage conversion circuit, the output ends are the upper plates Vop and Von of capacitors C1 and C2 respectively.

4. The time-to-voltage conversion circuit with common-mode feedback function according to claim 1, characterized in that: In a single clock cycle, a certain correlation should be maintained between the phases of the control clock CLK and the time signal inputs Tp and Tn; when CLK is at a high level, the rising edges of Tp and Tn appear and lag behind the rising edge of CLK; when CLK is at a low level, Tp and Tn are also at a low level; in addition, in the circuit, DELAY1 is exactly the same as DELAY2, INV1 is exactly the same as INV2, Ib1 is exactly the same as Ib2, and C1 is exactly the same as C2; for DELAY1 and DELAY2, their delay increases with the increase of the control code of the delay control end, and decreases with the decrease of the control code of the delay control end.

5. The time-to-voltage conversion circuit with common-mode feedback function according to claim 1, characterized in that: When CLK is at a low level, the circuit is in a reset stage, the switches S1 and S6 are turned on, and the switches S2 and S5 are turned off. At this time, the upper plates of the capacitors C1 and C2 are connected to the power supply, and the output voltages Vop and Von are reset to the power supply voltage; when CLK is at a high level, the circuit is in a time-voltage conversion stage, at this time, the switches S1 and S6 are turned off, and the switches S2, S3, S4, and S5 control the discharge of the capacitors C1 and C2 under the control of Tp, Tn, Tp_B, and Tn_B, and discharge; when the rising edges of Tp and Tn appear, the capacitors C1 and C2 are turned off. Capacitors C2 and C1 start to discharge respectively; when the falling edges of Tp_B and Tn_B appear, capacitors C1 and C2 stop discharging respectively; let the time difference between the rising edges of Tp and Tn be tin, and the total delay of DELAY1 and INV1 be td, then the discharge time of C1 is td-tin, the discharge time of C2 is td+tin, and the discharge time difference between C1 and C2 is 2·tin; since the discharge process is linear, the corresponding relationship between the output voltage difference and the discharge time difference is also linear; finally, the circuit realizes the linear conversion from time to output voltage difference.

6. The time-to-voltage conversion circuit with common-mode feedback function according to claim 1, characterized in that: When CMFB_EN is low, the feedback control circuit keeps the output at the current code value, and the common-mode detector stops working, turning off the common-mode feedback function; when CMFB_EN is high, the common-mode feedback function is turned on; let the power supply voltage be VDD, the current value of the current source Ib1 and Ib2 be I, and the capacitance of the capacitor C1 and C2 be C, and the output common-mode voltage is derived to be VDD-I·td / C, and the output common-mode voltage is changed by changing the delay of DELAY1 and DELAY2; in a single clock cycle, when CLK is high and the time voltage conversion has been completed, the common-mode detector generates the output common-mode voltage Vcm_out of this conversion according to Von and Vop, and then the feedback control circuit compares Vcm_out with the reference common-mode voltage Vcm _ref comparison; if Vcm_out is less than Vcm_ref, then when the rising edge of CLK_CNT arrives, the feedback control circuit will reduce the output delay control code Ddly by 1, and the delays of DELAY1 and DELAY2 will be reduced, thereby increasing the output common-mode voltage for the next conversion; if Vcm_out is greater than Vcm_ref, then when the rising edge of CLK_CNT arrives, the feedback control circuit will increase the output delay control code Ddly by 1, and the delays of DELAY1 and DELAY2 will be increased, thereby reducing the output common-mode voltage for the next conversion; after multiple conversion cycles, the output common-mode voltage will gradually stabilize around Vcm_ref, so that the output common-mode voltage automatically matches the next-level voltage domain ADC, avoiding manual adjustment while improving the robustness of the circuit.

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