Dynamic device matching apparatus and method for high precision digital-to-analog converter

Abstract

The present disclosure relates to the technical field of integrated circuit design, and discloses a dynamic device matching device and method suitable for high-precision digital-to-analog converters. The device comprises a pointer updating unit configured to receive an input signal; a pointer ending position determining unit configured to determine an ending position of a pointer according to the input signal and a starting position of the pointer; and n DAC control units respectively connected to the pointer updating unit; each DAC control unit comprises a comparison unit, a sorting storage unit, and a sorting updating unit; the sorting storage unit is configured to store a current sorting sequence number of the DAC control unit; the comparison unit is configured to compare the current sorting sequence number with target sorting sequence numbers indicated by the starting position and the ending position respectively; an output signal of the DAC control unit is determined based on a comparison result; and the sorting updating unit is configured to update the current sorting sequence number based on the comparison result, so that the DAC control unit is selected later when receiving the input signal next time in the case that the DAC control unit is selected this time. The device can improve the shaping capability and reduce the hardware implementation complexity.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and in particular to a dynamic device matching device and method suitable for high-precision digital-to-analog converters. Background Technology

[0002] The selection logic circuit of a digital-to-analog converter (DAC) is a type of digital logic circuit. Its core function is to generate multiple 0 or 1 control signals based on the input multi-bit digital signal, ensuring that the sum of these signals equals the value of the input signal, thereby controlling the output of the multiplexed feedback DAC. Specifically, the output of each DAC's selection logic circuit contains two states: 0 or 1. When a digital value is input to the selection logic circuit, it selects a corresponding number of circuits to output 1, while the rest output 0, thus achieving high-precision digital-to-analog conversion. For example, if the input is 3, three selection logic circuits will output 1, and the rest will output 0; the sum of these 1s equals the input value of 3.

[0003] DAC selection logic circuits are commonly used in multi-feedback DACs of high-precision oversampling analog-to-digital converters (ADCs) to achieve the ADC conversion function. In actual circuit design, there is a deviation between the actual output value and the design value of each DAC (device mismatch error). Therefore, the output signals of multiple DACs deviate from the design values, which leads to a significant decrease in the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the ADC conversion. To avoid this problem, device mismatch error is generally reduced by calibrating or optimizing the selection logic circuit.

[0004] Dynamic Element Matching (DEM) is a technique that uses selection logic circuits to address the issue of device mismatch errors in oversampling ADCs, which affect in-band SNDR and SFDR. Specifically, DEM technology can shape and suppress in-band mismatch errors by controlling the selection order of DACs with the same output weight.

[0005] Traditional dynamic device matching techniques include the following:

[0006] The first type is Data Weighted Averaging (DWA), a common dynamic device matching technique. It controls the selection order of DACs, selecting each DAC sequentially to ensure that each DAC is selected an equal number of times. This can achieve first-order error shaping of device mismatch errors in the DAC and reduce the impact of mismatch errors within the signal band.

[0007] However, DWA technology has the problem of weak shaping capability and introduces high-order harmonic distortion under small signal conditions. Therefore, in high-precision ADC applications, the mismatch error of the DAC control unit using DWA is still the main factor limiting the SNDR and SFDR of the ADC.

[0008] The second type is high-order dynamic device matching technology. It can achieve high-order device mismatch error shaping through complex vector quantization logic circuits. Its DAC selection order has the characteristics of first-in-last-out selection. While ensuring that the number of selections of each DAC is balanced, it gives the DACs that were selected earlier a lower selection priority. The DACs that were selected later in the previous selection order are selected first. This makes the randomness stronger, does not produce high-order harmonic distortion, and has a stronger ability to shape and suppress mismatch errors.

[0009] However, the logic implementation of high-order dynamic device matching technology is extremely complex. For the same number of DACs, the hardware overhead of high-order dynamic device matching technology is tens to hundreds of times that of DWA. Therefore, its application in high-precision oversampling ADCs is not widespread. Summary of the Invention

[0010] In view of this, this disclosure proposes a dynamic device matching device and method suitable for high-precision digital-to-analog converters, which can solve the problems of poor shaping capability of traditional DWA circuits and signal harmonic distortion under low signal input, as well as the problem that the logic implementation design of traditional high-order dynamic device matching technology is too complicated, resulting in large power consumption and area in practical applications, making it unsuitable for industrial products.

[0011] According to one aspect of this disclosure, a dynamic device matching device suitable for high-precision digital-to-analog converters is provided, the device comprising:

[0012] The pointer update unit is configured to: receive an input signal; determine the end position of the pointer based on the input signal and a pre-stored pointer start position; the start position and the end position are used to indicate the target sorting sequence number of the selected DAC control unit;

[0013] There are n DAC control units, each connected to the pointer update unit; each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit; where n is an integer greater than 1.

[0014] The sorting storage unit is used to: store the current sorting sequence number of the DAC control unit, which indicates the sorting order of the DAC control unit among n DAC control units;

[0015] The comparison unit is configured to: compare the current sorting number with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; and determine the output signal of the DAC control unit based on the comparison result.

[0016] The sorting update unit is used to update the current sorting number based on the comparison result, so that if the DAC control unit is selected this time, it will be selected later when the input signal is received next time.

[0017] In one possible implementation, the pointer update unit is further configured to: determine whether the summation result of the input signal and the starting position overflows; if overflow occurs, subtract n from the summation result to obtain the ending position;

[0018] Accordingly,

[0019] The comparison unit is used to: determine the output signal of the DAC control unit based on the comparison result and the determination result of whether overflow occurs;

[0020] The sorting update unit is used to update the current sorting number based on the comparison result and the determination result of whether overflow occurs.

[0021] In one possible implementation, the sorting update unit is used for:

[0022] If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is subtracted from the target sorting number indicated by the starting position to obtain the updated sorting number.

[0023] If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit remains unchanged.

[0024] If the summation result does not overflow, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to the value indicated by the input signal to obtain the updated sorting number.

[0025] If the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to n and the target sorting number indicated by the starting position is subtracted to obtain the updated sorting number.

[0026] In the event that the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit remains unchanged.

[0027] If the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to the value indicated by the input signal minus the difference obtained by n, to obtain the updated sorting number.

[0028] In one possible implementation, the sorting update unit includes: a first adder, a first data selector and a first register respectively connected to the input of the first adder, and a second data selector and a third data selector respectively connected to the first data selector; the output of the first adder is connected to the input of the first register.

[0029] The first register is used to store the current sorting sequence number;

[0030] The first data selector is configured to connect to the second data selector via a first input terminal when the summation result overflows, and to connect to the third data selector via a second input terminal when the summation result does not overflow.

[0031] The second data selector includes a first data input terminal, a second data input terminal, and a third data input terminal; the first data input terminal is used to input the difference between the value indicated by the input signal and n into the second data selector; the second data input terminal is used to input the difference between n and the target sorting number indicated by the starting position into the second data selector; the third data input terminal is used to input 0 into the second data selector.

[0032] The third data selector includes a fourth data input terminal, a fifth data input terminal, and a sixth data input terminal; the fourth data input terminal is used to input 0 to the second data selector; the fifth data input terminal is used to input the negative value of the target sorting number indicated by the starting position to the second data selector; and the sixth data input terminal is used to input the value indicated by the input signal to the second data selector.

[0033] In one possible implementation, the comparison unit is configured to:

[0034] If the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the output signal is determined to be 1;

[0035] or,

[0036] If the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 1;

[0037] or,

[0038] If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 1.

[0039] In one possible implementation, the first output of the pointer update unit outputs 1 when the summation result overflows, and outputs 0 when the summation result does not overflow; accordingly,

[0040] The comparison unit includes a first comparator, a second comparator, and an XOR unit;

[0041] The first comparator is configured to output 1 if the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and output 0 if the current sorting number is less than the target sorting number indicated by the starting position.

[0042] The second comparator is configured to output 1 if the current sorting number is greater than or equal to the target sorting number indicated by the end position, and output 0 if the current sorting number is less than the target sorting number indicated by the end position.

[0043] The XOR is connected to the first comparator, the second comparator, and the first output terminal respectively; the XOR is used to output 0 or 1 based on the first comparison result, the second comparison result, and the determination result output by the first output terminal.

[0044] In one possible implementation, the pointer update unit includes a second adder and a second register;

[0045] The second register is used to store the starting position of the pointer;

[0046] The second adder includes a signal input terminal and a pointer input terminal. The signal input terminal is used to input the input signal into the second adder. The pointer input terminal is connected to the output terminal of the second register to input the starting position stored in the second register into the second adder. The second adder also includes a first output terminal and a second output terminal. The first output terminal is used to output a determination result of whether overflow has occurred. The second output terminal is used to output the ending position.

[0047] In one possible implementation, the second output terminal is connected to the input terminal of the second register to store the end position, so that when the input signal is received again, the end position is used as the starting position of the pointer corresponding to the next input signal to determine the end position of the pointer corresponding to the next input signal.

[0048] In one possible implementation, each DAC control unit further includes a reset unit for updating the current sorting sequence number stored in the sorting storage unit to a preset value upon receiving a reset signal. The preset value is different for different DAC control units.

[0049] According to another aspect of this disclosure, a dynamic device matching method suitable for high-precision digital-to-analog converters is provided, the method comprising:

[0050] Receive input signals;

[0051] The end position of the pointer is determined based on the input signal and the pre-stored start position of the pointer; the start position and the end position are used to indicate the target sorting sequence number of the selected DAC control unit;

[0052] For each DAC control unit, the current sorting number corresponding to the DAC control unit is compared with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; wherein, the current sorting number is used to indicate the sorting order of the DAC control unit among the n DAC control units;

[0053] The output signal of the DAC control unit is determined based on the comparison result, and the current sorting number is updated so that if the DAC control unit is selected this time, it will be selected later when the next input signal is received.

[0054] A pointer update unit is configured to: receive input signals; determine the end position of the pointer based on the input signals and the pre-stored start position of the pointer; and n DAC control units are connected to the pointer update unit respectively; each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit; the sorting storage unit is configured to: store the current sorting sequence number of the DAC control unit, which indicates the sorting order of the DAC control unit among the n DAC control units; the comparison unit is configured to: compare the current sorting sequence number with the target sorting sequence number indicated by the start position and the target sorting sequence number indicated by the end position respectively, and obtain the comparison result; determine the output signal of the DAC control unit based on the comparison result; the sorting update unit is configured to update the current sorting sequence number based on the comparison result, so as to update the DAC control unit output signal. If a control unit is selected this time, its selection will be delayed when the next input signal is received. On the one hand, compared with traditional digital weighted averaging circuits, this dynamic device matching device adopts a last-in-first-out design, making the selection result of the DAC control unit similar to that of the high-order DEM. Therefore, its shaping capability is similar to that of the high-order DEM, with strong shaping capability and extremely strong harmonic suppression capability, which can solve the problem of poor shaping capability of traditional data weighted averaging circuits. On the other hand, compared with high-order DEMs, the sorting update unit of this dynamic device matching device can directly operate on the current sorting number of each DAC control unit, without the need for the complex digital filtering circuits and comparison sorting circuits in traditional high-order DEMs. Therefore, the hardware implementation complexity is low, which can solve the problem that the logic circuit implementation of high-order DEMs is complex and cannot be widely used.

[0055] In addition, the dynamic device matching device provided in this application can be used in high-precision oversampling ADC and DAC control unit products. This solution has extremely low power consumption and area overhead, and the digital logic of this solution has good process compatibility. Under advanced processes, its power consumption and area advantages will be further improved. Therefore, it can be easily integrated into the ADC and DAC control unit module to help the ADC and DAC control unit achieve the requirements of low power consumption and high linearity under advanced processes, and further improve the versatility of the dynamic device matching device.

[0056] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0057] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0058] Figure 1 A block diagram of a dynamic device matching apparatus for a high-precision digital-to-analog converter according to an embodiment of the present disclosure is shown;

[0059] Figure 2 A schematic diagram of the logic circuit implementation of a dynamic device matching device for a high-precision digital-to-analog converter according to an embodiment of the present disclosure is shown.

[0060] Figure 3 A schematic diagram of a dynamic device matching device for selecting a DAC control unit for a high-precision digital-to-analog converter according to an embodiment of the present disclosure is shown.

[0061] Figure 4 A schematic diagram is shown illustrating the updating of the current sorting number of a DAC control unit by a dynamic device matching apparatus for a high-precision digital-to-analog converter according to an embodiment of the present disclosure;

[0062] Figure 5 A schematic diagram illustrating the updating of the current sorting number of a DAC control unit by a dynamic device matching apparatus for a high-precision digital-to-analog converter according to another embodiment of the present disclosure;

[0063] Figure 6 A schematic diagram is shown of a dynamic device matching apparatus for a high-precision digital-to-analog converter according to an embodiment of the present disclosure, which selects a DAC control unit and updates the current sorting number of the DAC control unit.

[0064] Figure 7 A schematic diagram illustrating the selection results of the present application, digital weighted averaging circuit, and second-order DEM according to an embodiment of the present disclosure;

[0065] Figure 8 A schematic diagram showing a comparison of the output spectrum of the shaping mismatch error of the present application, the digital weighted averaging circuit, and the second-order DEM according to an embodiment of the present disclosure;

[0066] Figure 9 A flowchart is shown for a dynamic device matching method for a high-precision digital-to-analog converter according to an embodiment of the present disclosure. Detailed Implementation

[0067] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0068] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0069] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0070] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0071] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0072] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0073] Figure 1 A block diagram of a dynamic device matching apparatus for a high-precision digital-to-analog converter according to an embodiment of the present disclosure is shown. The dynamic device matching apparatus for selecting the DAC includes the following:

[0074] 1. The number of DACs selected from all DACs is the same as the magnitude of the input signal. The selected DACs output 1, and the unselected DACs output 0.

[0075] 2. For different DACs, if the number of times a DAC has been selected is different, the DAC with fewer selections is prioritized; if the number of times a DAC has been selected is the same, the DAC that was selected later in the selection process is prioritized, i.e., it has a last-in-first-out (LIFO) selection characteristic. In this way, the idea of ​​variable DAC selection priority can reduce the output nonlinearity caused by DAC device mismatch error.

[0076] Based on the above selection criteria, such as Figure 1As shown, the device includes a pointer update unit 110 and n DAC control units 120. Here, n is an integer greater than 1. For example, n is a multiple of 2.

[0077] The pointer update unit 110 is used to update the position of the pointer, which indicates the sorting sequence number of the currently selected DAC control unit 120. In this embodiment, each of the n DAC control units 120 corresponds to a sorting sequence number, and different DAC control units 120 correspond to different sorting sequence numbers. The pointer moves sequentially according to the sorting sequence number. For example, if there are 8 DAC control units 120, and the sorting sequence numbers of the 8 DAC control units 120 are 0 to 7, then the pointer can move sequentially from 0 to 7. After reaching 7, it can return to 0 and move sequentially again.

[0078] In one example, the pointer update unit 110 is used to: receive an input signal; and determine the end position of the pointer based on the input signal and the pre-stored start position of the pointer. The start and end positions are used to indicate the target sorting sequence number of the selected DAC control unit.

[0079] The input signal is used to indicate the number of DAC control units that output 1 this time; that is, the value of the input signal is less than or equal to n.

[0080] For example, the pointer update unit 110 sums the input signal and the starting position of the pointer to obtain the ending position of the pointer. Accordingly, the pointer update unit 110 is also configured to: determine whether the summation result of the input signal and the starting position overflows; if overflow occurs, subtract n from the summation result to obtain the ending position.

[0081] Overflow occurs when the summation result exceeds the maximum sort index. In this case, the pointer needs to return to the first sort index (e.g., return to 0) and start moving sequentially again.

[0082] Taking the example of 8 DAC control units 120 with corresponding sequence numbers 0 to 7, if the sum of the starting position of the pointer and the input signal is greater than 7, for example, the sum is 10, then 8 needs to be subtracted from the sum, and the ending position is 10-8=2.

[0083] For example, refer to Figure 2 The schematic diagram shown illustrates the logic circuit implementation of the dynamic device matching device. This logic circuit is similar to a digital weighted average algorithm, using a pointer that continuously updates the integral input signal to store the number of DAC control units 120 that have been selected and output 1 in each round of selection. For example... Figure 2 As shown, the pointer update unit 110 includes a second adder 210 and a second register 220.

[0084] The second register 220 is used to store the starting position of the pointer.

[0085] The second adder 210 includes a signal input terminal and a pointer input terminal. The signal input terminal is used to input the aforementioned input signal D into the second adder 210. in The pointer input terminal is connected to the output terminal (i.e., data output pin Q) of the second register 220 to input the starting position PT stored in the second register 220 into the second adder 210.

[0086] The second adder 210 further includes a first output terminal and a second output terminal. The first output terminal is used to output the result C0 indicating whether overflow has occurred; the second output terminal is used to output the end position PTN.

[0087] Optionally, the second output terminal is connected to the input terminal (i.e., data input pin D) of the second register 220 to store the end position. This end position is used as the starting position of the pointer corresponding to the next input signal when the next input signal is received, thus determining the end position of the pointer corresponding to the next input signal. That is, when the next input signal is received, the data received at pin D is latched to pin Q to determine the end position of the pointer corresponding to the next input signal.

[0088] In other embodiments, the pointer update unit 110 may further include a third register for storing the end position and storing the end position in the second register 220 the next time an input signal is received.

[0089] Optionally, the number of bits in the second register 220 and the second adder 210 is determined based on the value of n. For example, the number of bits in the second register 220 and the second adder 210 is m, 2^n. m =n.

[0090] Optionally, the second register 220 also includes a clock synchronization pin CLK to ensure operational synchronization between the various units in the dynamic device matching device.

[0091] n DAC control units 120 are each connected to the pointer update unit 110 to receive the input signal D received by the pointer update unit 110. in The pointer update unit 110 stores the starting position PT, the ending position PTN of the output of the second adder 210, and the overflow determination result C0 in the second register 220.

[0092] Each DAC control unit 120 internally contains a finite state machine. That is, the DAC control unit 120 can update its sorting order based on each output result, thereby implementing a last-in-first-out (LIFO) DAC control unit selection logic. The LIFO DAC control unit selection logic means that the DAC control unit 120 that was selected later in the previous selection process is selected first.

[0093] For example, the finite state machine in each DAC control unit 120 includes: a comparison unit 121, a sorting storage unit 122, and a sorting update unit 123.

[0094] The sorting storage unit 122 is used to store the current sorting sequence number of the DAC control unit 120, which is used to indicate the sorting order of the DAC control unit 120 among the n DAC control units 120.

[0095] The comparison unit 121 is used to: compare the current sorting number with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; and determine the output signal of the DAC control unit 120 based on the comparison result.

[0096] Optionally, the output of each DAC control unit 120 is used to connect to one DAC. In this case, the output signal (i.e., digital signal) of the DAC control unit 120 is used to control the output of the corresponding DAC, thereby selecting the DAC by selecting the DAC control unit 120. For example, if the DAC control unit 120 outputs 1 to the DAC connected to it, it indicates that the DAC is selected; if the DAC control unit 120 outputs 0 to the DAC connected to it, it indicates that the DAC is not selected.

[0097] If the summation result of the starting position and the input signal does not overflow, and the current sorting number is between the target sorting number indicated by the starting position and the target sorting number indicated by the ending position (for example, between the target sorting number indicated by the starting position and the target sorting number indicated by the position before the ending position), then the current sorting number indicates that the DAC control unit 120 selected by the pointer needs to output 1 this time, and the output signal is 1 accordingly; if the current sorting number exceeds the range between the target sorting number indicated by the starting position and the target sorting number indicated by the ending position, then the current sorting number indicates that the DAC control unit 120 selected by the pointer needs to output 1 this time, and the output signal is 0 accordingly.

[0098] For example: Reference Figure 3Assuming n = 8, the current sorting numbers Rank1 to Rank8 stored in each DAC control unit 120, namely E1 to E8, are 4, 5, 0, 1, 2, 3, 6, and 7, respectively. If the pointer moves sequentially according to the sorting numbers from smallest to largest, then based on the different current sorting numbers stored in the 8 DAC control units 120, Rank1 to Rank8 of the 8 DAC control units 120 can be arranged into a selection sequence from left to right. If the starting position PT stored in the second register 220 is 0, then when the input signal is 4, it means that 4 DAC control units 120 need to be selected. The pointer needs to move 4 times from the starting position, that is, the pointer moves from 0 to 4. The DAC control units 120s with current sorting numbers of 0, 1, 2, and 3 (i.e., E3, E4, E5, and E6) are selected and need to output 1. In this example, we will use the example of setting the sorting number starting from 0 and moving the pointer in ascending order of the sorting number. In actual implementation, the sorting number of the DAC control unit 120 can also be set starting from 1, and the pointer can move in descending order of the sorting number. The specific implementation principle is the same. When updating the sorting number, we can make adaptive adjustments according to the last-in-first-out selection principle.

[0099] If the sum of the starting position and the input signal overflows, and the ending position is before the starting position, then the sorting sequence number between the ending position and the starting position is no longer the target sorting sequence number. In this case, the comparison unit 121 also needs to combine the overflow determination result to determine the output signal. That is, the comparison unit 121 is used to: determine the output signal of the DAC control unit 120 based on the comparison result and the overflow determination result.

[0100] For example, the comparison unit 121 is configured to: determine that the output signal is 1 when the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the start position, and the current sorting number is greater than or equal to the target sorting number indicated by the end position; or, determine that the output signal is 1 when the summation result overflows, the current sorting number is less than the target sorting number indicated by the start position, and the current sorting number is less than the target sorting number indicated by the end position; or, determine that the output signal is 1 when the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the start position, and the current sorting number is less than the target sorting number indicated by the end position.

[0101] Accordingly, if the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the output signal is determined to be 0; or, if the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the output signal is determined to be 0; or, if the summation result does not overflow, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 0.

[0102] To implement the comparison logic of the comparison unit 121 mentioned above, refer to Figure 2 The schematic diagram shown illustrates the logic circuit implementation of the dynamic device matching device. It is assumed that when the summation result overflows, the first output of the pointer update unit 110 outputs 1, and when the summation result does not overflow, the first output of the pointer update unit 110 outputs 0. Figure 2 As shown, the comparison unit 121 includes a first comparator 1211, a second comparator 1212, and an XOR unit 1213.

[0103] The first comparator 1211 includes two input terminals and one output terminal. The two input terminals of the first comparator 1211 respectively input the current sorting number (Rank) of the DAC control unit 120. i And the starting position PT, to compare the current sort number Rank i Whether it is greater than the target sorting number indicated by the starting position PT. The output of the first comparator 1211 is used to output the comparison result C1. The first comparator 1211 is used to: output 1, that is, C1 is 0, when the current sorting number is greater than or equal to the target sorting number indicated by the starting position; and output 0, that is, C1 is 0, when the current sorting number is less than the target sorting number indicated by the starting position.

[0104] The second comparator 1212 includes two input terminals and one output terminal. The two input terminals of the second comparator 1212 respectively input the current sorting number (Rank) of the DAC control unit 120. i And the end position PTN, to compare the current sort number Rank. i Is it greater than the target sorting number indicated by the end position PTN? The output of the second comparator 1212 is used to output the comparison result C2. The second comparator 1212 is used to: output 1 (i.e., C2 is 1) when the current sorting number is greater than or equal to the target sorting number indicated by the end position; and output 0 (i.e., C2 is 0) when the current sorting number is less than the target sorting number indicated by the end position.

[0105] XOR 1213 is connected to the first comparator 1211, the second comparator 1212, and the first output terminal, respectively. XOR 1213 is used to output 0 or 1 based on the first comparison result C1, the second comparison result C2, and the determination result C0 output from the first output terminal.

[0106] According to the XOR calculation logic, when C0 = 1, C1 = 1, and C2 = 1 (i.e., the summation result overflows, the current sorting index is greater than or equal to the target sorting index indicated by the starting position, and the current sorting index is greater than or equal to the target sorting index indicated by the ending position), the XOR value SV is calculated. i The value is 1, which conforms to the comparison logic of the comparison unit 121 mentioned above.

[0107] When C0 = 1, C1 = 0, and C2 = 0, i.e., the summation result overflows, the current sorting index is less than the target sorting index indicated by the starting position, and the current sorting index is less than the target sorting index indicated by the ending position, the XOR value SV is... i The value is 1, which conforms to the comparison logic of the comparison unit 121 mentioned above.

[0108] When C0 = 0, C1 = 1, and C2 = 0, i.e., the summation result has not overflowed, the current sorting index is greater than or equal to the target sorting index indicated by the starting position, and the current sorting index is less than the target sorting index indicated by the ending position, the XOR value SV is... i The value is 1, which conforms to the comparison logic of the comparison unit 121 mentioned above.

[0109] It should be explained that, since there is no situation where the current sorting number is less than the target sorting number indicated by the starting position and greater than the target sorting number indicated by the ending position when the summation result does not overflow, and there is no situation where the current sorting number is less than the target sorting number indicated by the starting position and greater than or equal to the target sorting number indicated by the ending position when the summation result overflows, these two situations do not need to be considered when determining the output signal.

[0110] To ensure that each DAC control unit 120 meets the last-in-first-out selection logic after this selection, the current sorting sequence number currently stored in the DAC control unit 120 also needs to be updated so that it can be used when the input signal is received next time.

[0111] In this embodiment, the sorting update unit 123 is used to update the current sorting sequence number based on the comparison result, so that if the DAC control unit 120 is selected this time, it will be selected later when the next input signal is received. That is, the sorting update unit 123 makes the current sorting sequence number of the DAC control unit 120 conform to the last-in-first-out selection logic.

[0112] According to the Last-In-First-Out (LIFO) selection logic, if the sum of the starting position and the input signal does not overflow, in order to delay the selection of the DAC control unit 120 selected this time next time, the current sorting number of the DAC control unit 120 can be updated to the front of the sorting. That is, the current sorting number of the DAC control unit 120 is subtracted from the target sorting number indicated by the starting position. In this way, the pointer moves backward in sequence, which will delay the selection of the DAC control unit 120 selected this time.

[0113] For example: Reference Figure 4 Assuming n = 8, the current sorting numbers Rank1 to Rank8 stored in each DAC control unit 120 (E1 to E8) are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. If the pointer moves sequentially according to the sorting numbers from smallest to largest, and the starting position PT is 2, then when the input signal is 3, the pointer needs to move 3 times from the starting position PT, that is, from 2 to 5. The DAC control units 120s currently sorted as 2, 3, and 4 (i.e., E3, E4, and E5) are selected and need to output 1. At this time, subtracting PT from the current sorting number of E3, E4, and E5 will move them to the front of the sorting sequence.

[0114] If the sum of the starting position and the input signal overflows, the ending position PTN of the pointer will be before the starting position PT. In this case, the sorting sequence number of the selected DAC control units 120 may already be at the beginning of the sorting sequence. Therefore, it is not necessary to move the sorting sequence number of these DAC control units 120. That is, the sorting update unit 123 also needs to determine the output signal based on the overflow determination result. In other words, the sorting update unit 123 is used to update the current sorting sequence number based on the comparison result and the overflow determination result.

[0115] For example: Reference Figure 5 Assuming n = 8, the current sorting numbers (Rank1 to Rank8) stored in each DAC control unit 120 (E1 to E8) are 3, 4, 0, 1, 2, 5, 6, and 7, respectively. If the pointer moves sequentially according to the sorting number from smallest to largest, and the starting position PT is 5, then when the input signal is 4, the pointer needs to move 4 times from the starting position PT. At this point, the pointer overflows and needs to move from 5 to 7, then back to 0, and continue moving sequentially to 1. The DAC control units 120s currently sorted as 5, 6, 7, and 0 (i.e., E6, E7, E8, and E3) are selected and need to output 1. At this time, only the current sorting numbers of E6, E7, and E8 need to be subtracted from PT, while E3 remains unchanged. This ensures that the selected DAC control unit 120 will be selected later.

[0116] To implement the above update logic, the sorting update unit 123 is used for:

[0117] If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 is subtracted from the target sorting number indicated by the starting position to obtain the updated sorting number.

[0118] refer to Figure 4 The summation result does not overflow, and for E3, E4 and E5, the current sorting number is greater than or equal to the target sorting number indicated by the starting position and less than the target sorting number indicated by the ending position. That is, E3, E4 and E5 are the selected DAC control units 120. At this time, the current sorting number of the DAC control unit 120 minus PT can make the DAC control unit 120 be selected later next time.

[0119] If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 remains unchanged.

[0120] refer to Figure 4 If the summation result does not overflow, and for E6, E7, and E8, the current sorting number is greater than or equal to the target sorting number indicated by the starting position and greater than or equal to the target sorting number indicated by the ending position, that is, E6, E7, and E8 are not the selected DAC control unit 120. In this case, the DAC control unit 120 needs to be selected first in the next selection, and the current sorting number can remain unchanged.

[0121] If the summation result does not overflow, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 is added to the value indicated by the input signal to obtain the updated sorting number.

[0122] refer to Figure 4The summation result did not overflow, and for E1 and E2, the current sorting sequence number is less than the target sorting sequence number indicated by the start position and less than the target sorting sequence number indicated by the end position. That is, E1 and E2 are not the selected DAC control unit 120. In this case, the DAC control unit 120 needs to be selected first in the next selection. Since E1 and E2 are before the start position, while E6, E7, and E8 are after the start position, it means that E1 and E2 entered the sorting before E6, E7, and E8. In order to ensure the last-in-first-out logic, E1 and E2 need to be selected after E6, E7, and E8. That is, E1 and E2 need to be before E6, E7, and E8. At this time, the current sorting sequence number of E1 and E2 is added to the value indicated by the input signal.

[0123] If the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 is added to n and the target sorting number indicated by the starting position is subtracted to obtain the updated sorting number.

[0124] refer to Figure 5 The summation result overflows, and for E4, E5, E1, and E2, the current sorting number is less than the target sorting number indicated by the starting position and greater than or equal to the target sorting number indicated by the ending position. That is, E4, E5, E1, and E2 are not selected DAC control units 120. In this case, in the next selection, E4, E5, E1, and E2 need to be selected first, that is, E4, E5, E1, and E2 need to be after E3, E6, E7, and E8. At this time, the current sorting number of E4, E5, E1, and E2 is added to 8 and the target sorting number 5 indicated by the starting position PT is subtracted to obtain the updated sorting number of E4, E5, E1, and E2, that is, the current sorting number is increased by 3.

[0125] In the event that the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 remains unchanged.

[0126] refer to Figure 5 The summation result overflows, and for E3, the current sorting number is less than both the target sorting number indicated by the starting position and the target sorting number indicated by the ending position; that is, E3 is the selected DAC control unit 120. In this case, E3 needs to be deferred in the next selection. However, E3 is already at the front of the sort, so its current sorting number does not need to be changed to ensure that E3 is deferred in the next selection.

[0127] If the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit 120 is added to the difference obtained by subtracting n from the value indicated by the input signal to obtain the updated sorting number.

[0128] refer to Figure 5 The summation result overflows, and for E6, E7, and E8, the current sorting sequence number is greater than or equal to the target sorting sequence number indicated by the start position and greater than or equal to the target sorting sequence number indicated by the end position. That is, E6, E7, and E8 are the selected DAC control units 120. At this time, in the next selection, E6, E7, and E8 need to be delayed in selection. Therefore, the current sorting sequence number of E6, E7, and E8 is added to the value indicated by the input signal 4 and subtracted by 8 to obtain the updated sorting sequence number, that is, the current sorting sequence number of E6, E7, and E8 is subtracted by 4.

[0129] To implement the above update logic, refer to... Figure 2 The schematic diagram shown illustrates the logic circuit implementation of the dynamic device matching device. Those skilled in the art should understand that... Figure 2 The logic circuit structure shown is merely an example. Those skilled in the art can design sorting and updating units as needed, as long as they can implement the above-described updating logic. Figure 2 As shown, each DAC control unit 120's sorting update unit 123 includes: a first adder 1231, a first data selector 1232 and a first register 1233 respectively connected to the input terminal of the first adder 1231, and a second data selector 1234 and a third data selector 1235 respectively connected to the first data selector 1232; the output terminal of the first adder 1231 is connected to the input terminal D of the first register 1233.

[0130] The first register 1233 is used to store the current sorting sequence number of the DAC control unit 120.

[0131] The first data selector 1232 is used to connect to the second data selector 1234 through the first input terminal when the summation result overflows; and to connect to the third data selector 1235 through the second input terminal when the summation result does not overflow.

[0132] The first data selector 1232 is also connected to the first output of the second adder to receive the overflow determination result C0. When the first data selector 1232 receives C0 = 0, it is connected to the third data selector 1235 through the second input; when the first data selector 1232 receives C0 = 1, it is connected to the second data selector 1234 through the first input.

[0133] The second data selector 1234 includes: a first data input terminal, a second data input terminal, and a third data input terminal.

[0134] The second data selector 1234 is also connected to the first comparator and the second comparator to receive the comparison result C1 output by the output terminal of the first comparator and the comparison result C2 output by the output terminal of the second comparator.

[0135] When C1=1 and C2=1, the second data selector 1234 connects the first data input terminal and disconnects the second and third data input terminals; when C1=0 and C2=1, it connects the second data input terminal and disconnects the first and third data input terminals; when C1=0 and C2=0, it connects the third data input terminal and disconnects the first and second data input terminals.

[0136] The first data input terminal is used to input the value D indicated by the input signal to the second data selector 1234. in Subtract n( Figure 2 The difference obtained is 8). At this time, the first data input terminal and the first input terminal implement the update logic corresponding to C0=1, C1=1, C2=1.

[0137] The second data input terminal is used to input n(…) into the second data selector 1234. Figure 2 The difference between 8) and the target sorting number PT indicated by the starting position is then subtracted. At this time, the first data input terminal and the second data input terminal implement the update logic corresponding to C0=1, C1=0, and C2=1.

[0138] The third data input terminal is used to input 0 to the second data selector 1234. At this time, the first data input terminal and the third data input terminal implement the update logic corresponding to C0=1, C1=0, and C2=0.

[0139] The third data selector 1235 includes a fourth data input terminal, a fifth data input terminal, and a sixth data input terminal. The third data selector 1235 is also connected to a first comparator and a second comparator to receive the comparison result C1 output by the output terminal of the first comparator and the comparison result C2 output by the output terminal of the second comparator.

[0140] When C1=1 and C2=1, the third data selector 1235 connects the fourth data input terminal and disconnects the fifth and sixth data input terminals; when C1=1 and C2=0, it connects the fifth data input terminal and disconnects the fourth and sixth data input terminals; when C1=0 and C2=0, it connects the sixth data input terminal and disconnects the fourth and fifth data input terminals.

[0141] The fourth data input terminal is used to input 0 to the second data selector 1234. At this time, the second data input terminal and the fourth data input terminal implement the update logic corresponding to C0=0, C1=1, and C2=1.

[0142] The fifth data input terminal is used to input the negative value of the target sorting sequence number indicated by the starting position, i.e., -PT, into the second data selector 1234. At this time, the second data input terminal and the fifth data input terminal implement the update logic corresponding to C0=0, C1=1, and C2=0.

[0143] The sixth data input terminal is used to input the value D indicated by the input signal to the second data selector 1234. in At this point, the second and sixth data input terminals implement the update logic described above when C0 = 0, C1 = 0, and C2 = 0.

[0144] At this time, the first adder 1231 receives the current sorting sequence number output from the output terminal Q of the first register 1233, as well as the data selected by each data selector, and sums them to obtain the updated sorting sequence number. This updated sorting sequence number is then output to the input terminal D of the first register 1233. The first register 1233 is used to latch the data received at input terminal D to pin Q when it receives an input signal again, so as to update the current sorting sequence number.

[0145] Optionally, the number of bits in the first register 1233 and the first adder 1231 is determined based on the value of n. For example, the number of bits in the first register 1233 and the first adder 1231 is m, 2^n. m =n.

[0146] Optionally, the first register 1233 also includes a signal synchronization pin CLK to ensure operational synchronization between the various units in the dynamic device matching device.

[0147] In one possible implementation, each DAC control unit 120 further includes a reset unit, used to: update the current sorting sequence number stored in the sorting storage unit 122 to a preset value upon receiving a reset signal RST. The preset value is different for different DAC control units 120. For example, the preset value is the number of the DAC control unit 120 - 1, i.e., the preset value is i.

[0148] For example, refer to Figure 2The reset unit is a data selector 124. One input of the data selector 124 is connected to the output of the first adder, and the other input is connected to a preset value; its output is connected to the input D of the first register. The data selector is also connected to the input of a reset signal. If a reset signal RST is received, the other input of the data selector 124 is turned on. At this time, the reset unit inputs the preset value to the first register, thereby resetting the current sorting sequence number of the DAC control unit 120. If no reset signal RST is received, one input of the data selector is turned on. At this time, the reset unit inputs the output result of the first adder to the first register, thereby updating the current sorting sequence number of the DAC control unit 120.

[0149] It should be noted that, although... Figure 2 The logic circuit shown above is an example of a dynamic device matching device suitable for high-precision digital-to-analog converters, but those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly design logic circuits based on the dynamic device matching principle of the dynamic device matching device.

[0150] In summary, the dynamic device matching device for high-precision digital-to-analog converters provided in this embodiment includes a pointer update unit for: receiving an input signal; determining the end position of the pointer based on the input signal and a pre-stored pointer start position; and n DAC control units, each connected to the pointer update unit. Each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit. The sorting storage unit stores the current sorting number of the DAC control unit, which indicates the sorting order of the DAC control unit among the n DAC control units. The comparison unit compares the current sorting number with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; and determines the output signal of the DAC control unit based on the comparison result. The sorting update unit is used to determine the output signal of the DAC control unit based on the comparison result. The result updates the current sorting sequence number so that if the DAC control unit is selected this time, its selection will be delayed when the next input signal is received. On the one hand, compared with the traditional digital weighted averaging circuit, this dynamic device matching device adopts the first-in, last-out design concept, making the selection result of the DAC control unit similar to that of the high-order DEM. Therefore, its shaping capability is similar to that of the high-order DEM, with strong shaping capability and extremely strong harmonic suppression capability, which can solve the problem of poor shaping capability of the traditional data weighted averaging circuit. On the other hand, compared with the high-order DEM, the sorting update unit of this dynamic device matching device can directly operate on the current sorting sequence number of each DAC control unit, without the need for the complex digital filtering circuit and comparison sorting circuit in the traditional high-order DEM. Therefore, the hardware implementation complexity is low, which can solve the problem that the logic circuit implementation of the high-order DEM is complex and cannot be widely used.

[0151] In addition, the dynamic device matching device provided in this application can be used in high-precision oversampling ADC and DAC control unit products. This solution has extremely low power consumption and area overhead, and the digital logic of this solution has good process compatibility. Under advanced processes, its power consumption and area advantages will be further improved. Therefore, it can be easily integrated into the ADC and DAC control unit module to help the ADC and DAC control unit achieve the requirements of low power consumption and high linearity under advanced processes, and further improve the versatility of the dynamic device matching device.

[0152] To better understand the DAC control unit selection principle of the dynamic device matching device for high-precision digital-to-analog converters provided in this application, an example is given below to illustrate the process of selecting the DAC control unit. (Reference) Figure 6 Assuming the total number of DAC control units is 8, i.e. n=8, initialize each DAC control unit: the current sorting order of E1 to E8 is 0, 1, 2, 3, 4, 5, 6, 7 respectively, and the starting position of the pointer PT is 0.

[0153] First selection: The input signal value is 3. At this time, PT = 0, PT + 3 = 3, the summation result does not overflow, PTN = 3, and the DAC control units selected in the sorting queue are E1 to E3. According to the above selection logic, E1 to E3 output 1, and the current sorting sequence number of each DAC control unit remains unchanged.

[0154] Second selection: The input signal value is 3. At this time, PT = PTN = 3, PT + 3 = 6. The summation result does not overflow, PTN = 6. The DAC control units selected in the sorting queue are E4 to E6. According to the above selection logic, E4 to E6 output 1, and the current sorting sequence number of E4 to E6 is updated to the front of the sorting, from 3 to 5, respectively updated to 0 to 2. Correspondingly, E1 to E3 are shifted 3 positions to the right, and the current sorting sequence number of E1 to E3 is updated from 0 to 2, respectively, to 3 to 5.

[0155] Third selection: The input signal value is 4. At this time, PT = PTN = 6, PT + 4 = 10, the sum overflows, PTN = 10 - 8 = 2. The DAC control units selected in the sorting queue are E7~E8 and E4~E5. According to the above selection logic, E7~E8 and E4~E5 output 1. The current sorting number of E4~E5 remains unchanged. The current sorting number of E7~E8 is after E4~E5, that is, it is updated from 6~7 to 2~3 respectively. Correspondingly, E6 and E1~E3 are shifted 2 positions to the right, and the current sorting number is updated from 2~5 to 4~7 respectively.

[0156] Fourth selection: The input signal value is 4. At this time, PT = PTN = 2, PT + 4 = 6, the summation result does not overflow, PTN = 6, the DAC control units selected in the sorting queue are E7, E8, E6, and E1. According to the above selection logic, E7, E8, E6, and E1 output 1, and the current sorting number moves to the front of the sorting, that is, from 2 to 5, they are updated to 0 to 3 respectively. Correspondingly, E4 and E5 move 4 positions backward, and the current sorting number is updated from 0 to 1 to 4 to 5 respectively. The current sorting numbers of E2 and E3 remain unchanged.

[0157] Fifth selection: The input signal value is 3. At this time, PT = PTN = 6, PT + 3 = 9, the sum overflows, PTN = 9 - 8 = 1. The DAC control units selected in the sorting queue are E2, E3 and E7. According to the above selection logic, E2, E3 and E7 output 1. The current sorting number of E7 remains unchanged. The current sorting numbers of E2 and E3 are after E7, that is, they are updated to 1 to 2 respectively from 6 to 7. Correspondingly, E8, E6, E1, E4 and E5 are shifted 2 positions to the right, and the current sorting numbers are updated to 3 to 7 respectively from 1 to 5.

[0158] 6th selection: The input signal value is 4. At this time, PT = PTN = 1, PT + 4 = 5, the summation result does not overflow, PTN = 5, the DAC control units selected in the sorting queue are E2, E3, E8, and E6. According to the above selection logic, E2, E3, E8, and E6 output 1, and the current sorting number moves to the front of the sorting, that is, from 1 to 4, they are updated to 0 to 3 respectively. Correspondingly, E7 moves 4 bits backward, and the current sorting number is updated from 0 to 4. The current sorting numbers of E1, E4, and E5 remain unchanged.

[0159] 7th selection: The input signal value is 3. At this time, PT = PTN = 5, PT + 3 = 8, the sum overflows, PTN = 8 - 8 = 0. The DAC control units selected in the sorting queue are E1, E4, and E5. According to the above selection logic, E1, E4, and E5 output 1. E1, E4, and E5 move to the front of the sorting, that is, they are updated from 5 to 7 to 0 to 2 respectively. Correspondingly, E2, E3, E8, E6, and E7 move 3 positions to the right, that is, the current sorting sequence number is updated from 0 to 4 to 3 to 7.

[0160] 8th selection: The input signal value is 4. At this time, PT = PTN = 0, PT + 4 = 4, the summation result does not overflow, PTN = 4, the DAC control units selected in the sorting queue are E1, E4, E5 and E2. According to the above selection logic, E1, E4, E5 and E2 output 1. The current sorting sequence number of E1, E4, E5 and E2 is already at the front of the sorting. Therefore, the current sorting sequence number of E1, E4, E5 and E2 remains unchanged. Correspondingly, the current sorting sequence number of E3, E8, E6 and E7 also remains unchanged.

[0161] 9th selection: The input signal value is 3. At this time, PT = PTN = 4, PT + 3 = 7. The summation result does not overflow, PTN = 7. The DAC control units selected in the sorting queue are E3, E8, and E6. According to the above selection logic, E3, E8, and E6 output 1. The current sorting sequence number of E3, E8, and E6 moves to the front of the sorting queue. Therefore, the current sorting sequence number of E3, E8, and E6 is updated from 4 to 6 to 0 to 2 respectively. Correspondingly, E1, E4, E5, and E2 are shifted 3 positions backward, that is, the current sorting sequence number of E1, E4, E5, and E2 is updated from 0 to 3 to 3 to 6 respectively. E7 remains unchanged.

[0162] 10th selection: The input signal value is 4. At this time, PT = PTN = 7, PT + 4 = 11, the sum overflows, PTN = 11 - 8 = 3. The DAC control units selected in the sorting queue are E7, E3, E8, and E6. According to the above selection logic, E7, E3, E8, and E6 output 1. E7 moves after E3, E8, and E6, that is, the current sorting number is updated from 7 to 3. Correspondingly, E1, E4, E5, and E2 move one position to the right, that is, the current sorting number is updated from 3 to 6 to 4 to 7.

[0163] Repeat the above selection process until a reset signal is received to update to the preset value, or a stop update signal is received, at which point the selection process stops.

[0164] By comparing the selection results of the dynamic device matching device for high-precision digital-to-analog converters provided in this application with the selection results of traditional digital weighted average circuits and second-order DEMs, the results obtained are referenced. Figure 7 As shown. According to Figure 7 It can be seen that the selection result of the dynamic device matching device provided in this application is consistent with... Figure 7 The leftmost number weighted average selection result and Figure 7 The dynamic device matching results of the rightmost second-order DEM are compared. The selection results of this application are similar to those of the second-order dynamic device matching results. Both have the first-in-last-out selection characteristics, that is, they can achieve the shaping effect of the second-order DEM.

[0165] The selection results of the dynamic device matching device, the selection results of the digital weighted average circuit, and the selection results of the second-order DEM provided in this application are compared with the shaping mismatch error output spectrum in the same delta sigma ADC (a high-precision ADC device). Figure 8 As shown, according to Figure 8 It can be seen that this application has similar shaping capabilities to the second-order DEM, and compared with the data weighted averaging circuit, this application has better suppression capabilities for harmonic distortion.

[0166] Figure 9 A flowchart illustrating a dynamic device matching method for a high-precision digital-to-analog converter according to an embodiment of the present disclosure is provided. This application describes the method using an example of its application in the dynamic device matching apparatus for a high-precision digital-to-analog converter provided in the above embodiment. The method includes the following steps:

[0167] Step 901: Receive input signal;

[0168] Step 902: Determine the end position of the pointer based on the input signal and the pre-stored start position of the pointer; the start position and end position are used to indicate the target sorting sequence number of the selected DAC control unit;

[0169] Step 903: For each DAC control unit, compare the current sorting number corresponding to the DAC control unit with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, and obtain the comparison result; wherein, the current sorting number is used to indicate the sorting order of the DAC control unit among the n DAC control units;

[0170] Step 904: Determine the output signal of the DAC control unit based on the comparison result, and update the current sorting number so that if the DAC control unit is selected this time, it will be delayed in being selected the next time an input signal is received.

[0171] For relevant details, please refer to the above embodiments.

[0172] In some embodiments, the functions or unit modules of the apparatus provided in this disclosure can be used to perform the methods described in the above embodiments, and their specific implementations can be referred to each other. For the sake of brevity, they will not be described in detail here.

[0173] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A dynamic device matching device suitable for high-precision digital-to-analog converters, characterized in that, The device includes: The pointer update unit is configured to: receive an input signal; determine the end position of the pointer based on the input signal and a pre-stored pointer start position; the start position and the end position are used to indicate the target sorting sequence number of the selected DAC control unit; There are n DAC control units, each connected to the pointer update unit; each DAC control unit includes a comparison unit, a sorting storage unit, and a sorting update unit; where n is an integer greater than 1. The sorting storage unit is used to: store the current sorting sequence number of the DAC control unit, which indicates the sorting order of the DAC control unit among n DAC control units; The comparison unit is configured to: compare the current sorting number with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; and determine the output signal of the DAC control unit based on the comparison result. The sorting update unit is used to update the current sorting number based on the comparison result, so that when the DAC control unit is selected this time and the sum of the starting position and the input signal does not overflow, the current sorting number of the DAC control unit is updated to the front of the sorting, ensuring that it is selected later when the input signal is received next time.

2. The apparatus according to claim 1, characterized in that, The pointer update unit is further configured to: determine whether the summation result of the input signal and the starting position overflows; if overflow occurs, subtract n from the summation result to obtain the ending position; Accordingly, The comparison unit is used to: determine the output signal of the DAC control unit based on the comparison result and the determination result of whether overflow occurs; The sorting update unit is used to update the current sorting number based on the comparison result and the determination result of whether overflow occurs.

3. The apparatus according to claim 2, characterized in that, The sorting update unit is used for: If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is subtracted from the target sorting number indicated by the starting position to obtain the updated sorting number. If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit remains unchanged. If the summation result does not overflow, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to the value indicated by the input signal to obtain the updated sorting number. If the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to n and the target sorting number indicated by the starting position is subtracted to obtain the updated sorting number. In the event that the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the current sorting number of the DAC control unit remains unchanged. If the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the current sorting number of the DAC control unit is added to the value indicated by the input signal minus the difference obtained by n, to obtain the updated sorting number.

4. The apparatus according to claim 3, characterized in that, The sorting update unit includes: a first adder, a first data selector and a first register respectively connected to the input of the first adder, and a second data selector and a third data selector respectively connected to the first data selector; the output of the first adder is connected to the input of the first register; The first register is used to store the current sorting sequence number; The first data selector is configured to connect to the second data selector via a first input terminal when the summation result overflows, and to connect to the third data selector via a second input terminal when the summation result does not overflow. The second data selector includes a first data input terminal, a second data input terminal, and a third data input terminal; the first data input terminal is used to input the difference between the value indicated by the input signal and n into the second data selector; the second data input terminal is used to input the difference between n and the target sorting number indicated by the starting position into the second data selector; the third data input terminal is used to input 0 into the second data selector. The third data selector includes a fourth data input terminal, a fifth data input terminal, and a sixth data input terminal; the fourth data input terminal is used to input 0 to the second data selector; the fifth data input terminal is used to input the negative value of the target sorting number indicated by the starting position to the second data selector; and the sixth data input terminal is used to input the value indicated by the input signal to the second data selector.

5. The apparatus according to claim 2, characterized in that, The comparison unit is used for: If the summation result overflows, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is greater than or equal to the target sorting number indicated by the ending position, the output signal is determined to be 1; or, If the summation result overflows, the current sorting number is less than the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 1; or, If the summation result does not overflow, the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and the current sorting number is less than the target sorting number indicated by the ending position, the output signal is determined to be 1.

6. The apparatus according to claim 5, characterized in that, When the summation result overflows, the first output of the pointer update unit outputs 1; when the summation result does not overflow, the first output of the pointer update unit outputs 0. Correspondingly, The comparison unit includes a first comparator, a second comparator, and an XOR unit; The first comparator is configured to output 1 if the current sorting number is greater than or equal to the target sorting number indicated by the starting position, and output 0 if the current sorting number is less than the target sorting number indicated by the starting position. The second comparator is configured to output 1 if the current sorting number is greater than or equal to the target sorting number indicated by the end position, and output 0 if the current sorting number is less than the target sorting number indicated by the end position. The XOR is connected to the first comparator, the second comparator, and the first output terminal respectively; the XOR is used to output 0 or 1 based on the first comparison result, the second comparison result, and the determination result output by the first output terminal.

7. The apparatus according to claim 2, characterized in that, The pointer update unit includes a second adder and a second register; The second register is used to store the starting position of the pointer; The second adder includes a signal input terminal and a pointer input terminal. The signal input terminal is used to input the input signal into the second adder. The pointer input terminal is connected to the output terminal of the second register to input the starting position stored in the second register into the second adder. The second adder also includes a first output terminal and a second output terminal. The first output terminal is used to output a determination result of whether overflow has occurred; the second output terminal is used to output the end position.

8. The apparatus according to claim 7, characterized in that, The second output terminal is connected to the input terminal of the second register to store the end position, so that when the input signal is received again, the end position is used as the starting position of the pointer corresponding to the next input signal to determine the end position of the pointer corresponding to the next input signal.

9. The apparatus according to any one of claims 1 to 8, characterized in that, Each DAC control unit also includes a reset unit, used to update the current sorting sequence number stored in the sorting storage unit to a preset value when a reset signal is received. The preset value is different for different DAC control units.

10. A dynamic device matching method suitable for high-precision digital-to-analog converters, characterized in that, The method includes: Receive input signals; The end position of the pointer is determined based on the input signal and the pre-stored start position of the pointer; the start position and the end position are used to indicate the target sorting sequence number of the selected DAC control unit; For each DAC control unit, the current sorting number corresponding to the DAC control unit is compared with the target sorting number indicated by the start position and the target sorting number indicated by the end position, respectively, to obtain a comparison result; wherein, the current sorting number is used to indicate the sorting order of the DAC control unit among the n DAC control units; Based on the comparison result, the output signal of the DAC control unit is determined, and the current sorting number is updated. If the DAC control unit is selected this time and the sum of the starting position and the input signal does not overflow, the current sorting number of the DAC control unit is updated to the front of the sort, ensuring that it is selected later when the input signal is received next time.

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