Voltage-time conversion circuit based on voltage-controlled oscillator

Abstract

The invention discloses a voltage-controlled oscillator-based voltage-time conversion circuit, which is characterized in that the whole circuit is divided into four parts: the first part is used for sampling an input voltage signal; the second part is to process the sampled voltage signal by using an analog domain division circuit; in the third part, the signal is used as a control signal of a voltage-controlled oscillator to generate corresponding output; and in the fourth part, two paths of time signals are obtained as output through a single-slip edge generation circuit, so that the conversion from a voltage input signal to a time output signal is completed. The voltage-controlled oscillator is adopted to convert a voltage signal into a time signal, and the output range is widened. And meanwhile, a voltage domain division circuit is used for preprocessing a sampling signal, so that the linearity of overall voltage-time conversion is ensured, and the input dynamic range is expanded at the same time.

Description

Technical Field

[0001] The present invention relates to a voltage-time conversion circuit based on a voltage-controlled oscillator, and belongs to the technical field of data converters. Background Art

[0002] In nature, the signals that can usually be felt are all analog signals. With the advent of the information society in the 21st century, people increasingly need to perform more refined processing on analog signals. With the development in multiple directions and fields, in order to provide more flexible directions for subsequent circuits, people have turned their attention to the time domain. Facing the conversion from the voltage domain to the time domain, the voltage-time converter undertakes the important task of data acquisition and conversion. In line with the index requirements of the overall conversion circuit, the voltage-time converter that plays a key conversion role has become the top priority. Currently, voltage-time converters are widely used in various fields, such as precision measurement, communication systems, and so on.

[0003] In a data acquisition system, a voltage-time converter is often used in combination with a time-to-digital converter to achieve high-resolution analog-to-digital conversion. Compared with traditional successive approximation type or integral type analog-to-digital converters, the conversion method based on a voltage-time converter has lower power consumption and higher speed; the voltage-time converter can encode an analog signal into time information, and this representation in the time domain is more efficient in some signal processing applications, such as signal mean calculation and modulation and demodulation techniques; in electronic testing and measurement, the voltage-time converter is used to perform precise timing analysis tasks. For example, in devices such as oscilloscopes, timers, and spectrum analyzers, the voltage-time converter can be used as a time reference module to provide higher-precision measurement capabilities. With the improvement of various indicators and requirements, voltage-time converters with high precision and wide input-output range have gradually become a research hotspot.

[0004] The basic working principle of the current voltage-time conversion circuit is as follows: The voltage margin is sampled by means of a switch control. The voltage margin is discharged or charged through a current mirror, and uniformly decreases or increases while ensuring linearity. The margin voltage and a fixed reference voltage are jointly input to a comparator, and the comparison result is output to a phase detector to obtain the start and stop signals for controlling the time-to-digital conversion circuit. Due to the influence of linearity, for an input with a relatively small voltage margin, the current mirror has good linearity. For the comparator, a reference voltage closer to the common-mode voltage can be input. In this way, the voltage-time conversion work can be completed within a relatively short conversion time. Therefore, this structure is more prominent in the case of a relatively small input voltage margin. However, for a relatively large voltage margin, the linearity decreases accordingly. The linearity can be compensated by increasing the capacitance, but at the same time, the chip area will increase significantly. In addition, the reference voltage of the input comparator will be much lower than the common-mode voltage, which is also a greater test for the comparator. The output signal of the voltage-time converter controls the start and stop of the time-to-digital conversion circuit, but there will be a time deviation when the control signal passes through the phase detector, which will cause a mismatch between the voltage and time for a high-precision time-to-digital converter. Finally, due to its principle, the input dynamic range and output range of some existing charge or discharge type voltage-time converters are limited. The present invention can overcome the deficiencies of the prior art and further improve the voltage-time conversion circuit based on a comparator. Summary of the Invention

[0005] The present invention proposes a new conversion method for the voltage-time conversion circuit, and expands the input dynamic range and output range of the voltage digital converter while ensuring accuracy. The overall circuit of the present invention is divided into four parts. The first part samples the input voltage signal; the second part uses an analog-domain division circuit to process the sampled voltage signal; the third part uses the signal as a control signal for a voltage-controlled oscillator to generate a corresponding output; the fourth part obtains two time signals as outputs through a single-transition-edge generation circuit, thereby completing the conversion from the voltage input signal to the time output signal.

[0006] The above object is achieved by the following technical solutions:

[0007] A voltage-time conversion circuit based on a voltage-controlled oscillator, which comprises: a sample-and-hold circuit, an analog-domain division circuit, a voltage-controlled oscillator, and a single-transition-edge generation circuit. It involves the conversion from a voltage-domain signal to a time-domain signal. In the overall structure, the sample-and-hold circuit is connected to the input voltage signal and transmitted to the input end of the analog-domain division circuit. After processing the sampled voltage, it is output to the voltage-controlled oscillator to generate a corresponding oscillation signal. This signal passes through the single-transition-edge generation circuit to obtain two time signals. The input voltage information is included in the difference between the rising edges of the two time signals. Thus, the overall circuit conversion work is completed.

[0008] The described sample-and-hold circuit includes a capacitor C 0 and a bootstrap switch S 1 、S 2 、a reset switch S 3 。The capacitor C 0 has its upper plate connected to the output of the bootstrap switch S 1 and its lower plate connected to V CM ; One end of the bootstrap switch S 1 is connected to the input analog signal Vin and is controlled by Ф S , and the other end is connected to the upper plate of the capacitor C 0 ; One end of the bootstrap switch S 2 is connected to the upper plate of the capacitor C 0 , and one end is connected to the output signal V samp and is controlled by Ф 1 ; One end of the reset switch S 3 is connected to the upper plate of the capacitor C 0 , and one end is connected to V CM and is controlled by Ф 2 。

[0009] The input of the analog-domain division circuit is V samp 、V REF , and the output is V ctrl,VCO 。

[0010] The input of the voltage-controlled oscillator is V ctrl,VCO , and the output is T VCO 。

[0011] The single-slip-edge generation circuit includes an inverter INV1, a driver BUFF1, and an adjustable delay unit DelayCell. The input of the inverter INV1 is connected to T VCO , and the output is T N ; The input of the BUFF1 is connected to T VCO , and the output is connected to the adjustable delay unit DelayCell; One end of the adjustable delay unit DelayCell is connected to the control voltage V ctrl,delay , and the output of the other end is T P 。

[0012] Different from the traditional way of uniformly decreasing or increasing the voltage through a current mirror, the present invention uses a voltage-controlled oscillator to convert a voltage signal into a time signal, improving the output range. At the same time, a voltage-domain division circuit is used to preprocess the sampling signal, ensuring the linearity of the overall voltage-time conversion and improving the input dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is the circuit principle structure block diagram of the present invention

[0014] Figure 2 is the single-cycle timing diagram of the single rotation difference edge generation circuit of the present invention Detailed implementation manners

[0015] The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0016] A voltage-time conversion circuit based on a voltage-controlled oscillator, as Figure 1 shown, a certain correlation should be maintained among the phases of the bootstrap switch S 1 , switch S 2 and reset switch S 3 . In the first phase, the bootstrap switch S 1 is closed, switch S 2 is open, reset switch S 3 is open, the sampling circuit samples the continuous analog signal and charges the capacitor C 0 ; in the second phase, the bootstrap switch S 1 is turned off, switch S 2 is closed, reset switch S 3 remains off, and the voltage V 0 sampled by C samp is input to the analog-domain division circuit. After the output is completed, S 2 is turned off, and the reset switch S 3 is closed.

[0017] The basic working principle of the present invention is that when the bootstrap switch S 1 , switch S 2 , and reset switch S 3 are in the first phase, the overall circuit performs the sampling operation of the circuit. The lower plate of the capacitor C 0 is connected to the common-mode voltage, and the value of this common-mode voltage can be adjusted according to the input signal. The upper plate is connected to the input of the overall circuit and is charged under the action of the continuous analog voltage Vin of the input. When the bootstrap switch S 1 , switch S 2 , and reset switch S 3 are in the second phase, the circuit officially starts the conversion operation. The sample-and-hold circuit transmits the sampled V samp to the input end of the analog-domain division circuit, and the division circuit performs a division operation on it according to the input quantities V samp , V REF , and the output value is as follows:

[0018]

[0019] where A is the inherent gain of the division circuit. It can be seen that the output voltage V ctrl,VCO and the input voltage V sampThe output voltage V ctrl,VCO As the control voltage of the voltage controlled oscillator, and the output signal T VCO The cycle presents the following relationship, and when V is substituted ctrl,VCO With V samp The relationship can be obtained:

[0020]

[0021] Where T TVCO The output signal T VCO The period of K is the inherent gain of the voltage controlled oscillator. It can be seen that the voltage value V samp It has a linear relationship with the output signal period of the voltage controlled oscillator, and the proportionality coefficient is determined by K, A, V REF OK. At this time, the input voltage domain signal V samp The information is already contained in the time domain signal T VCO inside.

[0022] Finally, the signal T VCO The circuit is passed to the single-slip edge generation circuit, which realizes the input signal T through the driver BUFF1 and the inverter INV1. VCO The output of driver BUFF1 is reshaped and inverted to generate two square wave signals with a phase difference of 180 degrees. D The delay unit is used to adjust the delay time according to the minimum value of the input signal so that samp When the minimum value is taken, the two output signals T P 、T N The difference between adjacent rising edges is zero. Finally, the time difference ΔT between the rising edges of the two signals is equal to the sampled voltage V samp The relationship is as follows:

[0023]

[0024] like Figure 2 As shown, where ΔT is T P 、T N The time difference between two adjacent rising edges, T D The delay provided by the adjustable delay unit DelayCell. samp The linear conversion to the time difference ΔT completes the conversion from voltage to time. The second phase working state ends. In the third term, the reset switch S3 is closed, and the capacitor C 0 After that, it returns to the first phase and performs sampling of the first-stage circuit, thereby improving the working efficiency and performance of the overall circuit.

[0025] Certainly, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those skilled in the art within the scope of the essence of the present invention should also fall within the protection scope of the present invention.

Claims

1. A voltage-to-time conversion circuit based on a voltage-controlled oscillator, characterized in that: include: The four parts are sampling and holding circuit, analog domain division circuit, voltage-controlled oscillator, and single-slip edge generation circuit; involving the conversion of voltage domain signals to time domain signals; In the overall structure, the sampling and holding circuit is connected to the input voltage signal and transmitted to the input end of the analog domain division circuit. After the sampled voltage is processed, it is output to the voltage-controlled oscillator to generate a corresponding oscillation signal. The oscillation signal passes through the single-slip edge generation circuit to obtain two time signals. The input voltage information is contained in the difference between the rising edges of the two time signals, thus completing the overall circuit conversion work.

2. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 1, characterized in that: The sampling and holding circuit comprises a capacitor C0, bootstrap switches S1, S2, and a reset switch S3; the upper plate of the capacitor C0 is connected to the output of the bootstrap switch S1, and the lower plate is connected to V CM One end of the bootstrap switch S1 is connected to the input analog signal Vin, by Ф S control, and the other end is connected to the upper plate of capacitor C0; one end of the bootstrap switch S2 is connected to the upper plate of capacitor C0, and the other end is connected to the output signal V samp connected and controlled by Ф1; one end of the reset switch S3 is connected to the upper plate of capacitor C0, and the other end is connected to V CM Connected and controlled by Ф2.

3. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 2, characterized in that: The analog domain divider circuit input is V samp 、V REF , the output is V ctrl,VCO .

4. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 2, characterized in that: The voltage controlled oscillator input is V ctrl,VCO , the output is T VCO .

5. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 1, characterized in that: The single-slip edge generation circuit comprises an inverter INV1, a driver BUFF1, and an adjustable delay unit DelayCell; the input end of the inverter INV1 is connected to the T VCO connected, the output is T N ; The BUFF1 input terminal and T VCO The output end is connected to the adjustable delay unit DelayCell; one end of the adjustable delay unit DelayCell is connected to the control voltage V ctrl,delay connected, the output at the other end is T P .

6. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 2, characterized in that: The phases of the bootstrap switch S1, switch S2 and reset switch S3 should maintain a certain relationship; in the first phase, the bootstrap switch S1 is closed, the switch S2 is opened, the reset switch S3 is opened, the sampling circuit samples the continuous analog signal and charges the capacitor C0; in the second phase, the bootstrap switch S1 is turned off, the switch S2 is closed, the reset switch S3 remains turned off, and the voltage V sampled by C0 is samp Input to the analog domain division circuit; after the output is completed, S2 is turned off and the reset switch S3 is closed.

7. The voltage-to-time conversion circuit based on a voltage-controlled oscillator according to claim 6, characterized in that: When the bootstrap switch S1, switch S2, and reset switch S3 are in the first phase, the whole circuit performs the sampling work of the circuit; the lower plate of capacitor C0 is connected to the common mode voltage, and the value of the common mode voltage can be adjusted according to the input signal; the upper plate is connected to the input of the whole circuit and is charged under the action of the input continuous analog voltage Vin; when the bootstrap switch S1, switch S2, and reset switch S3 are in the second phase, the circuit officially starts the conversion work; the sample and hold device converts the sampled V samp Transmitted to the input of the analog domain divider circuit, the divider circuit divides the input value V samp 、V REF Performing a division operation on it, the output value is as follows: Where A is the inherent gain of the divider circuit; it can be seen that the output voltage V ctrl,VCO With input voltage V samp shows an inverse proportional relationship; while the output voltage V ctrl,VCO As the control voltage of the voltage controlled oscillator, and the output signal T VCO The cycle presents the following relationship, and when V is substituted ctrl,VCO With V samp The relationship can be obtained: Where T TVCO The output signal T VCO period, K is the inherent gain of the voltage-controlled oscillator; it can be seen that the voltage value V samp It has a linear relationship with the output signal period of the voltage controlled oscillator, and the proportionality coefficient is determined by K, A, V REF Determine; input voltage domain signal V samp The information is already contained in the time domain signal T VCO inside; Finally, the signal T VCO The circuit is passed to the single-slip edge generation circuit, which realizes the input signal T through the driver BUFF1 and the inverter INV1. VCO The shaping and inversion generate two square wave signals with a phase difference of 180 degrees; the output of the driver BUFF1 is T-connected by the adjustable delay unit DelayCell. D The delay unit is used to adjust the delay time according to the minimum value of the input signal so that samp When the minimum value is taken, the two output signals T P , T N The difference between adjacent rising edges is zero; ultimately, the time difference ΔT between the rising edges of the two signals is equal to the sampled voltage V samp The relationship is as follows: Where ΔT is T P , T N The time difference between two adjacent rising edges, T D The delay provided by the adjustable delay unit DelayCell; thus, the sampling voltage V samp The linear conversion is performed into the time difference ΔT, completing the conversion from voltage to time; the second phase working state ends; in the third item, the reset switch S3 is closed, and the charge on the capacitor C0 is cleared; After that, it returns to the first phase to perform sampling work on the first-stage circuit to improve the working efficiency and performance of the overall circuit.

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