Radio comprehensive detector

Abstract

The invention relates to the technical field of radio testing, in particular to a radio comprehensive detector which comprises a main control part, an upper computer part and a radio frequency part. The main control part is composed of an MCU and an FPGA in a cooperative mode, the MCU communicates with an upper computer through a communication interface, and the FPGA is connected with the radio frequency part through a parallel bus and is provided with a PS mode program loading interface; the radio frequency part adopts a zero intermediate frequency software radio architecture and comprises a receiving channel and a transmitting channel; the upper computer part comprises a touch screen and is connected with the main control board through a communication interface, communication navigation signals of an airplane, a ship, a control tower and a satellite can be simulated, and function testing of 17 types of radio airborne equipment such as a short wave / ultra-short wave radio station, a microwave / instrument landing system and a radio altimeter is completed; the outfield maintenance targets of single-person carrying, single-person operation and single-person flying are achieved, and the universality, efficiency and environmental adaptability of maintenance are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of radio testing technology, and particularly relates to a radio comprehensive detector. Background Art

[0002] With the rapid iteration of aviation equipment and the improvement of the intensity of actual combat training, the efficiency of aircraft maintenance has become a key factor affecting the mission execution ability of aircraft. At present, the detection of aviation radio equipment mainly relies on traditional ground support equipment, but these equipment have significant defects due to design limitations: poor versatility leads to the need to match special instruments for different aircraft models, single functions are difficult to cover complex testing requirements, the hardware architecture is redundant, resulting in large volume and high weight, and the operation process is cumbersome and relies on manual intervention. These problems seriously restrict the agility of on-site maintenance, especially in emergency mission scenarios, it is difficult to achieve rapid deployment and efficient detection. Summary of the Invention

[0003] In order to solve the problems of the prior art, the present invention provides a radio comprehensive detector, which realizes the on-site maintenance goals of single-person carrying, single-person operation, and single-person flying, and significantly improves the versatility, efficiency, and environmental adaptability of aircraft maintenance.

[0004] The present invention is realized through the following technical solutions: A radio comprehensive detector includes a main control part, a host computer part, and a radio frequency part; The main control part is jointly composed of an MCU and an FPGA. The MCU communicates with the host computer through a communication interface. The FPGA is connected to the radio frequency part through a parallel bus and is configured with a PS mode program loading interface; The radio frequency part adopts a zero-intermediate frequency software radio architecture, including a receiving channel and a transmitting channel; The receiving channel sequentially includes a limiter, a preselection filter bank, a digital control attenuator, a low-noise amplifier, and a single-pole double-throw switch group; the preselection filter bank is composed of filters in six independent frequency bands and is used to suppress external interference signals in segments; The single-pole double-throw switch group in the receiving channel divides the received signal into frequency band one and frequency band two. Among them, frequency band one is up-converted by the dot frequency signal generated by the phase-locked loop PLL1, and then demodulated by the IQ demodulator and the broadband signal of the phase-locked loop PLL2 to generate a baseband IQ signal; frequency band two is directly input to the IQ demodulator for demodulation; The transmitting channel sequentially includes an IQ modulator, a driver amplifier, a digital control attenuator, and a preselection filter bank, and the receiving and transmitting channels share the preselection filter bank in six independent frequency bands; The input end of the IQ modulator in the transmitting channel receives the baseband IQ signal and modulates it with the wideband signal of the phase-locked loop PLL2 to generate a radio frequency signal; the single-pole double-throw switch group divides the modulated radio frequency signal into frequency band one and frequency band two, where frequency band one is down-converted by the dot frequency signal generated by the phase-locked loop PLL1, and frequency band two is directly connected to the driver amplifier and output through the preselection filter bank; The upper computer part includes a touch screen and is connected to the main control board through a communication interface.

[0005] Further, the preselection filter bank of the receiving channel covers below the L band and the microwave band, the bandwidth of each independent band filter matches the working band of the airborne equipment, and the filter switching is dynamically controlled by the MCU according to the test requirements.

[0006] Further, the receiving channel and the transmitting channel of the radio frequency part are respectively connected to a dual-channel 14-bit ADC / DAC, the sampling rate of the ADC / DAC is not less than 40 MHz, and the FPGA analyzes the phase and frequency information of the baseband signal through the amplitude threshold decision algorithm.

[0007] Further, the power supply module of the main control part includes an 8.4V rechargeable lithium battery, a 27V external DC interface, and a 3.3V, 1.5V, 1.1V, ±5V secondary power conversion circuit implemented by a TPS chip. The power supply link of the lithium battery is configured with overvoltage / overcurrent protection circuits, and all secondary power supplies are independently powered by the lithium battery.

[0008] Further, the interface module of the detector includes two antenna interfaces and two altimeter interfaces; A multifunctional multiplexing interface that integrates the functions of MCU program downloading, FPGA configuration loading, and battery charging; An expansion interface with two SPI communication pins and general-purpose IO ports for connecting external sensors.

[0009] Further, the function module of the detector includes a monitoring unit that real-time monitors the power supply voltage, battery power, and radio frequency signal power, and displays warning information through the QT interface; A test unit that includes TACAN test, microwave landing test, heading test, ship automatic identification test, etc.; A system setting unit that configures communication protocol encryption parameters, touch screen response time, and three-level event interrupt priorities, and the interrupt priorities are implemented through a preemptive scheduling mechanism.

[0010] Further, the phase-locked loops PLL1 and PLL2 of the radio frequency part respectively generate dot frequency signals and wideband signals, and the bandwidth of PLL2 covers the entire working band of the IQ demodulator.

[0011] The present invention can simulate the communication and navigation signals of aircraft, ships, towers, and satellites, complete the functional tests of 17 types of radio airborne equipment such as short-wave / ultra-short-wave radios, microwave / instrument landing systems, and radio altimeters, achieving the outfield maintenance goals of single-person carrying, single-person operation, and single-person launching, and significantly improving the versatility, efficiency, and environmental adaptability of aircraft maintenance.

[0012] Advantages of the present invention: (1) A radio comprehensive detector proposed by the present invention adopts a zero-IF software radio architecture, omits the traditional multi-stage frequency conversion circuit, combines the cooperative control of MCU+FPGA and modular design, greatly simplifies the RF link, reduces the device volume by about 50%, and reduces the weight to the single-person carrying standard, meeting the requirements of rapid outfield deployment. The six-segment independent frequency band division of the preselection filter bank and the shared design of the transceiver channels reduce redundant hardware and further compress the space occupation; (2) A radio comprehensive detector proposed by the present invention dynamically switches frequency bands one and two between the receiving channel and the transmitting channel through a single-pole double-throw switch group, and combines the cooperative work of PLL1 and PLL2 to achieve full-band compatibility from the L band to the microwave band, which can be adapted to the aviation radio frequency band of 2Mhz to 6GHz, covering the detection requirements of current and new airborne equipment. The frequency band bandwidth of the preselection filter bank is strictly matched with the airborne equipment, and the MCU dynamically controls the filter switching to avoid the poor compatibility problem caused by the fixed frequency band of traditional equipment; (3) A radio comprehensive detector proposed by the present invention integrates a QT interface on the touch screen upper computer, supports one-key channel configuration, dynamic azimuth / distance simulation, and identification tone control, improves the automation degree of the test process by 80%, reduces the manual operation steps to within 3 steps, and the signal automatic generation function in the continuous mode replaces the traditional manual item-by-item configuration, significantly shortening the test time; (4) A radio comprehensive detector proposed by the present invention supports comprehensive functions such as power measurement, sensitivity test, and precise ranging. By using FPGA to real-time analyze the phase and frequency information of the baseband signal, the detection accuracy reaches ±0.1dB, and the dual-channel 14-bit ADC / DAC ensures the fidelity of signal acquisition and generation, meeting the requirements of high dynamic range tests; (5) A radio comprehensive detector proposed by the present invention adopts a domestic solution for key devices (such as ADC / DAC, power management chips), combines the multi-stage conversion of TPS series power chips and overvoltage / overcurrent protection circuits to ensure the stable operation of the device in a complex outfield environment. The encrypted communication protocol and the three-level event interruption preemption mechanism prevent data leakage and system jamming, reducing the failure rate. Description of the Drawings

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the attached drawings required in the description of the embodiments. Obviously, the attached drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other attached drawings can be obtained based on these attached drawings without creative efforts.

[0014] Figure 1 It is a system block diagram of a radio comprehensive detector proposed by the present invention; Figure 2 It is the principle of the digital-to-analog / analog-to-digital conversion circuit of a radio comprehensive detector proposed by the present invention Figure 1 ; Figure 3 It is the principle of the digital-to-analog / analog-to-digital conversion circuit of a radio comprehensive detector proposed by the present invention Figure 2 Figure 4 It is the principle of the power supply circuit of a radio comprehensive detector proposed by the present invention Figure 1 ; Figure 5 It is the principle of the power supply circuit of a radio comprehensive detector proposed by the present invention Figure 2 ; Figure 6 It is the principle of the power supply circuit of a radio comprehensive detector proposed by the present invention Figure 3 ; Figure 7 It is the principle of the power supply circuit of a radio comprehensive detector proposed by the present invention Figure 4 ; Figure 8 It is the schematic diagram of the MUC control circuit of a radio comprehensive detector proposed by the present invention; Figure 9 It is the principle of the FPGA control circuit of a radio comprehensive detector proposed by the present invention Figure 1 ; Figure 10 It is the principle of the FPGA control circuit of a radio comprehensive detector proposed by the present invention Figure 2 ; Figure 11 It is the principle of the interface circuit of a radio comprehensive detector proposed by the present invention Figure 1 ; Figure 12 It is the principle of the interface circuit of a radio comprehensive detector proposed by the present invention Figure 2 ; Figure 13 It is the audio decoding flowchart of a radio comprehensive detector proposed by the present invention; Figure 14 It is the system block diagram of the radio frequency part of a radio comprehensive detector proposed by the present invention Figure 15 The system framework diagram of a radio comprehensive detector proposed by the present invention; Figure 16 The operation response flow chart of a radio comprehensive detector proposed by the present invention; Figure 17 The interface synchronization flow chart of a radio comprehensive detector proposed by the present invention; Figure 18 The event interruption priority flow chart of a radio comprehensive detector proposed by the present invention. Detailed implementation manners

[0015] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the embodiments and the accompanying drawings. The illustrative embodiments and descriptions thereof of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0016] Embodiment 1 Refer to Figure 1 , a radio comprehensive detector proposed in this embodiment includes a main control part, a radio frequency part and a host computer part.

[0017] Among them, the main control part responds to the operation instructions of the host computer, transfers necessary data to the host computer for display, and at the same time coordinates with the radio frequency part to complete signal transmission, reception, encoding and decoding. It mainly consists of wireless communication, digital-to-analog / analog-to-digital conversion, power supply, interface, control core, expansion slot, etc.

[0018] Refer to Figures 2 - 3 , the digital-to-analog / analog-to-digital conversion includes 2 ADC / DACs. The dual-channel ADC / DAC maximizes the use of space. To ensure the quality and bandwidth of the transmitted and received signals, a model with better than 40M and 14 bits is used. Since the battery power also needs to be collected by the ADC and the accuracy requirement is not high, the ADC built in the MCU or FPGA is used in this embodiment.

[0019] Refer to Figures 4 - 7 , the power supply uses an 8.4V rechargeable battery as the main power supply and 27V external direct current as the external backup power supply. The secondary power supplies required by the detector are 3.3V, 1.5V, 1.1V, ±5V. According to the required power and usage, general voltage chips are selected to achieve power conversion.

[0020] Refer to Figures 8 - 10 , the core control is built with an MCU+FPGA architecture. The FPGA is mainly responsible for cooperating with the radio frequency module to complete signal transmission and reception, and changing the corresponding signal content according to the instructions of the MCU. The MCU is responsible for communicating with the host computer, monitoring the power supply, configuring the FPGA program, switch control, etc.

[0021] This embodiment also includes an interface module, which includes a multi-functional multiplexing interface, two antenna interfaces, two altimeter interfaces, and an expansion interface. Refer to Figure 11 The multi-functional multiplexing interface is used to integrate functions such as MCU program downloading, FPGA configuration loading, and battery charging. Refer to Figure 12 The expansion interface includes two-way SPI communication pins and general-purpose IO ports, which are used to externally connect new modules.

[0022] The wireless communication in this embodiment adopts a split design. To meet the confidentiality requirements, communication encryption is required for wireless communication. In this embodiment, point-to-point communication is discarded, and a networking communication form is adopted for function expansion; Among them, the wireless communication involves the audio encoding function. In this embodiment, a wireless communication headset is used to implement audio encoding and decoding. Refer to Figure 13 The encoding and decoding process is realized through the circuit.

[0023] For the upper computer part, to cooperate with the functions of corresponding buttons, switches and other controls on the program interface, an IPS industrial-grade capacitive touch display screen is adopted to provide users with a comfortable and efficient human-computer interaction experience. The human-computer interaction board mainly realizes carrying the linux system and adopting the QT interface to realize human-computer interaction, and communicates with the MCU through the SPI bus internally to issue control instructions.

[0024] Among them, the radio frequency part is constructed based on the zero-IF software radio technology. By simplifying the mixing link in the traditional superheterodyne architecture, the hardware circuit is streamlined and miniaturized. While maintaining high-precision signal processing capabilities, the radio frequency part effectively reduces the physical space occupation, and is especially suitable for application scenarios sensitive to volume and power consumption. The whole set of solutions consists of key modules such as a controller, a filter bank, a radio frequency switch, a phase-locked loop PLL, and a direct digital frequency synthesizer DDS. Through the collaborative work of digital and analog circuits, the full process operation from radio frequency signal reception, processing to transmission is completed. Refer to Figure 14 .

[0025] In this embodiment, the signal processing in the receiving channel starts from amplitude limiting protection. The externally input radio frequency signal first passes through an amplitude limiter, whose core function is to limit the signal amplitude within the safe operating range to prevent device damage caused by overload or sudden high-power signals in the subsequent circuit. The signal after amplitude limiting processing enters the preselection filter bank, which contains six independent frequency bands, and the corresponding frequency band filtering channel is selected through the controller. Each filter is designed for a specific frequency range, effectively suppressing out-of-band interference signals while ensuring low-loss transmission of useful signals.

[0026] The signal after pre-filtering enters the digital controlled attenuator module. This module adjusts the attenuation amount through digital control signals to dynamically adjust the gain of the receiving channel. The controller automatically adjusts the attenuation value according to the signal strength, which not only ensures that small signals can be effectively amplified but also avoids amplifier saturation caused by large signals, enabling the system to adapt to input signals of different strengths and maintain stable signal processing quality. The attenuated signal is initially amplified by a low-noise amplifier to enhance the strength of weak signals and provide sufficient signal amplitude for subsequent demodulation processing. The low-noise characteristics of the amplifier ensure that the signal-to-noise ratio of the signal will not deteriorate significantly during the amplification process.

[0027] To meet the processing requirements of broadband signals, a frequency band switch is set at the front end of the demodulation in the system. When the input signal belongs to the low-frequency band, the switch directs it to the mixing channel for up-conversion processing with the dot-frequency signal generated by the phase-locked loop PLL1, shifting the signal to the frequency band suitable for the demodulator to work; when the signal is in the high-frequency band, it directly enters the demodulation link through the switch's direct-through path. The IQ demodulator receives the frequency-divided RF signal and performs quadrature demodulation with the broadband signal generated by the phase-locked loop PLL2 to separate the I-channel and Q-channel baseband signals. The two demodulated output signals are amplified and filtered to remove high-frequency residual components and then form an analog signal that meets the sampling requirements of the subsequent ADC.

[0028] The transmitting channel adopts a design architecture symmetrical to the receiving channel. The IQ signal generated by baseband processing enters the IQ modulator after amplification and filtering and performs quadrature modulation with the broadband signal generated by the phase-locked loop PLL2 to shift the baseband signal to the target RF frequency band. The modulated RF signal also needs to go through the frequency band division switch. For the frequency bands that need to be down-converted, the signal is mixed with the dot-frequency signal of PLL1; for the direct-through frequency bands, the original frequency is maintained. Subsequently, the digital controlled attenuator is used to precisely adjust the transmitting power to achieve dynamic adjustment of the transmitting intensity through digital control. The driver amplifier boosts the power of the signal to ensure that the output signal reaches the required transmitting power level. The final-stage pre-selection filter bank suppresses out-of-band spurs of the transmitting signal, and its six segmented filters can effectively filter out harmonic components to ensure the spectral purity of the output signal.

[0029] In the receiving channel of this embodiment, the FPGA receives the digital IQ signal from ADC sampling and extracts the phase information through amplitude threshold decision. For 4PSK modulated signals, when the amplitudes of the I-channel and Q-channel signals are both within a specific range, the system determines that the current symbol phase is 45 degrees and corresponds to the baseband data 00. The frequency information is obtained by calculating the phase change rate between adjacent symbols to extract the frequency modulation characteristics of the signal. The reverse process of the transmitting channel is implemented by the FPGA to generate the baseband signal, map the data to be transmitted to the corresponding IQ amplitude combination, and form an analog baseband signal through digital-to-analog conversion. The entire processing process uses digital algorithms to achieve modulation and demodulation.

[0030] Example 2 Reference Figure 15 , on the basis of Example 1, this embodiment describes in detail the implementation of the test function of the detector and the software architecture. Taking the TACAN system in aeronautical radio as an example, it includes TACAN function test, power sensitivity measurement and system stability guarantee.

[0031] The TACAN function test process in this embodiment is as follows: The MCU stores the transmit / receive frequency tables corresponding to 252 channels 1X~126X and 1Y~126Y. The user selects the target channel through the touch screen, and the MCU sends instructions to the FPGA to control the RF module to switch the PLL frequency and the preselection filter.

[0032] The FPGA generates the corresponding pulse code signal according to the azimuth and distance values input by the host computer. The FPGA automatically generates a dynamic signal at an azimuth change rate of 5° / s and a distance change rate of 5 km / s to simulate the aircraft motion state.

[0033] After the user triggers the recognition key, the FPGA generates a continuous audio Tone mode or Morse code Random mode, which is modulated by the RF part and then output. The detector verifies the normal recognition function through the wireless headset to receive the feedback from the on-board equipment.

[0034] The FPGA real-time collects the amplitude of the received signal, performs Kalman filtering and dBm conversion through the MCU. The display range is from -55 dBm to -90 dBm, with an accuracy of ±0.1 dB. The peak power captures the maximum value of the signal envelope through the FPGA and uploads it to the host computer. The detector gradually reduces the transmit power from -55 dBm to -90 dBm in steps of 5 dB until the on-board equipment does not respond. At this time, the power value is the received sensitivity.

[0035] This embodiment takes the air traffic control transponder system in aeronautical radio as an example, including A / C mode function test, sidelobe suppression measurement and S mode coding test.

[0036] The air traffic control transponder function test process in this embodiment is as follows: The detector emits an A mode interrogation signal to trigger the transponder on the aircraft to make an A mode response. The aircraft batch code information is decoded from the response signal and displayed on the screen. The working performance of the transponder A mode encoding / decoding can be completed by checking the consistency between the screen display and the on-board settings.

[0037] The detector uses the C mode interrogation to trigger the transponder to make a response, receives and analyzes the Gray code in the response signal, and converts it into the corresponding altitude and then displays it on the screen. At this time, the working ability of the transponder C mode encoding / decoding function can be completed by checking the altitude indication on the aircraft and the detector.

[0038] The detector simulates the situation of the aircraft being illuminated by side lobes by adjusting the signal amplitude of the P2 pulse in the interrogation signal, and can simulate three scenarios: "reply area", "ambiguous area" and "non - reply area".

[0039] The checker uses S - mode interrogation to trigger the transponder to make a reply, receives and analyzes the batch code, address code, and Gray code in the reply signal, converts them into corresponding data and displays them on the screen. At this time, by checking the display on the S - mode transponder control box on the aircraft and the indication of the checker, the working ability of the S - mode encoding and decoding function of the transponder can be completed.

[0040] The software in this embodiment adopts a discrete architecture and is divided into the following units: The monitoring unit is used to monitor the battery voltage, radio frequency signal power and temperature in real time, and trigger a three - level alarm in case of abnormal conditions.

[0041] The test unit integrates test modes such as Tacan, DME / P (Precision Distance Measuring), VOR (VHF Omnidirectional Range), etc., supports test script editing and batch execution, for example, continuously switching 10 channels and recording the results.

[0042] The system setting unit is used to configure communication protocols and touch - screen response time.

[0043] Embodiment 3 Based on Embodiment 2, this embodiment proposes an operation process of a radio comprehensive detector Reference Figure 16 , operation detection. Operation detection is the start of the entire program startup, and the process is as follows: After the detector is started, the touch - screen enters the standby state and continuously scans for user operation signals. At this time, the screen displays the current test mode and parameter interface, waiting for user input.

[0044] The user selects function buttons or enters parameters through the touch - screen. The touch - screen controller detects the change of capacitance signal in real time and triggers the operation detection program.

[0045] The system accurately locates the user operation area by scanning the coordinate grid of the touch - screen and maps the coordinates to the current interface layout.

[0046] According to the current display page and system status, verify whether the user operation conforms to logic and permissions. If it is a valid operation, the system executes the corresponding operation, updates the interface display, and records the operation log.

[0047] If it is an invalid operation, it returns to the scanning state.

[0048] Reference Figure 17, the operation display interface. After the operator makes a correct operation, corresponding changes should appear on the display interface to give notice, and the processor will also update the record of the current state of the display interface in real time to ensure the correctness of the operation. Specifically: After the detector is powered on, the main control part starts, and the power management module completes self-check to ensure that all voltage outputs are normal.

[0049] The Linux system starts, the QT interface framework loads the preset test configuration file, and the standby interface displays the touch screen main interface, including channel configuration, power measurement, azimuth simulation, function buttons, and current parameter status.

[0050] The user triggers an operation through the touch screen, and the system enters the event response process: Replace the original value with a new value for display: For example, if the user switches from channel 31X to channel 45X, the interface will display the new channel number in real time; Change the displayed value: If the user slides the power adjustment bar, the value will be dynamically updated from -70 dBm to -75 dBm.

[0051] The system classifies and processes operations according to the operation type, including parameter modification and function switching.

[0052] The processor makes an operation response according to the new value, releases the original value and retains the new value.

[0053] If the user cancels the operation, the interface will restore the original parameter display (such as channel 31X); if the operation is confirmed, the new value will take effect and continue to be displayed.

[0054] After completing the current operation, the system returns to the standby interface or jumps to the associated function page (such as the continuous mode monitoring interface) and continues to wait for user input.

[0055] Reference Figure 18 , through the software architecture, all event responses in the radio comprehensive detector are prioritized to ensure that the system will not be stuck or run disorderly due to receiving too many response events at the same time.

[0056] The event interruption priority is divided into first-level interrupts, namely power failure and over-temperature; second-level interrupts, namely communication timeout and data verification error; third-level interrupts: namely user operation instructions.

[0057] During the operation of the detector, various events may be triggered.

[0058] Judge whether there is an event being executed currently. If there is no event being executed, directly execute the new event; if there is an event being executed, enter the priority comparison process.

[0059] Compare the preset event priorities The system determines the event priority according to the preset rules: Level 1 interrupt (highest priority): power failure, over-temperature, emergency stop; Level 2 interrupt: communication timeout, data verification error; Level 3 interrupt (lowest priority): user parameter adjustment, routine test task.

[0060] Perform operations according to the priority. When the priority of the new event is higher, immediately terminate the current event and execute the new event; when the priority of the old event is higher, continue to execute the current event and process the new event after completion; when the priorities are equal, the new event overrides.

[0061] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A radio integrated detector, characterized in that: It includes main control part, host computer part and radio frequency part; The main control part is composed of MCU and FPGA. The MCU communicates with the host computer through a communication interface. The FPGA is connected to the radio frequency part through a parallel bus and is configured with a PS mode program loading interface. The radio frequency part adopts a zero intermediate frequency software radio architecture, including a receiving channel and a transmitting channel; The receiving channel includes a limiter, a pre-selection filter group, a digitally controlled attenuator, a low noise amplifier and a single-pole double-throw switch group in sequence; the pre-selection filter group is composed of filters of six independent frequency bands, which is used to suppress external interference signals in sections; The single-pole double-throw switch group in the receiving channel divides the received signal into frequency band 1 and frequency band 2. Frequency band 1 is up-converted by the point frequency signal generated by the phase-locked loop PLL1, and then demodulated by the IQ demodulator and the broadband signal of the phase-locked loop PLL2 to generate a baseband IQ signal; frequency band 2 is directly input into the IQ demodulator for demodulation; The transmitting channel includes an IQ modulator, a driving amplifier, a digitally controlled attenuator and a pre-selection filter group in sequence, and the transmitting and receiving channels share a pre-selection filter group of six independent frequency bands; The input end of the IQ modulator in the transmitting channel receives the baseband IQ signal and modulates it with the broadband signal of the phase-locked loop PLL2 to generate a radio frequency signal; the single-pole double-throw switch group divides the modulated radio frequency signal into frequency band one and frequency band two, wherein frequency band one is down-converted by the point frequency signal generated by the phase-locked loop PLL1, and frequency band two is directly passed to the driving amplifier and output through the pre-selection filter group; The host computer part includes a touch screen, which is connected to the main control board through a communication interface.

2. A radio integrated detector according to claim 1, characterized in that: The preselected filter group of the receiving channel covers the band below L-band and microwave band, the bandwidth of each independent frequency band filter matches the operating frequency band of the airborne equipment, and the filter switching is dynamically controlled by the MCU according to the test requirements.

3. A radio integrated detector according to claim 1, characterized in that: The receiving channel and transmitting channel of the RF part are respectively connected to a dual-channel 14-bit ADC / DAC, the sampling rate of the ADC / DAC is not less than 40MHz, and the FPGA analyzes the phase and frequency information of the baseband signal through an amplitude threshold judgment algorithm.

4. A radio integrated detector according to claim 1, characterized in that: The power module of the main control part includes an 8.4V rechargeable lithium battery, a 27V external DC interface, and a 3.3V, 1.5V, 1.1V, ±5V secondary power conversion circuit implemented by a TPS chip. The lithium battery power supply link is configured with an overvoltage / overcurrent protection circuit, and all secondary power supplies are independently powered by lithium batteries.

5. A radio integrated detector according to claim 1, characterized in that: The interface module of the detector includes two antenna interfaces and two altimeter interfaces; Multi-function multiplexing interface, integrating MCU program download, FPGA configuration loading and battery charging functions; Expansion interface, two SPI communication pins and general IO port for external sensors.

6. A radio integrated detector according to claim 1, characterized in that: The functional modules of the detector include a monitoring unit, which monitors the power supply voltage, battery power and RF signal power in real time, and displays alarm information through the QT interface; Test unit, including TACAN test, microwave landing test, heading test, automatic ship identification test, etc.; The system setting unit configures the communication protocol encryption parameters, the touch screen response time and the three-level event interrupt priority, and the interrupt priority is realized through a preemptive scheduling mechanism.

7. A radio integrated detector according to claim 1, characterized in that: The phase-locked loops PLL1 and PLL2 of the radio frequency part generate a spot frequency signal and a broadband signal respectively, and the bandwidth of PLL2 covers the full working frequency band of the IQ demodulator.

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