Semiconductor structure and sense amplifier

Abstract

The present disclosure provides a semiconductor structure, relates to the technical field of semiconductor, and is used to solve the technical problem that the semiconductor structure is easy to break. The semiconductor structure comprises an active structure, a first gate structure and a second gate structure. The active structure comprises a first active region and a second active region connected along a first direction, and the first active region and the second active region are respectively provided with a first recess and a second recess at one end away from each other, and the first recess and the second recess have a spacing along the first direction, so as to increase the thickness of the active structure along the first direction between the first recess and the second recess, and the active structure is not easy to break. The first gate structure is arranged on the first active region, spans the first recess and is spaced from the end of the first recess, and the second gate structure is arranged on the second active region, spans the second recess and is spaced from the end of the second recess, so as to avoid additional increase of the channel length opposite to the first gate structure and the second gate structure, and ensure the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a sensing amplifier. Background Technology

[0002] With the development of semiconductor technology, the application of semiconductor structures is becoming increasingly widespread. Semiconductor structures are used in memory, especially dynamic random access memory (DRAM), to improve the storage density and read / write speed of DRAM.

[0003] Dynamic random access memory (DRAM) comprises multiple memory cells, each typically including a transistor and a capacitor. The transistor's gate is connected to the word line, its drain to the bit line, and its source to the capacitor. Voltage signals on the word line control the transistor's on / off state, allowing data to be read from or written to the capacitor via the bit line.

[0004] However, semiconductor structures are prone to breakage during fabrication, which affects yield. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and a sensing amplifier to reduce disconnections and improve yield.

[0006] According to some embodiments, this disclosure provides a semiconductor structure comprising:

[0007] An active structure includes a first active region and a second active region connected along a first direction. A first recess is provided at the end of the first active region away from the second active region, and a second recess is provided at the end of the second active region away from the first active region. The first recess and the second recess are spaced apart along the first direction.

[0008] A first gate structure and a second gate structure are spaced apart along the first direction. Both the first gate structure and the second gate structure extend along the second direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess. The second gate structure is disposed on the second active region, spans the second recess, and is spaced apart from the end of the second recess. The second direction intersects the first direction.

[0009] In some possible examples, the first active region includes a first connecting portion and a plurality of first extension portions disposed at one end of the first connecting portion, the plurality of first extension portions being spaced apart along the second direction, and a first recess being formed between two adjacent first extension portions.

[0010] The second active region includes a second connecting portion and a plurality of second extension portions disposed at one end of the second connecting portion. The plurality of second extension portions are arranged at intervals along the second direction, and a second recess is formed between two adjacent second extension portions.

[0011] The first connecting part and the second connecting part are connected.

[0012] In some possible examples, the first extension includes a first portion connected to the first connection portion and a second portion connected to the first portion on the side away from the first connection portion, wherein along the second direction, the distance between adjacent first portions is greater than the distance between adjacent second portions, and the first gate structure is in contact with the corresponding first portion;

[0013] The second extension includes a third portion connected to the second connection portion and a fourth portion connected to the third portion on the side away from the second connection portion. Along the second direction, the distance between adjacent third portions is greater than the distance between adjacent fourth portions, and the second gate structure is in contact with the corresponding third portion.

[0014] In some possible examples, the first recess of the first active region is directly opposite the second recess of the second active region along the first direction.

[0015] In some possible examples, the first recess of the first active region and the second recess of the second active region are offset along the second direction.

[0016] In some possible examples, the first recess of the first active region is directly opposite the second extension of the second active region along the first direction, and the second recess of the second active region is directly opposite the first extension of the first active region along the first direction.

[0017] In some possible examples, along the second direction, the width of the first recess of the first active region is smaller than the width of the first extension of the first active region, and the width of the second recess of the second active region is smaller than the width of the extension of the second active region.

[0018] In some possible examples, along the second direction, the width of the first recess in the first active region is equal to the width of the second recess in the second active region;

[0019] And / or, along the second direction, a plurality of first recesses in the first active region are arranged at equal intervals, and a plurality of second recesses in the second active region are arranged at equal intervals.

[0020] In some possible examples, along the first direction, the length of the first extension of the first active region is greater than the length of the second extension of the second active region;

[0021] The number of first gate structures disposed on the first active region is greater than the number of second gate structures disposed on the second active region.

[0022] In some possible examples, the distance between the first recess and the second recess along the first direction ranges from 10 nm to 50 nm.

[0023] The semiconductor structure provided in this disclosure has at least the following advantages:

[0024] The semiconductor structure provided in this disclosure includes an active structure, a first gate structure, and a second gate structure. The active structure includes a first active region and a second active region connected along a first direction. A first recess is provided at the end of the first active region away from the second active region, and a second recess is provided at the end of the second active region away from the first active region. The first recess and the second recess are spaced apart along the first direction. The connection between the first and second active regions increases the thickness of the active structure between the first and second recesses along the first direction, making it less prone to breakage during the formation of the first and second recesses, thus improving the yield of the semiconductor structure. The first gate structure and the second gate structure are spaced apart along the first direction and both extend along a second direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess, avoiding contact between the first gate structure and the portion of the first active region directly opposite the first recess along the second direction. This avoids additionally increasing the relative channel length of the first gate structure and ensures the performance of the semiconductor structure. The second gate structure is disposed on the second active region, spans the second recess and is spaced apart from the end of the second recess, so as to avoid the second gate structure from contacting the part of the second active region that is directly opposite the second recess along the second direction, so as to avoid additionally increasing the relative channel length of the second gate structure and ensuring the performance of the semiconductor structure.

[0025] According to some embodiments, this disclosure also provides a sensing amplifier, including an equalization unit, a readout amplification unit, and a column selection unit; wherein the equalization unit includes the semiconductor structure described above. This sensing amplifier includes the aforementioned semiconductor structure, and therefore has at least the advantages of being less prone to breakage and having a higher yield. Specific effects are described above and will not be repeated here. Attached Figure Description

[0026] Figure 1 This is a first schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0027] Figure 2 This is a second schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 3 This is a third schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0029] Figure 4 This is a fourth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0030] Figure 5 This is a fifth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0031] Figure 6 This is a sixth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0032] Figure 7 This is a seventh schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0033] Figure 8 This is an eighth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0034] Figure 9 This is a ninth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0035] Figure 10 This is a tenth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0036] Figure 11 This is an eleventh schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0037] Figure 12 This is a twelfth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0038] Figure 13 This is a thirteenth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0039] Figure 14 This is a fourteenth schematic diagram of a semiconductor structure in one embodiment of the present disclosure;

[0040] Figure 15 This is a schematic diagram illustrating the application of a sensing amplifier in one embodiment of the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 11-First connecting part; 12-First extension part;

[0043] 13 - Part One; 14 - Part Two;

[0044] 15-The first recessed part; 21-The second connecting part;

[0045] 22 - Second extension; 23 - Third part;

[0046] 24-The fourth part; 25-The second concave part;

[0047] 30 - First gate structure; 40 - Second gate structure;

[0048] 50-bit line; 60-complementary bit line;

[0049] 70 - Equalizer unit; 71 - Third signal terminal;

[0050] 72 - Fourth signal terminal; 80 - Readout amplifier unit;

[0051] 81 - First signal terminal; 82 - Second signal terminal;

[0052] 90 - Column selection unit; 91 - Fifth signal terminal;

[0053] 100-Semiconductor structure. Detailed Implementation

[0054] A problem exists in related technologies: semiconductor structures are prone to breakage. The inventors discovered that this is because semiconductor structures have recesses, which reduce their size. During the formation of these recesses, the bottom is easily etched through, causing the semiconductor structure to break. This is especially true as semiconductor dimensions shrink, making it even easier to etch through the bottom of the recesses, leading to increased breakage and reduced yield.

[0055] This disclosure provides a semiconductor structure including an active structure, a first gate structure, and a second gate structure. The active structure includes a first active region and a second active region connected along a first direction. A first recess and a second recess are respectively disposed at opposite ends of the first and second active regions, and the first and second recesses are spaced apart along the first direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess. The second gate structure is disposed on the second active region, spans the second recess, and is spaced apart from the end of the second recess. The connection between the first and second active regions increases the thickness of the active structure between the first and second recesses along the first direction. When the first and second recesses are formed, the active structure is less likely to break, thus improving the yield of the semiconductor structure.

[0056] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0057] See Figure 1 This disclosure provides a semiconductor structure 100, which includes an active structure AS, a first gate structure 30, and a second gate structure 40. The active structure AS includes a first active region and a second active region, the first active region... Figure 1 As shown at point A, the second active region is as follows: Figure 1 As shown at point B. The first active region and the second active region are connected along the first direction, and the opposite ends of the first active region and the second active region are connected to form a single unit. The first direction is as follows: Figure 1 Y direction shown in .

[0058] A first recess 15 is provided at the end of the first active region A that is away from the second active region B, and a second recess 25 is provided at the end of the second active region B that is away from the first active region A. That is, the first recess 15 and the second recess 25 are respectively provided at the ends of the first active region A and the second active region B that are opposite to each other. The opening of the first recess 15 is away from the second active region B, and the bottom of the first recess 15 is close to the second active region B. The opening of the second recess 25 is away from the first active region A, and the bottom of the second recess 25 is close to the first active region A.

[0059] The first recess 15 and the second recess 25 are spaced apart by a distance D along the first direction, that is, the ends of the first recess 15 and the second recess 25 are spaced apart along the first direction Y. The sum of the depths of the first recess 15 and the second recess 25 along the first direction Y is less than the sum of the widths of the first active region A and the second active region B along the first direction.

[0060] The method for forming a semiconductor structure provided in this disclosure includes: providing a substrate, forming a mask pattern on the substrate, etching the substrate based on the mask pattern to form an active structure, filling a shallow trench isolation structure, and forming a first gate structure and a second gate structure on the active structure and the shallow trench isolation structure. The shallow trench isolation structure fills a first recess and a second recess defined by the active structure. The shallow trench isolation structure can be a low-dielectric-constant material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing coupling between transistors formed based on the active structure.

[0061] With this configuration, compared to a single first active region A and a single first recess 15, or a single second active region B and a single second recess 25, the first active region A and the second active region B are connected, and the bottom portion of the first active region A and the bottom portion of the second active region B of the first recess 15 are connected. This increases the thickness of the active structure AS between the first recess 15 and the second recess 25 along the first direction, making it less likely for the active structure AS to break when the first recess 15 and the second recess 25 are formed, thus improving the yield of the semiconductor structure.

[0062] Furthermore, while ensuring the continuity of the active structure AS, the critical dimension (CD) of the active structure AS can be further reduced. For example, the critical dimension of the first active region A opposite to the first recess 15 can be less than 50 nm, and the critical dimension of the second active region A opposite to the second recess 25 can be less than 50 nm.

[0063] For example, such as Figure 1 As shown, the first direction is the Y direction, and the first active region A and the second active region B are connected at their end faces along the Y direction. One end of the first active region A is connected to one end of the second active region B. The other end of the first active region A has a first recess 15, the opening of which faces away from the second active region B. The other end of the second active region B has a second recess 25, the opening of which faces away from the first active region A.

[0064] In some possible examples, the distance D between the first recess 15 and the second recess 25 along the first direction Y ranges from 10 nm to 50 nm. The distance between the first recess 15 and the second recess 25 along the first direction is greater than or equal to 10 nm and less than or equal to 50 nm, i.e., 10 nm ≤ D ≤ 50 nm. This configuration avoids the distance D between the first recess 15 and the second recess 25 along the first direction Y being too small, thereby preventing the active structure AS from being broken along the first direction when forming the first recess 15 and the second recess 25. Simultaneously, it also avoids the distance D between the first recess 15 and the second recess 25 along the first direction Y being too large, thereby improving the space utilization of the semiconductor structure.

[0065] Continue reading Figure 1 The first gate structure 30 and the second gate structure 40 are spaced apart along the first direction Y and both extend along the second direction X. The first gate structure 30 is disposed on the first active region A, spans the first recess 15 and is spaced apart from the end of the first recess 15. The second gate structure 40 is disposed on the second active region B, spans the second recess 25 and is spaced apart from the end of the second recess 25. The second direction X intersects the first direction Y, for example, perpendicularly. The second direction X can be as follows: Figure 1 The X direction is shown in the diagram. The second direction X and the first direction Y are parallel to the plane containing the substrate.

[0066] The first recess 15 includes an opening and a bottom. A first gate structure 30 extends across the first recess 15 along the second direction X, and its two side walls along the first direction Y are spaced apart from the corresponding ends of the first recess 15. The first gate structure 30 is spaced apart from the portion of the first active region A (i.e., the first active region at the bottom of the first recess 15) directly opposite the first recess 15 along the first direction Y, thus preventing the first gate structure 30 from contacting the portion of the first active region directly opposite the first recess 15 along the first direction, thereby avoiding additional increase in the relative channel length of the first gate structure 30.

[0067] The end portion of the second recess 25 includes an opening and a bottom. The first gate structure 30 extends across the second recess 25 along the second direction X, and the side walls of the second gate structure 40 along the first direction Y are spaced apart from the corresponding ends of the second recess 25. The second gate structure 40 is spaced apart from the portion of the second active region B (i.e., the second active region at the bottom of the second recess 25) directly opposite the second recess 25 along the first direction Y, thus preventing the second gate structure 40 from contacting the portion of the second active region directly opposite the second recess 25 along the first direction, thereby avoiding additional increase in the relative channel length of the second gate structure 40.

[0068] Continue reading Figure 1 The first active region A includes a first connecting portion 11 and a plurality of first extension portions 12 disposed at one end of the first connecting portion 11. The plurality of first extension portions 12 are arranged at intervals along the second direction X, and a first recess 15 is formed between two adjacent first extension portions 12. The second active region B includes a second connecting portion 21 and a plurality of second extension portions 22 disposed at one end of the second connecting portion 21. The plurality of second extension portions 22 are arranged at intervals along the second direction X, and a second recess 25 is formed between two adjacent second extension portions 22. The first connecting portion 11 and the second connecting portion 21 are connected.

[0069] In this configuration, the first connecting portion 11 and the second connecting portion 21 are connected at opposite ends, a plurality of first extension portions 12 are disposed at the end of the first connecting portion 11 away from the second connecting portion 21, and a plurality of second extension portions 22 are disposed at the end of the second connecting portion 21 away from the first connecting portion 11.

[0070] A plurality of first extensions 12 are arranged at intervals along a second direction X, and a first recess 15 is formed between two adjacent first extensions 12 along the second direction X. For example, at least two first recesses 15 may be formed. A plurality of second extensions 22 are arranged at intervals along the second direction X, and a second recess 25 is formed between two adjacent second extensions 22 along the second direction. For example, at least two second recesses 25 may be formed. This arrangement can improve the integration density of the semiconductor structure.

[0071] It is understood that the first gate structure 30 contacts the plurality of first extensions 12 along the second direction X, and is spaced apart from the first connection portion 11 along the first direction Y, that is, the first gate structure 30 and the first connection portion 11 are not in contact. The second gate structure 40 contacts the plurality of second extensions 22 along the second direction X, and is spaced apart from the second connection portion 21 along the first direction Y, that is, the second gate structure 40 and the second connection portion 21 are not in contact.

[0072] See some possible examples. Figure 1 The first extension 12 includes a first portion 13 connected to the first connecting portion 11, and a second portion 14 connected to the side of the first portion 13 away from the first connecting portion 11. The first portion 13 is connected between the first connecting portion 11 and the second portion 14, with one end of the first portion 13 connected to the first connecting portion 11 and the other end of the first portion 13 connected to the second portion 14.

[0073] Along the second direction X, the distance between adjacent first portions 13 is greater than the distance between adjacent second portions 14, and the first gate structure 30 is in contact with the corresponding first portion 13. The width of the first portion 13 along the second direction X is less than the width of the second portion 14 along the second direction X, and the two opposite ends of the second portion 14 along the second direction X protrude beyond the two opposite ends of the first portion 13 along the second direction X.

[0074] like Figure 1 As shown, the left end of the first part 13 is located to the left of the left end of the second part 14, and the right end of the first part 13 is located to the right of the right end of the second part 14. The first gate structure 30 is opposite to the first part 13 along a direction perpendicular to the plane of the substrate, and is spaced apart from both the second part 14 and the first connection part 11, that is, the first gate structure 30 is spaced apart from both the second part 14 and the first connection part 11.

[0075] Continue reading Figure 1 The second extension 22 includes a third portion 23 connected to the second connecting portion 21, and a fourth portion 24 connected to the side of the third portion 23 away from the second connecting portion 21. The third portion 23 is connected between the second connecting portion 21 and the fourth portion 24, with one end of the third portion 23 connected to the second connecting portion 21 and the other end of the third portion 23 connected to the fourth portion 24.

[0076] Along the second direction, the distance between adjacent third portions 23 is greater than the distance between adjacent fourth portions 24, and the second gate structure 40 is in contact with the corresponding third portion 23. The width of the third portion 23 along the second direction is less than the width of the fourth portion 24 along the second direction, and the opposite ends of the fourth portion 24 along the second direction protrude beyond the opposite ends of the third portion 23 along the second direction.

[0077] like Figure 1 As shown, the left end of the third part 23 is located to the left of the left end of the fourth part 24, and the right end of the third part 23 is located to the right of the right end of the fourth part 24. The second gate structure 40 is opposite to the third part 23, and is staggered from both the fourth part 24 and the second connecting part 21, that is, the second gate structure 40 is spaced apart from both the fourth part 24 and the second connecting part 21.

[0078] It is understandable that, at least in a GDS (Graphic Design System, a data conversion format for integrated circuit layouts) layout, along the second direction, the distance between adjacent first portions 13 is greater than the distance between adjacent second portions 14, and the distance between adjacent third portions 23 is greater than the distance between adjacent fourth portions 24. After actual development inspection (ADI) or etching inspection (AEI), it is possible that along the second direction X, the distance between adjacent first portions 13 is greater than the distance between adjacent second portions 14, and the distance between adjacent third portions 23 is greater than the distance between adjacent fourth portions 24. Alternatively, it is possible that along the second direction X, the distance between adjacent first portions 13 is less than the distance between adjacent second portions 14, and / or the distance between adjacent third portions 23 is less than the distance between adjacent fourth portions 24.

[0079] See some possible examples. Figures 2 to 4 The first recess 15 of the first active region A is directly opposite the second recess 25 of the second active region along the first direction Y, that is, along the first direction, the first recess 15 and the second recess 25 are directly opposite each other.

[0080] like Figure 2 As shown, in some possible implementations, along the second direction X, the width of the first recess 15 is equal to the width of the second recess 25, the two sides of the first recess 15 are aligned with the two sides of the second recess 25 respectively, and the first recess 15 and the second recess 25 are axially symmetrically distributed.

[0081] like Figure 3 As shown, in some other possible implementations, along the second direction, the width of the first recess 15 is greater than the width of the second recess 25, and the two sides of the first recess 15 are located outside the two sides of the second recess 25, respectively.

[0082] like Figure 4 As shown, in some other possible implementations, along the first direction, the width of the first recess 15 is smaller than the width of the second recess 25, and the two sides of the first recess 15 are respectively located between the two sides of the second recess 25.

[0083] In some other possible examples, see Figures 5 to 7 The first recess 15 of the first active region A and the second recess 25 of the second active region B are offset along the second direction X, that is, along the second direction X, the first recess 15 and the second recess 25 are at least partially offset. The projections of the first recess 15 and the second recess 25 in the first direction Y only partially overlap. With this arrangement, the portion of the second recess 25 that is offset from the first recess 15 also faces a portion of the first active region A, increasing the thickness of the active structure and making it less likely for the active structure to break along the second direction. The portion of the first recess 15 that is offset from the second recess 25 also faces a portion of the second extension 22 of the second active region B along the first direction Y, increasing the thickness of the connecting portion of the active structure and making it less likely for the active structure to break along the second direction.

[0084] Based on the above examples, such as Figure 5 As shown, in some possible implementations, with respect to projection along the first direction Y, one of the two sidewalls of the first recess 15 is between the two sidewalls of the second recess 25, and the other sidewall is outside the two sidewalls of the second recess 25, with the first recess 15 and the second recess 25 partially offset.

[0085] Based on the above examples, such as Figure 6 As shown, in some other possible implementations, with respect to projection along the first direction Y, the two sidewalls of the first recess 15 are on the same side of the two sidewalls of the second recess 25, the first recess 15 and the second recess 25 are completely offset and spaced apart along the first direction.

[0086] Based on the above examples, such as Figure 7 As shown, in some possible implementations, the first recess 15 of the first active region A is directly opposite the second extension 22 of the second active region B along the first direction Y, and the second recess 25 of the second active region B is directly opposite the first extension 12 of the first active region A along the first direction Y. The first recess 15 and the second recess 25 are completely offset and are sequentially adjacent along the second direction X. For example, the first recess 15 has a second recess 25 on both its left and right sides, the left side wall of the first recess 15 is flush with the right side wall of the second recess 25 on its left side, and the right side wall of the first recess 15 is flush with the left side wall of the second recess 25 on its right side.

[0087] See Figure 5 and Figure 6In some possible examples, along the second direction, the width of the first recess 15 of the first active region A is smaller than the width of the first extension 12 of the first active region A, and the width of the second recess 25 of the second active region B is smaller than the width of the second extension 22 of the second active region B. This configuration, with a smaller width of the first recess 15, can improve the transistor integration density formed in the first active region A; and with a smaller width of the second recess 25, can improve the transistor integration density formed in the second active region B.

[0088] See Figure 8 In some possible examples, along the second direction X, the width of the first recess 15 of the first active region A is greater than the width of the first extension 12 of the first active region A, and the width of the second recess 25 of the second active region B is greater than the width of the second extension 22 of the second active region B. This configuration, with a larger width of the first recess 15, results in a larger spacing between adjacent first extensions 12, which can reduce interference between adjacent transistors formed in the first active region A. Similarly, the larger width of the second recess 25 results in a larger spacing between adjacent second extensions 22, which can reduce interference between adjacent transistors formed in the second active region B.

[0089] In some possible examples, along the second direction X, the width of the first recess 15 of the first active region A is equal to the width of the second recess 25 of the second active region B. With this configuration, along the second direction X, the spacing between adjacent first extensions 12 is equal to the spacing between adjacent second extensions 22, resulting in the same interference effect between adjacent transistors in the first active region A and the same interference effect between adjacent transistors in the second active region B.

[0090] In some possible examples, along the second direction, a plurality of first recesses 15 of the first active region A are arranged at equal intervals, and a plurality of second recesses 25 of the second active region B are arranged at equal intervals. With this arrangement, along the second direction X, the widths of the plurality of first extensions 12 are the same, resulting in better consistency of the transistors formed in the first active region A. Similarly, along the second direction X, the widths of the plurality of second extensions 22 are the same, resulting in better consistency of the transistors formed in the second active region B.

[0091] For example, see Figure 9Along the second direction X, the width L1 of the first recess 15 is equal to the width L2 of the second recess 25. Multiple first recesses 15 in the first active region A are arranged at equal intervals, and multiple second recesses 25 in the second active region B are arranged at equal intervals. The distance L3 between adjacent first recesses 15 is equal to the distance L4 between adjacent second recesses 25, i.e., L1 = L2, L3 = L4. The width L1 of the first recess 15 is the distance between adjacent first extensions 12, the width L2 of the second recess 25 is the distance between adjacent second extensions 22, the distance L3 between adjacent first recesses 15 is the width of the first extension 12, and the distance L4 between adjacent second recesses 25 is the width of the second extension 22. With this configuration, along the second direction X, the width of the first extension 12 and the width of the second extension 22 are equal, and the spacing between adjacent first extensions 12 is equal to the spacing between adjacent second extensions 22. The transistors formed in the first active region A and the transistors formed in the second active region B have equal channel lengths and are arranged in the same way, resulting in a better equalization effect.

[0092] For another example, see Figure 10 Along the second direction X, the width L1 of the first recess 15 is greater than or less than the width L2 of the second recess 25. Multiple first recesses 15 in the first active region A are arranged at equal intervals, and multiple second recesses 25 in the second active region B are arranged at equal intervals. The distance L3 between adjacent first recesses 15 is equal to the distance L4 between adjacent second recesses 25, i.e., L1≠L2, L3=L4. With this configuration, along the second direction X, the width of the first extension 12 and the width of the second extension 22 are equal, but the distance between adjacent first extensions 12 is unequal to the distance between adjacent second extensions 22. The transistors formed in the first active region A and the transistors formed in the second active region B have the same channel length but different intervals.

[0093] For example, see [link to relevant document]. Figure 11 Along the second direction X, the width L1 of the first recess 15 is equal to the width L2 of the second recess 25. Multiple first recesses 15 in the first active region A are arranged at equal intervals, and multiple second recesses 25 in the second active region B are arranged at equal intervals. The distance L3 between adjacent first recesses 15 is unequal to the distance L4 between adjacent second recesses 25, i.e., L1 = L2, L3 ≠ L4. With this configuration, along the second direction X, the widths of the first extension 12 and the second extension 22 are unequal, and the distance between adjacent first extensions 12 is equal to the distance between adjacent second extensions 22. The transistors formed in the first active region A and the transistors formed in the second active region B have different channel lengths, but the spacing between them is the same.

[0094] For another example, see [link to relevant documentation]. Figure 12Along the second direction X, the width L1 of the first recess 15 is not equal to the width L2 of the second recess 25. Multiple first recesses 15 in the first active region A are arranged at equal intervals, and multiple second recesses 25 in the second active region B are arranged at equal intervals. Furthermore, the distance L3 between adjacent first recesses 15 is not equal to the distance L4 between adjacent second recesses 25, i.e., L1≠L2, L3≠L4. With this configuration, along the second direction X, the width of the first extension 12 and the width of the second extension 22 are not equal, and the distance between adjacent first extensions 12 is not equal to the distance between adjacent second extensions 22. Therefore, the transistors formed in the first active region A and the transistors formed in the second active region B have different channel lengths and different intervals.

[0095] It is understood that in the above example, along the first direction Y, the first recess 15 and the second recess 25 are of equal width, adjacent first recesses 15 are of equal width, and adjacent second recesses 25 are of equal width; that is, both the first recess 15 and the second recess 25 are rectangular. When the first recess 15 and the second recess 25 are of other shapes, the width of the first recess 15 and the width of the second recess 25 refer to the width of the first recess 15 and the width of the second recess 25 respectively at the same distance along the first direction Y from the bottom of the first recess 15 and the bottom of the second recess 25.

[0096] See Figure 13 and Figure 14 Multiple first gate structures 30 can be provided on the first active region A, so that multiple transistors formed in the first active region A share a common source / drain, thereby improving the integration density of the transistors. At least one second gate structure 40 can be provided on the second active region B, so that multiple transistors formed in the second active region B share a common source / drain, thereby improving the integration density of the transistors.

[0097] In some possible examples, such as Figure 13 and Figure 14 As shown, along the first direction Y, the length of the first extension 12 of the first active region A is greater than the length of the second extension 22 of the second active region B. The number of first gate structures 30 disposed on the first active region A is greater than the number of second gate structures 40 disposed on the second active region B. With this configuration, along the first direction Y, the length of the first extension 12 is longer and the depth of the first recess 15 is greater. Compared to the second extension 22 and the second recess 25, more first gate structures 30 can be disposed on the first extension 12 and the first recess 15, improving the space utilization of the semiconductor structure.

[0098] In summary, the semiconductor structure provided in this embodiment includes an active structure AS, a first gate structure 30, and a second gate structure 40. The active structure AS includes a first active region and a second active region connected along a first direction. A first recess 15 is provided at the end of the first active region away from the second active region, and a second recess 25 is provided at the end of the second active region away from the first active region. The first recess 15 and the second recess 25 are spaced apart along the first direction. The connection between the first and second active regions increases the thickness of the active structure between the first recess 15 and the second recess 25 along the first direction, making it less likely for the active structure to break during the formation of the first recess 15 and the second recess 25, thus improving the yield of the semiconductor structure. The first gate structure 30 and the second gate structure 40 are spaced apart along the first direction and both extend along a second direction. The first gate structure 30 is disposed on the first active region, spans the first recess 15, and is spaced apart from the end of the first recess 15. This prevents the first gate structure 30 from contacting the portion of the first active region of the first recess 15 that faces the first active region along the second direction, thereby avoiding an additional increase in the relative channel length of the first gate structure 30 and ensuring the performance of the semiconductor structure. The second gate structure 40 is disposed on the second active region, spans the second recess 25, and is spaced apart from the end of the second recess 25. This prevents the second gate structure 40 from contacting the portion of the second active region of the second recess 25 that faces the second active region along the second direction, thereby avoiding an additional increase in the relative channel length of the second gate structure 40 and ensuring the performance of the semiconductor structure.

[0099] This disclosure also provides a sense amplifier (SA), see [link to relevant documentation]. Figure 15 The sensing amplifier includes an equalization unit 70, a readout amplification unit 80, and a column selection unit 90. The equalization unit 70 includes the aforementioned semiconductor structure. The sensing amplifier can be applied to a dynamic random access memory (DRAM), which performs data writing and reading operations through capacitor cells.

[0100] An equalization unit 70, a readout amplification unit 80, and a column selection unit 90 are connected between bit line 50 and complementary bit line 60. During the pre-charging phase of the read operation, the equalization unit 70 stabilizes bit line 50 and complementary bit line 60 at a reference voltage based on the equalization signal. The readout amplification unit 80 reads and amplifies the voltage difference between bit line 50 and complementary bit line 60. The column selection unit 90 is used to select the corresponding bit line 50.

[0101] In some possible examples, the readout amplification unit 80 includes a first P-type transistor T1, a second P-type transistor T2, a first N-type transistor T3, and a second N-type transistor T4. The first P-type transistor T1 is connected between the first signal terminal 81 and the bit line 50, and has a control terminal connected to the complementary bit line 60. The second P-type transistor T2 is connected between the first signal terminal 81 and the complementary bit line 60, and has a control terminal connected to the bit line 50. The first N-type transistor T3 is connected between the second signal terminal 82 and the bit line 50, and has a control terminal connected to the complementary bit line 60. The second N-type transistor T4 is connected between the second signal terminal 82 and the complementary bit line 60, and has a control terminal connected to the bit line 50.

[0102] Specifically, the source of the first P-type transistor T1 is connected to the first signal terminal 81, the drain is connected to bit line 50, and the gate is connected to the complementary bit line 60. The source of the second P-type transistor T2 is connected to the first signal terminal 81, the drain is connected to the complementary bit line 60, and the gate is connected to bit line 50. The source of the first N-type transistor T3 is connected to the second signal terminal 82, the drain is connected to bit line 50, and the gate is connected to the complementary bit line 60. The source of the second N-type transistor T4 is connected to the second signal terminal 82, the drain is connected to the complementary bit line 60, and the gate is connected to bit line 50. The first signal terminal 81 receives the first level signal SAP, and the second signal terminal 82 receives the second level signal SAN.

[0103] In some possible examples, the voltage of the first level signal SAP is greater than the voltage of the second level signal SAN. For example, the first level signal SAP is a high level corresponding to logic "1", and the second level signal SAN is a low level corresponding to logic "0". In other examples, the voltage of the first level signal SAP is less than the voltage of the second level signal SAN, that is, the first level signal SAP is a low level corresponding to logic "0", and the second level signal SAN is a high level corresponding to logic "1".

[0104] The equalization unit 70 includes a first transistor T5, a second transistor T6, and a third transistor T7, and each of these transistors has a control terminal for receiving the equalization signal EQ. The first transistor T5 is connected between the third signal terminal 71 and the bit line 50, and has a control terminal connected to the fourth signal terminal 72. The second transistor T6 is connected between the third signal terminal 71 and the complementary bit line 60, and has a control terminal connected to the fourth signal terminal 72. The third transistor T7 is connected between the bit line 50 and the complementary bit line 60, and has a control terminal connected to the fourth signal terminal 72. The fourth signal terminal 72 receives the equalization signal EQ.

[0105] Specifically, the source of the first transistor T5 is connected to bit line 50, the drain is connected to the third signal terminal 71, and the gate is connected to the fourth signal terminal 72. The source of the second transistor T6 is connected to the complementary bit line 60, the drain is connected to the third signal terminal 71, and the gate is connected to the fourth signal terminal 72. The source of the third transistor T7 is connected to bit line 50, the drain is connected to the complementary bit line 60, and the gate is connected to the fourth signal terminal 72.

[0106] The column selection unit 90 includes a fourth transistor T8 and a fifth transistor T9, which are respectively disposed on bit line 50 and complementary bit line 60, and each has a control terminal for receiving a strobe signal. The fourth transistor T8 is located on bit line 50 and has a control terminal connected to a fifth signal terminal 91. The fifth transistor T9 is located on complementary bit line 60 and has a control terminal connected to a fifth signal terminal 91. The fifth signal terminal 91 receives the strobe signal SCL.

[0107] It should be noted that the specific connection methods of the "source" and "drain" of each transistor defined above do not constitute a limitation on the embodiments of this disclosure. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used.

[0108] During the data reading process of the dynamic random access memory, a pre-charge phase is first performed to pre-charge bit line 50 and complementary bit line 60 to a preset voltage V. ref Then proceed to the next stage, such as the data reading stage.

[0109] During the pre-charging phase, an equalization signal EQ is provided to turn on the first transistor T5, the second transistor T6, and the third transistor T7. After the first transistor T5, the second transistor T6, and the third transistor T7 are turned on, the voltage of bit line 50 and complementary bit line 60 is stabilized at a preset voltage V. ref Up. Preset voltage V ref The voltage received by the third signal terminal 71, in this embodiment of the disclosure, is V. ref =1 / 2V DD V DD This is the internal power supply voltage of the dynamic random access memory; in other embodiments, the preset voltage V... ref It can be configured according to the specific application scenario.

[0110] In summary, the sensing amplifier in this embodiment includes an equalization unit 70, a readout amplification unit 80, and a column selection unit 90, with the equalization unit 70 comprising the aforementioned semiconductor structure. This sensing amplifier, including the aforementioned semiconductor structure, possesses at least the advantages of being less prone to breakage and having a higher yield rate. Specific effects are described above and will not be repeated here.

[0111] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: An active structure includes a first active region and a second active region connected along a first direction. A first recess is provided at the end of the first active region away from the second active region, and a second recess is provided at the end of the second active region away from the first active region. The first recess and the second recess are spaced apart along the first direction. A first gate structure and a second gate structure are spaced apart along the first direction. Both the first gate structure and the second gate structure extend along the second direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess. The second gate structure is disposed on the second active region, spans the second recess, and is spaced apart from the end of the second recess. The second direction intersects the first direction. The first recess of the first active region and the second recess of the second active region are offset along the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The first active region includes a first connecting portion and a plurality of first extension portions disposed at one end of the first connecting portion. The plurality of first extension portions are arranged at intervals along the second direction, and a first recess is formed between two adjacent first extension portions. The second active region includes a second connecting portion and a plurality of second extension portions disposed at one end of the second connecting portion. The plurality of second extension portions are arranged at intervals along the second direction, and a second recess is formed between two adjacent second extension portions. The first connecting part and the second connecting part are connected.

3. The semiconductor structure according to claim 2, characterized in that, The first extension includes a first portion connected to the first connection portion and a second portion connected to the first portion on the side away from the first connection portion. Along the second direction, the distance between adjacent first portions is greater than the distance between adjacent second portions, and the first gate structure is in contact with the corresponding first portion. The second extension includes a third portion connected to the second connection portion and a fourth portion connected to the third portion on the side away from the second connection portion. Along the second direction, the distance between adjacent third portions is greater than the distance between adjacent fourth portions, and the second gate structure is in contact with the corresponding third portion.

4. The semiconductor structure according to claim 2, characterized in that, The first recess of the first active region is directly opposite the second extension of the second active region along the first direction, and the second recess of the second active region is directly opposite the first extension of the first active region along the first direction.

5. The semiconductor structure according to any one of claims 2-4, characterized in that, Along the second direction, the width of the first recess of the first active region is smaller than the width of the first extension of the first active region, and the width of the second recess of the second active region is smaller than the width of the second extension of the second active region.

6. The semiconductor structure according to any one of claims 1-4, characterized in that, Along the second direction, the width of the first recess in the first active region is equal to the width of the second recess in the second active region; And / or, along the second direction, a plurality of first recesses in the first active region are arranged at equal intervals, and a plurality of second recesses in the second active region are arranged at equal intervals.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, Along the first direction, the length of the first extension of the first active region is greater than the length of the second extension of the second active region; The number of first gate structures disposed on the first active region is greater than the number of second gate structures disposed on the second active region.

8. The semiconductor structure according to any one of claims 1-4, characterized in that, The distance between the first recess and the second recess along the first direction ranges from 10 nm to 50 nm.

9. A semiconductor structure, characterized in that, include: An active structure includes a first active region and a second active region connected along a first direction. A first recess is provided at the end of the first active region away from the second active region, and a second recess is provided at the end of the second active region away from the first active region. The first recess and the second recess are spaced apart along the first direction. A first gate structure and a second gate structure are spaced apart along the first direction. Both the first gate structure and the second gate structure extend along the second direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess. The second gate structure is disposed on the second active region, spans the second recess, and is spaced apart from the end of the second recess. The second direction intersects the first direction. Along the first direction, the length of the first extension of the first active region is greater than the length of the second extension of the second active region.

10. The semiconductor structure according to claim 9, characterized in that, The number of first gate structures disposed on the first active region is greater than the number of second gate structures disposed on the second active region.

11. The semiconductor structure according to claim 9, characterized in that, The first active region includes a first connecting portion and a plurality of first extension portions disposed at one end of the first connecting portion. The plurality of first extension portions are arranged at intervals along the second direction, and a first recess is formed between two adjacent first extension portions. The second active region includes a second connecting portion and a plurality of second extension portions disposed at one end of the second connecting portion. The plurality of second extension portions are arranged at intervals along the second direction, and a second recess is formed between two adjacent second extension portions. The first connecting part and the second connecting part are connected.

12. The semiconductor structure according to claim 11, characterized in that, The first extension includes a first portion connected to the first connection portion and a second portion connected to the first portion on the side away from the first connection portion. Along the second direction, the distance between adjacent first portions is greater than the distance between adjacent second portions, and the first gate structure is in contact with the corresponding first portion. The second extension includes a third portion connected to the second connection portion and a fourth portion connected to the third portion on the side away from the second connection portion. Along the second direction, the distance between adjacent third portions is greater than the distance between adjacent fourth portions, and the second gate structure is in contact with the corresponding third portion.

13. The semiconductor structure according to any one of claims 9-12, characterized in that, Along the second direction, the width of the first recess of the first active region is smaller than the width of the first extension of the first active region, and the width of the second recess of the second active region is smaller than the width of the extension of the second active region.

14. A semiconductor structure, characterized in that, include: An active structure includes a first active region and a second active region connected along a first direction. A first recess is provided at the end of the first active region away from the second active region, and a second recess is provided at the end of the second active region away from the first active region. The first recess and the second recess are spaced apart along the first direction. A first gate structure and a second gate structure are spaced apart along the first direction. Both the first gate structure and the second gate structure extend along the second direction. The first gate structure is disposed on the first active region, spans the first recess, and is spaced apart from the end of the first recess. The second gate structure is disposed on the second active region, spans the second recess, and is spaced apart from the end of the second recess. The second direction intersects the first direction. The first active region includes a first connecting portion and a plurality of first extension portions disposed at one end of the first connecting portion. The plurality of first extension portions are arranged at intervals along the second direction, and a first recess is formed between two adjacent first extension portions. The second active region includes a second connecting portion and a plurality of second extension portions disposed at one end of the second connecting portion. The plurality of second extension portions are arranged at intervals along the second direction, and a second recess is formed between two adjacent second extension portions. The first connecting portion and the second connecting portion are connected along the second direction. The width of the first recess of the first active region is smaller than the width of the first extension of the first active region, and the width of the second recess of the second active region is smaller than the width of the second extension of the second active region.

15. A sensing amplifier, comprising an equalization unit, a readout amplification unit, and a column selection unit; in, The equalization unit includes a semiconductor structure as described in any one of claims 1-14.

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