Memory cell, memory and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a storage unit, a memory and a manufacturing method thereof, wherein the storage unit comprises: a gate conductive part extending along a first direction; a first dielectric layer arranged on a part of the surface of the gate conductive part around the gate conductive part along the first direction; a channel layer located on the first dielectric layer; a second dielectric layer located on the channel layer; a first word line located on the second dielectric layer; a bit line located at one end of the gate conductive part along the first direction and spaced from the gate conductive part, and connected with the channel layer; a capacitor located at the other end of the gate conductive part away from the bit line and spaced from the gate conductive part, and connected with the channel layer; and a second word line connected with the gate conductive part. The performance of the storage unit can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a memory cell, a memory and a manufacturing method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, which is composed of a plurality of repeated memory cells. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected with a word line, the drain is connected with a bit line, and the source is connected with the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, thereby reading the data information stored in the capacitor through the bit line or writing the data information into the capacitor for storage through the bit line.

[0003] It is necessary to improve the performance of the memory. SUMMARY

[0004] Embodiments of the present disclosure provide a memory cell, a memory and a manufacturing method thereof, which can at least improve the performance of the memory cell.

[0005] According to some embodiments of the present disclosure, in one aspect, a memory cell is provided, comprising: a gate conductive part, the gate conductive part extending along a first direction; a first dielectric layer, the first dielectric layer being arranged on a part of the surface of the gate conductive part around the gate conductive part along the first direction as an axis; a channel layer, the channel layer being located on the first dielectric layer; a second dielectric layer, the second dielectric layer being located on the channel layer; a first word line, the first word line being located on the second dielectric layer; a bit line, the bit line being located at one end of the gate conductive part along the first direction and being spaced apart from the gate conductive part, the bit line being connected with the channel layer; a capacitor, the capacitor being located at the other end of the gate conductive part away from the bit line and being spaced apart from the gate conductive part, the capacitor being connected with the channel layer; and a second word line, the second word line being connected with the gate conductive part.

[0006] In some embodiments, the material of the channel layer comprises indium gallium zinc oxide or zinc tin oxide.

[0007] In some embodiments, the material of the first dielectric layer is different from the material of the second dielectric layer, and the relative dielectric constant of the material of the second dielectric layer is greater than the relative dielectric constant of the material of the first dielectric layer.

[0008] In some embodiments, the boundary of the first dielectric layer in the first direction is aligned with the boundary of the gate conductive part.

[0009] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a memory, comprising: the memory cell as described above, and the memory cells are arranged along a second direction and a third direction, the first direction, the second direction and the third direction being different.

[0010] In some embodiments, the memory cells arranged along the second direction share the bit line, and / or the memory cells arranged along the third direction share the first word line and the second word line.

[0011] According to some embodiments of the present disclosure, still another aspect of the embodiments of the present disclosure further provides a manufacturing method of a memory, comprising: forming a plurality of memory cells arranged along a second direction and a third direction, the method of forming the memory cell comprising: forming a gate conductive part, the gate conductive part extending along a first direction; forming a first dielectric layer, the first dielectric layer being arranged on a part of the surface of the gate conductive part around the first direction; forming a channel layer, the channel layer being located on the first dielectric layer; forming a second dielectric layer, the second dielectric layer being located on the channel layer; forming a first word line, the first word line being located on the second dielectric layer; forming a bit line, the bit line being located at one end of the gate conductive part along the first direction and spaced apart from the gate conductive part, the bit line being connected with the channel layer; forming a capacitor, the capacitor being located at the other end of the gate conductive part away from the bit line and spaced apart from the gate conductive part, the capacitor being connected with the channel layer; and forming a second word line, the second word line being connected with the gate conductive part.

[0012] In some embodiments, the method of forming the gate conductive part comprises: providing a stack structure, the stack structure comprising an insulating layer and an initial gate conductive part arranged in layers; etching the stack structure, the remaining stack structure comprising a first part extending along the first direction and a second part extending along the second direction; etching the initial gate conductive part of the second part and part of the initial gate conductive part of the first part, the remaining initial gate conductive part serving as the gate conductive part.

[0013] In some embodiments, the method of forming the first word line comprises: etching part of the insulating layer in contact with the gate conductive part to form a first recess; forming the first dielectric layer, the first dielectric layer covering the inner wall of the first recess and part of the surface of the gate conductive part; forming the channel layer, the channel layer covering the surface of the first dielectric layer; forming the second dielectric layer, the second dielectric layer covering the surface of the channel layer; and forming the first word line, the first word line covering the surface of the second dielectric layer.

[0014] In some embodiments, the method further comprises, before forming the first groove, forming an initial isolation layer covering surfaces of the insulating layer exposed by etching the initial gate conductive portion, wherein the method comprises: etching the initial isolation layer of the second portion and part of the initial isolation layer of the first portion, leaving the initial isolation layer as an isolation layer covering sidewalls of the gate conductive portion arranged along the first direction; forming the bit line in contact with the isolation layer on one side of the gate conductive portion; and forming the capacitor in contact with the isolation layer on the other side of the gate conductive portion.

[0015] The technical scheme provided by the embodiment of the present disclosure has at least the following advantages: by arranging the first dielectric layer to surround part of the surface of the gate conductive portion, and then arranging the channel layer, the facing area of the gate conductive portion and the channel layer can be increased, so that the control ability of the gate conductive portion is increased; by arranging the first word line and the second word line to control the conduction path between the bit line and the capacitor to be turned off, the conductivity of the channel layer can be increased on the one hand, and the turning-off effect of the channel layer can be better on the other hand. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified; in order to make the technical scheme of the embodiments of the present disclosure or the prior art clearer, a brief introduction will be given to the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0017] Figure 1 A structural schematic diagram of a storage unit provided by an embodiment of the present disclosure is shown in the figure.

[0018] Figure 2 Another structural schematic diagram of a storage unit provided by an embodiment of the present disclosure is shown in the figure.

[0019] Figure 3 A sectional structural schematic diagram of a storage unit provided by an embodiment of the present disclosure is shown in the figure.

[0020] Figure 4 Another sectional structural schematic diagram of a storage unit provided by an embodiment of the present disclosure is shown in the figure.

[0021] Figure 5 A structural schematic diagram of a storage unit provided by an embodiment of the present disclosure is shown in the figure.

[0022] Figures 6 to 25A structure diagram corresponding to each step of a manufacturing method of a memory provided by an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0023] As can be known from the background, it is necessary to provide a memory cell with better performance.

[0024] An embodiment of the present disclosure provides a memory cell, which increases the control ability of the gate conductive part by setting the first dielectric layer to surround the surface of the part of the gate conductive part, and further setting the channel layer to increase the facing area of the gate conductive part and the channel layer, and controls the conduction path between the bit line and the capacitor to be turned off by setting the first word line and the second word line, and on the one hand, increases the conductivity of the channel layer, and on the other hand, makes the turning-off effect of the channel layer better.

[0025] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0026] Reference Figure 1 , Figure 3 and Figure 4 , Figure 1 A structure diagram of a memory cell provided by an embodiment of the present disclosure is provided, Figure 3 is Figure 1 a sectional view along the AA1 direction, Figure 4 is Figure 1 a sectional view along the BB1 direction.

[0027] In some embodiments, the memory cell provided by the embodiment of the present disclosure can include: a gate conductive part 101, the gate conductive part 101 extending along a first direction X.

[0028] The memory cell provided by the embodiment of the present disclosure can further include: a first dielectric layer 102, the first dielectric layer 102 being arranged to surround part of the surface of the gate conductive part 101 along the first direction X.

[0029] The memory cell provided by the embodiment of the present disclosure can further include: a channel layer 103, the channel layer 103 being located on the first dielectric layer 102.

[0030] The memory cell provided by the embodiment of the present disclosure can further include: a second dielectric layer 104, the second dielectric layer 104 being located on the channel layer 103.

[0031] The memory cell provided by the embodiment of the present disclosure can further include: a first word line 105, the first word line 105 being located on the second dielectric layer 104.

[0032] The storage unit provided by the embodiment of the present disclosure can further include a bit line 106, the bit line 106 is located at one end of the gate conductive part 101 along the first direction X and is spaced from the gate conductive part 101, and the bit line 106 is connected with the channel layer 103.

[0033] The storage unit provided by the embodiment of the present disclosure can further include a capacitor 107, the capacitor 107 is located at one end of the gate conductive part 101 away from the bit line 106 and is spaced from the gate conductive part 101, and the capacitor 107 is connected with the channel layer 103.

[0034] The storage unit provided by the embodiment of the present disclosure can further include a second word line 108, the second word line 108 is connected with the gate conductive part 101.

[0035] The embodiment of the present disclosure can increase the control ability of the gate conductive part 101 by setting the first dielectric layer 102 to surround part of the surface of the gate conductive part 101 and then setting the channel layer 103, thereby increasing the control ability of the gate conductive part 101, and the first word line 105 and the second word line 108 can be set to control the conduction path between the bit line 106 and the capacitor 107 to be turned off, and the first word line 105 and the second word line 108 can be set to increase the conductivity of the channel layer 103 on the one hand and make the channel layer 103 have a better turn-off effect on the other hand.

[0036] In some embodiments, the shape of the gate conductive part 101 can be a cuboid, a cylinder or a cube, and the following will be described by taking the shape of the gate conductive part 101 as a cuboid as an example. The gate conductive part 101 can include a first side surface and a second side surface arranged along the first direction X, can further include a third side surface and a fourth side surface arranged along the second direction Y, and can further include a fifth side surface and a sixth side surface arranged along the third direction Z.

[0037] In some embodiments, the material of the gate conductive part 101 can be a semiconductor material, for example, can be a polysilicon layer doped with doping ions.

[0038] Reference Figure 1 and Figure 3 In some embodiments, the first dielectric layer 102 can cover the third side surface, part of the fifth side surface and part of the sixth side surface of the gate conductive part 101, and in some embodiments, the first dielectric layer 102 can also cover one or two of the third side surface, part of the fifth side surface and part of the sixth side surface of the gate conductive part 101, and so on.

[0039] In some embodiments, the gate conductive part 101 is a cylinder, and the first dielectric layer 102 can also be part of the side wall of the cylinder.

[0040] In some embodiments, the first dielectric layer 102 is aligned with the boundary of the gate conductive part 101 in the first direction X. By aligning the first dielectric layer 102 with the boundary of the gate conductive part 101 in the first direction X, the first dielectric layer 102 is prevented from blocking the contact between the channel layer 103 and the bit line 106, and the contact between the channel layer 103 and the capacitor 107 is also prevented. Moreover, the formation of the first dielectric layer 102 is simplified, and the difficulty of forming the first dielectric layer 102 is reduced.

[0041] In some embodiments, the channel layer 103 can cover the entire surface of the first dielectric layer 102, that is, the channel layer 103 can be opposite to the third side, part of the fifth side and part of the sixth side of the gate conductive part 101. In other embodiments, the channel layer 103 can only cover part of the surface of the first dielectric layer 102, that is, the channel layer 103 can be opposite to one or two of the third side, part of the fifth side and part of the sixth side of the gate conductive part 101. It should be noted that, in order to facilitate the contact between the channel layer 103 and the capacitor 107 and the bit line 106, the length of the channel layer 103 in the first direction X is greater than the length of the first dielectric layer 102.

[0042] In some embodiments, the material of the channel layer 103 can include indium gallium zinc oxide or zinc tin oxide. By setting the material of the channel layer 103 as indium gallium zinc oxide or zinc tin oxide, the ion mobility of the channel layer 103 is improved, and the performance of the channel layer 103 as a channel region is improved. The material of the channel layer 103 can also be one or more of indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, and other similar materials.

[0043] In some embodiments, the second dielectric layer 104 can cover the entire surface of the channel layer 103, that is, the second dielectric layer 104 can be opposite to the third side, part of the fifth side and part of the sixth side of the gate conductive part 101. In other embodiments, the second dielectric layer 104 can only cover part of the surface of the channel layer 103, that is, the area of the orthographic projection of the second dielectric layer 104 on the gate conductive part 101 can be less than the area of the orthographic projection of the channel layer 103 on the gate conductive part 101.

[0044] In some embodiments, the material of the first dielectric layer 102 is different from the material of the second dielectric layer 104, and the relative dielectric constant of the material of the second dielectric layer 104 is greater than the relative dielectric constant of the material of the first dielectric layer 102. By setting the relative dielectric constant of the material of the second dielectric layer 104 to be greater than the relative dielectric constant of the material of the first dielectric layer 102, the leakage current on the first word line 105 can be reduced, and the performance of the memory cell can be further improved.

[0045] In some embodiments, the material of the second dielectric layer 104 can include hafnium oxide, and the material of the first dielectric layer 102 can include silicon oxide.

[0046] It should be noted that the relative dielectric constant herein is a physical parameter representing the dielectric or polarization property of a dielectric material. The value of the relative dielectric constant is equal to the ratio of the capacitance of a capacitor made of a predetermined material to the capacitance of a capacitor of the same size made of vacuum.

[0047] In some embodiments, the first word line 105 can cover the entire surface of the second dielectric layer 104, in other words, the first word line 105 can be opposite to the third side, part of the fifth side and part of the sixth side of the gate conductive part 101; in other embodiments, the first word line 105 can also cover only part of the surface of the second dielectric layer 104, in other words, the area of the orthographic projection of the first word line 105 on the gate conductive part 101 can be smaller than the area of the orthographic projection of the second dielectric layer 104 on the gate conductive part 101.

[0048] By setting the first word line 105 to surround the channel layer 103, the ability of the first word line 105 to control the conduction of the channel layer 103 can be improved, and the performance of the memory cell can be increased.

[0049] Reference Figure 1 and Figure 4In some embodiments, the bit line 106 can be in contact with the first side of the gate conductive part 101, and the bit line 106 can include a first sub-bit line 116 extending along the second direction Y and a second sub-bit line 126 extending along the first direction X, wherein the second sub-bit line 126 can be in contact with the channel layer 103. The first sub-bit line 116 and the second sub-bit line 126 can have the same shape, such as a cuboid, a cylinder, or a cube, and so on. Taking the cuboid as an example, the first sub-bit line 116 can include a first side and a second side arranged along the first direction X, a third side and a fourth side arranged along the second direction Y, and a fifth side and a sixth side arranged along the third direction Z. The first side of the first sub-bit line 116 can be in contact with the second sub-bit line 126, the second side can be opposite to the gate conductive part 101, and the channel layer 103 can be in contact with the third side, part of the fifth side, and part of the sixth side of the first sub-bit line 116.

[0050] In some embodiments, there is an isolation layer 191 between the bit line 106 and the gate conductive part 101, so as to avoid direct contact between the bit line 106 and the gate conductive part 101.

[0051] In some embodiments, the capacitor 107 can also have the shape of a cuboid, a cylinder, or a cube, and so on. Taking the cuboid as an example, the capacitor 107 can include a first side and a second side arranged along the first direction X, a third side and a fourth side arranged along the second direction Y, and a fifth side and a sixth side arranged along the third direction Z. The channel layer 103 can cover part of the third side, part of the fifth side, and part of the sixth side of the capacitor 107.

[0052] In some embodiments, the capacitor 107 can include a lower electrode layer 117, a capacitor dielectric layer 127 surrounding the lower electrode layer 117, and an upper electrode layer 137 surrounding the capacitor dielectric layer 127. The distance between the lower electrode layer 117 and the upper electrode layer 137 of the capacitor 107 and the material of the capacitor dielectric layer 127 can affect the capacity of the capacitor 107. Therefore, the distance between the lower electrode layer 117 and the upper electrode layer 137, the opposite area between the lower electrode layer 117 and the upper electrode layer 137, and the material of the capacitor dielectric layer 127 of the capacitor 107 can be set according to actual needs.

[0053] In some embodiments, there is an isolation layer 191 between the capacitor 107 and the gate conductive part 101, so as to avoid direct contact between the capacitor 107 and the gate conductive part 101.

[0054] In some embodiments, the second word line 108 can be in contact with the fourth side of the gate conductive part 101, so that the gate conductive part 101 can be controlled to conduct by transmitting an electrical signal to the gate conductive part 101 through the second word line 108, and the capacitor 107 can be connected to the bit line 106.

[0055] In some embodiments, the first word line 105 and the second word line 108 can be set as a read-on word line and a write-on word line, respectively, or the first word line 105 and the second word line 108 can be set as a write-on word line and a read-on word line, respectively, in other words, the first word line 105 and the second word line 108 can control the conduction path between the capacitor 107 and the bit line 106 independently, so that the off effect of the channel layer 103 can be better; in some embodiments, the first word line 105 and the second word line 108 can control the conduction path between the capacitor 107 and the bit line 106 simultaneously, so that the carrier in the channel layer 103 can be increased, the conductivity of the channel layer 103 can be increased, and the reliability of the storage unit can be increased.

[0056] Reference Figure 2 , Figure 2 Another structure of a storage unit is provided in an embodiment of the present disclosure, and in some embodiments, the storage unit can further include a connection structure 109, one end of the connection structure 109 being in contact with the first word line 105, and the other end of the connection structure 109 being in contact with the second word line 108, so that the first word line 105 and the second word line 108 can control the conduction path between the capacitor 107 and the bit line 106 simultaneously, and the performance of the storage unit can be increased.

[0057] In some embodiments, the first word line 105, the second word line 108, and the connection structure 109 can be made of the same material, for example, all can be made of a metal material such as tungsten, by setting the same material for the first word line 105, the second word line 108, and the connection structure 109, the lattice defects of the contact surface between the first word line 105 and the connection structure 109 can be reduced, and the lattice defects of the contact surface between the second word line 108 and the connection structure 109 can be reduced, so that the performance of the storage unit can be further improved.

[0058] The embodiment of the present disclosure can increase the control ability of the gate conductive part 101 by setting the first dielectric layer 102 to surround the surface of the gate conductive part 101 and then setting the channel layer 103 to increase the facing area of the gate conductive part 101 and the channel layer 103. The first word line 105 and the second word line 108 are set to control the conduction path between the bit line 106 and the capacitor 107 to be turned off. The first word line 105 and the second word line 108 can increase the conductivity of the channel layer 103 and make the channel layer 103 have better turn-off effect.

[0059] Another embodiment of the present disclosure also provides a memory including the memory cell described in the above embodiments or all of the above embodiments, and the memory cells are arranged along a second direction Y and a third direction Z, and the first direction X, the second direction Y and the third direction Z are different. The memory provided by the another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the above embodiments can refer to the corresponding description of the above embodiments, and the following will not be repeated.

[0060] Reference Figure 5 , Figure 5 FIG. 1 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure.

[0061] In some embodiments, the memory cells arranged along the second direction Y share the bit line 106, and / or the memory cells arranged along the third direction Z share the first word line 105 and the second word line 108. The memory cells in the memory can share the bit line 106, or share the first word line 105 and the second word line 108, or share the bit line 106 and share the first word line 105 and the second word line 108. By setting the memory cells arranged along the second direction Y to share the bit line 106, and / or the memory cells arranged along the third direction Z to share the first word line 105 and the second word line 108, the integration of the memory can be improved.

[0062] Another embodiment of the present disclosure also provides a manufacturing method of a memory, which can be used to form the memory in the above embodiments. The manufacturing method of the memory provided by the another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the above embodiments can refer to the corresponding description of the above embodiments, and the following will not be repeated.

[0063] Reference Figures 6 to 25 , Figures 6 to 25 FIG. 1 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure.

[0064] In some embodiments, the method for manufacturing the memory can include: forming a plurality of memory cells arranged along a second direction X and a third direction, and the method for manufacturing the memory cell can include: forming a gate conductive part 201 extending along the first direction X.

[0065] The method for manufacturing the memory cell can further include: forming a first dielectric layer 202 arranged on a part of the surface of the gate conductive part 201 around the first direction X.

[0066] The method for manufacturing the memory cell can further include: forming a channel layer 203 on the first dielectric layer 202.

[0067] The method for manufacturing the memory cell can further include: forming a second dielectric layer 204 on the channel layer 203.

[0068] The method for manufacturing the memory cell can further include: forming a first word line 205 on the second dielectric layer 204.

[0069] The method for manufacturing the memory cell can further include: forming a bit line 206 on one end of the gate conductive part 201 along the first direction X and spaced from the gate conductive part 201, and the bit line 206 is connected to the channel layer 203.

[0070] The method for manufacturing the memory cell can further include: forming a capacitor 207 on the other end of the gate conductive part 201 away from the bit line 206 and spaced from the gate conductive part 201, and the capacitor 207 is connected to the channel layer 203.

[0071] The method for manufacturing the memory cell can further include: forming a second word line 208 connected to the gate conductive part 201.

[0072] The first dielectric layer 202 formed around a part of the surface of the gate conductive part 201 can avoid direct contact between the gate conductive part 201 and the channel layer 203, the second dielectric layer 204 can avoid direct contact between the first word line 205 and the channel layer 203, the bit line 206 and the capacitor 207 can transmit electrical signals from the bit line 206 to the capacitor 207, the first word line 205 and the second word line 208 can control the conduction path between the bit line 206 and the capacitor 207 to be turned off, and the first word line 205 and the second word line 208 can increase the conductivity of the channel layer 203 and improve the turn-off effect of the channel layer 203.

[0073] Reference Figures 6 to 10In some embodiments, the method of forming the gate conductive part 201 comprises: providing a stack structure 200, the stack structure 200 comprising the insulating layer 210 and the initial gate conductive part 220 arranged in a stack; etching the stack structure 200, the remaining stack structure 200 comprising a first part 230 extending along the first direction X and a second part 240 extending along the second direction Y; etching the initial gate conductive part 220 of the second part 240 and the initial gate conductive part 220 of the part of the first part 230, the remaining initial gate conductive part 220 being the gate conductive part 201. By providing the stack structure 200 first and then forming the gate conductive part 201 by etching, the gate conductive part 201 arranged along the second direction X and the third direction Y can be formed, thereby providing a basis for forming the memory cell arranged along the second direction X and the third direction Y.

[0074] Referring to Figure 6 In some embodiments, the substrate 209 can also be included, and the insulating layer 210 and the initial gate conductive part 220 arranged in a stack are formed on the substrate 209, and the insulating layer 210 and the initial gate conductive part 220 arranged in a stack constitute the stack structure 200.

[0075] Referring to Figure 7 The stack structure 200 is etched to form a plurality of second grooves 250 arranged at intervals along the second direction Y, and the second grooves 250 expose the surface of the substrate 209.

[0076] Referring to Figure 8 After the second grooves 250 are formed, the first sacrificial layer 300 can also be formed, and the first sacrificial layer 300 can also fill the second grooves 250.

[0077] Referring to Figure 9 and Figure 10 In order to facilitate the illustration of the internal structure, Figure 9 The first sacrificial layer is transparentized, Figure 10 is a schematic diagram of the structure after etching the initial gate conductive part; in some embodiments, the initial gate conductive part 220 is etched after the first sacrificial layer 300 is formed to form the gate conductive part 201.

[0078] Referring to Figures 11 to 18The method for forming the first word line 205 can include: etching the insulating layer 210 in contact with the gate conductive part 201 to form a first recess 301; forming a first dielectric layer 202 covering the inner wall of the first recess 301 and the surface of the gate conductive part 201; forming a channel layer 203 covering the surface of the first dielectric layer 202; forming a second dielectric layer 204 covering the surface of the channel layer 203; and forming the first word line 205 covering the surface of the second dielectric layer 204. The first dielectric layer 202, the channel layer 203 and the second dielectric layer 204 are formed before the first word line 205 is formed, thereby simplifying the manufacturing method of the memory and reducing the difficulty of forming the memory.

[0079] Referring to Figure 11 and Figure 12 wherein, for ease of showing the internal structure, Figure 11 transparencizing the first sacrificial layer, Figure 12 is a schematic diagram of the structure after the initial isolation layer is formed; after the gate conductive part 201 is formed before the first recess 301 is formed, the method can further include: first forming an initial isolation layer 302 covering the surface of the insulating layer 210 exposed by etching the initial gate conductive part 220.

[0080] Referring to Figure 13 and Figure 14 wherein, for ease of showing the internal structure, Figure 13 transparencizing the first sacrificial layer, Figure 14 is a schematic diagram of the structure after the insulating layer is etched; after the initial isolation layer 302 is formed, the second part of the insulating layer 210 and the first part of the insulating layer 210 are etched, and the length of the remaining insulating layer 210 in the first direction X is greater than the length of the gate conductive part 201. By forming the insulating layer 210 with a length greater than the length of the gate conductive part 201 in the first direction X, a process basis can be provided for subsequently forming the channel layer 203 with a length greater than the length of the gate conductive part 201 in the first direction X.

[0081] Referring to Figure 15 and Figure 16 wherein, for ease of showing the internal structure, Figure 15 transparencizing the first sacrificial layer, Figure 16 is a schematic diagram of the structure after the second sacrificial layer is formed; in some embodiments, after the insulating layer 210 is etched, the method can further include: forming a second sacrificial layer 303 to fill the recess formed after the insulating layer 210 is etched.

[0082] Referring to Figure 17In some embodiments, before forming the first recess 301, the method further comprises: removing the first sacrificial layer 300 to expose a surface of the insulating layer 210. The first sacrificial layer 300 is removed first to provide a process basis for forming the first recess 301.

[0083] In some embodiments, only a part of the first sacrificial layer 300 can be etched, for example, only the first sacrificial layer 300 on one side of the gate conductive part 201 is etched, and only the surface on one side of the gate conductive part 201 is exposed.

[0084] With reference to Figure 17 In some embodiments, a part of the insulating layer 210 is etched to form the first recess 301, and the first recess 301 exposes a part of the fifth side surface and a part of the sixth side surface of the gate conductive part 201.

[0085] It should be noted that the fifth side surface and the sixth side surface of the gate conductive part 201 refer to two side surfaces arranged along the third direction when the gate conductive part 201 is a cuboid.

[0086] With reference to Figure 18 The first dielectric layer 202 is formed, and in some embodiments, the method of forming the first dielectric layer 202 can comprise: oxidizing the exposed surface of the gate conductive part 201 exposed after etching the insulating layer 210 and removing the first sacrificial layer 300 by in-situ oxidation, so that the first dielectric layer 202 can be formed. By in-situ oxidation, the length of the first dielectric layer 202 formed in the first direction X can be controlled to be equal to the length of the gate conductive part 201, so as to avoid the first dielectric layer 202 formed covering the surface of the initial isolation layer 302, and to avoid affecting the formation of the channel layer 203 later.

[0087] In some embodiments, the first dielectric layer 202 can be formed on the surface of the gate conductive part 201 by atomic deposition, and the first dielectric layer 202 formed by atomic deposition has higher density.

[0088] With reference to Figure 18 The channel layer 203 is formed, and the channel layer 203 can cover the entire surface of the first dielectric layer 202 and can also cover a part of the surface of the initial isolation layer 302. The channel layer covering a part of the surface of the initial isolation layer 302 provides a contact basis for the subsequent formation of the bit line and the capacitor.

[0089] With reference to Figure 18forming a second dielectric layer 204 and a first word line 205, wherein the second dielectric layer 204 can cover the entire surface of the channel layer 203, and the first word line 205 can cover the entire surface of the second dielectric layer 204. By setting the second dielectric layer 204 to cover the entire surface of the channel layer 203, the first word line 205 can cover the entire surface of the second dielectric layer 204, which can increase the ability of the first word line 205 to control the channel layer 203 and enhance the performance of the formed memory.

[0090] Referring to Figure 19 and Figure 20 , in order to facilitate the illustration of the internal structure, Figure 19 transparency of the filling layer, Figure 20 is a schematic diagram of the structure after the formation of the filling layer; after the formation of the first word line 205, it further includes: forming a filling layer 304, which fills the recess formed after the etching of the stack structure 200.

[0091] Continuing to refer to Figure 19 and Figure 20 , etching the second part of the initial isolation layer 302 and the first part of the initial isolation layer 302 on one side of the gate conductive part 201, and forming a bit line 206, etching the initial isolation layer 302 to expose the bottom surface of the channel layer 203, and then forming the bit line 206 to form the bit line 206 in contact with the channel layer 203.

[0092] The formation of the bit line 206 can include a first sub-bit line 216 extending along the second direction Y and a second sub-bit line 226 extending along the first direction X.

[0093] It should be noted that the second part and the first part in the above-mentioned refer to the structure corresponding to the first part 230 and the second part 240 of the etched stack structure in Figure 7 .

[0094] Referring to Figure 21 and Figure 22 , in order to facilitate the illustration of the internal structure, Figure 21 transparency of the filling layer, Figure 22 is a schematic diagram of the structure after the formation of the capacitor; etching the initial isolation layer 302 on the other side of the gate conductive part 201, and forming a capacitor 207, etching the initial isolation layer 302 to expose the bottom surface of the channel layer 203, and then forming the capacitor 207 to form the capacitor 207 in contact with the channel layer 203.

[0095] The formed capacitor 207 can include a lower electrode layer 217, a capacitor dielectric layer 227 surrounding the lower electrode layer 217, and an upper electrode layer 237 surrounding the capacitor dielectric layer 227, and the same or corresponding description can be referred to the above-mentioned embodiments.

[0096] It should be noted that the initial isolation layer 302 is not etched completely before forming the bit line 206 and the capacitor 207, and part of the initial isolation layer 302 is reserved as the isolation layer 312. The isolation layer 312 on one side of the gate conductive part 201 is in contact with the bit line 206, and the isolation layer 312 on the other side of the gate conductive part 201 is in contact with the capacitor 207. The capacitor 207 and the gate conductive part 201 are isolated by the isolation layer 312, and the bit line 206 and the gate conductive part 201 are isolated by the isolation layer 312, so as to avoid direct contact between the gate conductive part 201 and the capacitor 207, and direct contact between the gate conductive part 201 and the bit line 206.

[0097] Reference is made to Figure 23 and Figure 24 In order to show the internal structure, Figure 23 The filling layer is transparentized, Figure 24 is a schematic diagram of the structure after forming the second word line. After forming the capacitor 207, the filling layer 304 in contact with the fourth side of the gate conductive part 201 is etched, and then the second word line 208 is formed. The second word line 208 extends in the third direction Z. The storage units arranged in the third direction Z are in contact with the same second word line 208, so as to control the plurality of storage units arranged in the third direction Z by the second word line 208.

[0098] Reference is made to Figure 25 In some embodiments, the connection structure 305 can also be formed. One end of the connection structure 305 is in contact with the first word line 205, and the other end of the connection structure 305 can be in contact with the second word line 208, so as to realize the electrical connection between the first word line 205 and the second word line 208.

[0099] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and modifications without departing from the spirit and scope of the embodiments of the present disclosure, therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A memory cell, comprising: The application relates to a memory cell, comprising: a gate conductive part extending along a first direction; a first dielectric layer arranged around a part of the surface of the gate conductive part along the first direction; a channel layer on the first dielectric layer; a second dielectric layer on the channel layer; a first word line on the second dielectric layer; a bit line on one end of the gate conductive part along the first direction and spaced from the gate conductive part, the bit line being connected to the channel layer, wherein the channel layer surrounds a part of the surface of the bit line along the first direction; a capacitor on the other end of the gate conductive part away from the bit line and spaced from the gate conductive part, the capacitor being connected to the channel layer; a second word line connected to the gate conductive part, the gate conductive part being between the first word line and the second word line.

2. The memory cell of claim 1, wherein, The material of the channel layer comprises indium gallium zinc oxide or zinc tin oxide.

3. The memory cell of claim 1, wherein, The material of the first dielectric layer is different from that of the second dielectric layer, and the relative dielectric constant of the material of the second dielectric layer is greater than that of the material of the first dielectric layer.

4. The memory cell of claim 1, wherein, The boundary of the first dielectric layer in the first direction is aligned with the boundary of the gate conductive part.

5. A memory, comprising: The application relates to a memory cell, comprising: The memory cell as claimed in any one of claims 1-4 is arranged along a second direction and a third direction, and the first direction, the second direction and the third direction are different.

6. The memory of claim 5, wherein, The memory cells arranged along the second direction share the bit line, and / or the memory cells arranged along the third direction share the first word line and the second word line.

7. A method for fabricating a memory, the method comprising: The application relates to a method for forming a memory cell, comprising: forming a gate conductive part extending along a first direction; forming a first dielectric layer arranged around a part of the surface of the gate conductive part along the first direction; forming a channel layer on the first dielectric layer; forming a second dielectric layer on the channel layer; forming a first word line on the second dielectric layer; forming a bit line on one end of the gate conductive part along the first direction and spaced from the gate conductive part, the bit line being connected to the channel layer; forming a capacitor on the other end of the gate conductive part away from the bit line and spaced from the gate conductive part, the capacitor being connected to the channel layer; forming a second word line connected to the gate conductive part. The method for forming the gate conductive part comprises:

8. The method of fabricating memory according to claim 7, wherein, providing a stack structure comprising an insulating layer and an initial gate conductive part arranged in layers; etching the stack structure, so that the remaining stack structure comprises a first part extending along the first direction and a second part extending along the second direction; etching the initial gate conductive part of the second part and the initial gate conductive part of part of the first part, so that the remaining initial gate conductive part serves as the gate conductive part. The method for forming the first word line comprises:

9. The method of claim 8, wherein ​ etching the insulating layer in contact with the gate conductive part to form a first recess; forming the first dielectric layer covering the inner wall of the first recess and the surface of the gate conductive part; forming the channel layer covering the surface of the first dielectric layer; forming the second dielectric layer covering the surface of the channel layer; forming the first word line covering the surface of the second dielectric layer.

10. The method of claim 9, wherein Before forming the first recess, the method further comprises forming an initial isolation layer covering the surface of the insulating layer exposed by etching the initial gate conductive part, and the method of forming the bit line and the capacitor comprises: etching the initial isolation layer of the second part and part of the initial isolation layer of the first part, and the remaining initial isolation layer as an isolation layer, the isolation layer covering the sidewall of the gate conductive part arranged along the first direction; forming the bit line in contact with the isolation layer on one side of the gate conductive part; forming the capacitor in contact with the isolation layer on the other side of the gate conductive part.

Images