Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate and a first dielectric layer, the substrate comprises a first part, a plurality of second parts located on the first part and arranged at intervals in the first direction, and a plurality of third parts located on the sides, away from the first part, of the second parts and arranged at intervals in the second direction, and the first dielectric layers are at least located between the adjacent second parts; removing at least part of the first part and part of the thickness of the second part to expose the residual area of the second part, and forming a groove between the adjacent first dielectric layers; metalizing the exposed second part of the groove to form a bit line extending along a second direction; at least one bit line contact block is formed in at least part of the groove, and one bit line is in contact connection with the at least one bit line contact block. The embodiment of the invention is at least beneficial to improving the alignment precision between the bit line and the bit line contact block.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by a unit memory cell. However, the integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology of forming fine patterns, making it limited to continuously increase the integration density of two-dimensional or planar semiconductor devices. Thus, the development of semiconductor devices has moved towards three-dimensional semiconductor devices, which can solve the density limitation in planar memory cells. Three-dimensional semiconductor devices include a memory array and peripheral circuits for facilitating the operation of the memory array.

[0003] However, as the feature size of a unit memory cell approaches the lower limit, the process and manufacturing technology become challenging and costly, and as the spacing between adjacent unit memory cells is reduced, higher requirements are imposed on the alignment accuracy between the unit memory cell and other devices. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least help to improve the alignment accuracy between a bit line and a bit line contact block.

[0005] According to some embodiments of the present disclosure, on the one hand, a manufacturing method of a semiconductor structure is provided, including: providing a substrate and a first dielectric layer, the substrate including a first part, a plurality of second parts located on the first part and arranged at intervals along a first direction, and a plurality of third parts located on a side of the second parts away from the first part and arranged at intervals along a second direction, the first dielectric layer being at least located between adjacent second parts, the second parts being used to form bit lines, the third parts being used to form semiconductor pillars, the first direction and the second direction intersecting; removing at least part of the first part and part of the thickness of the second part to expose the remaining area of the second part, and forming a groove between adjacent first dielectric layers; performing metallization treatment on the second part exposed by the groove to form the bit line extending along the second direction; forming at least one bit line contact block in at least part of the groove, and a bit line being in contact connection with at least one bit line contact block.

[0006] In some embodiments, the step of removing at least a portion of the first portion and a portion of the thickness of the second portion includes: forming a first mask layer having first openings extending in the first direction, with a plurality of the first openings arranged at intervals in the second direction; using the first mask layer as a mask to etch the first portion and the portion of the thickness of the second portion exposed by the first openings to form a plurality of the grooves arranged at intervals in the first direction and the second direction; the step of forming at least one of the bit line contact blocks in at least a portion of the grooves includes: forming a second dielectric layer filling the grooves; removing a portion of the second dielectric layer in the grooves and forming the bit line contact blocks.

[0007] In some embodiments, the first direction and the second direction form a reference plane, the orthographic projection of the first opening on the reference plane is a first projection, the interval between adjacent third portions in the second direction on the reference plane is a second projection, and the orthographic projection of the third portion on the reference plane is a third projection; wherein, the first projection is located within the second projection; or, the first projection at least partially overlaps with the third projection.

[0008] In some embodiments, the step of removing at least a portion of the first portion and a portion of the thickness of the second portion includes: removing the first portion entirely to expose the second portion; continuing to remove a portion of the thickness of the second portion to form the grooves extending in the second direction, with one groove corresponding to one second portion; the step of forming at least one of the bit line contact blocks in at least a portion of the grooves includes: forming a second dielectric layer filling the grooves; patterning the second dielectric layer to expose a partial area of the grooves, and a partial area of the grooves exposes the bit lines; forming the bit line contact blocks in the partial area of the grooves.

[0009] In some embodiments, the bit line contact blocks connected to adjacent bit line contacts are arranged staggeredly in the first direction, and / or, the bit line contact blocks connected to adjacent bit line contacts are arranged staggeredly in the second direction.

[0010] In some embodiments, in the direction from the first part to the second part, the third part includes a first sub - part, a second sub - part, and a third sub - part arranged in sequence, and the first direction and the second direction form a reference plane; the substrate further includes: a gate structure and a third dielectric layer, the gate structure surrounds the side walls of a plurality of the second sub - parts arranged along the first direction, and the third dielectric layer is at least located between adjacent gate structures; the manufacturing method further includes: removing the first part; forming a second mask layer on the side of the first dielectric layer away from the gate structure, the second mask layer having a plurality of second openings, and the positive projection of one second opening on the reference plane overlaps at least with the positive projection of one gate structure on the reference plane; using the third dielectric layer as an etching stop layer, etching the first dielectric layer exposed by the second opening with the second mask layer as a mask until the gate structure is exposed and a through - hole is formed; forming a word - line contact block in the through - hole, and one gate structure is in contact connection with at least one word - line contact block.

[0011] In some embodiments, the positive projection of one second opening on the reference plane only overlaps with the positive projection of one gate structure on the reference plane, and one second opening is only used to form one word - line contact block.

[0012] In some embodiments, along the second direction, the length of the second opening is greater than the distance between adjacent third dielectric layers. In the step of forming the through - hole, at least a part of the top surface of the third dielectric layer away from the second part is also exposed, and along the second direction, only the positive projection of one of the adjacent gate structures on the reference plane overlaps with the positive projection of the second opening on the reference plane.

[0013] In some embodiments, the third dielectric layer is also located between adjacent bit lines. The positive projection of one second opening on the reference plane overlaps with the positive projections of at least two adjacent gate structures on the reference plane, and one second opening is used to form at least two word - line contact blocks; in the step of etching the first dielectric layer exposed by the second opening with the third dielectric layer as an etching stop layer and the second mask layer as a mask, at least two through - holes separated by the third dielectric layer are formed along the second direction.

[0014] In some embodiments, the formed through - hole exposes at least the side wall of one first sub - part; after forming the through - hole and before forming the word - line contact block, it further includes: forming a protective layer on the side wall of the through - hole, and the protective layer and the bottom surface of the through - hole jointly enclose a sub - through - hole; forming the word - line contact block in the through - hole includes: forming the word - line contact block that fills the sub - through - hole.

[0015] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a semiconductor structure, including: a substrate, in which a vertical transistor is provided, the vertical transistor includes a semiconductor column extending in a third direction, the semiconductor column has a first surface and a second surface opposite to each other in the third direction, and the first surface is the back surface of the substrate; a plurality of bit lines arranged at intervals in a first direction, one of the bit lines is in contact with a plurality of first surfaces arranged at intervals in a second direction, the bit line has a metal semiconductor compound therein, and the first direction, the second direction, and the third direction intersect pairwise; a plurality of bit line contact blocks, one of the bit lines is in contact connection with at least one of the bit line contact blocks on a side away from the semiconductor column in the third direction, and side walls of the bit line contact blocks extending in the third direction are all surrounded by a dielectric layer.

[0016] In some embodiments, in the third direction, the semiconductor column includes a first sub - portion, a second sub - portion, and a third sub - portion arranged in sequence, and the first sub - portion is in contact connection with the bit line; the vertical transistor further includes a gate structure that surrounds side walls of a plurality of the second sub - portions arranged in the first direction; the semiconductor structure further includes: a plurality of word line contact blocks, one of the gate structures is in contact connection with at least one of the word line contact blocks on a side away from the second surface in the third direction.

[0017] In some embodiments, the semiconductor structure further includes: a protective layer located on two opposite side walls of the word line contact block in the first direction, and / or located on two opposite side walls of the word line contact block in the second direction.

[0018] In some embodiments, word line contact blocks in contact connection with adjacent gate structures are arranged in a staggered manner in the first direction, and / or word line contact blocks in contact connection with adjacent gate structures are arranged in a staggered manner in the second direction.

[0019] In some embodiments, bit line contact blocks in contact connection with adjacent bit lines are arranged in a staggered manner in the first direction, and / or bit line contact blocks in contact connection with adjacent bit lines are arranged in a staggered manner in the second direction.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] On the one hand, combining the step of metallizing a partial region of the substrate to form bit lines and the step of forming bit line contact pads is beneficial to simplifying the process steps of forming bit lines and bit line contact pads. On the other hand, removing a part of the substrate to expose the remaining region of the second part in the substrate and forming a groove between adjacent first dielectric layers, it can be understood that the remaining region of the second part constitutes the bottom surface of the groove, and at least part of the side surface of the groove is formed by the second dielectric layer. In other words, there is a second dielectric layer between different grooves corresponding to adjacent two bit lines. Therefore, when forming at least one bit line contact pad in at least part of the grooves, since the bit line contact pad is located in the groove, there is also a second dielectric layer between different bit line contact pads corresponding to adjacent two bit lines, effectively avoiding the short-circuit situation where adjacent two bit lines are short-circuited through the same bit line contact pad. Thus, it is beneficial to improve the conductivity of the finally formed bit lines while enabling self-alignment between the bit line contact pads and the bit lines, so as to improve the alignment accuracy between the bit line contact pads and the bit lines. Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a proportional limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a flowchart corresponding to each step in the semiconductor structure manufacturing method provided by an embodiment of the present disclosure;

[0024] Figures 2 to 28 It is a schematic structural diagram corresponding to each step in the semiconductor structure manufacturing method provided by an embodiment of the present disclosure. Detailed Embodiments

[0025] As can be seen from the background art, the alignment accuracy between the unit memory cells and other devices in three-dimensional semiconductor devices needs to be improved.

[0026] Upon analysis, it is found that in three-dimensional semiconductor devices, the pitch between adjacent bit lines and adjacent word lines is reduced to increase the integration density of unit memory cells. However, due to the reduction of the pitch between adjacent bit lines and adjacent word lines, higher requirements are imposed on the alignment accuracy between the conductive structures respectively connected to each bit line in the peripheral circuit and the bit lines, and higher requirements are imposed on the alignment accuracy between the conductive structures respectively connected to each word line in the peripheral circuit and the word lines. In the current process of mask and patterning, due to the existence of alignment errors between the mask and the memory cells, when the pitch between adjacent bit lines and adjacent word lines is reduced, it is easy to cause problems where the conductive structures in the peripheral circuit are in contact with at least two bit lines, or at least two word lines, or both word lines and bit lines, thus easily causing short circuits between adjacent bit lines, or between adjacent word lines, or between bit lines and word lines, thereby affecting the electrical performance of the semiconductor device.

[0027] In the manufacturing method provided by an embodiment of the present disclosure for a semiconductor structure, on the one hand, combining the step of metallizing a partial region of the substrate to form bit lines and the step of forming bit line contact pads is beneficial to simplifying the process steps of forming bit lines and bit line contact pads; on the other hand, removing a part of the substrate to expose the remaining region of the second part in the substrate and forming a groove between adjacent first dielectric layers. It can be understood that the remaining region of the second part constitutes the bottom surface of the groove, and at least part of the side surface of the groove is formed by a second dielectric layer. In other words, there is a second dielectric layer between different grooves corresponding to adjacent two bit lines. Therefore, when forming at least one bit line contact pad in at least part of the grooves, since the bit line contact pad is located in the groove, there is also a second dielectric layer between different bit line contact pads corresponding to adjacent two bit lines, effectively avoiding the situation where adjacent two bit lines are short-circuited through the same bit line contact pad. In this way, it is beneficial to improve the conductivity of the finally formed bit lines while enabling self-alignment between the bit line contact pads and the bit lines to improve the alignment accuracy between the bit line contact pads and the bit lines.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be implemented.

[0029] An embodiment of the present disclosure provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 1A flowchart corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 28 A schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that, for the convenience of description and to clearly illustrate the steps of the semiconductor structure manufacturing method, in an embodiment of the present disclosure Figures 2 to 28 Are all partial structural schematic diagrams of the semiconductor structure.

[0030] Referring to Figures 1 to 28 , the method for manufacturing a semiconductor structure includes the following steps:

[0031] S101: Referring to Figure 2 and Figure 3 , a substrate 100 and a first dielectric layer 111 are provided. The substrate 100 includes a first part 110, a plurality of second parts 120 arranged at intervals along a first direction X on the first part 110, and a plurality of third parts 130 arranged at intervals along a second direction Y on a side of the second parts 120 away from the first part 110. The first dielectric layer 111 is at least located between adjacent second parts 120. The second parts 120 are used to form bit lines 102, and the third parts 130 are used to form semiconductor pillars. The first direction X and the second direction Y intersect.

[0032] Among them, Figure 2 Is a three-dimensional structural schematic diagram of the substrate and the first dielectric layer in the manufacturing method provided by an embodiment of the present disclosure; Figure 3 Is Figure 2 A cross-sectional structural schematic diagram of the structure shown along a first cross-sectional direction AA1.

[0033] It should be noted that in the substrate 100, the first part 110 can be regarded as the bottom of the substrate 100, and the first part 110 is a whole film layer, that is, the first part 110 has a relatively large extension width along both the first direction X and the second direction Y; the second parts 120 can be regarded as initial bit lines, that is, semiconductor material layers that have not been doped with metal elements, and at least part of the second parts 120 are subsequently metallized to form bit lines with better conductivity. The second parts 120 are strip-shaped structures extending along the second direction Y; the third parts 130 are used to form semiconductor pillars, and the third parts 130 are columnar structures, and the columnar structures are arranged in an array along the first direction X and the second direction Y.

[0034] In some cases, referring to Figure 1, the material type of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc. Moreover, the first part 110, the second part 120, and the third part 130 are all components of the substrate 100, that is, the first part 110, the second part 120, and the third part 130 have the same semiconductor element. In practical applications, the first part 110, the second part 120, and the third part 130 can be formed using the same film layer structure, which is composed of semiconductor elements, so that the first part 110, the second part 120, and the third part 130 are an integral structure, thereby improving the performance of the semiconductor structure by reducing the interface state defects between the bit lines formed based on the second part 120 and the semiconductor pillars formed based on the third part 130 in the subsequent process.

[0035] It should be noted that in one embodiment of the present disclosure, the method for forming the first part 110, the second part 120, and the third part 130 is not limited.

[0036] In some embodiments, the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, the first part 110, the second part 120, and the third part 130 all include silicon elements.

[0037] It can be understood that, continuing to refer to Figure 1 , a plurality of second parts 120 extending along the second direction Y are all located on the first part 110, and a plurality of third parts 130 arranged at intervals along the second direction Y are located on one side of the same second part 120 away from the first part 110.

[0038] In some embodiments, the first part 110 can be used as the bottom of the substrate 100, and the subsequently formed gate structure can be located in the intervals between the plurality of third parts 130. Moreover, the first direction X can be the extension direction of the subsequently formed gate structure, and the second direction Y can be the extension direction of the subsequently formed bit lines.

[0039] It should be noted that Figure 2 the first part 110, the second part 120, and the third part 130 in the substrate 100 are divided by a dashed line; in addition, Figure 2 shows an example in which 4 second parts 120 are arranged at intervals along the first direction X, and 4 third parts 130 are arranged at intervals on one second part 120. In practical applications, the number of second parts 120 arranged at intervals along the first direction X and the number of third parts 130 arranged at intervals on one second part 120 are not limited.

[0040] S102: With reference to Figures 3 to 6, at least part of the first part 110 and part of the thickness of the second part 120 are removed to expose the remaining area of the second part 120, and a groove 140 is formed between adjacent first dielectric layers 111. Alternatively, with reference to Figure 3 to Figures 7 to 9 , at least part of the first part 110 and part of the thickness of the second part 220 are removed to expose the remaining area of the second part 220, and a groove 240 is formed between adjacent first dielectric layers 211. It should be noted that in different embodiments, 120 and 220 both represent the second part, 130 and 230 both represent the third part, 111 and 211 both represent the first dielectric layer, and 140 and 240 both represent the groove.

[0041] It should be noted that the groove formed in step S102 includes at least the following two cases, so step S102 includes at least the following two embodiments:

[0042] In some embodiments, with reference to Figures 3 to 6 , step S102, that is, removing at least part of the first part 110 and part of the thickness of the second part 120, may include the following steps:

[0043] Among them, Figure 4 is a top view structural schematic diagram of a first mask layer in the manufacturing method provided by an embodiment of the present disclosure; Figure 5 is a top view structural schematic diagram after forming a groove in the manufacturing method provided by an embodiment of the present disclosure; Figure 6 is Figure 5 a cross-sectional structural schematic diagram of the structure shown along the second cross-section direction BB1 and the third cross-section direction CC1. It should be noted that subsequently, one or both of the cross-sectional structural schematic diagrams along the second cross-section direction BB1 and the cross-sectional structural schematic diagram along the third cross-section direction CC1 will be set according to the expression needs.

[0044] With reference to Figure 4 , a first mask layer 104 is formed. The first mask layer 104 has a first opening 114 extending along the first direction X, and a plurality of first openings 114 are arranged at intervals along the second direction Y. It should be noted that to show the first opening 114 in the first mask layer 104, Figure 4 only the first mask layer 104 without the first opening 114 is filled with oblique lines, and the approximate outline of each first opening 114 is drawn.

[0045] In some cases, with reference to Figure 2 and Figure 4 , the first opening 114 and a plurality of third parts 130 arranged along the first direction X all have facing parts. In other words, the first opening 114 and the gate structure located in the interval of the third part 130 ( Figure 2is not shown) face each other, so that each of the first openings 114 and a plurality of second portions 120 arranged at intervals along the first direction X has a facing portion. In practical applications, the first opening may also face the interval between two adjacent third portions in the second direction. It should be noted that the statement that there is a facing portion or facing between the two above refers to the fact that the positive projections of the two on the reference plane formed by the first direction X and the second direction Y coincide or have a large overlap. In addition, the statement that there is a facing portion or facing between the two mentioned in the subsequent description will not be further explained.

[0046] In some embodiments, with reference to Figure 2 and Figure 4 , the first direction X and the second direction Y form a reference plane. The positive projection of the first opening 114 on the reference plane is the first projection, the positive projection of the interval between adjacent third portions 130 along the second direction Y on the reference plane is the second projection, and the positive projection of the third portion 130 on the reference plane is the third projection.

[0047] In some cases, the first projection is located in the second projection, that is, the first opening in the foregoing description faces the interval between two adjacent third portions in the second direction. Thus, the positive projection of the subsequently formed bit line contact block on the reference plane is located between the two positive projections of the adjacent gate structures on the reference plane; in other cases, the first projection and the third projection at least partially overlap, that is, each of the first openings 114 and a plurality of second portions 120 arranged at intervals along the first direction X has a facing portion as described above. Thus, the positive projection of the subsequently formed bit line contact block on the reference plane is located in the positive projection of the third portion 130 on the reference plane.

[0048] Reference Figures 3 to 6 , using the first mask layer 104 as a mask, etch the first portion 110 exposed by the first opening 114 and a part of the thickness of the second portion 120 to form a plurality of grooves 140 arranged at intervals along the first direction X and the second direction Y.

[0049] In some cases, the back surface of the substrate 100 includes the first portion 110. In the step of etching the first portion 110 exposed by the first opening 114 and a part of the thickness of the second portion 120 using the first mask layer 104 as a mask, the etching process starts from the back surface of the substrate 100 to etch the first portion 110 and the second portion 120.

[0050] It should be noted that in the step of etching the substrate 100 using the first mask layer 104 as a mask, with reference to Figure 6 the cross-sectional structure schematic diagram along the third cross-section direction CC1, not the entire first portion 110 of the surface is etched, but the first opening 114 (reference Figure 4)The exposed first portion 110 is etched. In other words, the etched first portion 110 and the first opening 114 are in alignment. Thus, the exposed first portion 110 can be etched through any one of the first openings 114 to finally expose a plurality of second portions 120 spaced apart along the first direction X.

[0051] It can be understood that, with reference to Figure 2 and Figure 4 , each of the first openings 114 not only has an aligned portion with each of the plurality of second portions 120 spaced apart along the first direction X, but also has an aligned portion with each of the plurality of first dielectric layers 111 spaced apart along the first direction X. Based on this, due to the difference in materials between the substrate 100 and the first dielectric layer 111, in the step of etching the substrate 100 using the first mask layer 104 as a mask, the first portion 110 exposed by the first opening 114 is etched, and the first dielectric layer 111 exposed by the first opening 114 is hardly etched, thereby forming a plurality of grooves 140 as shown in Figure 5 and Figure 6 . Thus, a plurality of grooves 140 are formed on one second portion 120.

[0052] Among them, the two opposite sidewalls of the groove 140 along the first direction X are formed by the first dielectric layer 111, and the two opposite sidewalls of the groove 140 along the second direction Y are formed by the remaining first portion 110.

[0053] In some other embodiments, with reference to Figure 3 , Figures 7 to 9 , step S102, that is, removing at least part of the first portion 110 and part of the thickness of the second portion 220 may include the following steps:

[0054] With reference to Figure 7 , the entire first portion (refer to Figure 2 ) is removed to expose the second portion 220. Thus, one side of any second portion 220 away from the third portion 230 along the third direction Z is exposed.

[0055] With reference to Figures 7 to 9 , the second portion 220 with part of its thickness is continuously removed to form a groove 240 extending along the second direction Y, and the groove 240 corresponds to the second portion 220 one by one. Thus, one groove 240 exposes the entire surface of one second portion 220 away from the third portion 230 along the third direction Z.

[0056] It should be noted that Figure 9 is a schematic cross-sectional structure diagram of a structure shown in Figure 8 along the second cross-sectional direction BB1 and the third cross-sectional direction CC1. In addition, Figure 9 the right figure in

[0057] S103: Metallize the second part 120 exposed by the groove 140 to form a bit line 102 extending along the second direction Y.

[0058] It should be noted that step S103 in the above two embodiments is similar. The following Figure 6 illustrates the groove 140 as an example to elaborate on step S103 in detail.

[0059] In some embodiments, the metallization process of the second part 120 exposed by the groove 140 includes the following steps: With reference to Figure 6 and Figure 10 , form a metal layer 132 on the surface of the groove 140 and the exposed surface of the first dielectric layer 111. The metal layer 132 provides metal elements for the subsequent formation of the bit line. In some embodiments, the material of the metal layer 132 may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0060] With reference to Figure 10 and Figure 11 , perform an annealing process to convert at least a part of the thickness of the second part 120 into a metal-semiconductor compound 122 and convert the second part 120 into a bit line 102; after forming the bit line 102, remove the remaining metal layer 132.

[0061] In some embodiments, during the annealing process, the metal layer 132 reacts with the second part 120, and a part of the thickness of the second part 120 is converted into a metal-semiconductor compound 122. In this way, the finally formed bit line 102 contains the metal-semiconductor compound 122. In other embodiments, the entire thickness of the second part can be converted into a metal-semiconductor compound, and the bit line is composed of the metal-semiconductor compound.

[0062] It can be understood that the metal-semiconductor compound 122 has a relatively small resistivity compared to the unmetallized semiconductor material. Therefore, compared with the second part 120, the bit line 102 has a smaller resistivity, which is beneficial to reducing the resistance of the bit line 102 and reducing the contact resistance between the bit line 102 and the third part 130, further improving the electrical performance of the semiconductor structure.

[0063] In some embodiments, taking silicon as the semiconductor element as an example, the metal-semiconductor compound 122 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0064] It should be noted that with reference to Figure 11, after metallizing the second part 120 exposed by the groove 140 to form the bit line 102 extending along the second direction Y, due to the process influence of the removal process of the remaining metal layer 132, the depth of the groove 140 in the third direction Z will be further deepened, and the third direction Z is the direction in which the third part 130 points to the first part 110.

[0065] In one example, the first direction X, the second direction Y, and the third direction Z intersect pairwise.

[0066] S104: Form at least one bit line contact block 112 in at least part of the groove 140, and a bit line 102 is in contact connection with at least one bit line contact block 112.

[0067] It should be noted that since the groove formed in step S102 includes at least two cases, the bit line contact block 112 formed based on the groove formed in step S102, that is, step S104 includes at least the following two embodiments:

[0068] In some embodiments, to form Figure 6 or Figure 11 Based on the groove 140 shown, step S104: Forming at least one bit line contact block 112 in at least part of the groove 140 may include the following steps:

[0069] With reference to Figures 11 to 13 , form a second dielectric layer 121 that fills the groove 140. Among them, Figure 13 is Figure 12 A schematic cross-sectional structure diagram of a structure along the second cross-sectional direction BB1 shown.

[0070] In some embodiments, the step of forming the second dielectric layer 121 may include: forming an initial second dielectric layer (not shown in the figure) that fills the surface of the groove 140 and the surface of the first dielectric layer 111, and performing chemical mechanical planarization on the initial second dielectric layer until the surface of the first dielectric layer 111 away from the third part 130 is exposed.

[0071] It should be noted that in some cases, in the aforementioned step of removing the remaining metal layer 132, the remaining first part 110 shown in Figure 6 is also removed. Therefore, the first part 110 no longer exists in both the step of forming the initial second dielectric layer and the step of performing chemical mechanical planarization on the initial second dielectric layer; in other cases, the aforementioned step does not remove Figure 6The remaining first portion 110 shown, thus, in the step of forming the initial second dielectric layer, the initial second dielectric layer may also be located on at least a part of the surface of the remaining first portion 110. In the step of performing chemical mechanical planarization on the initial second dielectric layer, both the remaining first portion 110 and the initial second dielectric layer protruding from the surface of the first dielectric layer 111 away from the third portion 130 are removed.

[0072] In this way, referring to Figure 12 , the finally formed second dielectric layer 121 corresponds one-to-one with the grooves 140 (referring to Figure 11 ).

[0073] Combined with reference Figure 12 and Figure 14 , the second dielectric layer 121 in some of the grooves 140 is removed to form the bit line contact pads 112.

[0074] It can be understood that in practical applications, the number of bit line contact pads 112 to be designed on the same bit line 102 can be selected according to requirements. Based on the number of bit line contact pads 112 to be designed, the same number of the second dielectric layers 121 among the multiple second dielectric layers 121 corresponding to the bit line 102 are removed, and the bit line contact pads 112 are formed in the grooves 140 formed after removing the second dielectric layers 121. The corresponding relationship between the bit line 102 and the bit line contact pads 112 will be described in detail later.

[0075] It should be noted that a mask layer with an opening is required in the step of removing the second dielectric layer 121 in some of the grooves 140. To form the bit line contact pads 112, it is necessary to selectively remove the second dielectric layer 121 in the structure shown in Figure 12 . Therefore, the position of the opening in the mask layer can be adjusted according to the actual situation, so that the opening only exposes the second dielectric layer 121 to be removed. Due to the differences between the materials of the second dielectric layer 121, the bit line 102, and the first dielectric layer 111, in the step of removing the second dielectric layer 121 in some of the grooves 140, even if the alignment accuracy between the opening in the mask layer and the second dielectric layer 121 to be removed is not high, the removal process will only remove the second dielectric layer 121 exposed by the opening in the mask layer. Based on this, the bit line contact pads 112 will only be formed in the grooves formed after removing the second dielectric layer 121, thus realizing the self-alignment forming process of the bit line contact pads 112, which is beneficial to improving the alignment accuracy between the bit line contact pads 112 and the bit line 102, and effectively avoiding the situation where the same bit line contact pad 112 is in contact connection with two adjacent bit lines 102, causing the short circuit of the two adjacent bit lines 102.

[0076] In addition, combining the step of metallizing a partial region of the substrate 100 to form the bit line 102 and the step of forming the bit line contact block 112 is conducive to simplifying the process steps of forming the bit line 102 and the bit line contact block 112. Moreover, a second dielectric layer 121 is provided between different grooves 140 corresponding to two adjacent bit lines 102. Thus, while improving the conductivity of the finally formed bit line 102, the bit line contact block 112 and the bit line 102 can be self-aligned to improve the alignment accuracy between the bit line contact block 112 and the bit line 102.

[0077] It should be noted that the low alignment accuracy between the opening in the mask layer and the second dielectric layer 121 to be removed includes the following situations: In some cases, the opening in the mask layer exposes a partial region of the second dielectric layer 121 and also exposes the first dielectric layer 111 or the bit line 102 adjacent to the second dielectric layer 121; in other cases, the opening in the mask layer exposes partial regions of two adjacent second dielectric layers 121 at the same time. It can be understood that due to the differences between the materials of the second dielectric layer 121, the bit line 102, and the first dielectric layer 11, the process of removing the second dielectric layer 121 only has a relatively large etching rate for the second dielectric layer 121.

[0078] In other embodiments, based on the formed Figure 9 groove 240 shown, step S104: forming at least one bit line contact block 212 in at least part of the groove 240 may include the following steps:

[0079] It should be noted that referring to Figure 9 and Figure 15 , the step of forming the bit line 202 in step S103 is similar to the step of forming the bit line 102 in the foregoing embodiment and will not be elaborated here.

[0080] Referring to Figure 15 , a second dielectric layer 221 filling the groove 240 is formed. The second dielectric layers 221 correspond to the bit lines 202 one by one, that is, the second dielectric layer 221 is also a strip-shaped structure extending in the second direction Y.

[0081] In some embodiments, the step of forming the second dielectric layer 221 may include: forming an initial second dielectric layer (not shown in the figure) on the surface of the groove 240 and the surface of the first dielectric layer 211, and performing chemical mechanical planarization on the initial second dielectric layer until the surface of the first dielectric layer 211 away from the third part 230 is exposed. It should be noted that in the foregoing step S102, referring to Figure 2 and Figure 9 , the first part has been entirely removed, so there is no need to remove the first part in the step of forming the second dielectric layer 221.

[0082] It should be noted that Figure 7 , Figure 9 and Figure 15 the first sub - part 250, the second sub - part 260, and the third sub - part 270 shown in

[0083] are respectively the same as those in the foregoing embodiments, and will not be elaborated herein. Figure 15 and Figure 16 , the second dielectric layer 221 is patterned to expose a partial area of the groove 240, and a partial area of the groove 240 exposes the bit line 202. It can be understood that only a partial area of the groove 240 is exposed, that is, only a partial area of the second dielectric layer 221 is etched.

[0084] With reference to Figure 16 and Figure 17 , bit - line contact pads 212 are formed in a partial area of the groove 240.

[0085] It should be noted that a mask layer with an opening is required in the step of patterning the second dielectric layer 221. To form the bit - line contact pads 212, it is necessary to selectively remove Figure 15 a partial area of any second dielectric layer 221 in the structure shown, so the position of the opening in the mask layer can be adjusted according to the actual situation, so that the opening only exposes the partial area of the second dielectric layer 221 that needs to be removed. Due to the differences between the materials of the second dielectric layer 221, the bit line 202, and the first dielectric layer 211, in the step of patterning the second dielectric layer 221, even if the alignment accuracy between the opening in the mask layer and the partial area of the second dielectric layer 221 to be removed is not high, the removal process will only remove the second dielectric layer 221 exposed by the opening in the mask layer. Based on this, the bit - line contact pads 212 will only be formed in the grooves formed after removing the partial area of the second dielectric layer 121, thereby realizing the self - alignment formation process of the bit - line contact pads 212, which is beneficial to improving the alignment accuracy between the bit - line contact pads 212 and the bit line 202, and effectively avoiding the situation where the same bit - line contact pad 212 is in contact connection with two adjacent bit lines 202, causing the short - circuit of the two adjacent bit lines 202.

[0086] In addition, combining the step of metallizing a partial area of the substrate to form the bit line 202 and the step of forming the bit - line contact pads 212 is beneficial to simplifying the process steps of forming the bit line 202 and the bit - line contact pads 212. Moreover, a second dielectric layer 221 is provided between different grooves 240 corresponding to two adjacent bit lines 202. In this way, while being beneficial to improving the conductivity of the finally formed bit line 202, the bit - line contact pads 212 and the bit line 202 can be self - aligned to improve the alignment accuracy between the bit - line contact pads 212 and the bit line 202.

[0087] It should be noted that the low alignment accuracy between the opening in the mask layer and the partial area of the second dielectric layer 221 to be removed includes the following situations: In some cases, while the opening in the mask layer exposes a partial area of a second dielectric layer 221, it also exposes the first dielectric layer 211 or the bit line 202 adjacent to the second dielectric layer 221; in other cases, the opening in the mask layer exposes partial areas of two adjacent second dielectric layers 221 at the same time. It can be understood that due to the differences between the materials of the second dielectric layer 221, the bit line 202, and the first dielectric layer 211, the process of removing the second dielectric layer 221 will only have a relatively large etching rate for the second dielectric layer 221.

[0088] It is worth noting that Figure 14 the corresponding relationship between the bit line contact block 112 and the bit line 102 shown in Figure 17 and the corresponding relationship between the bit line contact block 212 and the bit line 202 shown in are both specific examples. In practical applications, the number of bit line contact blocks 112 in contact connection with the same bit line 102 is not limited, the spacing between two adjacent ones among the multiple bit line contact blocks 112 in contact connection with the same bit line 102 in the second direction Y is not limited, and the number of bit lines 102 included in the semiconductor structure is not limited. Therefore, various examples of the corresponding relationship between the bit line contact block 112 and the bit line 102 can be designed according to the actual situation, and it is impossible to list them all here. Therefore, the corresponding relationship between the bit line contact block 112 and the bit line 102 is summarized to a certain extent below. It is worth noting that in different embodiments, 112 and 212 both represent bit line contact blocks, 102 and 202 both represent bit lines, and 121 and 221 both represent second dielectric layers.

[0089] In some embodiments, taking the semiconductor structure shown in Figure 17 as an example, the bit line contact blocks 212 in contact connection with adjacent bit lines 202 can be arranged in a staggered manner along the first direction X. In other words, the different bit line contact blocks 212 in contact connection with adjacent bit lines 202 are not directly opposite along the first direction X, that is, the orthographic projections of the different bit line contact blocks 212 in contact connection with adjacent bit lines 202 on the projection plane formed by the first direction X and the third direction Z do not overlap; or, the different bit line contact blocks 212 in contact connection with adjacent bit lines 202 are only partially directly opposite along the first direction X, that is, the orthographic projections of the different bit line contact blocks 212 in contact connection with adjacent bit lines 202 on the projection plane formed by the first direction X and the third direction Z only partially overlap. In this way, it is beneficial to increase the spacing between the different bit line contact blocks 212 located on adjacent bit lines 202, reduce the electrical interference between the different bit line contact blocks 212, and thus be beneficial to improving the electrical performance of the semiconductor structure.

[0090] Still takingFigure 17 The semiconductor structure shown is an example. The bit-line contact blocks 212 in contact connection with the adjacent bit lines 202 can be arranged with a dislocation along the second direction Y. It should be noted that Figure 17 in the shown example, each bit line 202 has at least 1 bit-line contact block 212 in contact connection therewith. Not only are the bit-line contact blocks 212 in contact connection with the adjacent bit lines 202 arranged with a dislocation along the first direction X, but also the bit-line contact blocks 212 in contact connection with the adjacent bit lines 202 are arranged with a dislocation along the second direction Y. In this way, it is beneficial to increase the spacing between any adjacent bit-line contact blocks 212, further reduce the electrical interference between different bit-line contact blocks 212, and thus is beneficial to further improve the electrical performance of the semiconductor structure.

[0091] It should be noted that Figure 14 some of the bit-line contact blocks 112 in contact connection with the adjacent bit lines 102 shown, such as Figure 14 the 4 bit-line contact blocks 112 in contact connection with 4 bit lines 102 respectively located above, are also arranged with a dislocation along the first direction X; moreover, Figure 14 some of the bit-line contact blocks 112 in contact connection with the adjacent bit lines 102 shown, such as Figure 14 the 4 bit-line contact blocks 112 in contact connection with 2 bit lines 102 respectively located on the left, are also arranged with a dislocation along the second direction Y.

[0092] In some other embodiments, referring to Figure 18 18a in, regarding two adjacent bit lines 102 as a pair of bit lines, for a pair of bit lines, the different bit-line contact blocks 112 in contact connection therewith can be arranged with a dislocation along the second direction Y. From the layout of the entire bit lines 102 and bit-line contact blocks 112, although not all the different partial bit-line contact blocks 112 located on any adjacent bit lines 102 are arranged with a dislocation along the first direction X, the different bit-line contact blocks 112 in contact connection with a pair of bit lines are arranged with a dislocation along the first direction X.

[0093] In still some other embodiments, referring to Figure 18 18b in, when there is one bit-line contact block 112 in contact connection on some of the bit lines 102, the bit-line contact blocks 112 in contact connection with the adjacent bit lines 102 can be arranged with a dislocation only along the first direction X.

[0094] It should be noted that in practical applications, the arrangement mode on the different bit-line contact blocks located on adjacent bit lines can be adjusted according to actual requirements. For example, the different bit-line contact blocks located on adjacent bit lines can also be arranged facing each other along the first direction; or, some of the different bit-line contact blocks located on adjacent bit lines are arranged facing each other along the first direction, and the other part of the different bit-line contact blocks located on adjacent bit lines are arranged with a dislocation along the first direction.

[0095] Among them,Figure 18 These are two top - view structural diagrams of the bit line, gate structure, and bit - line contact block in an embodiment of the present disclosure. It should be noted that, for clearly showing the positional relationship among the bit line, gate structure, and bit - line contact block, Figure 18 in [reference] the bit line 102 is drawn in a perspective manner.

[0096] In the above various embodiments, taking the example shown in Figures 13 to 14 as a reference, along the direction from the first part 110 (refer to Figure 2 ), the third part 130 includes a first sub - part 150, a second sub - part 160, and a third sub - part 170 arranged in sequence. The first direction X and the second direction Y form a reference plane.

[0097] Refer to Figure 19 and Figure 20 , the substrate 100 may further include: a gate structure 105 and a third dielectric layer 131. The gate structure 105 surrounds the sidewalls of a plurality of second sub - parts 160 arranged along the first direction X, and the third dielectric layer 131 is at least located between adjacent gate structures 105.

[0098] It can be understood that the entire gate structure 105 can be regarded as a signal line extending along the first direction X, and this signal line surrounds the sidewalls of a plurality of second sub - parts 160 arranged along the first direction X. In other words, a second sub - part 160 and a partial region of the gate structure 105 surrounding its sidewall together form a vertical transistor. The second sub - part 160 can serve as the channel region in the vertical transistor, and one gate structure 105 can control the conduction or cutoff of a plurality of second sub - parts 160 arranged along the first direction X.

[0099] In some embodiments, the gate structure 105 may include: a gate dielectric layer (not shown in the figure), covering the sidewall surface of the second sub - part 160; a gate conductive layer (not shown in the figure), covering the sidewall surface of the gate dielectric layer away from the second sub - part 160, and there is a gap between adjacent gate conductive layers. Based on this, the third dielectric layer 131 at least fills the gap between adjacent gate conductive layers.

[0100] In some embodiments, refer to Figure 19 and Figure 20 , the substrate 100 may further include: a fourth dielectric layer 141. The fourth dielectric layer 141 fills the gap between the third part 130, the gate structure 105, and the third dielectric layer 131. It should be noted that the fourth dielectric layer 141 can be a multi - film layer structure.

[0101] It should be noted that Figures 1 to 15 in the figure which is a cross - sectional structure diagram, the gate structure, the third dielectric layer, and the fourth dielectric layer are not shown.

[0102] The manufacturing method provided by an embodiment of the present disclosure may further include the following steps:

[0103] Remove the first portion 110 (refer to Figure 2 ). It should be noted that in the foregoing embodiment, the remaining first portion 110 may be removed in step S103 or step S104. In practical applications, if the remaining first portion 110 is not removed in step S103 or step S104, it may be removed in this step.

[0104] Refer to Figures 21 to 23 , a second mask layer 106 is formed on a side of the first dielectric layer 111 away from the gate structure 105. The second mask layer 106 has a plurality of second openings 116. The orthographic projection of a second opening 116 on a reference plane overlaps at least with the orthographic projection of a gate structure 105 on the reference plane. It should be noted that to show the second openings 116 in the second mask layer 106, Figure 21 only the second mask layer 106 without the second openings 116 is filled with diagonal lines, and the approximate outline of each second opening 116 is drawn.

[0105] Wherein, Figure 22 is Figure 21 a schematic cross-sectional structure diagram of the structure shown in the second cross-sectional direction BB1; Figure 22 is Figure 21 a schematic cross-sectional structure diagram of the structure shown in the fourth cross-sectional direction DD1.

[0106] In some embodiments, the manufacturing method further includes: a spin-on dielectric layer is further formed between the second mask layer 106 and the first dielectric layer 111 to relieve the contact stress between the second mask layer 106 and the first dielectric layer 111 through the spin-on dielectric layer, and to improve the accuracy of pattern transfer from the second openings 116 in the second mask layer 106 to the first dielectric layer 111 and other dielectric layers opposite thereto.

[0107] It should be noted that in the second mask layer 106, the orthographic projection of any second opening 116 not only overlaps at least with the orthographic projection of a gate structure 105 on the reference plane, but also the orthographic projection of any second opening 116 on the reference plane is located in the orthographic projection of the first dielectric layer 111 on the reference plane. In other words, the orthographic projection of any second opening 116 on the reference plane is located in the orthographic projection of the interval between two adjacent bit lines 102 on the reference plane.

[0108] Combined with reference to Figure 22 and Figure 24 , and Figure 23 and Figure 25, using the third dielectric layer 131 as an etching stop layer, and using the second mask layer 106 as a mask to etch the first dielectric layer 111 exposed by the second opening 116 until the gate structure 105 is exposed and a via hole 107 is formed.

[0109] It should be noted that, in combination with reference Figure 22 and Figure 23 , there is a fourth dielectric layer 141 between adjacent first sub-parts 150. In other words, the fourth dielectric layer 141 surrounds the side walls of each first sub-part 150. Based on this, during the process of etching the first dielectric layer 111 exposed by the second opening 116 with the second mask layer 106 as a mask, the fourth dielectric layer 141 directly opposite to the second opening 116 in the third direction Z will also be exposed, and the fourth dielectric layer 141 will be patterned based on the second opening 116 to form a via hole 107 exposing the gate structure 105.

[0110] It should be noted that the materials of the first dielectric layer 111 and the fourth dielectric layer 141 can be the same, and there is a large difference between the material of the first dielectric layer 111 and the material of the third dielectric layer 131; or, although the materials of the first dielectric layer 111 and the fourth dielectric layer 141 are different, both of their materials have a large difference from the material of the third dielectric layer 131. In this way, in the step of forming the via hole 107, the etching process will only have a relatively high etching rate for the first dielectric layer 111 and the fourth dielectric layer 141, and will hardly etch the third dielectric layer 131, so that the third dielectric layer 131 can be used as an etching stop layer.

[0111] In one example, the materials of the first dielectric layer 111 and the fourth dielectric layer 141 can both be silicon oxide, and the material of the third dielectric layer 131 can be silicon nitride.

[0112] In combination with reference Figure 24 and Figure 26 , or with reference to Figure 25 and Figure 27 , a word line contact block 115 is formed in the via hole 107, and one gate structure 105 is in contact connection with at least one word line contact block 115.

[0113] In some embodiments, the orthographic projection of a second opening 116 on a reference plane only overlaps with the orthographic projection of one gate structure 105 on the reference plane, and one second opening 116 is only used to form one word line contact block 115.

[0114] It should be noted that Figures 21 to 23 the corresponding relationship between the second opening 116 and the gate structure 105 shown in Figures 21 to 23 is only an example. Since one second opening 116 corresponds to one word line contact block 115, Figure 26) and the corresponding relationship with the gate structure 105. In practical applications, there is no limit to the number of word line contact blocks 115 that are in contact connection with the same gate structure 105, nor is there a limit to the spacing between two adjacent ones among the multiple word line contact blocks 115 that are in contact connection with the same gate structure 105 in the first direction X, nor is there a limit to the number of gate structures 105 included in the semiconductor structure. Therefore, various examples of the corresponding relationship between the word line contact blocks 115 and the gate structure 105 can be designed according to the actual situation, and it is impossible to list them all here. Therefore, the corresponding relationship between the word line contact blocks 115 and the gate structure 105 is summarized to a certain extent below.

[0115] In some embodiments, referring to Figure 28 FIG. 28a, the word line contact blocks 115 in contact connection with adjacent gate structures 105 are arranged in a staggered manner along the first direction X. In other words, different word line contact blocks 115 in contact connection with adjacent gate structures 105 are not directly opposite to each other along the first direction X, that is, the orthographic projections of different word line contact blocks 115 in contact connection with adjacent gate structures 105 on the projection plane formed by the first direction X and the third direction Z do not overlap; or, different word line contact blocks 115 in contact connection with adjacent gate structures 105 are only partially directly opposite to each other along the first direction X, that is, the orthographic projections of different word line contact blocks 115 in contact connection with adjacent gate structures 105 on the projection plane formed by the first direction X and the third direction Z only partially overlap. In this way, it is beneficial to increase the spacing between different word line contact blocks 115 located on adjacent gate structures 105, reduce the electrical interference between these different word line contact blocks 115, and thus is beneficial to improving the electrical performance of the semiconductor structure.

[0116] In other embodiments, continuing to refer to Figure 28 FIG. 28a, the word line contact blocks 115 in contact connection with adjacent gate structures 105 are arranged in a staggered manner along the second direction Y. It should be noted that Figure 28 in the example shown in FIG. 28a, some gate structures 105 have no less than 1 word line contact block 115 in contact connection therewith. Not only are the word line contact blocks 115 in contact connection with adjacent gate structures 105 arranged in a staggered manner along the first direction X, but also the word line contact blocks 115 in contact connection with adjacent gate structures 105 are arranged in a staggered manner along the second direction Y. In this way, it is beneficial to increase the spacing between any adjacent word line contact blocks 115, further reduce the electrical interference between these different word line contact blocks 115, and thus is beneficial to further improving the electrical performance of the semiconductor structure.

[0117] In other embodiments, referring to Figure 28 FIG. 28b, when there is one word line contact block 115 in contact connection with adjacent multiple gate structures 105, the word line contact blocks 115 in contact connection with adjacent gate structures 105 can be arranged in a staggered manner only along the second direction Y.

[0118] In other embodiments, the word line contact blocks in contact connection with adjacent gate structures may be staggeredly arranged only along the first direction.

[0119] It should be noted that in practical applications, the arrangement modes on different word line contact blocks located on adjacent gate structures can be adjusted according to actual requirements. For example, different word line contact blocks located on adjacent gate structures may also be directly opposite along the first direction; or, some different word line contact blocks located on adjacent gate structures are directly opposite along the first direction, and other different word line contact blocks located on adjacent gate structures are staggeredly arranged along the first direction.

[0120] Among them, Figure 28 are two top-view structural schematic diagrams of the bit line, gate structure, bit line contact block and word line contact block in an embodiment of the present disclosure. It should be noted that, for clearly showing the positional relationship of the bit line, gate structure, bit line contact block and word line contact block, Figure 28 the bit line 102 is drawn in a perspective view in

[0121] In some embodiments, referring to Figure 23 , along the second direction Y, the length L1 of the second opening 116 is greater than the spacing L2 between two adjacent third dielectric layers 131; in combination with referring to Figure 23 and Figure 25 , in the step of forming the through hole 107, at least a part of the top surface of the third dielectric layer 131 far from the second part 120 (refer to Figure 2 ) is also exposed, and, along the second direction Y, only one of the adjacent gate structures 105 has a positive projection on the reference plane overlapping with the positive projection of the second opening 116 on the reference plane.

[0122] It should be noted that there are a plurality of second openings 116 in the second mask layer 106, and the lengths of the plurality of second openings 116 in the second direction Y may be different, and the length L1 of some of the second openings 116 may be greater than the spacing L2 between two adjacent third dielectric layers 131.

[0123] Based on this, even if the alignment accuracy between the second opening 116 in the second mask layer 106 and the gate structure 105 to be exposed is not high, in other words, as Figure 23As shown, the second opening 116 also faces the partial third dielectric layer 131. However, the etching process will only remove the first dielectric layer 111 exposed by the second opening 116 and the fourth dielectric layer 141 facing the second opening 116. The third dielectric layer 131 located between adjacent gate structures 105 will block the progress of the etching process, such that the bottom surface of a through hole 107 will only expose one gate structure 105, thereby realizing the self-alignment formation process of the word line contact block 115, which is conducive to improving the alignment accuracy between the word line contact block 115 and the gate structure 105, and effectively avoiding the situation where the same word line contact block 115 is in contact connection with two adjacent gate structures 105, causing the short circuit of the two adjacent gate structures 105, so as to improve the electrical performance of the semiconductor structure.

[0124] In addition, referring to Figure 23 , when in the second direction Y, the length L1 of the second opening 116 is greater than the spacing L2 between two adjacent third dielectric layers 131, referring to Figure 25 , in the second direction Y, the length of the part of the through hole 107 facing the first dielectric layer 111 is greater than the length of the part of the through hole 107 facing the third dielectric layer 131, such that the word line contact block 115 finally formed based on the through hole 107 is a dual damascene structure, that is, the word line contact block 115 is wider at the top and narrower at the bottom, which is conducive to increasing the conductivity of the word line contact block 115 itself by increasing the size of the word line contact block 115 while ensuring that one word line contact block 115 is only in contact connection with one gate structure 105.

[0125] Moreover, in the second direction Y, referring to Figure 21 and Figure 23 , only one of the adjacent gate structures 105 has a positive projection on the reference plane overlapping with the positive projection of the second opening 116 on the reference plane. In other words, among the multiple gate structures 105 arranged at intervals in the second direction Y, there is a complete gate structure 105 between two adjacent second openings 116 in the fourth cross-section direction DD1. The partial area of the gate structure 105 exposed by the through hole 107 (referring to Figure 25 ) will not be in the fourth cross-section direction DD1. For example, Figure 21 the second opening 116 corresponding to the gate structure 105 is located in the central area. Thus, the second openings 116 corresponding to two adjacent gate structures 105 are not adjacent in the second direction Y, so as to avoid the through holes 107 corresponding to two adjacent gate structures 105 being connected during the subsequent step of forming the through hole 107 based on the second opening 116, which is conducive to further avoiding the contact connection of the word line contact blocks 115 corresponding to two adjacent gate structures 105 in the second direction Y, and thus further avoiding the short circuit of the adjacent gate structures 105 through the word line contact block 115.

[0126] In practical applications, the third dielectric layer may also be located between adjacent bit lines. With reference to Figure 23 , the third dielectric layer may be embedded in the first dielectric layer, and the top surface of the third dielectric layer is flush with the top surface of the first dielectric layer. That is, the third dielectric layer is also located in the interval between adjacent bit lines. It can be understood that along the second direction Y, the first dielectric layer located between any two bit lines is also separated into two parts by the third dielectric layer.

[0127] Based on this, the orthographic projection of a second opening on the reference plane may overlap with the orthographic projections of at least two adjacent gate structures on the reference plane. That is, a second opening can simultaneously expose the first dielectric layer separated into two parts by the third dielectric layer, so that a second opening can be used to form at least two word line contact blocks. It can be understood that since a second opening can simultaneously expose the first dielectric layer separated into two parts by the third dielectric layer, using the third dielectric layer as an etching stop layer and the second mask layer as a mask to etch the first dielectric layer exposed by the second opening, a through hole is formed in each of the first dielectric layers separated into two parts by the third dielectric layer, so that at least two through holes spaced apart by the third dielectric layer can be formed along the second direction.

[0128] In some embodiments, with reference to Figure 22 and Figure 24 , the formed through hole 107 exposes at least the side wall of a first sub - part 150. It should be noted that the sizes of the multiple second openings 116 in the second mask layer 106 may be different in both the first direction X and the second direction Y. In practical applications, the sizes of the multiple second openings 116 in the second mask layer 106 may be approximately similar to the size of one of the multiple second openings 116 mentioned in the above embodiments. Figures 21 to 23 The purpose of showing different sizes of the multiple second openings 116 in

[0129] is to have corresponding legends for multiple size types of second openings 116 for detailed description. Figure 22 With reference to Figure 24 , since the size of some second openings 116 in the first direction X is equal to the interval between adjacent bit lines 102 in the first direction X, in practical applications, the size of some second openings in the first direction may be slightly larger than the interval between adjacent bit lines in the first direction. With reference to

[0130] It should be noted that Figure 24Taking the example that two side walls of the two first sub-parts 150 are exposed through a through hole 107, in actual reference, due to the alignment deviation between the second opening and the first dielectric layer, for example, the second opening exposes a partial area of the first dielectric layer 111 and a small part of the second dielectric layer, so the through hole formed based on the second opening will only expose the side wall of one first sub-part 150.

[0131] On the premise that the through hole 107 formed based on the formation of the second opening 116 exposes at least the side wall of one first sub-part 150, after forming the through hole 107 and before forming the word line contact block 115, the manufacturing method may further include: referring to Figure 24 and Figure 26 Forming a protective layer 108 on the side wall of the through hole 107, and the protective layer 108 and the bottom surface of the through hole 107 jointly enclose a sub-through hole; forming a word line contact block 115 in the through hole 107, including: forming a word line contact block 115 that fills the sub-through hole. In this way, when the through hole 107 formed due to the alignment deviation between the second opening 116 and the first dielectric layer 111 exposes at least the side wall of one first sub-part 150, it is beneficial to form a protective layer 108 on the side wall of the through hole 107 to avoid the contact connection between the formed word line contact block 115 and the bit line 102 and the third part 130, thereby effectively avoiding the problem of short circuit between the bit line 102 and the gate structure 105 through the word line contact block 115 and improving the electrical performance of the semiconductor structure.

[0132] It should be noted that forming the protective layer 108 on the side wall of the through hole 107 includes the following two situations: In some cases, referring to Figure 26 , the protective layer 108 is formed on all side walls of the through hole 107 extending in the third direction Z, and the sub-through hole is jointly enclosed by the protective layer 108 and the bottom surface of the through hole 107. In this way, whether in the first direction X or in the second direction Y, the side wall of the through hole 107 is formed with the protective layer 108.

[0133] In other cases, referring to Figure 27 , the protective layer 108 is only formed on two opposite side walls of the through hole 107 in the first direction X, and the protective layer will not be formed on two opposite side walls of the through hole 107 in the second direction Y. In this way, the protective layer 108 can be formed between the bit line 102, the first sub-part 150 and the word line contact block 115, and the size of the word line contact block 115 in the second direction Y can be increased to ensure that the word line contact block 115 has good electrical conductivity.

[0134] In other embodiments, continuing to refer to Figure 22 , the size of a part of the second opening 116 in the first direction X can also be smaller than the interval between adjacent bit lines 102 in the first direction X. Referring to Figure 24, the through hole 107 formed based on the formation of the second opening 116 of this type will not expose the side wall of the first sub - part 150. The side wall of the through hole 107 is jointly surrounded by the remaining first dielectric layer 111 and the remaining fourth dielectric layer 11. It can be understood that in this case, there is no need to form a protective layer.

[0135] It should be noted that the above - mentioned method for forming the word - line contact block is applicable to the above - mentioned two methods for forming the bit - line.

[0136] In summary, on the one hand, combining the step of metallizing a partial area of the substrate 100 to form the bit - line 102 and the step of forming the bit - line contact block 112 is beneficial to simplifying the process steps of forming the bit - line 102 and the bit - line contact block 112. On the other hand, removing a part of the substrate 100 to expose the remaining area of the second part 120 in the substrate 100 and forming a groove 140 between adjacent first dielectric layers 111. It can be understood that the remaining area of the second part 120 constitutes the bottom surface of the groove 140, and at least part of the side surface of the groove 140 is formed by the second dielectric layer 121. In other words, there is a second dielectric layer 121 between different grooves 140 corresponding to two adjacent bit - lines 12. Therefore, when forming at least one bit - line contact block 112 in at least part of the grooves 140, since the bit - line contact block 112 is located in the groove 140, there is also a second dielectric layer 121 between different bit - line contact blocks 112 corresponding to two adjacent bit - lines 102, effectively avoiding the situation where two adjacent bit - lines 102 are short - circuited through the same bit - line contact block 112. Thus, it is beneficial to improve the conductivity of the finally formed bit - line 102 while enabling self - alignment between the bit - line contact block 112 and the bit - line 102 to improve the alignment accuracy between the bit - line contact block 112 and the bit - line 102.

[0137] Another embodiment of the present disclosure also provides a semiconductor structure formed by the manufacturing method provided in the foregoing embodiment. The following will describe in detail the semiconductor structure provided in another embodiment of the present disclosure with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiment will not be described in detail here.

[0138] Refer to Figure 26 and Figure 27, the semiconductor structure includes: a substrate 100, within which there are vertical transistors. The vertical transistors include semiconductor pillars extending along a third direction Z. The semiconductor pillars have a first surface and a second surface opposite to each other in the third direction Z. The first surface is the back surface of the substrate 100; a plurality of bit lines 102 arranged at intervals along a first direction X, one bit line 102 is in contact with a plurality of first surfaces arranged at intervals along a second direction Y. The bit lines 102 have metal-semiconductor compounds 122. The first direction X, the second direction Y, and the third direction intersect pairwise; a plurality of bit line contact blocks 112, one side of a bit line 102 away from the semiconductor pillar is in contact connection with at least one bit line contact block 112, and the side walls of the bit line contact blocks 112 extending along the third direction are surrounded by dielectric layers.

[0139] It can be understood that the bit line contact blocks 112 extend from the back surface of the substrate 100 into the substrate to achieve contact connection with the bit lines 102. Among them, one side of a bit line 102 away from the semiconductor pillar is in contact connection with at least one bit line contact block 112, that is, the bit line contact blocks 112 are formed in the semiconductor structure based on the back surface of the substrate 100.

[0140] It should be noted that the semiconductor pillars extending along the third direction Z included in the vertical transistors are Figure 26 and Figure 27 the third part 130 shown in Figure 26 and Figure 27 the substrate 100 shown in

[0141] In addition, that the side walls of the bit line contact blocks 112 extending along the third direction Z are surrounded by dielectric layers means that, referring to Figure 19 and Figure 20 , the side walls of the bit line contact blocks 112 extending along the third direction Z are either covered by a first dielectric layer 111 or covered by a second dielectric layer 121.

[0142] In some embodiments, continuing to refer to Figure 26 and Figure 27 , along the third direction Z, the semiconductor pillar includes a third sub-part 170, a first sub-part 150, and a second sub-part 160 arranged in sequence. The first sub-part 150 is in contact connection with the bit line 102; the vertical transistor further includes a gate structure 105, and the gate structure 105 surrounds the side walls of a plurality of second sub-parts 160 arranged along the first direction X; the semiconductor structure may further include: a plurality of word line contact blocks 115, one side of a gate structure 105 away from the second surface is in contact connection with at least one word line contact block 115.

[0143] In some embodiments, continuing to refer to Figure 26 and Figure 27The semiconductor structure may further include: a protection layer 108 located on two opposite sidewalls of the word line contact block 115 along the first direction X, and / or located on two opposite sidewalls of the word line contact block 115 along the second direction Y.

[0144] In some embodiments, reference Figure 28 The word line contact blocks 115 that are in contact with the adjacent gate structures 105 are arranged in a staggered manner along the first direction X, and / or the word line contact blocks 115 that are in contact with the adjacent gate structures 105 are arranged in a staggered manner along the second direction Y.

[0145] In some embodiments, reference Figure 14 , Figure 17 and Figure 18 The bit line contact blocks 112 that are in contact with the adjacent bit lines 102 are arranged in a staggered manner along the first direction X, and / or the bit line contact blocks 112 that are in contact with the adjacent bit lines 102 are arranged in a staggered manner along the second direction Y.

[0146] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, comprising: providing a substrate and a first dielectric layer, the substrate including a first part, a plurality of second parts located on the first part and arranged at intervals along a first direction, and a plurality of third parts located on a side of the second parts away from the first part and arranged at intervals along a second direction, the first dielectric layer being at least located between adjacent second parts, the second parts being used to form bit lines, the third parts being used to form semiconductor columns, and the first direction and the second direction intersecting; removing at least part of the first part and part of the thickness of the second part to expose the remaining area of the second part, and forming grooves between adjacent first dielectric layers; performing a metallization process on the second part exposed by the grooves to form the bit lines extending along the second direction; forming at least one bit line contact block in at least part of the grooves, and one of the bit lines being in contact connection with at least one of the bit line contact blocks.

2. The manufacturing method according to claim 1, characterized in that, the step of removing at least part of the first part and part of the thickness of the second part includes: forming a first mask layer having first openings extending along the first direction, and a plurality of the first openings being arranged at intervals along the second direction; etching the first part and part of the thickness of the second part exposed by the first openings with the first mask layer as a mask to form a plurality of the grooves arranged at intervals along the first direction and the second direction; the step of forming at least one of the bit line contact blocks in at least part of the grooves includes: forming a second dielectric layer filling the grooves; removing the second dielectric layer in part of the grooves and forming the bit line contact blocks.

3. The manufacturing method according to claim 2, characterized in that, the first direction and the second direction form a reference plane, a positive projection of the first opening on the reference plane is a first projection, a positive projection on the reference plane of an interval between adjacent third parts along the second direction is a second projection, and a positive projection on the reference plane of the third parts is a third projection; wherein, the first projection is located in the second projection; or, the first projection and the third projection at least partially overlap.

4. The manufacturing method according to claim 1, characterized in that, the step of removing at least part of the first part and part of the thickness of the second part includes: entirely removing the first part to expose the second part; continuing to remove part of the thickness of the second part to form the grooves extending along the second direction, and the grooves corresponding to the second parts one by one; the step of forming at least one of the bit line contact blocks in at least part of the grooves includes: forming a second dielectric layer filling the grooves; performing a patterning process on the second dielectric layer to expose part of the areas of the grooves, and part of the areas of the grooves exposing the bit lines; forming the bit line contact blocks in part of the areas of the grooves.

5. The manufacturing method according to any one of claims 1 to 4, It is characterized in that the bit line contact blocks in contact connection with adjacent said bit lines are arranged in a staggered manner along the first direction, and / or, the bit line contact blocks in contact connection with adjacent said bit lines are arranged in a staggered manner along the second direction.

6. The manufacturing method according to any one of claims 1 to 4, It is characterized in that along the direction from the first part to the second part, the third part includes a first sub-part, a second sub-part and a third sub-part arranged in sequence, and the first direction and the second direction form a reference plane; the substrate further includes: a gate structure and a third dielectric layer, the gate structure surrounds the side walls of a plurality of the second sub-parts arranged along the first direction, and the third dielectric layer is at least located between adjacent said gate structures; The manufacturing method further includes: removing the first part; forming a second mask layer on a side of the first dielectric layer away from the gate structure, the second mask layer having a plurality of second openings, and a positive projection of one of the second openings on the reference plane overlaps at least with a positive projection of one of the gate structures on the reference plane; using the third dielectric layer as an etching stop layer and using the second mask layer as a mask to etch the first dielectric layer exposed by the second opening until the gate structure is exposed and a through hole is formed; forming a word line contact block in the through hole, and one of the gate structures is in contact connection with at least one of the word line contact blocks.

7. The manufacturing method according to claim 6, It is characterized in that a positive projection of one of the second openings on the reference plane only overlaps with a positive projection of one of the gate structures on the reference plane, and one of the second openings is only used to form one of the word line contact blocks.

8. The manufacturing method according to claim 7, It is characterized in that along the second direction, the length of the second opening is greater than the distance between adjacent two of the third dielectric layers, and in the step of forming the through hole, at least a part of the top surface of the third dielectric layer away from the second part is also exposed, and along the second direction, only a positive projection of one of the adjacent gate structures on the reference plane overlaps with a positive projection of the second opening on the reference plane.

9. The manufacturing method according to claim 6, It is characterized in that the third dielectric layer is also located between adjacent said bit lines, a positive projection of one of the second openings on the reference plane overlaps with positive projections of at least two adjacent gate structures on the reference plane, and one of the second openings is used to form at least two of the word line contact blocks; in the step of using the third dielectric layer as an etching stop layer and using the second mask layer as a mask to etch the first dielectric layer exposed by the second opening, at least two through holes spaced apart by the third dielectric layer are formed along the second direction.

10. The manufacturing method according to claim 6, It is characterized in that the formed through hole exposes at least a side wall of one of the first sub-parts; after forming the through hole and before forming the word line contact block, it further includes: forming a protective layer on the side wall of the through hole, and the protective layer and the bottom surface of the through hole together enclose a sub-through hole. Forming the word line contact block in the through hole includes: forming the word line contact block that fills the sub-through hole.

11. A semiconductor structure characterized in that it includes: a substrate having vertical transistors therein, the vertical transistors including semiconductor columns extending along a third direction, the semiconductor columns having a first surface and a second surface opposite to each other in the third direction, and the first surface being the back surface of the substrate; a plurality of bit lines arranged at intervals along a first direction, one of the bit lines contacting a plurality of first surfaces arranged at intervals along a second direction, the bit lines having metal semiconductor compounds therein, and the first direction, the second direction, and the third direction intersect pairwise; a plurality of bit line contact blocks, one of the bit lines contacting and connecting with at least one of the bit line contact blocks on a side away from the semiconductor column along the third direction, and side walls of the bit line contact blocks extending along the third direction being surrounded by dielectric layers.

12. The semiconductor structure according to claim 11, characterized in that along the third direction, the semiconductor column includes a first sub - part, a second sub - part, and a third sub - part arranged in sequence, the first sub - part contacting and connecting with the bit line; the vertical transistor further includes a gate structure surrounding side walls of a plurality of the second sub - parts arranged along the first direction; the semiconductor structure further includes: a plurality of word line contact blocks, one of the gate structures contacting and connecting with at least one of the word line contact blocks on a side away from the second surface along the third direction.

13. The semiconductor structure according to claim 12, characterized in that it further includes: a protective layer located on two opposite side walls of the word line contact block along the first direction, and / or located on two opposite side walls of the word line contact block along the second direction.

14. The semiconductor structure according to claim 12, characterized in that the word line contact blocks contacting and connecting with adjacent gate structures are arranged staggeredly along the first direction, and / or the word line contact blocks contacting and connecting with adjacent gate structures are arranged staggeredly along the second direction.

15. The semiconductor structure according to claim 11, characterized in that the bit line contact blocks contacting and connecting with adjacent bit lines are arranged staggeredly along the first direction, and / or the bit line contact blocks contacting and connecting with adjacent bit lines are arranged staggeredly along the second direction.

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