Semiconductor device with channel structure

Abstract

A semiconductor device includes: an information storage structure on a substrate; a landing pad on the information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; and a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure. The lower surface of the horizontal portion is located at a level lower than the upper end of the landing pad. A side surface of the vertical channel portion is in partial contact with the landing pad.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device including a channel structure. Background Art

[0002] As the demand for high performance, speed, and / or multifunctionality of semiconductor devices increases, the integration degree of semiconductor devices also increases. When manufacturing a finely patterned semiconductor device in response to the trend of high integration of semiconductor devices, it is necessary to implement a pattern having a fine width or a fine pitch distance. Summary of the Invention

[0003] One aspect of the inventive concept is to provide a semiconductor device including a channel structure disposed on an information storage structure.

[0004] According to an aspect of the inventive concept, a semiconductor device includes: an information storage structure on a substrate; a landing pad on the information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; and a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure. A lower surface of the horizontal portion is located at a level lower than an upper end of the landing pad. A side surface of the vertical channel portion is in partial contact with the landing pad.

[0005] According to an aspect of the inventive concept, a semiconductor device includes: a cell array structure; and a peripheral circuit structure vertically overlapping the cell array structure and including circuit elements. The cell array structure includes: an information storage structure; a landing pad on the information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; a first insulating pattern contacting the vertical channel portion; a second insulating pattern covering the gate electrode; and a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure. An upper surface of the vertical channel portion is disposed at a level higher than an upper surface of the first insulating pattern, and a lower surface of the horizontal portion is disposed at a level lower than a lower surface of the first insulating pattern.

[0006] According to an aspect of the inventive concept, a semiconductor device includes: an information storage structure on a substrate; a landing pad on the information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; a dielectric structure between the channel structure and the gate electrode; a first insulating pattern contacting the vertical channel portion; a second insulating pattern covering the gate electrode and the dielectric structure; a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure; a first bonding layer on the bit line; and a peripheral circuit structure including a second bonding layer bonded to the first bonding layer and circuit elements on the second bonding layer. A side surface of a lower portion of the vertical channel portion contacts the landing pad, and a side surface of an upper portion of the vertical channel portion contacts the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan view of a semiconductor device according to an exemplary embodiment.

[0009] Figure 2 is Figure 1 a vertical cross-sectional view taken along line I-I' of the semiconductor device shown in

[0010] Figure 3 is Figure 1 a vertical cross-sectional view taken along line II-II' of the semiconductor device shown in

[0011] Figure 4 is Figure 2 a partial enlarged view of the semiconductor device shown in

[0012] Figures 5 to 10 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0013] Figure 11 and Figure 12 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0014] Figures 13A to 13K is a vertical cross-sectional view shown in process sequence for illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0015] Figure 14 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0016] Figure 15 is Figure 14 a partial enlarged view of the semiconductor device shown in

[0017] Figure 16 and Figure 17 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0018] Figures 18A to 18C is a vertical cross-sectional view shown according to a process sequence for illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0019] Figure 19 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0020] Figure 20 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0021] Figures 21A to 21D is a vertical cross-sectional view shown according to a process sequence for illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. Detailed Embodiments

[0022] Hereinafter, preferred embodiments of the inventive concept will be described with reference to the accompanying drawings. Like reference numerals always refer to like elements.

[0023] It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, it can be directly connected or coupled to the other element or on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "in contact" with another element or "contacting" another element (or any form of the word "contact" is used), there are no intervening elements at the point of contact.

[0024] Terms used herein, such as "identical," "equal," "planar," or "coplanar," when referring to an orientation, layout, position, shape, size, quantity, or other metric, do not necessarily denote exactly the same orientation, layout, position, shape, size, quantity, or other metric, but are intended to encompass orientations, layouts, positions, shapes, sizes, quantities, or other metrics that are almost the same within an acceptable range of variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

[0025] Figure 1 is a plan view of a semiconductor device according to an exemplary embodiment. Figure 2 is Figure 1 a vertical cross-sectional view taken along line I-I' of the semiconductor device shown in Figure 3 is Figure 1 a vertical cross-sectional view taken along line II-II' of the semiconductor device shown in

[0026] Reference Figures 1 to 3 According to an embodiment, the semiconductor device 100 may include a cell array structure CS and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS may include an information storage structure DS, a landing pad 120, a channel structure 140, and a bit line 160 disposed on a substrate 103. Hereinafter, the X direction and the Y direction may be parallel to the upper surface of the substrate 103 and may be defined as horizontal directions, and the Z direction may be perpendicular to the upper surface of the substrate 103 and may be defined as a vertical direction (e.g., an upward direction or a downward direction). The X direction, the Y direction, and the Z direction may be orthogonal to each other.

[0027] The substrate 103 may include a semiconductor material, such as a group-IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor. For example, the group-IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 103 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0028] The information storage structure DS may be disposed on the substrate 103. In an embodiment, the semiconductor device 100 may further include an insulating layer 105 disposed between the substrate 103 and the information storage structure DS. The insulating layer 105 may electrically insulate the substrate 103 from the peripheral circuit structure PS. The insulating layer 105 may contact the upper surface of the substrate 103 and the lower surface of the information storage structure DS, but the embodiment is not limited thereto.

[0029] The information storage structure DS may include a plate electrode PL, a first electrode E1, a second electrode E2 on the first electrode E1, and a dielectric layer DL between each first electrode E1 and the second electrode E2.

[0030] The plate electrode PL may be disposed on the insulating layer 105 and may cover the insulating layer 105. The first electrode E1 may be disposed on the plate electrode PL and may extend in a vertical direction (e.g., the Z direction). The first electrodes E1 may be spaced apart from each other in a horizontal direction (e.g., the X direction). The plate electrode PL and the first electrode E1 may be formed of or include at least one of TiN, TiAlN, TiSiN, TaN, TaAlN, TaSiN, or WN.

[0031] The unit array structure CS may further include a lower support layer 110 and an upper support layer 113 disposed between the first electrodes E1. The lower support layer 110 and the upper support layer 113 may be in contact with the side surfaces of the first electrodes E1 and may support the first electrodes E1. The upper support layer 113 may be disposed on the lower support layer 110. For example, the upper surface of the upper support layer 113 may be coplanar with the upper surface of the first electrodes E1. In an embodiment, the lower support layer 110 may be omitted. The lower support layer 110 and the upper support layer 113 may include an insulating material and may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the lower support layer 110 and the upper support layer 113 may include silicon nitride.

[0032] The dielectric layer DL may cover the first electrodes E1, the lower support layer 110, and the upper support layer 113. For example, the dielectric layer DL may be conformally formed along the surfaces of the plate electrode PL, the first electrodes E1, the lower support layer 110, and the upper support layer 113. The dielectric layer DL may cover the upper and lower surfaces of the lower support layer 110 and the lower surface of the upper support layer 113. For example, the dielectric layer DL may be in contact with the upper and lower surfaces of the lower support layer 110 and the lower surface of the upper support layer 113. In addition, the dielectric layer DL may be in contact with the side surfaces of the first electrodes E1.

[0033] In an embodiment, the information storage structure DS may be a capacitor that stores information in a DRAM. For example, the dielectric layer DL of the information storage structure DS may be a capacitor dielectric layer of a DRAM, and the dielectric layer DL may be formed of or include a high-κ dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0034] In another example, the information storage structure DS may be a structure that stores information in a memory different from a DRAM. For example, the information storage structure DS may be a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer DL may be a ferroelectric layer capable of recording data using a polarization state. In another example, the dielectric layer DL may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. In this case, the lower dielectric layer may be formed of or include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-κ dielectric.

[0035] In an embodiment, when the dielectric layer DL includes an information storage layer, the information storage structure DS may be omitted.

[0036] The second electrode E2 may cover the dielectric layer DL and may fill the space between the first electrodes E1. The second electrode E2 may not cover the upper surface of the first electrode E1, and the upper surface of the second electrode E2 may be at a level lower than the upper surface of the first electrode E1. The second electrode E2 may include a semiconductor material and may include, for example, silicon germanium (SiGe) containing impurities. In an embodiment, the first electrode E1 may be referred to as a lower electrode, and the plate electrode PL and the second electrode E2 may be referred to as upper electrodes.

[0037] The landing pad 120 may be disposed on the information storage structure DS. For example, each landing pad 120 may be in contact with and electrically connected to the upper surface of the corresponding first electrode E1. In an embodiment, the horizontal width of the lower surface of the landing pad 120 may be greater than the horizontal width of the upper surface of the first electrode E1. In an embodiment, the horizontal width of the landing pad 120 may become smaller in the upward direction (e.g., the Z direction). For example, the horizontal width of the landing pad 120 may become smaller toward the channel structure 140. In an exemplary embodiment, the horizontal width of the lower surface of the landing pad 120 and the horizontal width of the upper surface of the landing pad 120 may be greater than the horizontal width of the upper surface of the first electrode E1.

[0038] The landing pad 120 may be formed of or include a metal nitride, a metal, or a combination thereof. The metal nitride may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the metal may include a metal material such as W, Mo, etc.

[0039] The cell array structure CS may further include a pad insulating layer 123 covering the landing pad 120. The pad insulating layer 123 may contact the side surface and the upper surface of the landing pad 120. The lower surface of the pad insulating layer 123 may be in contact with the upper surface of the upper support layer 113, and the upper surface of the pad insulating layer 123 may be at a level higher than the level of the upper surface of the landing pad 120. The lower surface of the pad insulating layer 123 may be coplanar with the lower surface of the landing pad 120. The pad insulating layer 123 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof, and may include, for example, silicon nitride.

[0040] The cell array structure CS may further include a first insulating pattern 130 contacting the pad insulating layer 123. The first insulating pattern 130 may extend longitudinally in the Y direction and may be spaced apart from each other in the X direction. The first insulating pattern 130 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first insulating pattern 130 may be formed as a single layer or multiple layers.

[0041] The channel structure 140 may be disposed on the landing pad 120. The channel structure 140 may include a horizontal portion 140L that contacts and is electrically connected to the landing pad 120, and a vertical channel portion 140S that extends in an upward direction (e.g., the Z direction) from one end of the horizontal portion 140L in the X direction. The lower surface of the horizontal portion 140L may contact the landing pad 120, and the horizontal portion 140L may be electrically connected to the landing pad 120. In an embodiment, the vertical channel portion 140S may extend in a direction inclined with respect to the vertical direction (Z direction), but the inventive concept is not limited thereto. The channel structures 140 may be spaced apart from each other in the X direction and the Y direction. The height of each channel structure 140 may be greater than the height of each first insulating pattern 130. For example, the upper surface of the channel structure 140 may be at a higher vertical level than the upper surface of the first insulating pattern 130.

[0042] Figure 4 is Figure 2 a partial enlarged view of the semiconductor device shown in Figure 4 may correspond to Figure 2 portion A shown in

[0043] Further referring to Figure 4 , the lower surface of the horizontal portion 140L and the side surface of the vertical channel portion 140S may contact the landing pad 120. For example, the lower surface of the horizontal portion 140L may be at a level lower than the upper surface of the landing pad 120. The landing pad 120 may include a recessed area R1 formed on the upper surface of the landing pad 120, and the recessed area R1 may contact the horizontal portion 140L and the vertical channel portion 140S. In addition, the side surface of the vertical channel portion 140S may partially contact the pad insulating layer 123.

[0044] As Figure 4 shown in , since two surfaces of the channel structure 140 according to an embodiment may contact the landing pad 120, the contact area between the channel structure 140 and the landing pad 120 may be increased and the contact resistance may be reduced. Accordingly, the electrical characteristics of the semiconductor device 100 may be improved.

[0045] The horizontal distance between the channel structures 140 may not be constant. For example, a first and a second channel structure 140 among the channel structures 140 may be spaced apart from each other with a second insulating pattern 150 therebetween. The distance D1 between the first channel structure 140 and the second channel structure 140 at a first vertical level equal to the lower surface of the bit line 160 may be greater than the distance D2 between the first channel structure 140 and the second channel structure 140 at a second vertical level equal to the upper surface of the landing pad 120.

[0046] The channel structure 140 can be formed of a semiconductor material such as silicon. The channel structure 140 can be formed of single-crystalline silicon or polycrystalline silicon. The channel structure 140 is not limited to semiconductor materials such as silicon, and can be formed of other semiconductor materials that can be used as the channel region of a transistor. For example, the channel structure 140 can include an oxide semiconductor layer or a two-dimensional material layer that can be used as the channel region of a transistor.

[0047] The oxide semiconductor layer can include indium gallium zinc oxide (IGZO), but the embodiments are not limited thereto. For example, the oxide semiconductor layer can include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc nitride oxide (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or indium gallium silicon oxide (InGaSiO).

[0048] The two-dimensional material layer can include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, and a hexagonal boron nitride (hBN) material layer, which can have semiconductor characteristics. For example, the two-dimensional material layer can be BiOSe, CrI, WSe 2 , MoS 2 , TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, or a Janus 2D material, which can form a two-dimensional material.

[0049] The cell array structure CS can further include a gate electrode 146 disposed on the channel structure 140 and a dielectric structure 143 disposed between the gate electrode 146 and the channel structure 140.

[0050] When viewed in a plan view, the gate electrode 146 may cross the bit line 160. For example, the gate electrode 146 may extend longitudinally in the Y direction along a side surface of the first insulating pattern 130 and may be spaced apart from each other in the X direction. The gate electrode 146 may overlap a horizontal portion 140L of the channel structure 140 in a vertical direction. An upper end of the gate electrode 146 may be located at a level lower than an upper surface of the first insulating pattern 130. At least one of the gate electrodes 146 may be a cell gate electrode or a word line.

[0051] The dielectric structure 143 may be disposed between the gate electrode 146 and the vertical channel portion 140S and between the gate electrode 146 and the horizontal portion 140L. The dielectric structure 143 may contact the gate electrode 146, the vertical channel portion 140S, the horizontal portion 140L, and the second insulating pattern 150. An upper surface of the dielectric structure 143 may contact the bit line 160. In an embodiment, a portion of the dielectric structure 143 may cover the upper surface of the first insulating pattern 130, but the inventive concept is not limited thereto.

[0052] In an example, each dielectric structure 143 may be a tunnel dielectric layer that does not include an information storage layer. For example, each dielectric structure 143 may include at least one of silicon oxide or a high-κ dielectric. The high-κ dielectric may include a metal oxide or a metal oxynitride. For example, the high-κ dielectric may be made of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 , Al 2 O 3 or a combination thereof, but the inventive concept is not limited thereto. Each dielectric structure 143 may be formed as a single layer or multiple layers of the above materials.

[0053] In another example, each dielectric structure 143 may include an information storage layer and a dielectric layer. For example, each dielectric structure 143 may have polarization characteristics depending on an electric field and may include a ferroelectric layer that may have a remanent polarization due to dipoles even in the absence of an external electric field. The polarization state in the ferroelectric layer may be used to record data. Thus, each dielectric structure 143 may include a ferroelectric layer, which may be referred to as an information storage layer. The ferroelectric layer that may be the information storage layer may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may include an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer that may be the information storage layer may include a ferroelectric material doped with impurities (such as at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, or Sr). For example, the ferroelectric layer that may be the information storage layer may be a material doped with at least one of impurities (C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, or Sr) in addition to at least one of HfO 2 , ZrO 2 or HZrO.

[0054] In the dielectric structure 143, the information storage layer is not limited to the above material types and may include materials capable of storing information.

[0055] The cell array structure CS may further include a second insulating pattern 150 covering the gate electrode 146. The second insulating pattern 150 may contact the gate electrode 146. The second insulating pattern 150 may include a lower portion 151 and an upper portion 152. The lower portion 151 of the second insulating pattern 150 may vertically extend between the horizontal portions 140L of the channel structure 140 and between the gate electrodes 146. The lower surface of the lower portion of the second insulating pattern 150 may be coplanar with the lower surface of the horizontal portion 140L. The horizontal width of the upper portion 152 of the second insulating pattern 150 may be greater than the horizontal width of the lower portion 151. The upper surface of the upper portion 152 of the second insulating pattern 150 may be coplanar with the upper surface of the vertical channel portion 140S. In an embodiment, the height of the second insulating pattern 150 may be equal to the height of the channel structure 140 and may be greater than the height of the first insulating pattern 130. The second insulating pattern 150 may longitudinally extend in the Y direction and may be spaced apart from each other in the X direction. The second insulating pattern 150 may be alternately arranged with the first insulating pattern 130 in the X direction.

[0056] The second insulating pattern 150 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The second insulating pattern 150 may be formed as a single layer or a multi-layer.

[0057] The bit line 160 can be disposed on the channel structure 140 and can cross the gate electrode 146. The bit line 160 can extend longitudinally in the X direction and can be spaced apart from each other in the Y direction. The bit line 160 can be electrically connected to the landing pad 120 through the channel structure 140. The bit line 160 can include a metal layer and a barrier layer covering the side and bottom surfaces of the metal layer. The barrier layer can include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the metal layer can include a metal material such as W, Mo, etc.

[0058] The upper and side surfaces of the vertical channel portion 140S can be in contact with the bit line 160. For example, the bit line 160 can include a protrusion 161 that contacts the first insulating pattern 130 and extends downward from the bottom surface of the bit line 160. The lower end of the protrusion 161 can be located at a level lower than the upper surface of the vertical channel portion 140S and can be in contact with the side surface of the vertical channel portion 140S. The bottom surface of the protrusion 161 can contact the upper surface of the first insulating pattern 130.

[0059] As Figure 4 shown, since two surfaces of the channel structure 140 according to the embodiment can be in contact with the bit line 160, the contact area between the channel structure 140 and the bit line 160 can be increased, and the contact resistance can be reduced. Therefore, the electrical characteristics of the semiconductor device 100 can be improved.

[0060] The cell array structure CS can further include a bit line insulating layer 165 disposed between the bit lines 160. The bit line insulating layer 165 can be disposed at the same level as the bit line 160 and can electrically insulate the bit lines 160 from each other. For example, the upper and lower surfaces of the bit line insulating layer 165 can be coplanar with the upper and lower surfaces of the bit line 160, respectively. The bit line insulating layer 165 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0061] Although not shown, in some embodiments, the cell array structure CS can further include shielding patterns that extend in the X direction and are spaced apart from each other in the Y direction. The shielding patterns can be alternately arranged with the bit lines 160 in the Y direction. The lower surface of the shielding pattern can be located at a level lower than the lower surface of the bit line 160, and the upper surface of the shielding pattern can be located at a level lower than the upper surface of the bit line 160. The shielding patterns can reduce the capacitance between the bit lines 160.

[0062] The shielding patterns can include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0063] The cell array structure CS may further include a bonding layer BL1 disposed on the bit line 160 and the bit line insulating layer 165. The bonding layer BL1 may include an upper insulating layer 170 and bonding pads 173. The bonding pads 173 may be disposed in the upper insulating layer 170. For example, the upper surface of the bonding pad 173 may be coplanar with the upper surface of the upper insulating layer 170. The upper insulating layer 170 may contact the lower surface and the side surfaces of the bonding pad 173. The bit line 160 may be electrically connected to at least one of the bonding pads 173. In an embodiment, an interconnection layer may be further disposed in the upper insulating layer 170 to electrically connect the bonding pad 173 and the bit line 160.

[0064] The peripheral circuit structure PS may be disposed on the cell array structure CS. The peripheral circuit structure PS may include a substrate 3, circuit elements TR, peripheral plugs 20, peripheral interconnections 23, a first peripheral insulating layer 30, and a second peripheral insulating layer 32.

[0065] The substrate 3 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 3 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0066] The circuit elements TR may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit. The circuit elements TR may include peripheral transistors. For example, the peripheral transistors may include a gate structure 12 disposed on a peripheral active region 9a defined by an element isolation region 9b in the substrate 3 and peripheral source / drain regions 15 disposed in the peripheral active region 9a on both sides of the gate structure 12.

[0067] The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers, for example, a first conductive layer 12b1 and a second conductive layer 12b2 below the first conductive layer 12b1.

[0068] The peripheral plugs 20 may be connected to the peripheral source / drain regions 15 and may extend vertically, and the peripheral interconnections 23 may be disposed below the peripheral plugs 20. The peripheral interconnections 23 may contact the peripheral plugs 20. The peripheral interconnections 23 may be electrically connected to the circuit elements TR through the peripheral plugs 20. The first peripheral insulating layer 30 may surround the side surfaces of the peripheral gate electrode 12b and the peripheral plugs 20. The second peripheral insulating layer 32 may be disposed below the first peripheral insulating layer 30 and may surround the peripheral plugs 20 and the peripheral interconnections 23. The lower surface of the second peripheral insulating layer 32 may be coplanar with the lower surface of the peripheral interconnections 23.

[0069] In an embodiment, the peripheral plug 20 and the peripheral interconnect 23 may include a metal layer and a barrier layer covering the side surface and the lower surface of the metal layer, respectively. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the metal layer may include a metal material such as W, Mo, etc. The first peripheral insulating layer 30 and the second peripheral insulating layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, or a combination thereof.

[0070] The peripheral circuit structure PS may further include a bonding layer BL2 disposed under the peripheral interconnect 23. The bonding layer BL2 may include a lower insulating layer 40 and bonding pads 43. The bonding pads 43 may be disposed in the lower insulating layer 40. For example, the lower surface of the bonding pad 43 may be coplanar with the lower surface of the lower insulating layer 40. The peripheral interconnect 23 may be electrically connected to at least one of the bonding pads 43. In an embodiment, an interconnect layer may be further disposed in the lower insulating layer 40 to electrically connect the bonding pads 43 and the peripheral interconnect 23.

[0071] The peripheral circuit structure PS may be bonded to the cell array structure CS and may be electrically connected to the cell array structure CS. For example, the bonding layer BL1 of the cell array structure CS may be bonded to the bonding layer BL2 of the peripheral circuit structure PS by a direct bonding method. The bonding pad 173 may be bonded to the bonding pad 43, and the upper insulating layer 170 may be bonded to the lower insulating layer 40. The bonding pads 173 and 43 may include a conductive material such as copper (Cu), and the upper insulating layer 170 and the lower insulating layer 40 may include an insulating material such as silicon oxide.

[0072] Figures 5 to 10 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment. Figures 5 to 8 Corresponds to Figure 2 part A shown in Figures 9 to 10 is Figure 1 a vertical cross-sectional view of the semiconductor device shown in

[0073] Refer to Figure 5 FIG., the semiconductor device 100a may include a channel structure 140 disposed on the landing pad 120. In an embodiment, the lower surface of the horizontal portion 140L of the channel structure 140 may contact and be coplanar with the upper surface of the landing pad 120. For example, the side surface of the vertical channel portion 140S of the channel structure 140 may not contact the landing pad 120.

[0074] Refer to Figure 6, the semiconductor device 100b may include a gate electrode 146 disposed on the landing pad 120. In an embodiment, the horizontal width of the gate electrode 146 may become smaller toward the bit line 160. For example, the upper surface of the gate electrode 146 may be rounded. Similarly, the lower surface of the second insulating pattern 150 may be curved to conform to the rounded shape of the upper surface of the gate electrode 146.

[0075] Reference Figure 7 , the semiconductor device 100c may include a channel structure 140 and a gate electrode 146 disposed on the landing pad 120. In an embodiment, the vertical channel portion 140S of the channel structure 140 may extend in the X direction and the Z direction. The vertical channel portion 140S of the channel structure 140 may form an inclined angle with respect to the upper surface of the pad insulating layer 123. For example, the distance between the vertical channel portions 140S of adjacent channel structures 140 in the X direction (with the first insulating pattern 130 therebetween) may decrease in the upward direction (e.g., the Z direction). The distance between the vertical channel portions 140S of adjacent channel structures 140 in the X direction (with the second insulating pattern 150 therebetween) may decrease in the downward direction. The horizontal width of the second insulating pattern 150 may decrease in the downward direction. For example, the horizontal width of the lower portion 151 of the second insulating pattern 150 may decrease in the downward direction, and the horizontal width of the upper portion 152 of the second insulating pattern 150 may decrease in the downward direction.

[0076] Reference Figure 8 , the semiconductor device 100d may include a bit line 160 disposed on the channel structure 140. In an embodiment, a part of the vertical channel portion 140S of the channel structure 140 may be buried in the bit line 160. For example, the bit line 160 may include a protrusion 161 extending toward the first insulating pattern 130 in the downward direction and a protrusion 162 extending toward the second insulating pattern 150 in the downward direction. The protrusion 162 may contact the upper portion 152 of the second insulating pattern 150. The lower end of the protrusion 162 may be located at a level lower than the upper surface of the vertical channel portion 140S. For example, the upper surface of the upper portion 152 of the second insulating pattern 150 may be at a vertical level lower than the upper surface of the channel structure 140. In Figure 8 , the vertical thicknesses of the protrusion 161 and the protrusion 162 are shown to be equal to each other, but the inventive concept is not limited thereto. In some embodiments, the vertical thickness of the protrusion 161 may be different from the vertical thickness of the protrusion 162.

[0077] Reference Figure 9, the semiconductor device 100e may include a channel structure 140 and a landing pad 120 disposed on a pad insulating layer 123. In an embodiment, the lower surface of the pad insulating layer 123 may be at a level lower than the lower surface of the landing pad 120. For example, the upper surface of the upper support layer 113 may include a recessed region R2, and the lower surface of the pad insulating layer 123 may further extend downward from the lower surface of the landing pad 120 to contact the recessed region R2.

[0078] Reference Figure 10 , the semiconductor device 100f may include a cell array structure CS on a peripheral circuit structure PS. For example, an insulating layer 50 may be disposed on the peripheral interconnect 23 of the peripheral circuit structure PS. An information storage structure DS may be disposed on the insulating layer 50. In an embodiment, an insulating layer 180 may be disposed on the bit line 160. Although not shown, an interconnect layer electrically connected to the bit line 160 may be disposed in the insulating layer 180, and the interconnect layer may be electrically connected to the peripheral circuit structure PS through a through plug penetrating the cell array structure CS.

[0079] Figure 11 and Figure 12 are flowcharts showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0080] Reference Figure 11 , a method of manufacturing a semiconductor device may include forming an information storage structure DS (S100) on a substrate 103, forming a landing pad 120 on the information storage structure DS (S200), forming a channel structure 140 and a gate electrode 146 on the landing pad 120 (S300), forming a bit line 160 on the channel structure 140 (S400), and bonding a peripheral circuit structure thereto (S500).

[0081] Reference Figure 12 , forming an information storage structure DS (S100) on a substrate 103 may include forming a mold layer (S110) on the substrate 103, forming a hole in the mold layer (S120), forming a first electrode E1 in the hole (S130), removing the mold layer (S140), and forming a dielectric layer DL and a second electrode E2 (S150).

[0082] Figures 13A to 13K is a vertical cross-sectional view shown according to a process sequence for showing a method of manufacturing a semiconductor device according to an exemplary embodiment. Figures 13A to 13K may be a Figure 2 vertical cross-sectional view.

[0083] Reference Figure 11 , Figure 12 and Figure 13A, a mold layer may be formed on the substrate 103 (S110). For example, the insulating layer 105, the plate electrode PL, the lower mold layer M1, the lower support layer 110, the upper mold layer M2, and the upper support layer 113 may be sequentially formed on the substrate 103.

[0084] The insulating layer 105 may electrically insulate the substrate 103 from the plate electrode PL. The lower mold layer M1 and the upper mold layer M2 may include materials having etching selectivity with respect to the lower support layer 110 and the upper support layer 113, respectively.

[0085] Reference Figure 11 , Figure 12 and Figure 13B , a hole H1 may be formed in the mold layers M1 and M2 (S120). The hole H1 may be formed by anisotropically etching the lower mold layer M1, the lower support layer 110, the upper mold layer M2, and the upper support layer 113 to expose the plate electrode PL. When viewed from the top, the hole H1 may be circular.

[0086] Reference Figure 11 , Figure 12 and Figure 13C , a first electrode E1 may be formed in the hole H1 (S130). The first electrode E1 may be formed by forming a conductive material to fill the hole H1 and planarizing the upper portion of the conductive material to expose the upper support layer 113. The upper surface of the first electrode E1 may be coplanar with the upper surface of the upper support layer 113.

[0087] Reference Figure 11 , Figure 12 and Figure 13D , the mold layers M1 and M2 may be removed (S140), and a dielectric layer DL and a second electrode E2 may be formed (S150). Since the lower mold layer M1 and the upper mold layer M2 include materials having etching selectivity with respect to the lower support layer 110 and the upper support layer 113, respectively, the lower support layer 110 and the upper support layer 113 may not be etched, and the lower mold layer M1 and the upper mold layer M2 may be selectively removed.

[0088] The dielectric layer DL may be conformally formed along the surfaces of the plate electrode PL, the first electrode E1, the lower support layer 110, and the upper support layer 113. The second electrode E2 may be prepared by forming a conductive material on the dielectric layer DL to fill the space between the first electrodes E1. In an embodiment, when the conductive material covers the upper surface of the upper support layer 113 and the upper surface of the first electrode E1, a planarization process may be further performed to expose the upper surface of the upper support layer 113 and the upper surface of the first electrode E1. The plate electrode PL, the first electrode E1, and the second electrode E2 may form an information storage structure DS.

[0089] Reference Figure 11 , Figure 13E andFigure 13F A landing pad 120 can be formed on the information storage structure DS (S200). A conductive layer 120p can be formed to cover the upper surface of the upper support layer 113 and the upper surface of the first electrode E1. The landing pad 120 can be prepared by forming a mask layer on the conductive layer 120p and performing an anisotropic etching process using the mask layer as an etching mask. The landing pads 120 can be respectively disposed on their corresponding first electrodes E1. After the landing pads 120 are formed, a pad insulating layer 123 can be formed to cover the landing pads 120. The upper surface of the pad insulating layer 123 can be at a level higher than the upper surface of the landing pads 120.

[0090] In an embodiment, as Figure 9 shown, the upper support layer 113 can be partially etched by an anisotropic etching process to form a recessed area R2 on the upper surface of the upper support layer 113.

[0091] Referring to Figure 11 and Figures 13G to 13J , a channel structure 140 and a gate electrode 146 can be formed on the landing pad 120 (S300). The first insulating pattern 130 can be formed by depositing an insulating material on the pad insulating layer 123 and performing an anisotropic etching process to expose the landing pad 120. The insulating material and the pad insulating layer 123 can be etched by an anisotropic etching process to form a trench T extending in the Y direction. The trench T can expose the side surface of the first insulating pattern 130 and can expose the upper surface of the landing pad 120. In an embodiment, a part of the landing pad 120 can be etched by an anisotropic etching process to form a recessed area R1 on the upper surface of the landing pad 120.

[0092] In an embodiment, as Figure 5 shown, the landing pad 120 may not be etched by an anisotropic etching process, and a recessed area R1 may not be formed on the upper surface of the landing pad 120.

[0093] A channel material layer 140p conformally covering the trench T and a sacrificial layer SL on the channel material layer 140p can be formed. The channel material layer 140p can be in contact with the upper surface of the landing pad 120, and the sacrificial layer SL can fill the trench T.

[0094] The portion of the channel material layer 140p covering the upper surface of the first insulating pattern 130 can be removed by a planarization process. After the planarization process, the channel material layer 140p can be disposed along the inner wall of the trench T, and the upper surface of the first insulating pattern 130 can be exposed.

[0095] The dielectric material layer 143p may be formed conformally along the first insulating pattern 130 and the channel material layer 140p. The conductive layer 146p may be formed conformally on the dielectric material layer 143p.

[0096] An anisotropic etching process may be performed to expose the upper surface of the pad insulating layer 123, and the channel material layer 140p, the dielectric material layer 143p, and the conductive layer 146p may be partially removed to form the channel structure 140, the dielectric structure 143, and the gate electrode 146. The channel structure 140, the dielectric structure 143, and the gate electrode 146 may be disposed on their corresponding landing pads 120, respectively.

[0097] In an embodiment, as Figure 6 and Figure 7 shown, the horizontal width of the gate electrode 146 may decrease in the upward direction.

[0098] After forming the gate electrode 146, a second insulating pattern 150 covering the gate electrode 146 may be formed. The upper surface of the second insulating pattern 150 may be coplanar with the upper surface of the channel structure 140.

[0099] Referring to Figure 13K , the first insulating pattern 130 may be partially etched to expose the side surface of the channel structure 140. For example, an isotropic etching process may be performed to remove the upper portion of the first insulating pattern 130. After performing the etching process, the upper surface of the first insulating pattern 130 may be at a level lower than the upper surface of the channel structure 140.

[0100] In an embodiment, as Figure 8 shown, a portion of the second insulating pattern 150 may be removed by an isotropic etching process. For example, the upper surface of the second insulating pattern 150 may be at a level lower than the upper surface of the channel structure 140.

[0101] After removing the upper portion of the first insulating pattern 130, a heating process may be performed. The channel structure 140 may be heated by the heating process, and oxygen atoms may move from the first insulating pattern 130 including silicon oxide to the channel structure 140. Accordingly, oxygen vacancies in the channel structure 140 including the oxide semiconductor layer may be reduced, and unit active leakage current (Ioff) may be reduced and prevented. For example, when the unit transistor is not operating, the unit active leakage current may be reduced, and when a voltage is applied to the gate electrode 146 and the unit transistor is operating, current may flow in the channel structure 140, thereby improving the switching characteristics of the semiconductor device 100.

[0102] Referring again to Figures 1 to 3, a bit line 160 may be formed on the channel structure 140 (S400). The bit line 160 may cover the first insulating pattern 130 and the channel structure 140 and may extend in the X direction. Since the upper surface of the first insulating pattern 130 may be at a level lower than the upper surface of the channel structure 140, the portion of the bit line 160 formed on the first insulating pattern 130 and the channel structure 140 may protrude toward the first insulating pattern 130. A bonding layer BL1 including an upper insulating layer 170 and a bonding pad 173 may be formed on the bit line 160. Components from the substrate 103 to the bonding layer BL1 may form a cell array structure CS.

[0103] The peripheral circuit structure PS may be bonded to the cell array structure CS (S500), and the semiconductor device 100 may be manufactured. For example, the peripheral circuit structure PS may include a bonding layer BL2 that includes a lower insulating layer 40 and a bonding pad 43, and the bonding layer BL2 may be bonded to the bonding layer BL1.

[0104] Figure 14 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment. Figure 15 is Figure 14 a partial enlarged view of the semiconductor device shown in Figure 15 corresponds to Figure 14 portion B shown in

[0105] Refer to Figure 14 and Figure 15 , the semiconductor device 100g may include a filling layer 135 disposed on the first insulating pattern 130. For example, the first insulating pattern 130 may include a recessed area R3 formed on the upper surface of the first insulating pattern 130. The filling layer 135 may fill the recessed area R3. The filling layer 135 may contact the side surface of the vertical channel portion 140S of the channel structure 140 and the first insulating pattern 130. The upper surface of the filling layer 135 may be at a level lower than the upper surface of the vertical channel portion 140S of the channel structure 140. The protrusion 161 of the bit line 160 may contact the filling layer 135.

[0106] In an embodiment, the filling layer 135 may be formed of a material different from that of the first insulating pattern 130 or may include a material different from that of the first insulating pattern 130. For example, the first insulating pattern 130 may be formed of or include silicon oxide, and the filling layer 135 may include silicon nitride.

[0107] Figure 16 and Figure 17 is Figure 14 a partial enlarged view of the semiconductor device shown in Figure 16 and Figure 17corresponding to Figure 14 Part B shown in. Mainly describe the differences, and repeated descriptions will not be repeated.

[0108] Reference Figure 16 , the semiconductor device 100h may include a second insulating pattern 150 covering the gate electrode 146. In an embodiment, the second insulating pattern 150 may include a first material layer 155 and a second material layer 156 on the first material layer 155. The first material layer 155 may cover the dielectric structure 143, the gate electrode 146, and the pad insulating layer 123. The second material layer 156 may fill the space between the gate electrodes 146.

[0109] In an embodiment, the first material layer 155 may be formed of a material different from that of the second material layer 156 or include a material different from that of the second material layer 156. For example, the first material layer 155 may be formed of or include silicon nitride, and the second material layer 156 may be formed of or include silicon oxide.

[0110] In an embodiment, the upper end of the first material layer 155 may be located at a level lower than the upper surface of the vertical channel portion 140S of the channel structure 140. For example, the bit line 160 may include a protrusion 163 extending downward from the lower surface of the bit line 160. The protrusion 163 may contact the side surface of the second material layer 156 and the side surface of the dielectric structure 143. The lower end of the protrusion 163 may be located at a level lower than the upper surface of the second material layer 156 and the upper surface of the vertical channel portion 140S.

[0111] Reference Figure 17 , the semiconductor device 100i may include a filling layer 135 disposed on the first insulating pattern 130. In an embodiment, the horizontal width of the filling layer 135 may decrease in the downward direction. For example, the horizontal width of the filling layer 135 may decrease toward the landing pad 120 and may increase toward the bit line 160.

[0112] Figures 18A to 18C is a vertical cross-sectional view shown according to the process sequence for showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0113] Reference Figure 18A , after the etching process of the first insulating pattern 130 as described in reference Figure 13K a protective layer 135p may be formed. The protective layer 135p may cover the first insulating pattern 130, the channel structure 140, the dielectric structure 143, and the second insulating pattern 150.

[0114] Reference Figure 18B, an anisotropic etching process may be performed to partially etch the protective layer 135p and the first insulating pattern 130. For example, a recessed region R3 may be formed on the upper surface of the first insulating pattern 130, and the side surface of the first insulating pattern 130 may be exposed. During the anisotropic etching process, the protective layer 135p may protect the channel structure 140 from being etched.

[0115] After the side surface of the first insulating pattern 130 is exposed, a heating process may be performed. The channel structure 140 may be heated by the heating process, and oxygen atoms may move from the first insulating pattern 130 including silicon oxide to the channel structure 140. Accordingly, oxygen vacancies in the channel structure 140 including the oxide semiconductor layer may be reduced, and unit active leakage current (Ioff) may be reduced and prevented. As Figure 18B shown, since the heating process may be performed after the side surface of the first insulating pattern 130 is exposed, oxygen vacancies in the channel structure 140 may be more effectively reduced.

[0116] Reference Figure 18C , a filling layer 135 may be formed on the first insulating pattern 130. The filling layer 135 may be formed of an insulating material to cover the recessed region R3, the channel structure 140, and the second insulating pattern 150, and then an anisotropic etching process may be performed to expose the channel structure 140. The insulating material may be etched by an isotropic etching process, and the upper surface of the filling layer 135 may be at a level lower than the upper surface of the vertical channel portion 140S of the channel structure 140.

[0117] Thereafter, a cell array structure CS may be prepared by forming a bit line 160 and a bonding layer BL1. A semiconductor device 100g may be manufactured by bonding a peripheral circuit structure PS to the cell array structure CS.

[0118] Figure 19 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment. Figure 19 is Figure 1 a vertical cross-sectional view taken along line I-I' of the semiconductor device shown in

[0119] Reference Figure 19, the semiconductor device 100j may include an information storage structure DS disposed under the channel structure 140. The information storage structure DS may include a plate electrode PL, a first electrode E1, a second electrode E2 on the first electrode E1, and a dielectric layer DL between each first electrode E1 and the second electrode E2. In an embodiment, the second electrode E2 may include a hole H2 on the upper surface of the second electrode E2, and the first electrode E1 may be disposed in the hole H2. For example, the dielectric layer DL may be conformally disposed along the inner wall of each hole H2, the first electrode E1 may be disposed on the dielectric layer DL, and may fill the hole H2. The lower surface of the first electrode E1 may be at a level higher than the lower surface of the second electrode E2. The upper surface of the first electrode E1 may be coplanar with the upper end of the dielectric layer DL and the upper surface of the second electrode E2.

[0120] The semiconductor device 100j may include landing pads 120 and a pad insulating layer 125 covering the landing pads 120. Each landing pad 120 may be in contact with the upper surface of the corresponding first electrode E1 and may be electrically connected. In an embodiment, the horizontal width of the lower surface of the landing pad 120 may be less than or equal to the horizontal width of the upper surface of the first electrode E1. In an embodiment, the horizontal width of the landing pad 120 may become smaller in the downward direction. For example, the horizontal width of the landing pad 120 may become smaller toward the information storage structure DS and may become larger toward the channel structure 140.

[0121] The pad insulating layer 125 may include a first pad insulating layer 126 and a second pad insulating layer 127 on the first pad insulating layer 126. The first pad insulating layer 126 may be disposed at the same level as the landing pad 120 and may cover the side surface of the landing pad 120. For example, the lower surface and the upper surface of the first pad insulating layer 126 may be coplanar with the lower surface and the upper surface of the landing pad 120, respectively. The first pad insulating layer 126 may contact the side surface of the landing pad 120. The lower surface of the first pad insulating layer 126 may contact the upper surface of the second electrode E2.

[0122] The second pad insulating layer 127 may be disposed on the first pad insulating layer 126 and the landing pad 120. The second pad insulating layer 127 may contact the upper surface of the first pad insulating layer 126 and the upper surface of the landing pad 120. The second pad insulating layer 127 may contact the side surface of the vertical channel portion 140S. The first pad insulating layer 126 and the second pad insulating layer 127 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof, and may include, for example, silicon nitride.

[0123] Figure 20 is a flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0124] Reference Figure 20, forming the information storage structure DS (S100) on the substrate 103 may include forming a second electrode E2 on the substrate 103 (S110a), forming a hole H2 in the second electrode E2 (S120a), and forming a dielectric layer DL and a first electrode E1 in the hole H2 (S130a).

[0125] Figures 21A to 21D is a vertical cross-sectional view shown according to the process sequence for showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0126] Reference Figure 20 and Figure 21A , a second electrode E2 may be formed on the substrate 103 (S110a). For example, the insulating layer 105, the plate electrode PL, and the second electrode E2 may be sequentially formed on the substrate 103.

[0127] Reference Figure 20 and Figure 21B , a hole H2 may be formed in the second electrode E2 (S120a). The hole H2 may be formed by anisotropically etching the second electrode E2, and the depth of the hole H2 may be less than the height of the second electrode E2. For example, the upper surface of the plate electrode PL may not be exposed.

[0128] Reference Figure 20 and Figure 21C , a dielectric layer DL and a first electrode E1 may be formed in each hole H2 (S130a). The dielectric layer DL may be conformally formed along the inner wall of the hole H2 and the upper surface of the second electrode E2. The first electrode E1 may be prepared by forming a conductive material to fill the hole H2 and performing a planarization process to expose the upper surface of the second electrode E2. The upper surface of the second electrode E2 may not be covered by the dielectric layer DL and the first electrode E1.

[0129] After forming the dielectric layer DL and the first electrode E1, an insulating material layer 126p may be formed on the dielectric layer DL, the first electrode E1, and the second electrode E2.

[0130] Reference Figure 21D , a hole may be formed by patterning the insulating material layer 126p such that the upper surface of the first electrode E1 is exposed. A landing pad 120 may be formed by filling the hole with a conductive material. The patterned insulating material layer 126p may be referred to as the first pad insulating layer 126. After forming the landing pad 120, a second pad insulating layer 127 covering the landing pad 120 and the first pad insulating layer 126 may be formed. The first pad insulating layer 126 and the second pad insulating layer 127 may form the pad insulating layer 125.

[0131] Thereafter, operations as described in reference Figures 1 to 3 and Figures 13G to 13KThe method of forming the unit array structure CS and the peripheral circuit structure PS to fabricate the semiconductor device 100j.

[0132] According to an embodiment of the technical idea of the present inventive concept, a channel structure may be disposed on an information storage structure. The lower surface and side surfaces of the channel structure may be in contact with a landing pad, and the upper surface and side surfaces of the channel structure may be in contact with a bit line. The contact area between the channel structure and the bit line and the contact area between the landing pad and the channel structure may be increased, and the contact resistance therebetween may be decreased. Accordingly, the electrical characteristics of the semiconductor device may be improved.

[0133] Various advantages and effects of the present inventive concept are not limited to the above and may be more easily understood through the description of the specific embodiments of the present inventive concept.

[0134] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present inventive concept defined by the appended claims.

[0135] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0176377, filed on Dec. 7, 2023, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: an information storage structure on a substrate; a landing pad on said information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; as well as a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure, wherein the lower surface of the horizontal portion is located at a lower level than the upper end of the landing pad, and A side surface of the vertical channel portion is partially in contact with the landing pad.

2. The semiconductor device according to claim 1, further comprising: a first insulating pattern disposed on the landing pad and contacting the vertical channel portion of the channel structure; as well as A second insulating pattern is disposed on the landing pad and covers the gate electrode.

3. The semiconductor device according to claim 2, wherein the bit line further includes a first protrusion extending in a downward direction from a lower surface of the bit line and contacting an upper surface of the first insulating pattern, and Wherein a lower end of the first protrusion is located at a level lower than the upper surface of the vertical channel portion of the channel structure.

4. The semiconductor device according to claim 3, wherein the bit line further includes a second protrusion extending from the lower surface of the bit line in the downward direction and contacting an upper surface of the second insulating pattern, and Wherein a lower end of the second protrusion is located at a level lower than the upper surface of the vertical channel portion of the channel structure.

5. The semiconductor device according to claim 3, The second insulating pattern includes a first material layer contacting the gate electrode and a second material layer on the first material layer, wherein the bit line further includes a second protrusion extending from the lower surface of the bit line in the downward direction and contacting an upper surface of the second insulating pattern and a side surface of the second material layer, and Wherein a lower end of the second protrusion is located at a level lower than the upper surface of the vertical channel portion of the channel structure. The semiconductor device according to claim 2 , wherein a horizontal width of the second insulating pattern decreases toward the landing pad.

7. The semiconductor device according to claim 2, wherein the first insulating pattern includes a recessed area on an upper surface of the first insulating pattern, and The semiconductor device further includes a filling layer filling the recessed region of the first insulating pattern. 8 . The semiconductor device according to claim 7 , wherein a horizontal width of the filling layer decreases toward the landing pad. 9 . The semiconductor device according to claim 1 , wherein a horizontal width of the gate electrode decreases toward the bit line. 10 . The semiconductor device according to claim 1 , further comprising a pad insulating layer covering a side surface and an upper surface of the landing pad. 11 . The semiconductor device according to claim 10 , wherein an upper surface of the pad insulating layer is located at a higher level than the lower surface of the horizontal portion of the channel structure. 12 . The semiconductor device according to claim 10 , wherein a lower surface of the pad insulating layer is located at a lower level than a lower surface of the landing pad.

13. A semiconductor device comprising: Cell array structure; as well as a peripheral circuit structure vertically overlapping the cell array structure and including circuit elements, The cell array structure comprises: Information storage structure; a landing pad on said information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; a first insulating pattern contacting the vertical channel portion; a second insulating pattern covering the gate electrode; and a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure, wherein the upper surface of the vertical channel portion is disposed at a higher level than an upper surface of the first insulating pattern, and wherein a lower surface of the horizontal portion is disposed at a lower level than a lower surface of the first insulating pattern.

14. The semiconductor device according to claim 13, wherein the bit line includes a protrusion extending in a downward direction from a lower surface of the bit line, and wherein a lower end of the protrusion is located at a level lower than the upper surface of the vertical channel portion.

15. The semiconductor device according to claim 13, wherein the channel structure includes a first channel structure and a second channel structure which are spaced apart from each other and between which the second insulating pattern is located, and Wherein a distance between the first channel structure and the second channel structure at a first vertical level is greater than a distance between the first channel structure and the second channel structure at a second vertical level, the first vertical level is equal to a lower surface of the bit line, and the second vertical level is equal to an upper surface of the landing pad. 16 . The semiconductor device of claim 15 , wherein a distance between a vertical channel portion of the first channel structure and a vertical channel portion of the second channel structure decreases toward the landing pad.

17. The semiconductor device according to claim 13, wherein the information storage structure comprises a first electrode, a second electrode on the first electrode, and a dielectric layer between each of the first electrode and the second electrode, wherein the cell array structure further comprises an upper support layer contacting a side surface of the first electrode, and The upper surface of the first electrode is coplanar with the upper surface of the upper supporting layer.

18. The semiconductor device according to claim 17, wherein the horizontal width of the landing pad decreases toward the channel structure, and The horizontal width of the lower surface of the landing pad is greater than the horizontal width of the upper surface of at least one of the first electrodes.

19. The semiconductor device according to claim 13, wherein the information storage structure comprises a first electrode, a second electrode on the first electrode, and a dielectric layer between each of the first electrode and the second electrode, and The upper surface of the first electrode is coplanar with the upper surface of the second electrode.

20. A semiconductor device comprising: an information storage structure on a substrate; a landing pad on said information storage structure; a channel structure including a horizontal portion contacting an upper surface of the landing pad and a vertical channel portion extending in an upward direction from one end of the horizontal portion; a gate electrode disposed on the horizontal portion; a dielectric structure between the channel structure and the gate electrode; a first insulating pattern contacting the vertical channel portion; a second insulating pattern covering the gate electrode and the dielectric structure; a bit line contacting an upper surface of the vertical channel portion and electrically connected to the channel structure; a first bonding layer on the bit line; as well as a peripheral circuit structure comprising a second bonding layer bonded to the first bonding layer and a circuit element on the second bonding layer, A side surface of a lower portion of the vertical channel portion contacts the landing pad, and a side surface of an upper portion of the vertical channel portion contacts the bit line.

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