Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises a first active structure, a second active structure and an isolation structure located between the adjacent first active structure and second active structure, and the first active structure and the second active structure are arranged at intervals; etching the substrate to form a plurality of spaced grooves which expose the top surface of the second active structure; forming a first isolation layer, wherein the first isolation layer covers the surface of the groove; forming a first semiconductor layer, wherein the first semiconductor layer covers the surface of the first isolation layer; etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structure; etching the first isolation layer to expose the top surface of the second active structure; and forming a bit line contact structure, wherein the bit line contact structure is at least in contact connection with the top surface of the second active structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely applied to data storage devices or apparatuses.

[0003] DRAM includes a plurality of memory cells, and each memory cell generally includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line (WL), the source is electrically connected to a bit line (BL) through a bit line contact structure (BLC), and the drain is electrically connected to the capacitor through a storage node contact (SNC). The on / off state of the transistor can be controlled by a voltage signal on the word line, and the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor for storage.

[0004] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and semiconductor process nodes are continuously reduced following Moore's law. At present, it is necessary to improve the reliability of semiconductor structures. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure, which can at least improve the reliability of the formed semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, a method for manufacturing a semiconductor structure is provided, including: providing a substrate, the substrate including a first active structure, a second active structure arranged at intervals, and an isolation structure located between the adjacent first active structure and the second active structure; etching the substrate to form a plurality of spaced grooves, the grooves exposing the top surface of the second active structure; forming a first isolation layer, the first isolation layer covering the surface of the grooves; forming a first semiconductor layer, the first semiconductor layer covering the surface of the first isolation layer; etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structure; etching the first isolation layer to expose the top surface of the second active structure; forming a bit line contact structure, the bit line contact structure being at least in contact connection with the top surface of the second active structure.

[0007] In some embodiments, the method of forming the bit line contact structure includes: forming an initial bit line contact structure that fills the groove and covers the top surface of the substrate; etching the initial bit line contact structure to form the spaced-apart bit line contact structures.

[0008] In some embodiments, the aspect ratio of the portion of the formed initial bit line contact structure corresponding to the groove is 2-3.

[0009] In some embodiments, the method of forming the initial bit line contact structure includes: forming a first initial bit line contact structure that fills the groove and covers the top surface of the substrate; removing a part of the first initial bit line contact structure so that the remaining first initial bit line contact structure is flush with the top surface of the groove; forming a second initial bit line contact structure on the top surface of the initial bit line contact structure, and the first initial bit line contact structure and the second initial bit line contact structure constitute the initial bit line contact structure.

[0010] In some embodiments, before etching the substrate, it further includes: forming a second isolation layer that covers the top surface of the substrate, and the formed first isolation layer also covers the surface of the second isolation layer. During the etching of the first semiconductor layer and the first isolation layer, the first semiconductor layer and the first isolation layer located on the top surface of the second isolation layer are also etched.

[0011] In some embodiments, the method of etching the first semiconductor layer includes: etching the first semiconductor layer by dry etching, and the dry etching is a gas containing a halogen element.

[0012] In some embodiments, during the etching of the first isolation layer, it further includes: etching the isolation structure to expose part of the sidewall of the second active structure.

[0013] In some embodiments, the method of etching the first isolation layer and the isolation structure includes: wet etching.

[0014] According to some embodiments of the present disclosure, on the other hand, the present disclosure embodiments further provide a semiconductor structure, including: a substrate, the substrate includes a first active structure, a second active structure arranged at intervals, and an isolation structure located between adjacent the first active structure and the second active structure, a plurality of spaced grooves are provided in the substrate, and the grooves expose the top surface of the second active structure; a first isolation layer, the first isolation layer covers the sidewalls of the grooves; a bit line contact structure, the bit line contact structure is at least in contact connection with the top surface of the second active structure, and the bit line contact structure located in the grooves is spaced apart from the first isolation layer.

[0015] In some embodiments, the bit line contact structure also covers the sidewalls of the second active structure.

[0016] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: During the process of forming the groove, since the etching process cannot be precisely controlled, the surface of the first active structure may be exposed during the formation of the groove. Thus, during the subsequent formation of the bit line contact structure, the first active structure and the second active structure may be electrically connected, and the first active structure may also be damaged during the formation of the bit line contact structure. Therefore, a first isolation layer and a first semiconductor layer are formed before forming the bit line contact structure, so as to form an isolation on the sidewalls of the groove by using the first isolation layer and the first semiconductor layer, and use the first isolation layer and the first semiconductor layer as the second isolation layer of the first active structure, thereby avoiding damaging the first active structure during the formation of the bit line contact structure, and preventing the bit line contact structure from electrically connecting the adjacent first active structure and the second active structure, which can improve the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation to the embodiments unless otherwise stated. The figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 2 It is a three-dimensional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0020] Figure 3 It is provided by an embodiment of the present disclosure along Figure 2 a cross-sectional view of the semiconductor structure in the M-M1 direction;

[0021] Figure 4 It is provided by an embodiment of the present disclosure in Figure 3 a schematic structural diagram of a groove formed on the basis of;

[0022] Figure 5 It is provided by an embodiment of the present disclosure in Figure 4 a schematic structural diagram of a first isolation layer and a first semiconductor layer formed on the basis of;

[0023] Figure 6 A structural schematic diagram of etching a first semiconductor layer and a first isolation layer based on Figure 5 ;

[0024] Figure 7 A structural schematic diagram of forming a first initial bit line contact structure based on Figure 6 ;

[0025] Figure 8 A structural schematic diagram of removing a part of the first initial bit line contact structure based on Figure 7 ;

[0026] Figure 9 A structural schematic diagram of forming a second initial bit line contact structure based on Figure 8 ;

[0027] Figure 10 A structural schematic diagram of forming a bit line contact structure based on Figure 9 ; Detailed implementation manners

[0028] Currently, in the process of forming a groove, due to the fact that the etching process cannot be precisely controlled, during the process of forming the groove, the surface of the first active structure may be exposed. Thus, during the subsequent process of forming the bit line contact structure, it may cause electrical connection between the first active structure and the second active structure, and may also cause damage to the first active structure during the process of forming the bit line contact structure. Therefore, it is necessary to provide a manufacturing method of a semiconductor structure to improve the reliability of the formed semiconductor structure.

[0029] In the embodiments of the present disclosure, by forming a first isolation layer and a first semiconductor layer before forming the bit line contact structure, isolation is formed on the sidewalls of the groove by using the first isolation layer and the first semiconductor layer, and the first isolation layer and the first semiconductor layer are used as the second isolation layer of the first active structure, so as to avoid damaging the first active structure during the process of forming the bit line contact structure, and can avoid the bit line contact structure from electrically connecting the adjacent first active structure and the second active structure, and can improve the reliability of the semiconductor structure.

[0030] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0031] Refer to Figure 1and Figures 2 to 10 , Figure 1 is a flowchart corresponding to a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 10 is a schematic structural diagram corresponding to each step of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure, Figures 3 to 10 is a sectional view in the MM1 direction of each step of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure in Figure 2 the

[0032] Referring to Figures 1 to 3 , a substrate is provided, wherein, Figure 1 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 is a three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 3 is a sectional view along the MM1 direction of Figure 2 .

[0033] S100: Provide a substrate 100, the substrate 100 includes a first active structure 101, a second active structure 102 arranged at intervals, and an isolation structure 103 located between the adjacent first active structure 101 and the second active structure 102.

[0034] In some embodiments, the substrate 100 may include a substrate 110, the first active structure 101, the second active structure 102 and the isolation structure 103 located on the surface of the substrate 110, wherein, the substrate 110 and the first active structure 101 and the second active structure 102 may be an integral structure, and the isolation structure 103 may be an STI (Shallow Trench Isolation). The material of the substrate 110 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide.

[0035] The first active structure 101 and the second active structure 102 may be active pillars formed on the substrate 110, and the materials of the first active structure 101 and the second active structure 102 may be the same as the material of the substrate, such as single crystal silicon, single crystal germanium or germanium silicon, etc.

[0036] The material of the isolation structure 103 may be silicon oxide, silicon nitride or silicon oxynitride, etc.

[0037] Referring to Figure 1 , Figure 2 and Figure 4 , Figure 4 a groove is formed on the basis of Figure 3 .

[0038] S200: Etch the substrate 100 to form a plurality of spaced grooves 130, and the grooves 130 expose the top surface of the second active structure 102.

[0039] In some embodiments, the method of forming the grooves 130 may include: forming by mask etching, that is, first forming a mask layer (not shown) on the top surface of the substrate 100, and then etching the substrate 100 using the mask layer as a mask to form the grooves 130, and removing the mask layer after forming the grooves 130.

[0040] Before forming the mask layer, a second isolation layer 120 is further formed on the surface of the substrate 100. The mask layer may be formed on the surface of the second isolation layer 120. During the etching process, a part of the second isolation layer 120 is also etched. During the process of removing the mask layer, the second isolation layer 120 can also serve as an etch stop layer to protect the substrate 100.

[0041] It can be understood that during the mask etching process, as the etching progresses, the width of the part of the groove 130 extending deeper into the substrate 110 becomes smaller, and due to the lateral etching during the etching process, the groove 130 may also expose the sidewalls of a part of the first active structure 101.

[0042] In some embodiments, a part of the second active structure 102 is also etched during the process of forming the grooves 130, so that the top surface of the first active structure 101 is higher than the top surface of the second active structure 102.

[0043] In some embodiments, a word line structure 140 may be further formed in the substrate 100 before forming the grooves 130. The word line structure 140 may include: a word line conductive layer 141, a word line isolation structure 142 located on the top surface of the word line conductive layer 141, and a word line dielectric layer 143 wrapping the surfaces of the word line conductive layer 141 and the word line isolation structure 142. The word line dielectric layer 143 is used to isolate the first active structure 101 or the second active structure 102 from the word line conductive layer 141, so as to prevent the first active structure 101 or the second active structure 102 from directly contacting the word line conductive layer 141 and prevent the carriers in the first active structure 101 or the second active structure 102 from directly flowing to the word line conductive layer 141.

[0044] In some embodiments, the word line conductive layer 141 may include: a first electron conductive layer 144 and a second electron conductive layer 145. The second electron conductive layer 145 covers the top surface of the first electron conductive layer 144. The material of the first electron conductive layer 144 may be a metal material, such as tungsten, etc., and the material of the second electron conductive layer 145 may be a semiconductor material, such as polysilicon, etc. By setting the second electron conductive layer 145 as a low work function material, the material difference between the second electron conductive layer 145 and the first active structure 101 or the second active structure 102 can be reduced, thereby reducing the leakage of the word line conductive layer 141. By setting the first electron conductive layer 144 as a metal material, the resistance can be reduced to increase the signal transmission rate of the first electron conductive layer 144.

[0045] It should be noted that the low work function material here refers to a material with a work function lower than that of silicon.

[0046] In some embodiments, before etching the substrate 100, it further includes: forming a second isolation layer 120. The second isolation layer 120 covers the top surface of the substrate 100, and the formed first isolation layer 104 also covers the surface of the second isolation layer 120. The second isolation layer 120 can be used to protect the parts that do not need to be etched, and can be used as an etch stop layer for subsequent etching of the first semiconductor layer 105 and the first isolation layer 104.

[0047] In some embodiments, the material of the second isolation layer 120 may include: silicon nitride, silicon oxide, or silicon oxynitride, etc.

[0048] Reference Figure 5 , Figure 5 For forming the first isolation layer and the first semiconductor layer on the basis of Figure 4 .

[0049] S300: Form the first isolation layer 104. The first isolation layer 104 covers the surface of the groove 130.

[0050] In some embodiments, the material of the first isolation layer 104 may be the same as that of the isolation structure 103, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. It can be understood that during the process of forming the groove 130, part of the isolation structure 103 may be etched, but part of the isolation structure 103 will still be retained. Therefore, during the process of forming the first isolation layer 104, using the same material as the isolation structure 103 can facilitate the growth of the first isolation layer 104.

[0051] S400: Form the first semiconductor layer 105. The first semiconductor layer 105 covers the surface of the first isolation layer 104.

[0052] The first isolation layer 104 covers the surface of the groove 130, and the first isolation layer 104 may also cover the surface of the second isolation layer 120; the first semiconductor layer 105 covers the surface of the first isolation layer 104.

[0053] The material of the first semiconductor layer 105 may be the same as that of the bit line contact structure, for example, semiconductor materials such as silicon, germanium, or silicon germanium. Similarly, making the material of the first semiconductor layer 105 the same as that of the bit line contact structure facilitates the subsequent formation of the bit line contact structure.

[0054] Reference Figure 6 , Figure 6 For etching the first semiconductor layer and the first isolation layer on the basis of Figure 5 .

[0055] S500: Etch the first semiconductor layer 105 to expose the first isolation layer 104 covering the top surface of the second active structure 102.

[0056] In some embodiments, the method of etching the first semiconductor layer 105 includes: etching the first semiconductor layer 105 by dry etching, and the dry etching is a gas containing a halogen element. During the process of etching the first semiconductor layer 105, it is necessary to avoid etching the first isolation layer 104 as much as possible. Therefore, a dry etching method with a large etching selectivity between the first semiconductor layer 105 and the first isolation layer 104 needs to be selected to etch the first semiconductor layer 105. Using dry etching, and the dry etching being a gas containing a halogen element, can avoid affecting the first isolation layer 104 as much as possible during the process of etching the first semiconductor layer 105, thereby improving the reliability of the entire semiconductor structure manufacturing method.

[0057] For the first semiconductor layer 105, usually the same material as the bit line contact structure 106 is selected to avoid the formation of the first semiconductor layer 105 affecting the bit line contact structure 106. For the bit line contact structure 106, in order to improve the contact performance with the second active structure 102, a semiconductor material such as polysilicon is usually selected. Based on this, the first semiconductor layer 105 also selects polysilicon material, and the first isolation layer 104 usually selects the same material as the isolation structure 103, such as silicon dioxide. During the dry etching process using a gas containing a halogen element, the ratio range of the etching selectivity of polysilicon to the etching selectivity of silicon dioxide can be 100 - 500, that is, dry etching is more likely to etch polysilicon, thus avoiding excessive damage to the first isolation layer 104 during the process of etching the first semiconductor layer 105.

[0058] S600: Etch the first isolation layer 104 to expose the top surface of the second active structure 102.

[0059] In some embodiments, the method of etching the first isolation layer 104 may include: using wet etching. Similarly, during the process of etching the first isolation layer 104, it is necessary to avoid etching damage to the second active structure 102 as much as possible. Therefore, an etching method with a relatively large etching selectivity between the second active structure 102 and the first isolation layer 104 needs to be selected to etch the first isolation layer 104. Using the wet etching method can avoid damaging the second active structure 102 when etching the first isolation layer 104.

[0060] For the first isolation layer 104, the first isolation layer 104 usually selects the same material as the isolation structure 103, such as silicon dioxide, while the material of the second active structure 102 is usually silicon. During the wet etching process, the ratio of the etching selectivity of silicon dioxide to the etching selectivity of silicon is 50 - 500, that is, wet etching is more likely to etch silicon dioxide, thereby avoiding damaging the second active structure 102 during the process of etching the first isolation layer 104.

[0061] The reagents used in wet etching may include hydrofluoric acid or nitric acid, etc.

[0062] In some embodiments, the process of etching the first isolation layer 104 further includes: etching the isolation structure 103 to expose part of the sidewall of the second active structure 102. By etching part of the isolation structure 103 during the process of etching the first isolation layer 104, the sidewall of the second active structure 102 is exposed. Subsequently, during the process of forming the bit line contact structure 106, it is also possible to control the bit line contact structure 106 to contact the sidewall of the second active structure 102, thereby improving the contact reliability between the bit line contact structure 106 and the second active structure 102 and reducing the contact resistance between the bit line contact structure 106 and the second active structure 102.

[0063] In some embodiments, during the process of etching the first semiconductor layer 105 and the first isolation layer 104, the first semiconductor layer 105 and the first isolation layer 104 located on the top surface of the second isolation layer 120 are also etched.

[0064] Reference Figures 7 to 10 , form a bit line contact structure.

[0065] S700: Form a bit line contact structure 106, and the bit line contact structure 106 is at least in contact connection with the top surface of the second active structure 102.

[0066] In some embodiments, the method of forming the bit line contact structure 106 includes: forming an initial bit line contact structure 116 that fills the groove 130 and covers the top surface of the substrate 100; etching the initial bit line contact structure 116 to form spaced-apart bit line contact structures 106. By forming the initial bit line contact structure 116 first and then etching, the topography of the formed bit line contact structure 106 can be improved, and the reliability of the formed bit line contact structure 106 can be enhanced.

[0067] In some embodiments, the aspect ratio range of the portion of the formed initial bit line contact structure 116 corresponding to the groove 130 can be 2 to 3. The portion of the initial bit line contact structure 116 corresponding to the groove 130 actually refers to the portion of the initial bit line contact structure 116 whose orthographic projection on the surface of the substrate 100 is located within the groove 130. By controlling the aspect ratio range of the portion of the formed initial bit line contact structure 116 corresponding to the groove 130 to be 2 to 3, the formation of holes within the initial bit line contact structure 116 caused by an excessively high aspect ratio of the initial bit line contact structure 116 can be avoided, and the reliability degradation of the formed bit line contact structure 106 can be avoided.

[0068] It can be understood that if the aspect ratio of the portion of the formed initial bit line contact structure 116 corresponding to the groove 130 is too large, for example, greater than 3, it is very easy to form concave holes during the formation of the initial bit line contact structure 116, resulting in the existence of concave holes within the subsequently formed bit line contact structure 106, which will reduce the reliability of the bit line contact structure 106 and lead to a decrease in the electrical signal transmission performance of the bit line contact structure 106.

[0069] The material of the initial bit line contact structure 116 can be silicon, germanium, or silicon-germanium, etc.

[0070] Refer to Figures 7 to 9 , and form the initial bit line contact structure.

[0071] In some embodiments, the method of forming the initial bit line contact structure 116 may further include: forming a first initial bit line contact structure 126 that fills the groove 130 and covers the top surface of the substrate 100; removing a portion of the first initial bit line contact structure 126 so that the remaining first initial bit line contact structure 126 is flush with the top surface of the groove 130; forming a second initial bit line contact structure 136 on the top surface of the initial bit line contact structure 116, where the first initial bit line contact structure 126 and the second initial bit line contact structure 136 constitute the initial bit line contact structure 116.

[0072] The first initial bit line contact structure 126 is used to fill the groove 130 completely, and then a part of the first initial bit line contact structure 126 is removed. Even if there are concave holes in the first initial bit line contact structure 126, the concave holes can be exposed when removing a part of the first initial bit line contact structure 126. Then, this part of the concave holes is filled by the second initial bit line contact structure 136, thereby further improving the reliability of the subsequently formed bit line contact structure 106.

[0073] In some embodiments, the thickness of the first initial bit line contact structure 126 is greater than the thickness of the formed initial bit line contact structure 116. In other words, the thickness of the first initial bit line contact structure 126 is greater than the sum of the thickness of the initial bit line contact structure 116 and the thickness of the second initial bit line contact structure 136. For the first initial bit line contact structure 126, the first consideration in forming the first initial bit line contact structure 126 is to fill the groove 130 completely, so as to facilitate the subsequent patterning to form the bit line contact structure 106. Therefore, the formed first initial bit line contact structure 126 is relatively thick. For the second initial bit line contact structure 136, what needs to be considered is to fill the possible concave holes and form a bit line contact structure 106 with an appropriate thickness. Therefore, the formed thickness of the second initial bit line contact structure 136 is relatively thin.

[0074] In some embodiments, the material of the first initial bit line contact structure 126 can be the same as the material of the second initial bit line contact structure 136. For example, both can be silicon, germanium, or germanium silicon, etc. Setting the material of the first initial bit line contact structure 126 to be the same as the material of the second initial bit line contact structure 136 can facilitate the growth of the second initial bit line contact structure 136, thereby improving the reliability of the formed initial bit line contact structure 116.

[0075] Reference Figure 10 , form the bit line contact structure.

[0076] Part of the initial bit line contact structure 116 can be etched by means of mask etching to form the bit line contact structure 106.

[0077] It can be understood that if the first isolation layer 104 and the first semiconductor layer 105 are not formed in advance during the formation of the initial bit line contact structure 116, then, when etching the initial bit line contact structure 116, it is inevitable to cause damage to the first active structure 101, resulting in a decrease in the reliability of the formed semiconductor structure.

[0078] When only the first isolation layer 104 is formed and the first semiconductor layer 105 is not formed, during the etching process of the first isolation layer 104, the entire first isolation layer 104 may be etched, and too much of the isolation structure 103 may be etched. Therefore, during the etching process of the first isolation layer 104, the first semiconductor layer 105 can serve as a mask layer. On the one hand, it can prevent over-etching of the first isolation layer 104. On the other hand, it can also prevent the isolation structure 103 from being overly affected.

[0079] When only the first semiconductor layer 105 is formed and the first isolation layer 104 is not formed, since the previous etching process may expose the first active structure 101, then when etching to form the bit line contact structure 106, as the etching process progresses, part of the first active structure 101 may be etched. Therefore, when etching to form the bit line contact structure 106, the first isolation layer 104 serves as a protective layer to prevent the first active structure 101 from being affected by etching. Moreover, the first isolation layer 104 can further improve the insulation of the film layer formed on the first active structure 101 and the second active structure 102, thereby improving the reliability of the formed semiconductor structure.

[0080] During the process of etching to form the bit line contact structure 106, the first semiconductor layer 105 is also etched and removed. Similarly, the first isolation layer 104 serves as a protective layer for protecting the first active structure 101 during the etching process of the bit line contact structure 106, thereby preventing damage to the first active structure 101 during the formation of the bit line contact structure 106 and improving the reliability of the formed semiconductor structure.

[0081] In some embodiments, after forming the bit line contact structure 106, a bit line structure 107 is further formed. The bit line structure 107 may include: a bit line conductive layer 117 and a bit line capping layer 127. The bit line conductive layer 117 is located on the top surface of the bit line contact structure 106; the bit line capping layer 127, and the bit line capping layer 127 is located on the top surface of the bit line conductive layer 117. By forming the bit line capping layer 127, the top surface of the bit line conductive layer 117 can be covered, thereby preventing the subsequent formed processes from affecting the bit line conductive layer 117, and thus improving the reliability of the semiconductor structure.

[0082] Among them, the bit line conductive layer 117 may include: a bit line metal-semiconductor layer 137 and a bit line metal layer 147. The bit line metal-semiconductor layer 137 covers the top surface of the bit line contact structure 106, and the bit line metal layer 147 covers the top surface of the bit line metal-semiconductor layer 137. By using the bit line metal-semiconductor layer 137, the material difference between the bit line metal layer 147 and the bit line contact structure 106 can be reduced, thereby improving the stability of carrier transmission between the bit line structure 107 and the bit line contact structure 106.

[0083] In an embodiment of the present disclosure, before forming the bit line contact structure 106, the first isolation layer 104 and the first semiconductor layer 105 are formed first, so as to form isolation on the sidewalls of the groove 130 by using the first isolation layer 104 and the first semiconductor layer 105, and use the first isolation layer 104 and the first semiconductor layer 105 as the second isolation layer 120 of the first active structure 101, thereby avoiding damage to the first active structure 101 during the formation of the bit line contact structure 106, and avoiding the bit line contact structure 106 from electrically connecting the adjacent first active structure 101 and the second active structure 102, which can improve the reliability of the semiconductor structure.

[0084] Another embodiment of the present disclosure further provides a semiconductor structure, which can be formed by the manufacturing methods of some or all of the semiconductor structures in the above embodiments. Hereinafter, the semiconductor structure provided by another embodiment of the present disclosure will be described with reference to the accompanying drawings. It should be noted that for the same or corresponding parts in the foregoing embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated hereinafter.

[0085] Refer to Figure 10 , Figure 10 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0086] In some embodiments, the semiconductor structure may include: a substrate 100, the substrate 100 includes a first active structure 101, a second active structure 102 arranged at intervals, and an isolation structure 103 located between the adjacent first active structure 101 and the second active structure 102, and a plurality of spaced grooves 130 are provided in the substrate 100, and the grooves 130 expose the top surface of the second active structure 102.

[0087] The semiconductor structure may include: a first isolation layer 104, and the first isolation layer 104 covers the sidewalls of the groove 130.

[0088] The semiconductor structure may include: a bit line contact structure 106, the bit line contact structure 106 is at least in contact connection with the top surface of the second active structure 102, and the bit line contact structure 106 located in the groove 130 is spaced apart from the first isolation layer 104.

[0089] By forming the first isolation layer 104 on the sidewalls of the groove 130, contact between the bit line contact structure 106 and the first active structure 101 can be avoided, thereby improving the reliability of the semiconductor structure.

[0090] In some embodiments, the bit line contact structure 106 also covers the sidewalls of the second active structure 102. By covering the sidewalls of the second active structure 102 with the bit line contact structure 106, the contact area between the bit line contact structure 106 and the second active structure 102 can be increased, thereby reducing the contact resistance between the second active structure 102 and the bit line contact structure 106, and the reliability of the semiconductor structure can be improved.

[0091] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first active structure and a second active structure arranged in an interval with each other, and an isolation structure located between the first active structure and the second active structure adjacent to each other; etching the substrate to form a plurality of spaced grooves, the grooves exposing a top surface of the second active structure; forming a first isolation layer, wherein the first isolation layer covers a surface of the groove; forming a first semiconductor layer, wherein the first semiconductor layer covers a surface of the first isolation layer; Etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structure; Etching the first isolation layer to expose the top surface of the second active structure; A bit line contact structure is formed, wherein the bit line contact structure is in contact connection with at least a top surface of the second active structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method of forming the bit line contact structure includes: forming an initial bit line contact structure, wherein the initial bit line contact structure completely fills the groove and covers the top surface of the substrate; The initial bit line contact structure is etched to form the bit line contact structures arranged at intervals.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The aspect ratio of the initial bit line contact structure formed and the portion corresponding to the groove is 2-3.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The method of forming the initial bit line contact structure includes: forming a first initial bit line contact structure, wherein the first initial bit line contact structure completely fills the groove and covers the top surface of the substrate; removing a portion of the first initial bit line contact structure, so that the remaining first initial bit line contact structure is flush with the top surface of the groove; A second initial bit line contact structure is formed, wherein the second initial bit line contact structure is located on a top surface of the initial bit line contact structure, and the first initial bit line contact structure and the second initial bit line contact structure constitute the initial bit line contact structure.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before etching the substrate, the method also includes: forming a second isolation layer, wherein the second isolation layer covers the top surface of the substrate, and the formed first isolation layer also covers the surface of the second isolation layer. During the process of etching the first semiconductor layer and the first isolation layer, the first semiconductor layer and the first isolation layer located on the top surface of the second isolation layer are also etched.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for etching the first semiconductor layer includes: etching the first semiconductor layer by dry etching, wherein the dry etching is a gas containing halogen elements.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The process of etching the first isolation layer also includes: etching the isolation structure to expose a portion of the sidewall of the second active structure.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The method of etching the first isolation layer and the isolation structure includes: using wet etching.

9. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first active structure and a second active structure arranged at intervals from each other, and an isolation structure located between the first active structure and the second active structure, wherein a plurality of spaced grooves are provided in the substrate, and the grooves expose a top surface of the second active structure; a first isolation layer, wherein the first isolation layer covers a sidewall of the groove; A bit line contact structure is provided, wherein the bit line contact structure is at least in contact with a top surface of the second active structure, and the bit line contact structure located in the groove is spaced apart from the first isolation layer.

10. The semiconductor structure according to claim 9, characterized in that: The bit line contact structure also covers the sidewalls of the second active structure.

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