Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, in the semiconductor structure, the inclined side wall of the transition part and the top of the doped region in the third region form an outward convex corner, the floating gate surrounds the doped region in the outward convex corner, when the semiconductor structure performs a write operation, according to the principle of the tip discharge, the electric field intensity between the doped region of the tip area in the outward convex corner and the floating gate is larger, the electrons in the doped region are easy to enter the floating gate, which is beneficial to improve the write performance of the semiconductor structure. The inclined side wall of the transition part and the top of the doped region in the first region form an inward concave corner, the doped region surrounds the floating gate in the inward concave corner, when the semiconductor structure performs an erase operation, according to the principle of the tip discharge, the electric field intensity between the floating gate of the tip area in the inward concave corner and the doped region is larger, the electrons in the floating gate are easy to enter the doped region, which is beneficial to improve the erase performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Non-volatile memory (NVMemory) is a storage technology that retains data even after power loss, playing a vital role in modern technology and daily life. Its importance is reflected in the following aspects: Data persistence: NVMemory ensures data retention after power failure, preventing data loss and guaranteeing system reliability. High-speed read / write: NVMemory, such as flash memory, provides fast data read and write speeds, improving device performance and responsiveness. Large-capacity storage: Modern NVMemory can provide enormous storage capacity to meet the ever-increasing demand for data storage. Low power consumption: Compared to volatile memory, NVMemory typically consumes less power, helping to extend battery life and reduce energy consumption.

[0003] EEPROM is a type of non-volatile memory. An EEPROM device contains multiple storage cells, each of which can be programmed and interrupted independently. Typically, each EEPROM cell includes a stacked gate (including a floating gate) and a select transistor. During operation, the select transistor selects the individual EEPROM cell to be erased or programmed. The stacked gate is the transistor in each cell that actually performs the erase and program operations. Programming and erasing the stacked gate utilizes the well-known Fowler-Nordheim tunneling phenomenon, storing positive or negative charges respectively within the floating gate of the stacked gate. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; doping a portion of the substrate to form a doped region, the doped region including a first region, a second region, and a third region arranged sequentially; thinning the doped regions in the first and second regions to make the thinned doped regions generally stepped, wherein the top of the doped region in the thinned first region is lower than the top of the doped region in the third region, the doped region in the second region is etched into a transition portion with inclined sidewalls, and the bottom end of the inclined sidewalls of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewalls of the transition portion is connected to the top of the doped region in the third region; after the thinning process, forming a conformally conformally stacked gate covering the doped region, the stacked gate including: a floating gate, an inter-gate dielectric layer located on the floating gate, and a control gate located on the inter-gate dielectric layer.

[0006] Optionally, a dry etching process can be used to thin the doped regions in the first and second regions.

[0007] Optionally, the dry etching process parameters include: the etching gas includes one or more of CF4, HBr and O2, the bias power is 200W to 1000W, and the chamber pressure is 10mTorr to 50mTorr.

[0008] Optionally, in the step of thinning the doped regions in the first and second regions, the distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

[0009] Optionally, in the thinning process, the angle between the top of the doped region and the inclined sidewall in the transition portion of the first region is 90° to 120°, and the angle between the top of the doped region and the inclined sidewall in the transition portion of the third region is 90° to 120°.

[0010] Optionally, in the step of thinning the doped regions in the first and second regions, the angle formed by the inclined sidewall in the transition portion and the top of the doped region in the first region is equal to the angle formed by the inclined sidewall in the transition portion and the top of the doped region in the third region.

[0011] Optionally, the method for forming the semiconductor structure further includes: after thinning the doped regions in the first region and the second region, removing a portion of the thickness of the doped regions in the first region and the second region before forming the stacked gate.

[0012] Optionally, the step of removing a portion of the thickness of the doped region in the first region and the second region includes: performing a high-temperature oxidation treatment on the surface of the doped region in the first region and the second region to form an oxide layer; and removing the oxide layer after performing the high-temperature oxidation treatment.

[0013] Optionally, during the process of removing a portion of the thickness of the doped region in the first and second regions, a portion of the thickness of the doped region in the third region is also removed.

[0014] Optionally, in the step of removing a portion of the thickness of the doped region in the first and second regions, the thickness of the doped region removed in the first and second regions is 80 angstroms to 110 angstroms.

[0015] Optionally, in the step of forming a stacked gate on the doped region, the stacked gate is further formed on the substrate in a portion of the region on both sides of the doped region.

[0016] Optionally, during the thinning process of the doped regions of the first region and the second region, the substrate on the side of the first region away from the second region is also thinned; in the step of forming the stacked gate, a selection gate is also formed on the substrate of the first region away from the second region, and the selection gate is spaced apart from the stacked gate.

[0017] Optionally, the method for forming the semiconductor structure further includes: after forming the stacked gate and the select gate, forming a source / drain doped region in the substrate between the select gate and the stacked gate, wherein the source / drain doped region and the doped region are adjacent to each other.

[0018] This invention provides a semiconductor structure, comprising: a substrate; a doped region located in a portion of the substrate, the doped region being stepped, the doped region including a first region, a second region, and a third region arranged sequentially; the top of the doped region in the first region being lower than the top of the doped region in the third region, the doped region in the second region including a transition portion with inclined sidewalls, the bottom end of the inclined sidewalls of the transition portion being connected to the top of the doped region in the first region, and the top end of the inclined sidewalls of the transition portion being connected to the top of the doped region in the third region; and a stacked gate conformally covering the doped region, the stacked gate including: a floating gate, an inter-gate dielectric layer located on the floating gate, and a control gate located on the inter-gate dielectric layer.

[0019] Optionally, the angle between the top of the doped region and the inclined sidewall in the transition portion in the first region is 90° to 120°, and the angle between the top of the doped region and the inclined sidewall in the transition portion in the third region is 90° to 120°.

[0020] Optionally, the angle formed by the inclined sidewall in the transition section and the top of the doped region in the first region is equal to the angle formed by the inclined sidewall in the transition section and the top of the doped region in the third region.

[0021] Optionally, the distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

[0022] Optionally, the stacked gate is also located on the substrate in a portion of the region on both sides of the doped region.

[0023] Optionally, the top of the substrate on the side of the first region away from the second region is flush with the top of the doped region in the first region; the method of forming the semiconductor structure further includes: a selection gate located on the substrate of the first region away from the second region, the selection gate being spaced apart from the stacked gate.

[0024] Optionally, the semiconductor structure further includes: source / drain doped regions located in the substrate between the selected gate and the stacked gate, wherein the source / drain doped regions and the doped regions are adjacent to each other.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] In the semiconductor structure formation method provided by this invention, a portion of the substrate is doped to form a doped region, which includes a first region, a second region, and a third region arranged sequentially. The doped regions in the first and second regions are thinned to make the thinned doped regions generally have a stepped shape. The top of the doped region in the first region is lower than the top of the doped region in the third region after etching. The doped region in the second region is etched into a transition portion with inclined sidewalls, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. Therefore, the inclined sidewall of the transition portion and the top of the doped region in the third region form a convex corner. The floating gate surrounds the doped region in the convex corner, which is equivalent to the doped region in the convex corner being inserted into the floating gate. During the write operation of the semiconductor structure, according to the principle of tip discharge, the electric field strength between the doped region in the tip region of the convex corner and the floating gate is relatively large, and electrons in the doped region can easily enter the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewalls of the transition section and the top of the doped region in the first region form a concave corner. The doped region surrounds the floating gate in the concave corner, which is equivalent to the floating gate being inserted into the doped region. When the semiconductor structure is erased, according to the principle of tip discharge, the electric field strength between the floating gate and the doped region in the tip region of the concave corner is relatively large, and electrons in the floating gate can easily enter the doped region, which is beneficial to improving the erasure performance of the semiconductor structure.

[0027] In the semiconductor structure provided by this invention, a doped region is located in a portion of the substrate. The doped region is stepped and includes a first region, a second region, and a third region arranged sequentially. The top of the doped region in the first region is lower than the top of the doped region in the third region. The doped region in the second region includes a transition portion with inclined sidewalls, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. A stacked gate conformally covers the doped region. The stacked gate is stepped and includes a floating gate, an inter-gate dielectric layer on the floating gate, and a control gate on the inter-gate dielectric layer. Therefore, the inclined sidewall of the transition portion and the top of the doped region in the third region form a convex corner. The floating gate surrounds the doped region in the convex corner, which is equivalent to the doped region in the convex corner being inserted into the floating gate. During the write operation of the semiconductor structure, according to the principle of tip discharge, the electric field strength between the doped region in the tip region of the convex corner and the floating gate is relatively large, and electrons in the doped region can easily enter the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion and the top of the doped region in the first region form a concave corner. The doped region surrounds the floating gate in the concave corner, which is equivalent to the floating gate being inserted into the doped region. During the erase operation of the semiconductor structure, according to the principle of tip discharge, the electric field strength between the floating gate in the tip region of the concave corner and the doped region is relatively large, and electrons in the floating gate can easily enter the doped region, which is beneficial to improving the erase performance of the semiconductor structure. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a semiconductor structure.

[0029] Figures 2 to 11 A schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an invention embodiment. Detailed Implementation

[0030] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0031] refer to Figure 1 The diagram shows a schematic of a semiconductor structure.

[0032] like Figure 1As shown, the semiconductor structure includes: a substrate 1, which includes a device region for forming memory cells and a peripheral region (not shown) for providing operating voltage to the memory cells; the substrate 1 of the device region includes a doped region 2; a stacked gate 3, located on the substrate 1 of the device region and covering the doped region 2; the stacked gate 3 includes: a floating gate 31, an inter-gate dielectric layer 32 on the floating gate 31, and a control gate 33 on the inter-gate dielectric layer 32; a select gate 5, located on the substrate 1 of the device region and spaced apart from the stacked gate 3; and source / drain doped regions 4, located in the substrate 1 between the select gate 5 and the stacked gate 3, in the substrate 1 on the side of the select gate 5 away from the stacked gate 3, and in the substrate on the side of the stacked gate 3 away from the select gate 5.

[0033] To improve the integration density of semiconductor structures, the area of ​​the peripheral region needs to be reduced. However, while reducing the peripheral region area, the operating voltage provided by the peripheral region to the memory cells in the working region also decreases accordingly. During write operations, if the peripheral region cannot provide a high voltage to the memory cells, the electric field strength between the doped region 2 and the floating gate 31 will be relatively low. Electrons in the doped region 2 will have difficulty entering the floating gate 31, resulting in poor electrical performance of the semiconductor structure. Similarly, during erase operations, if the peripheral region cannot provide a high voltage to the memory cells, the electric field strength between the doped region 2 and the floating gate 31 will be relatively low, making it difficult for electrons in the floating gate 31 to enter the doped region 2, resulting in poor electrical performance of the semiconductor structure.

[0034] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. A portion of the substrate is doped to form a doped region, which includes a first region, a second region, and a third region arranged sequentially. The doped regions in the first and second regions are thinned to create a stepped shape. The top of the doped region in the first region is lower than the top of the doped region in the third region after etching. The doped region in the second region is etched into a transition portion with inclined sidewalls, the bottom of which connects to the top of the doped region in the first region, and the top of which connects to the top of the doped region in the third region. Therefore, the inclined sidewalls of the transition portion and the top of the doped region in the third region form a convex corner. The floating gate surrounds the doped region in the convex corner, effectively inserting the doped region in the convex corner into the floating gate. During a write operation on the semiconductor structure, based on the principle of tip discharge, the electric field strength between the doped region in the tip region of the convex corner and the floating gate is relatively large, making it easier for electrons in the doped region to enter the floating gate, thus improving the write performance of the semiconductor structure. The inclined sidewalls of the transition section and the top of the doped region in the first region form a concave corner. The doped region surrounds the floating gate in the concave corner, which is equivalent to the floating gate being inserted into the doped region. When the semiconductor structure is erased, according to the principle of tip discharge, the electric field strength between the floating gate and the doped region in the tip region of the concave corner is relatively large, and electrons in the floating gate can easily enter the doped region, which is beneficial to improving the erasure performance of the semiconductor structure.

[0035] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 11 A schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an invention embodiment.

[0037] refer to Figure 2 Provides a base of 100.

[0038] The substrate 100 provides the operational basis for the formation process of the semiconductor structure, which belongs to electrically erasable programmable read-only memory.

[0039] In this embodiment, the substrate 100 includes a device region for forming a memory cell and a peripheral region (not shown in the figure) for providing the operating voltage of the memory cell. Generally, the larger the area of ​​the peripheral region, the greater the operating voltage that the peripheral region can provide to the device region.

[0040] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0041] refer to Figure 3 A portion of the substrate 100 is doped to form a doped region 101, which includes a first region I, a second region II, and a third region III arranged sequentially.

[0042] The method for forming the semiconductor structure further includes subsequently forming a stacked gate on the doped region 101, the stacked gate including a floating gate, and source / drain doped regions formed on the side of the doped region 101. During semiconductor operation, the doped region 101 can block direct current flow between the floating gate and the source / drain doped regions. Furthermore, FN tunneling (Fowler-Nordheim tunneling) occurring between the doped region 101 and the floating gate enables the stacked gate to read and write data.

[0043] In this embodiment, the doped region 101 is prepared for subsequent thinning of the doped regions 101 of the first region I and the second region II.

[0044] In this embodiment, the doped region 101 is a heavily N-type doped region (BNP). The more N-type ions incorporated, the better it is for reducing the write and erase voltages of the memory cells during semiconductor structure operation. Specifically, the N-type doped ions include one or more of P, As, and Sb.

[0045] In this embodiment, the step of doping a portion of the substrate 100 to form a doped region 101 includes: forming a doped mask layer (not shown in the figure) on the substrate 100, the doped mask layer having an opening that exposes the region to be doped 101; and performing ion doping using the doped mask layer as a mask to form the doped region 101 in the substrate 100.

[0046] In this embodiment, a portion of the substrate 100 is doped using ion implantation to form a doped region 101. Ion implantation is characterized by its simplicity and low processing cost.

[0047] It should be noted that the doped region 101 is formed in a portion of the substrate 100 and is also located on top of the substrate 100. The doped region 101 is formed on top of a portion of the substrate 100, so that after the doped region 101 of the first region I and the second region II is subsequently thinned, the top of the first region I, the second region II and the third region III are N-type ion doped regions.

[0048] refer to Figure 4 The doped regions 101 in the first region I and the second region II are thinned to make the thinned doped regions 101 generally have a stepped shape. The top of the doped region 101 in the first region I is lower than the top of the doped region 101 in the third region III. The doped region 101 in the second region II is etched into a transition portion 101a with inclined sidewalls. The bottom end of the inclined sidewall of the transition portion 101a is connected to the top of the doped region 101 in the first region I, and the top end of the inclined sidewall of the transition portion 101a is connected to the top of the doped region 101 in the third region III.

[0049] The doped regions 101 in the first region I and the second region II are thinned, while the doped region 101 in the third region III is not thinned. Therefore, the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III form a convex corner. The subsequently formed floating gate surrounds the doped region 101 in the convex corner, which is equivalent to the doped region 101 in the convex corner being inserted into the floating gate. When the semiconductor structure is written, according to the principle of tip discharge, the electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate is relatively large. Electrons in the doped region 101 can easily enter the floating gate, which is beneficial to improving the writing performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner. The doped region 101 surrounds the floating gate in the concave corner, which is equivalent to the floating gate being inserted into the doped region 101. When the semiconductor structure is erased, according to the principle of tip discharge, the electric field strength between the floating gate in the tip region of the concave corner and the doped region 101 is relatively large. Electrons in the floating gate can easily enter the doped region 101, which is beneficial to improving the erasure performance of the semiconductor structure.

[0050] Specifically, the step of thinning the doped regions 101 of the first region I and the second region II includes: forming a first mask layer 102 on the third region III, with the first mask layer 102 exposing the first region I and the second region II; and using the first mask layer 102 as a thinning mask to perform thinning treatment on the first region I and the second region II.

[0051] In this embodiment, a dry etching process is used to thin the doped regions 101 in the first region I and the second region II. Dry etching is an anisotropic etching process, which offers good control over the etching profile. This allows the doped regions 101 in the second region II to be etched into transition portions 101a with inclined sidewalls, while simultaneously ensuring a relatively smooth surface in the first region I. This results in the doped regions 101 exhibiting a stepped shape after etching. Furthermore, the dry etching process facilitates precise control over the removal thickness of the doped regions 101 in the first region I.

[0052] In this embodiment, the substrate 100 is made of silicon, and the etching gas in the dry etching process includes one or more of CF4, HBr and O2.

[0053] During the dry etching process to thin the doped regions 101 in the first region I and the second region II, if the bias power is too high, the material removal rate of the doped regions 101 in the first region I and the second region II will be too fast, resulting in poor control of the etching process. This can easily lead to poor surface flatness of the top and transition portion 101a of the doped region 101 in the first region I. Subsequently, when a stacked gate is formed on the doped region 101, the electron tunneling rate at different positions on the surface of the stacked gate and the top and transition portion 101a of the doped region 101 in the first region I will differ significantly during semiconductor structure operation, reducing the reliability of the semiconductor structure. If the bias power is too low, it will require excessive processing time to form the stepped doped regions 101. In this embodiment, the bias power in the dry etching is 200W to 1000W.

[0054] During the dry etching process to thin the doped regions 101 of the first region I and the second region II, if the chamber pressure is too high, reaction byproducts in the chamber will be redeposited onto the doped regions 101 of the first region I and the second region II. This results in poor surface flatness between the top of the doped region 101 and the transition portion 101a of the first region I. Subsequently, a stacked gate is formed on the doped region 101. During semiconductor structure operation, the electron tunneling rate at different locations on the top of the doped region 101 and the transition portion 101a of the first region I differs significantly, reducing the reliability of the semiconductor structure. If the chamber pressure is too low, it will require excessive processing time to form the stepped doped regions 101. In this embodiment, the chamber pressure during dry etching is 10 mTorr to 50 mTorr.

[0055] It should be noted that the first mask layer 102 also covers the substrate 100 of the third region III that is away from the second region II, and exposes the substrate 100 of the first region I that is away from the second region II. Correspondingly, during the thinning process of the doped regions 101 of the first region I and the second region II, the substrate 100 on the side of the first region I that is away from the second region II is also thinned.

[0056] It should also be noted that, in the step of thinning the doped regions 101 of the first region I and the second region II, the angle formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I is equal to the angle formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III. This ensures that when the semiconductor structure is written, the electric field strength between the tip region formed by the doped regions 101 of the second region II and the doped regions 101 of the third region II and the floating gate is the same as the electric field strength between the tip region of the doped regions 101 of the second region II and the doped regions 101 of the first region I and the doped region 101 when the semiconductor structure is erased. This is beneficial for making the writing operation rate and the erasing operation rate consistent.

[0057] It should be noted that, during the thinning process, if the included angle α between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III (e.g., ...) Figure 4 If the angle α between the doped region 101 in the second region II and the doped region 101 in the third region III and the floating gate is too large, according to the principle of tip discharge, during the write operation of the semiconductor structure, the increase in electric field strength between the tip region and the floating gate formed by the doped region 101 in the second region II and the doped region 101 in the third region III is small. Electrons in the doped region 101 are not easy to enter the floating gate, resulting in a lack of significant improvement in the write performance of the semiconductor structure. If the angle α between the top of the doped region 101 and the inclined sidewall in the transition portion 101a in the third region III is too large (as shown), Figure 4 The angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III is less than 90°. In this embodiment of the invention, the thinning process is performed by etching, but an angle less than 90° is difficult to form through etching. In this embodiment, during the thinning process, the angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III is between 90° and 120°.

[0058] For similar reasons, if the included angle α between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I (e.g., ...) Figure 4If the angle α between the top of the doped region 101 and the inclined sidewall in the transition portion 101a of the first region I is too large (as shown), according to the principle of tip discharge, during the erase operation of the semiconductor structure, the increase in electric field strength between the tip region formed by the doped regions of the second region and the first region and the floating gate is small. Electrons in the floating gate are not easy to enter the doped region 101, resulting in a non-significant improvement in the erase performance of the semiconductor structure. Figure 4 The angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I is less than 90°. In this embodiment of the invention, the thinning process is performed by etching, but an angle less than 90° is difficult to achieve through etching. In this embodiment, during the thinning process, the angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I is between 90° and 120°.

[0059] It should be noted that, in the step of thinning the doped regions 101 in the first region I and the second region II, if the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is (e.g., ... Figure 4 If the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too large, the thinning process will take too long, which is not conducive to improving the formation efficiency of the semiconductor structure. In addition, it will also easily lead to low mechanical strength of the stacked gate formed in the second region II, making it easy to break, resulting in the stacked gate not being able to write and erase data normally. If the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too small, the overall step morphology of the doped region 101 will be poor. That is, the convex corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III, and the concave corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I will have poor morphology. When the semiconductor structure is working, the tip effect is not significant, resulting in a small electric field intensity at the convex and concave corners, which will prevent the stacked gate formed later from performing normal erase and write operations. In this embodiment, the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is 200 angstroms to 500 angstroms.

[0060] refer to Figure 5 and Figure 6 The method for forming the semiconductor structure further includes: after thinning the doped regions 101 of the first region I and the second region II, removing part of the thickness of the doped regions 101 in the first region I and the second region II before forming the stacked gate.

[0061] During the dry etching process to thin the doped regions 101 of the first region I and the second region II, some etching ions remain on the top of the doped regions 101 of the first region I and the second region II. Subsequently, a stacked gate covering the doped regions 101 is formed. During the writing and reading of data in the semiconductor structure, the residual etching ions will hinder electrons from entering the floating gate from the doped regions of the first region I and the second region II, and from entering the doped regions 101 of the first region I and the second region II from the floating gate. Therefore, it is necessary to remove the residual etching ions on the top of the doped regions 101 in the first region I and the second region II.

[0062] In this embodiment, the step of removing part of the thickness of the doped region 101 in the first region I and the second region II includes: performing a high-temperature oxidation treatment on the surface of the doped region 101 in the first region I and the second region II to form an oxide layer 103; and removing the oxide layer 103 after the high-temperature oxidation treatment.

[0063] In this embodiment, the oxide layer 103 is made of silicon oxide. Silicon oxide has the advantages of high process compatibility, low formation difficulty, and easy removal.

[0064] In this embodiment, the oxide layer 103 is formed using a high-temperature oxidation process. The high-temperature oxidation process is easy to operate, and the resulting oxide layer 103 exhibits good thickness uniformity and density.

[0065] In this embodiment, the wet etching process is isotropic etching, which is simple to operate and has low process cost. The process parameters of wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0066] It should be noted that in the step of removing a portion of the thickness of the doped region 101 in the first region I and the second region II, the thickness of the doped region 101 removed in the first region I and the second region II should not be too large or too small. If the thickness of the doped region 101 removed in the first region I and the second region II is too large, it will require too much processing time and will not easily improve the formation efficiency of the semiconductor structure. If the thickness of the doped region 101 removed in the first region I and the second region II is too small, the etching ions remaining on the top of the doped region 101 in the first region I and the second region II will not be completely removed during the thinning process. During the writing and reading of data in the semiconductor structure, the residual etching ions will hinder electrons from entering the floating gate and the doped region 101 in the first region I and the second region II, which is not conducive to the writing and erasing operations of the semiconductor structure. In this embodiment, the thickness of the doped region 101 removed in the first region I and the second region II is 80 angstroms to 110 angstroms.

[0067] In this embodiment, during the process of removing a portion of the thickness of the doped region 101 in the first region I and the second region II, a portion of the thickness of the doped region 101 in the third region III is also removed. The simultaneous removal of a portion of the thickness from the doped regions 101 in the first region I, the second region II, and the third region III in this embodiment of the invention is beneficial in ensuring that the stepped morphology of the doped region after removal is consistent with the stepped morphology before removal.

[0068] It should also be noted that during the process of removing a portion of the thickness of the doped region 101 in the first region I and the second region II using a maskless method, a portion of the thickness of the substrate 100 on both sides of the doped region 101 is also removed. In other words, removing a portion of the thickness of the entire substrate does not require forming a removal mask; that is, a maskless method is used, which simplifies the removal process.

[0069] It should also be noted that the thickness of the oxide layer 103 formed on the doped region 101 and the substrates on both sides is equal during the high-temperature oxidation process. Before and after removing the oxide layer 103, the distance from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III does not change.

[0070] refer to Figures 7 to 9 After the thinning process, a stacked gate 105 is formed to conformally cover the doped region 101. The stacked gate 105 is stepped and includes a floating gate 1051, an inter-gate dielectric layer 1052 on the floating gate 1051, and a control gate 1053 on the inter-gate dielectric layer 1052.

[0071] In the semiconductor structure formation method provided in this embodiment of the invention, the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III form an outwardly convex corner. The floating gate 1051 surrounds the doped region 101 in the outwardly convex corner, which is equivalent to the doped region 101 in the outwardly convex corner being inserted into the floating gate 1051. When the semiconductor structure is written, according to the principle of tip discharge, the electric field strength between the doped region 101 in the tip region of the outwardly convex corner and the floating gate 1051 is relatively large. Electrons in the doped region 101 can easily enter the floating gate 1051, which is beneficial to improving the writing performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner. The doped region 101 surrounds the floating gate 1051 in the concave corner, which is equivalent to the floating gate 1051 being inserted into the doped region 101. When the semiconductor structure is erased, according to the principle of tip discharge, the electric field strength between the floating gate 1051 and the doped region 101 in the tip region of the concave corner is relatively large. Electrons in the floating gate 1051 can easily enter the doped region 101, which is beneficial to improving the erasure performance of the semiconductor structure.

[0072] It should also be noted that when the peripheral area of ​​the substrate 100 is small, and the peripheral area can only provide a low voltage to the control gate 1053 of the memory cell, according to the principle of tip discharge, the doped region 101 in the tip region of the convex corner and the floating gate 1051 can also have a sufficiently large electric field strength. When the semiconductor structure is working, the peripheral area only needs to provide a low operating voltage to the memory cell to enable the semiconductor structure to perform erase and write operations smoothly. The small area of ​​the peripheral area is beneficial to reducing the overall area of ​​the semiconductor structure and improving the integration of the semiconductor structure.

[0073] In this embodiment, the stacked gate is used as a storage unit for storing data and maintaining data state. By storing or not storing electrons in the floating gate 1051, the storage unit is in a state after storing or erasing information.

[0074] In this embodiment, during the step of forming the stacked gate 105 on the doped region 101, the stacked gate 105 is also formed on the substrate 100 in a portion of both sides of the doped region 101. That is, the doped region 101 is completely covered by the stacked gate 105, so that when the semiconductor structure performs data writing and erasing operations, the stacked gate 105 can more effectively control the electrons in the doped region 101. During the writing operation, electrons can easily enter the floating gate 1051 from the doped region 101, and during the erasing operation, electrons can easily enter the doped region 101 from the floating gate 1051.

[0075] In this embodiment, the floating gate 1051 is made of polycrystalline silicon. The floating gate 1051 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0076] The control gate 1053 is used to connect to an external power source to control the longitudinal electric field of the floating gate 1051. During a write operation, it controls the injection or movement of the electron flow in the floating gate 1051, changing the charge state of the floating gate 1051. During an erase operation, the control gate 1053 creates an erase electric field.

[0077] The control gate 1053 is used to inject electrons into the floating gate 1051 or pull electrons out of the floating gate 1051 during the process of writing or erasing data in the memory cell.

[0078] In this embodiment, the control gate 1053 is made of polycrystalline silicon.

[0079] It should be noted that the control gate 1053 is doped with P-type ions, which makes the control gate 1053 less likely to be in a depleted state, thereby making the control gate 1053 in a conductive state.

[0080] The inter-gate dielectric layer 1052 is used to electrically isolate the floating gate 1051 and the control gate 1053.

[0081] In this embodiment, the inter-gate dielectric layer 1052 is made of a dielectric material. Specifically, the material of the inter-gate dielectric layer 1052 includes one or both of silicon oxide and silicon nitride. In this embodiment, the inter-gate dielectric layer 1052 is a sandwich structure composed of silicon oxide, silicon nitride, and silicon oxide (ONO).

[0082] It should also be noted that, in the step of forming the stacked gate 105, a select gate 110 (EG) is also formed on the substrate 100 of the first region I away from the second region II, and the select gate 110 is spaced apart from the stacked gate 105.

[0083] Gate 110 is selected for access control of memory cells, data transfer, and selection and erasure operations of memory cells.

[0084] The semiconductor structure further includes a floating gate oxide layer 104, located between the substrate 100 and the stacked gate 105, and between the substrate 100 and the select gate 110.

[0085] A floating gate dielectric layer 104 is used to isolate the stacked gate 105 and the substrate 100, as well as the select gate 110 and the substrate 100.

[0086] In this embodiment, the floating gate dielectric layer 104 is made of a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer 104 may also be a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0087] In this embodiment, the select gate 110 and the stacked gate 105 are formed in the same step. Specifically, the steps for forming the select gate 110 and the stacked gate 105 include: forming a floating gate material layer 1091, an inter-gate dielectric material layer 1092 on the floating gate material layer 1091, and a control gate material layer 1093 on the inter-gate dielectric material layer 1092 on the doped region 101 and the substrate 100 on both sides of the doped region 101; forming a second mask layer 106 on the control gate material layer 1093, wherein the second mask layer 106 is formed at a predetermined location where the select gate and the stacked gate need to be formed; and etching the floating gate material layer 1091, the inter-gate dielectric material layer 1092, and the control gate material layer 1093 using the second mask layer 106 as a mask to form the stacked gate 105 and the select gate 110.

[0088] It should be noted that the method for forming the semiconductor structure further includes: before forming the floating gate material layer 1091, forming a floating gate dielectric material layer 111 on the doped region 101 and the substrate 100 on both sides of the doped region 101; during the process of forming the stacked gate 105 and the select gate 110, the floating gate dielectric material layer 111 is also etched to form the floating gate dielectric layer 104.

[0089] In this embodiment, the method for forming the semiconductor structure further includes: after forming the stacked gate and the select gate, forming a sidewall layer 107 on the sidewalls of the select gate and the stacked gate (e.g., ...). Figure 9 (As shown).

[0090] The sidewall layer 107 is used to protect the sidewalls of the select gate and the stacked gate, and also serves as a mask for subsequent source and drain doping.

[0091] refer to Figure 10 and Figure 11 The method for forming the semiconductor structure further includes: after forming the stacked gate 105 and the select gate 110, forming a source / drain doped region 108 in the substrate 100 between the select gate 110 and the stacked gate 105, wherein the source / drain doped region 108 and the doped region 101 are adjacent to each other.

[0092] The source / drain doped regions 108 and 101 are adjacent to each other, which makes the charge transfer distance shorter during write or erase operations, thereby reducing the time required for write and erase operations, reducing the diffusion and leakage of charge in the flow channel, and improving the efficiency of programming and erasing operations.

[0093] In this embodiment, the source / drain doped region 108 is doped with P-type ions, which include one or more of B, Ga, and In.

[0094] In this embodiment, source / drain doped regions 108 are formed in the substrate 100 between the select gate 110 and the stacked gate 105 using ion implantation. Ion implantation has the advantages of simple operation and low process cost.

[0095] Specifically, the source / drain doped region 108 includes a lightly doped region 1081 (LDD) and a heavily doped region 1082 located on top of the lightly doped region 1081. The lightly doped region 1081 is used to change the electric field distribution, and the heavily doped region 1082 is used to reduce resistance and provide better current transport capability.

[0096] It should be noted that the source / drain doped region 108 is formed not only in the substrate 100 between the select gate 110 and the stacked gate 105, but also in the substrate on the side of the select gate 110 away from the stacked gate 105, and in the substrate on the side of the stacked gate 105 away from the select gate 110.

[0097] refer to Figure 11 The present invention also provides a semiconductor structure.

[0098] The semiconductor structure includes: a substrate 100; doped regions 101 located in a portion of the substrate 100, the doped regions 101 being stepped, the doped regions 101 including a first region I, a second region II, and a third region III arranged sequentially; the top of the doped regions 101 in the first region I is lower than the top of the doped regions 101 in the third region III, the doped regions 101 in the second region II including a transition portion 101a with inclined sidewalls, the bottom end of the inclined sidewall of the transition portion 101a being connected to the top of the doped regions 101 in the first region I, and the top end of the inclined sidewall of the transition portion 101a being connected to the top of the doped regions 101 in the third region III; and a stacked gate 105 conformally covering the doped regions 101, the stacked gate 105 including: a floating gate 1051, an inter-gate dielectric layer 1052 located on the floating gate 1051, and a control gate 1053 located on the inter-gate dielectric layer 1052.

[0099] In this embodiment of the invention, the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III form a convex corner. The floating gate 1051 surrounds the doped region 101 in the convex corner, which is equivalent to the doped region 101 in the convex corner being inserted into the floating gate 1051. When the semiconductor structure is written, according to the principle of tip discharge, the electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate 1051 is relatively large. Electrons in the doped region 101 can easily enter the floating gate 1051, which is beneficial to improving the writing performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner. The doped region 101 surrounds the floating gate 1051 in the concave corner, which is equivalent to the floating gate 1051 being inserted into the doped region 101. When the semiconductor structure is erased, according to the principle of tip discharge, the electric field strength between the floating gate 1051 and the doped region 101 in the tip region of the concave corner is relatively large. Electrons in the floating gate 1051 can easily enter the doped region 101, which is beneficial to improving the erasure performance of the semiconductor structure.

[0100] In this embodiment, the substrate 100 includes a device region for accommodating the memory cell and a peripheral region (not shown in the figure) for providing the operating voltage of the memory cell. Generally, the larger the area of ​​the peripheral region, the greater the operating voltage that the peripheral region can provide to the device region.

[0101] It should be noted that when the peripheral area of ​​the substrate 100 is small, and the peripheral area can only provide a low voltage to the control gate 1053 of the memory cell, according to the principle of tip discharge, the doped region 101 in the tip region of the convex corner and the floating gate 1051 can also have a sufficiently large electric field strength. When the semiconductor structure is working, the peripheral area only needs to provide a low operating voltage to the memory cell to enable the semiconductor structure to perform erase and write operations smoothly. The small area of ​​the peripheral area is beneficial to reducing the overall area of ​​the semiconductor structure and improving the integration of the semiconductor structure.

[0102] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0103] When the semiconductor is working, the doped region 101 can block the direct current flow between the floating gate and the source / drain doped regions. In addition, the FN tunneling (Fowler-Nordheim Tunneling) that occurs between the doped region 101 and the floating gate 1051 enables the stacked gate 105 to read and write data.

[0104] In this embodiment, the doped region 101 is a heavily N-type doped region (BNP). The more N-type ions incorporated, the better it is for reducing the write and erase voltages of the memory cells during semiconductor structure operation. Specifically, the N-type doped ions include one or more of P, As, and Sb.

[0105] It should also be noted that the angle α formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the first region I is equal to the angle α formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the third region III. This makes the electric field strength between the tip region formed by the doped region 101 in the second region II and the doped region 101 in the third region III and the floating gate 1051 during the write operation of the semiconductor structure the same as the electric field strength between the tip region of the doped region 101 in the second region II and the doped region 101 in the first region I and the doped region 101 during the erase operation of the semiconductor structure. This is beneficial to make the write operation rate and the erase operation rate consistent.

[0106] It should be noted that if the included angle α between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III (e.g., ...) Figure 4 If the angle α between the doped region 101 in the second region II and the doped region 101 in the third region III and the floating gate is too large, according to the principle of tip discharge, during the write operation of the semiconductor structure, the increase in electric field strength between the tip region and the floating gate formed by the doped region 101 in the second region II and the doped region 101 in the third region III is small. Electrons in the doped region 101 are not easy to enter the floating gate, resulting in a lack of significant improvement in the write performance of the semiconductor structure. If the angle α between the top of the doped region 101 and the inclined sidewall in the transition portion 101a in the third region III is too large (as shown), Figure 4 The angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III is less than 90°. In this embodiment of the invention, the stepped doped region is formed by etching, but when the angle is less than 90°, it is difficult to form by etching. In this embodiment, the angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the third region III is 90° to 120°.

[0107] For similar reasons, if the included angle α between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I (e.g., ...) Figure 4If the angle α between the top of the doped region 101 and the inclined sidewall in the transition portion 101a of the first region I is too large (as shown), according to the principle of tip discharge, during the erase operation of the semiconductor structure, the increase in electric field strength between the tip region formed by the doped regions of the second region and the first region and the floating gate is small. Electrons in the floating gate are not easy to enter the doped region 101, resulting in a non-significant improvement in the erase performance of the semiconductor structure. Figure 4 The angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I is less than 90°. In this embodiment of the invention, the stepped doped region is formed by etching, but when the angle is less than 90°, it is difficult to form by etching. In this embodiment, the angle between the top of the doped region 101 and the inclined sidewall of the transition portion 101a in the first region I is 90° to 120°.

[0108] It should be noted that if the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too large, the overall stepped morphology of the doped region 101 will require excessive processing time to form. Furthermore, it can easily lead to low mechanical strength of the stacked gate formed on the second region II, making it prone to breakage and preventing normal writing and erasing of data. If the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too small, the overall stepped morphology of the doped region 101 will be poor. That is, the convex corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III, and the concave corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I will have poor morphology. During semiconductor structure operation, the tip effect will be insignificant, resulting in low electric field strength at the convex and concave corners, preventing normal erasing and writing operations of the formed stacked gate 105. In this embodiment, the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is 200 angstroms to 500 angstroms.

[0109] It should be noted that the top of the substrate 100 on the side of the first region I away from the second region II is flush with the top of the doped region of the first region I.

[0110] The stacked gate 105 is stepped and includes: a floating gate 1051, an inter-gate dielectric layer 1052 on the floating gate 1051, and a control gate 1053 on the inter-gate dielectric layer 1052.

[0111] In this embodiment, the stacked gate 105 is used as a storage unit for storing data and maintaining data state. By storing or not storing electrons in the floating gate 1051, the storage unit is in a state after storing or erasing information.

[0112] In this embodiment, the stacked gate 105 is also located on the substrate 100 in a portion of both sides of the doped region 101. That is, the doped region 101 is completely covered by the stacked gate 105, so that when the semiconductor structure performs data writing and erasing operations, the stacked gate 105 can more effectively control the electrons in the doped region 101. During the writing operation, electrons can easily enter the floating gate 1051 from the doped region 101, and during the erasing operation, electrons can easily enter the doped region 101 from the floating gate 1051.

[0113] In this embodiment, the floating gate 1051 is made of polycrystalline silicon. The floating gate 1051 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0114] The control gate 1053 is used to connect to an external power source to control the longitudinal electric field of the floating gate 1051. During a write operation, it controls the injection or movement of the electron flow in the floating gate 1051, changing the charge state of the floating gate 1051. During an erase operation, the control gate 1053 creates an erase electric field.

[0115] The control gate 1053 is used to inject electrons into the floating gate 1051 or pull electrons out of the floating gate 1051 during the process of writing or erasing data in the memory cell.

[0116] In this embodiment, the control gate 1053 is made of polycrystalline silicon.

[0117] It should be noted that the control gate 1053 is doped with P-type ions, which makes the control gate 1053 less likely to be in a depleted state, thereby making the control gate 1053 in a conductive state.

[0118] The inter-gate dielectric layer 1052 is used to electrically isolate the floating gate 1051 and the control gate 1053.

[0119] In this embodiment, the inter-gate dielectric layer 1052 is made of a dielectric material. Specifically, the material of the inter-gate dielectric layer 1052 includes one or both of silicon oxide and silicon nitride. In this embodiment, the inter-gate dielectric layer 1052 is a sandwich structure composed of silicon oxide, silicon nitride, and silicon oxide (ONO).

[0120] The semiconductor structure further includes a select gate (EG) located on the substrate 100 of the first region I away from the second region II, and the select gate 110 is spaced apart from the stacked gate 105.

[0121] Gate 110 is selected for access control of memory cells, data transfer, and selection and erasure operations of memory cells.

[0122] The semiconductor structure further includes a floating gate oxide layer 104, located between the substrate 100 and the stacked gate 105, and between the substrate 100 and the select gate 110.

[0123] A floating gate dielectric layer 104 is used to isolate the stacked gate 105 and the substrate 100, as well as the select gate 110 and the substrate 100.

[0124] In this embodiment, the floating gate dielectric layer 104 is made of a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer 104 may also be a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0125] In this embodiment, the semiconductor structure further includes a sidewall layer 107 located on the sidewall of the selected gate and the stacked gate.

[0126] The sidewall layer 107 is used to protect the sidewalls of the select gate and the stacked gate.

[0127] The semiconductor structure further includes a source / drain doped region 108 located in the substrate 100 between the selected gate 110 and the stacked gate 105, and the source / drain doped region 108 and the doped region 101 are adjacent to each other.

[0128] The source / drain doped regions 108 and 101 are adjacent to each other, which makes the charge transfer distance shorter during write or erase operations, thereby reducing the time required for write and erase operations, reducing the diffusion and leakage of charge in the flow channel, and improving the efficiency of programming and erasing operations.

[0129] In this embodiment, the source / drain doped region 108 is doped with P-type ions, which include one or more of B, Ga, and In.

[0130] Specifically, the source / drain doped region 108 includes a lightly doped region 1081 (LDD) and a heavily doped region 1082 located on top of the lightly doped region 1081. The lightly doped region 1081 is used to change the electric field distribution, and the heavily doped region 1082 is used to reduce resistance and provide better current transport capability.

[0131] It should be noted that the source / drain doped region 108 is also located in the substrate on the side of the select gate 110 away from the stacked gate 105, and in the substrate on the side of the stacked gate 105 away from the select gate 110.

[0132] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0133] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A portion of the substrate is doped to form a doped region, the doped region comprising a first region, a second region, and a third region arranged sequentially. The doped regions in the first and second regions are thinned to make the thinned doped regions generally have a stepped shape. The top of the doped region in the first region is lower than the top of the doped region in the third region. The doped region in the second region is etched into a transition portion with inclined sidewalls. The bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. After the thinning process, a conformally conformally stacked gate covering the doped regions is formed. The stacked gate includes: a floating gate, an inter-gate dielectric layer on the floating gate, and a control gate on the inter-gate dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The doped regions in the first and second regions are thinned using a dry etching process.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The dry etching process parameters include: etching gas including one or more of CF4, HBr and O2, bias power of 200W to 1000W, and chamber pressure of 10mTorr to 50mTorr.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of thinning the doped regions in the first and second regions, the distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the thinning process, the angle between the top of the doped region and the inclined sidewall in the transition portion of the first region is 90° to 120°, and the angle between the top of the doped region and the inclined sidewall in the transition portion of the third region is 90° to 120°.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of thinning the doped regions in the first and second regions, the angle formed by the inclined sidewall in the transition section and the top of the doped region in the first region is equal to the angle formed by the inclined sidewall in the transition section and the top of the doped region in the third region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after thinning the doped regions in the first region and the second region, removing a portion of the thickness of the doped regions in the first region and the second region before forming the stacked gate.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The steps of removing a portion of the thickness of the doped region in the first and second regions include: The surfaces of the doped regions in the first and second regions are subjected to high-temperature oxidation treatment to form an oxide layer; After the high-temperature oxidation treatment, the oxide layer is removed.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, During the process of removing a portion of the thickness of the doped region in the first and second regions, a portion of the thickness of the doped region in the third region is also removed.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of removing a portion of the thickness of the doped region in the first and second regions, the thickness of the doped region removed in the first and second regions is 80 angstroms to 110 angstroms.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a stacked gate on the doped region, the stacked gate is also formed on the substrate in a portion of the region on both sides of the doped region.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the thinning process of the doped regions in the first and second regions, the substrate on the side of the first region away from the second region is also thinned. In the step of forming the stacked gate, a selection gate is also formed on the substrate of the first region away from the second region, and the selection gate is spaced apart from the stacked gate.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the semiconductor structure further includes: after forming the stacked gate and the selected gate, forming a source / drain doped region in the substrate between the selected gate and the stacked gate, wherein the source / drain doped region and the doped region are adjacent to each other.

14. A semiconductor structure, characterized in that, include: Base; A doped region is located in a portion of the substrate. The doped region is stepped and includes a first region, a second region, and a third region arranged sequentially. The top of the doped region in the first region is lower than the top of the doped region in the third region. The doped region in the second region includes a transition portion with inclined sidewalls. The bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. A stacked gate, conformally covering the doped region, the stacked gate comprising: a floating gate, an inter-gate dielectric layer on the floating gate, and a control gate on the inter-gate dielectric layer.

15. The semiconductor structure as described in claim 14, characterized in that, In the first region, the angle between the top of the doped region and the inclined sidewall in the transition section is 90° to 120°, and in the third region, the angle between the top of the doped region and the inclined sidewall in the transition section is 90° to 120°.

16. The semiconductor structure as claimed in claim 14, characterized in that, The angle formed by the inclined sidewall in the transition section and the top of the doped region in the first region is equal to the angle formed by the inclined sidewall in the transition section and the top of the doped region in the third region.

17. The semiconductor structure as claimed in claim 14, characterized in that, The distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

18. The semiconductor structure as described in claim 14, characterized in that, The stacked gate is also located on the substrate in a portion of the region on both sides of the doped region.

19. The semiconductor structure as claimed in claim 14, characterized in that, The top of the substrate on the side of the first region opposite to the second region is flush with the top of the doped region in the first region; The method for forming the semiconductor structure further includes: selecting a gate, located on the substrate in the first region away from the second region, wherein the selected gate is spaced apart from the stacked gate.

20. The semiconductor structure as claimed in claim 19, characterized in that, The semiconductor structure further includes: source / drain doped regions located in the substrate between the selected gate and the stacked gate, wherein the source / drain doped regions and the doped regions are adjacent to each other.

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