Non-volatile memory including stacked capacitors

Abstract

The present invention relates to a reduced size non-volatile memory comprising an array of non-volatile memory cells, each memory cell in the array comprising a transistor comprising a source, a drain, and a gate, and a capacitor over the transistor comprising two plates and a dielectric layer therebetween, one polar plate of the capacitor is communicated with the drain electrode of the transistor; and in each row or each column, two adjacent storage units form a group, and capacitors of the two storage units in the group are superposed and share a polar plate communicated with a transistor drain electrode of each unit.

Description

Technical Field

[0001] The present application relates to a novel non-volatile memory, specifically to a novel non-volatile memory in which a memory cell includes a transistor and a capacitor, and particularly to such a memory in which, in each row or each column of its array, the capacitors of two adjacent memory cells share a plate. Background Art

[0002] In recent years, with the rapid development of semiconductor technology, various types of memories have emerged on the market and have been widely used. In electronic systems such as computers, dynamic random access memory (DRAM) and static random access memory (SRAM) are widely used to store information. However, both DRAM and SRAM are volatile memories and lose the stored information whenever the power supply is interrupted.

[0003] Therefore, it is desirable to store critical information in non-volatile memories, especially in portable electronic systems such as, for example, mobile Internet devices (MIDs), and there is a particular need for non-volatile memories. Flash memory is a type of non-volatile memory. However, since the information is stored as charges in a floating gate and reducing the number of electrons per bit reduces the reliability of the stored information, the further miniaturization of flash memory is limited.

[0004] In addition, currently many industries have huge demands for data storage and transmission, and traditional memories such as DRAM, SRAM, and Flash are gradually unable to cope. Moreover, the process miniaturization of traditional memories has become increasingly difficult. In this situation, the semiconductor industry has turned to the development of novel memories with higher storage efficiency, lower cost, and the ability to be miniaturized in the process, such as ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), and magnetic random access memory (MRAM).

[0005] These novel memories can combine the functions of random access memory, are non-volatile memories, and at the same time have the potential for further process miniaturization, and have attracted much attention in the industry.

[0006] The memory cells of FRAM, RRAM, PCRAM, and MRAM all contain capacitors, but the dielectric layer materials in the capacitors of the three are different. The middle dielectric layer of the capacitor in FRAM is a ferroelectric material layer, that in RRAM is a resistive switching material layer, that in PCRAM is a phase change material layer, and that in MRAM is a ferromagnetic material layer. When the direction of the externally applied electric field changes in the ferroelectric material, the polarization of the ferroelectric domains in the material will reverse, and the polarization state will change. The high and low polarization states before and after the electric field reversal are used to store information. The resistive switching material stores information by forming and breaking filaments (i.e., conductive paths) in the material to form high and low resistance states. The phase change material can be transformed between crystallization (low resistance state) and amorphous (high resistance state), and the difference in resistance before and after the phase change is used to store information. When the magnetization orientation of the ferromagnetic layer material changes, the resistance of the magnetic tunnel junction can be changed between a low resistance state and a high resistance state. Since the polarization state and resistance of the dielectric layer material are physical properties that can be measured very precisely, these new types of memories are non-volatile memories that can be scaled down to extremely small sizes.

[0007] Currently, the market has a strong demand for these new types of memories with good performance and the ability to be further scaled down in size. Although there are already some commercial products on the market, there is still a demand for new non-volatile memories with smaller sizes. Summary of the Invention

[0008] The purpose of this application is to provide a new type of non-volatile memory that can be further scaled down in size.

[0009] To solve the above technical problems, this application provides the following technical solutions.

[0010] The first aspect of the present invention relates to a new type of non-volatile memory, which includes an array of non-volatile memory cells. The memory cells are arranged in rows and columns. Each memory cell includes a transistor and a capacitor. The transistor is located on a substrate and includes a source electrode, a drain electrode, and a gate electrode. The capacitor is located above the transistor and includes two electrodes and the dielectric layer therebetween. One electrode of the capacitor is connected to the drain electrode of the transistor. In each row or each column, two adjacent memory cells form a group. The capacitors of the two memory cells in the group are stacked and share an electrode that is connected to the drain electrode of the transistor in their respective cells.

[0011] In a preferred embodiment, the stacked capacitors in the group are located above the drain electrodes of the two transistors in the group in an upright manner with the electrodes perpendicular to the surface of the substrate, and the shared electrode of the stacked capacitors is connected to the drain electrodes of the two transistors. Preferably, the shared electrode is connected to the drain electrodes of the two transistors through a conductive via.

[0012] In another preferred embodiment, the transistors of two memory cells within the group share a drain. More preferably, the transistors of each memory cell within the group share a source with the transistors of adjacent memory cells in the adjacent group.

[0013] In yet another preferred embodiment, two side plates of the vertically stacked capacitors within the group each extend outwards with a flange in a direction normal to the plate away from the common plate, starting from the lower edge or the upper edge of each plate. More preferably, each of the upper edges of the two side plates of the stacked capacitors within the group has a flange, such that the two side plates are respectively in a positive upright reverse L shape, i.e., and shape; or respectively in an inverted reverse L shape, i.e., and

[0014] In yet another preferred embodiment, the array includes: bit lines arranged along each column, and word lines and plate lines arranged along each row; wherein the bit lines of each column are connected to the sources of the transistors of the memory cells in that column, the word lines of each row are connected to the gates of the transistors of the memory cells in that row, and the plate lines of each row are connected to the plates of the capacitors of the memory cells in that row that are not connected to the transistor drains; wherein in each column, two adjacent memory cells form a group. More preferably, in each column, the transistors of two memory cells within the group share a drain, and in each column, the transistors of each memory cell within the group share a source with the transistors of adjacent memory cells in the adjacent group.

[0015] The above non-volatile memory of the present invention is preferably selected from: ferroelectric memory, resistive random access memory, phase change memory, or magnetic random access memory.

[0016] The second aspect of the present invention relates to a method for manufacturing the above non-volatile memory, wherein two side plates of the stacked capacitors within the group each extend outwards with a flange in a direction normal to the plate away from the common plate, starting from the upper edge of each plate, and the method sequentially includes the following steps:

[0017] (1) Form a transistor array arranged in rows and columns on a substrate,

[0018] (2) In each row or each column, form a stacked capacitor between two transistors within the group, above the drains of the two transistors within the group, and the following steps are sequentially included:

[0019] (a) Form a vertically upright drain conductive via perpendicular to the substrate surface above the transistor drain, with the bottom connected to the drain;

[0020] (b) A rectangular opening is formed above the drain conductive via, such that the length of the rectangular opening is the same as the full length of the stacked capacitor, and the vertical distance from the bottom of the rectangular opening to the underlying drain conductive via is equal to the upright height of the stacked capacitor;

[0021] (c) From the middle of the bottom of the rectangular opening, etch downward to the top surface of the drain conductive via to form a trench, where the length and height of the trench are respectively equal to the length and height of the stacked capacitor, and the sidewalls and the two bottom corners of the rectangular opening remaining after etching constitute the outward-expanded steps on the top surface of the trench;

[0022] (d) Deposit the materials for the two side plates and the intermediate dielectric layer of the stacked capacitor on the trench in sequence, and etch and remove the deposited materials at the bottom inside the trench;

[0023] (e) Etch and remove the dielectric layer materials and the materials for the two side plates deposited on the parts above the top surface of the trench and outside the trench;

[0024] (f) Etch from the bottom of the outward-expanded step on the top surface of the trench, such that the bottom of the outward-expanded step moves down below the top surface of the trench, and the downward movement distance is equal to the height of the flanges on the upper edges of the two side plates of the stacked capacitor;

[0025] (g) Deposit the material for the common plate of the stacked capacitor, then deposit the sacrificial metal, and then remove all the structures and deposits above the top surface of the trench to form the stacked capacitor, where the upper edges of its two side plates respectively have a flange protruding outward along the normal direction of the plate away from the common plate;

[0026] (3) Above the two flanges of the two side plates of the stacked capacitor in each group, form two conductive vias respectively, with the bottoms respectively connected to the two flanges, and form two plate lines above the two flange conductive vias, such that the top surfaces of the two flange conductive vias are respectively connected to the two plate lines.

[0027] In the memory array of the present invention, two adjacent memory cells in each row or each column form a group, and the capacitors of the two cells in the group are stacked, sharing a common plate connected to the drain of the transistor of each respective cell. Thus, the capacitance size of two adjacent memory cells can be reduced, which helps to reduce the size of the memory array. More preferably, the transistors of the two memory cells in the group share a common drain, and / or the transistors of each cell in the group share a common source with the transistors of the cells in another adjacent group, which can reduce the pitch of the memory cells in the array, increase the density of the memory cells in the array, and reduce the size of the memory. Description of the Drawings

[0028] Figure 1 is a top view of an embodiment of the non-volatile memory array of the present invention.

[0029] Figure 2 isFigure 1 The circuit diagram of the array.

[0030] Figure 3 is Figure 1 A top view of the memory cells of the first group in the first column of the array shown.

[0031] Figure 4 is Figure 1 A sectional view of the memory cells of the first group in the first column of the array shown taken along the section line A - A'.

[0032] Figure 5 is Figure 1 A sectional view of the memory cells of the first group in the first column of the array shown taken along the section line B - B'.

[0033] Figures 6a - 6u Shows a series of sectional views in the normal direction of the plates of the stacked capacitor with a flange at the upper edge of the side plates of the present invention during its formation process.

[0034] Figures 7a - 7l Shows a series of sectional views in the normal direction of the plates of the stacked capacitor with a flange at the lower edge of the side plates of the present invention during its formation process. Detailed implementation mode

[0035] The present invention will be described in detail below. All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

[0036] Generally, terms can be understood according to their meanings in the context. "One or more", at least in part according to the context, can be understood as describing any feature, structure, or property in the singular form, or a combination of features, structures, or properties in the plural form. Similarly, terms such as "a", "an", or "the" can be understood as expressing the singular or the plural at least in part according to the context. Unless otherwise defined, the singular forms of "a" and "the" include explicit support for plural objects. For example, "the layer" can include multiple such layers.

[0037] It is easily understood that the meanings of "on", "above", and "over" in the present invention should be interpreted in the broadest way, such that "on" not only means directly on something, but also can include being on something in the case where there are intermediate features or intermediate layers between the two, and "above" or "over" not only mean above or over something, but also can include being above or over something in the case where there are no intermediate features or intermediate layers between the two (i.e., directly on something). Similarly, "under", "below", or "beneath" have similar meanings.

[0038] In addition, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., may be used herein to describe a spatial relationship of one element or feature to another element or feature as illustrated in the figures. Spatial relative terms are intended to cover not only the spatial position and orientation of the device as depicted in the figures, but also other orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptions used herein may accordingly apply equally.

[0039] As used herein, the term "layer" refers to a portion of a material that includes a region having a certain thickness. The layer may extend over all or a portion of the region of the underlying / overlying structure above / below it. In addition, the layer may be a region in a homogeneous or heterogeneous continuous structure, and the thickness of the region is less than the thickness of the continuous structure. For example, the layer may be located between any pair of horizontal planes, or at the top or bottom surface of a continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, and / or one or more layers thereunder. The meaning of a layer may include multiple layers therein. For example, an interconnect layer may include one or more conductor and contact layers (wherein contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0040] Next, the novel non-volatile memory of the present invention will be described in more detail.

[0041] The non-volatile memory of the present invention includes an array of non-volatile memory cells. The memory cells in the array are arranged in rows and columns. Each memory cell is a 1T1C structure, that is: it includes a transistor (T) and a capacitor (C). In each memory cell, the capacitor is located above the transistor, and one plate of the capacitor is connected to the drain of the transistor. In each row or column, two adjacent memory cells form a group, and the capacitors of the two memory cells in the group are stacked and share a plate that is connected to the drain of the transistor of each respective cell. Stacking the capacitors of the two cells helps miniaturization.

[0042] In the memory cell of the present invention, both poles of the transistor may be referred to as the drain. In the case where one pole is referred to as the drain, the other pole is referred to as the source.

[0043] Preferably, the transistors of two memory cells within a group share a drain, and the stacked capacitor is located above the shared drain. This can effectively reduce the pitch between the two memory cells within the group. More preferably, within each row or column, the transistors of each memory cell within a group share a source with the transistors of adjacent memory cells in the adjacent group along the direction of the channel between their source and drain. This helps to reduce the pitch between adjacent groups, increase the density of memory cells, and reduce the size of the entire memory array and its memory.

[0044] The two capacitors forming the stacked capacitor are preferably exactly the same, including shape, structure, and composition of each part.

[0045] In the stacked capacitor, the common plate shared by the two capacitors is called the common plate and is connected to the drain of the transistor in its respective cell. The two non-common plates not connected to the transistor drain are called side plates and are respectively connected to two plate lines through their respective conductive vias.

[0046] The stacked capacitor has two side plates. Preferably, the materials, shapes, and structures of its two side plates are the same. There are also two intermediate dielectric layers in the stacked capacitor, and preferably the materials, shapes, and structures of the two dielectric layers are the same.

[0047] In the present invention, the terms "vertical" or "upright" refer to perpendicular to the surface of the substrate; the term "flat" refers to parallel to the surface of the substrate.

[0048] Within a group of memory cells described in the present invention, the stacked capacitor can be located upright above the transistor drain or flat above the transistor drain.

[0049] In the case where the stacked capacitor is located flat above the transistor drain, preferably the common plate is at the bottom of the stacked capacitor. In this case, the dielectric layers of the two capacitors are located flat on the common plate but are separated from each other by an isolation material; the side plates of the two capacitors are located flat on their respective dielectric layers and are also separated from each other by an isolation material.

[0050] In the case where the stacked capacitor is located upright above the transistor drain, the two capacitors are combined upright with their plates perpendicular to the surface of the substrate to form an integral capacitor.

[0051] Preferably, the stacked capacitor within the group is located upright above the drains of the two transistors, and the common plate of the stacked capacitor is connected to the drains of the two transistors through a conductive via. The upright arrangement of the stacked capacitor can reduce the planar area occupied by the stacked capacitor. In the case where the stacked capacitor is upright, preferably its two side plates and two dielectric layers are symmetric about the common plate.

[0052] Furthermore, the orientation of the vertically stacked capacitor is such that its plate plane is parallel to or perpendicular to the direction of the channel between the source and drain of the transistor of the memory cells within its group. Preferably, with its plate plane parallel to the direction of the channel between the source and drain of the transistor of the memory cells within its group, it stands upright above the transistor drain.

[0053] For facilitating the connection of the two side plates of the vertically stacked capacitor to their respective plate lines, preferably, from the lower edge or the upper edge of each side plate, along the normal direction of the side plate away from the common plate, there is a flange protruding outward. More preferably, the flange is a narrow strip that protrudes outward along the normal direction of the plate from the entire lower edge or the upper edge of the side plate, such that the two side plates are respectively in a positive upright reverse L shape, i.e., and shape; or respectively in an inverted reverse L shape, i.e., and

[0054] Preferably, the memory array of the present invention includes: bit lines arranged along each column, and word lines and plate lines arranged along each row; wherein the bit lines of each column are connected to the sources of the transistors of the memory cells in that column, the word lines of each row are connected to the gates of the transistors of the memory cells in that row, and the plate lines of each row are connected to the plates of the capacitors of the memory cells in that row that are not connected to the transistor drains; wherein in each column, two adjacent memory cells form a group. More preferably, in each column, the transistors of the two memory cells within a group share a drain; in each column, the transistors of each memory cell within a group share a source with the transistors of the adjacent memory cells in the adjacent group.

[0055] The above array structure of the present invention is applicable to all memories that include one transistor and one capacitor. The memory is preferably selected from: ferroelectric memory, resistive random access memory, phase change memory, or magnetic random access memory. The memory cells of these memories all include a transistor and a capacitor, usually 1T1C. The structures of the capacitors of these different types of memory cells are the same, all including two plates and an intermediate dielectric layer, and the difference lies only in the type of material of the intermediate dielectric layer. The intermediate dielectric layers of the capacitors in the ferroelectric memory, resistive random access memory, phase change memory, and magnetic random access memory are respectively a ferroelectric material layer, a resistive switching material layer for RRAM, a phase change material layer for PCRAM, and a ferromagnetic material layer for MRAM.

[0056] The non-volatile memory of the present invention and its stacked capacitor can be prepared by the following method.

[0057] When the stacked capacitors in the memory cell group of the present invention are in a flat state, the memory and its array can be fabricated by conventional methods in the memory industry. Since the size of the common plate at the bottom of the stacked capacitor is relatively large, the dielectric layer and side plates of each capacitor are relatively small, and the dielectric layers and side plates of the two capacitors are separated from each other. In the steps of fabricating the common plate, dielectric layer, and side plates of the stacked capacitor, corresponding photomasks with different sizes are used for etching to complete the process.

[0058] When the stacked capacitors in the memory cell group of the present invention are upright, the fabrication method of the memory and its array is as described below.

[0059] In the fabrication method of the memory array including upright stacked capacitors described below, the lengths, heights, and widths involved are defined as follows. The total length of the upright stacked capacitor is the length of the entire capacitor along the normal direction of its plates, including the lengths of the two flanges; the length of the upright stacked capacitor is the length between the two side plates of the capacitor along the normal direction of the plates, excluding the lengths of the two flanges. The lengths of the plate flanges, rectangular openings, and trenches are their dimensions along the direction parallel to the normal direction of the plates of the stacked capacitor, respectively.

[0060] The height of the upright stacked capacitor is its dimension along the direction perpendicular to the substrate surface, and the width is its dimension along the direction parallel to the substrate surface and parallel to the plate surface. The heights of the plate flanges, rectangular openings, and trenches are their dimensions along the direction perpendicular to the substrate surface, respectively.

[0061] In the present invention, the flanges of the two side plates of the upright stacked capacitor can be located at the upper edge or the lower edge of the side plates. The fabrication methods for the two cases are different, and the fabrication method with the flanges located at the lower edge of the side plates is relatively easy.

[0062] When the side plate flanges of the upright stacked capacitor are located at the lower edge of the side plates, the fabrication method of the memory array successively includes the following steps:

[0063] (1) Form a transistor array: Form a transistor array arranged in rows and columns on the substrate. In each row or each column, two adjacent transistors form a group.

[0064] (2) Form the stacked capacitors within each group: In each row or each column, between the two transistors within the group, form a stacked capacitor above the drains of the two transistors within the group, which successively includes the following steps:

[0065] (a) Formation of a drain conductive via, two plate lines, and conductive vias for two side plate flanges of a stacked capacitor: Above the transistor array, through three depositions of dielectric layers and etching operations, from bottom to top, a drain conductive via, two plate lines, and conductive vias for two side plate flanges of a stacked capacitor are formed in sequence. First, by depositing a bottom dielectric layer and etching, the drain conductive via is formed vertically upright above the drain, communicating with the drain at the bottom; in the subsequent two dielectric layer depositions and etching operations, the formed drain conductive via continues to extend upward, and its top corresponds to such a position: namely, the position of the common plate of the stacked capacitor to be formed above it later. The two plate lines are formed by depositing another bottom dielectric layer and etching again; subsequently, the conductive vias for the two side plate flanges are formed by depositing a first dielectric layer and etching, such that the conductive vias for the two flanges are respectively formed vertically upright above the two plate lines, communicating with their respective plate lines at the bottom, and their tops corresponding to such a position: namely, the positions of the two side plate flanges of the stacked capacitor to be formed above them later; the tops of the drain conductive via and the flange conductive vias are in a plane;

[0066] (b) Formation of two side plate flanges of the stacked capacitor: On the first dielectric layer deposited in step (a), and on the formed drain conductive via and flange conductive vias, deposit the material of the side plates of the capacitor, and use a photomask and dry etching to form such a side plate material deposition layer: such that its length in the normal direction of the capacitor plate to be formed later is equal to the full length of the stacked capacitor;

[0067] (c) Formation of a trench for accommodating the stacked capacitor: Deposit a second dielectric layer, on this second dielectric layer, above the side plate material deposit, with the position corresponding to the drain conductive via below as the center, use a photomask and dry etching to etch downward to form a deep trench until the top of the drain conductive via is exposed, such that the length and height of the trench are respectively equal to the length and height of the stacked capacitor;

[0068] (d) Formation of the side plates and the intermediate dielectric layer of the stacked capacitor: Deposit the materials of the two side plates of the stacked capacitor on the second dielectric layer, and on the side walls and bottom of the trench, then use dry etching to remove the side plate materials deposited on the second dielectric layer and at the bottom of the trench, only retaining the side plate material layer on the side walls of the trench; then, deposit the intermediate dielectric layer material of the stacked capacitor on the second dielectric layer and on the side walls and bottom of the trench, and then use a photomask and dry etching to remove the dielectric layer material deposited at the bottom of the trench, and the dielectric layer material and side plate material deposited on the side walls parallel to the normal direction of the plate in the trench;

[0069] (e) Forming a common electrode plate and a stacked capacitor: On the dielectric layer material outside the trench and at the bottom of the trench, deposit the material of the common electrode plate, then deposit a sacrificial metal, and then, using chemical mechanical polishing, remove all the structures and deposits above the top surface of the trench to form a stacked capacitor, with a flange extending outward in the normal direction of the electrode plate at the lower edges of both side electrode plates.

[0070] Then, on the formed stacked capacitor, as needed, a conventional protective layer or dielectric layer or other layers can be continuously deposited, such as a SiN protective layer and other dielectric layers.

[0071] In the case where the flange of the side electrode plate of the vertical stacked capacitor is located at the upper edge of the side electrode plate, the method for manufacturing a memory array sequentially includes the following steps:

[0072] (1) Forming a transistor array: Form a transistor array arranged in rows and columns on a substrate. In each row or each column, two adjacent transistors form a group.

[0073] (2) Forming a stacked capacitor within each group: In each row or each column, between the two transistors within the group, form a stacked capacitor above the drain electrodes of the two transistors within the group, which sequentially includes the following steps:

[0074] (a) Forming a drain conductive via: Form a vertical drain conductive via perpendicular to the surface of the substrate above the transistor drain to connect the drain.

[0075] (b) Forming a rectangular opening: Form a rectangular opening above the drain conductive via, such that the length of the rectangular opening is the same as the full length of the stacked capacitor, and the vertical distance from the bottom to the lower conductive via is equal to the vertical height of the stacked capacitor.

[0076] (c) Forming a trench for accommodating the stacked capacitor: From the middle of the bottom of the rectangular opening, etch downward to the top surface of the drain conductive via to form a trench, the length and height of the trench being equal to the length and height of the stacked capacitor respectively. The side walls and the two bottom corners remaining after etching of the rectangular opening form two outwardly extending steps on the top surface of the trench.

[0077] To more conveniently form the trench, preferably, before forming the rectangular opening, deposit a layer of isolation material on the dielectric layer where the rectangular opening is to be formed, and the isolation material is preferably SiN; after forming the rectangular opening, deposit another layer of the isolation material on the rectangular opening and the isolation material layer, such that the thickness of the isolation material deposited on the side walls of the rectangular opening is equal to the length of the flange of the side electrode plate of the stacked capacitor; then dry-etch the isolation material until reaching the bottom of the rectangular opening, and the length of the exposed part at the bottom of the opening after etching is the length of the stacked capacitor; dry-etch downward from the exposed part at the bottom of the rectangular opening until the top surface of the drain conductive via is exposed to form the trench.

[0078] (d) Forming the two side plate layers and the middle dielectric layer of the stacked capacitor: Deposit the materials for the two side plates of the stacked capacitor on the trench, and then etch away the side plate materials deposited on the bottom of the trench and the side walls of the trench along the normal direction of the plates; then, deposit the material for the middle dielectric layer of the stacked capacitor on the trench, and then etch away the material for the middle dielectric layer deposited on the bottom of the trench and the side walls of the trench along the normal direction of the plates.

[0079] (e) Removing the dielectric layer material and the two side plate materials deposited outside the trench: Etch away the dielectric layer material and the materials of the two side plates deposited on the part above the top surface of the trench and the part outside the trench;

[0080] Due to the uneven structure inside the trench, in order to make the surface obtained after etching smoother and of better quality, it is preferred to spin-coat an organic photoresist on the trench before etching. After the photoresist is cured, dry etching is carried out to remove the photoresist on the part of the outer expansion step and above on the top surface of the trench, exposing the dielectric layer material and the materials of the two side plates deposited on the outer expansion step and its side walls and on the second dielectric layer. Then, dry etching is carried out again to remove the exposed dielectric layer material and the materials of the two side plates.

[0081] (f) Forming a groove for accommodating the side plate flange: Etch from the bottom of the outer expansion step on the top surface of the trench so that the bottom of the outer expansion step moves down below the top surface of the trench, and the moving distance is equal to the height of the flange of the two side plates of the stacked capacitor. From the outer edge of the top surface of the trench downward, a sunken groove is formed for accommodating the side plate flange of the stacked capacitor.

[0082] In the case of spin-coating an organic photoresist in step (e), after forming the groove for the side plate flange, dry etching is used to remove the remaining photoresist inside the trench.

[0083] (g) Forming the common plate and the stacked capacitor: Deposit the material for the common plate of the stacked capacitor, then deposit the sacrificial metal, and then remove all the structures and deposits above the top surface of the trench to form the stacked capacitor, and the upper edges of the two side plates of which respectively have an outward-expanded flange along the normal direction of the plates away from the common plate;

[0084] (3) Forming the plate lines connecting the side plates of the stacked capacitor: Above the flanges of the two side plates of the stacked capacitor in each group, form two conductive vias to respectively communicate with the two flanges, and form two plate lines above the two conductive vias so that the two conductive vias are respectively connected to the two plate lines.

[0085] Then, on the formed stacked capacitor, if necessary, a conventional protective layer or dielectric layer or other layers can be continuously deposited.

[0086] In the preparation method of the present invention, the etching or dry etching mentioned all refers to dry etching.

[0087] The deposition of the dielectric layer, photomask, dry etching in the preparation method of the present invention, as well as the etching agent and organic photoresist used, etc. are all conventional operations and conventional substances in this industry and are well-known to those of ordinary skill in the art. The dry etching agent includes, but is not limited to, fluorine-containing or chlorine-containing gases. The dielectric layer, capacitor plates (including common plates and side plates), dielectric layers (including the ferroelectric material layer of FRAM, the resistive switching material layer of RRAM, the phase change material layer of PCRAM, and the ferromagnetic material layer of MRAM), isolation dielectric layer, isolation layer, sacrificial metal, etc. described in the present invention are consistent with the corresponding conventional definitions in this industry, and their materials are also conventional materials in this industry. The isolation layer material includes, but is not limited to, SiN or SiO 2 .

[0088] The memory of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments shown in the drawings are illustrative, and the terms used in the description are only for the purpose of describing specific embodiments and are not intended to be limiting; moreover, the drawings are not necessarily drawn to scale. Although for the purpose of illustration, the description of the specific implementation and its preparation contains many details, those of ordinary skill in the art will understand that many changes and substitutions can be made to these details, and these changes and substitutions are considered to be included in the scope of the present invention. In addition, those skilled in the art will recognize that the embodiments of the present invention can be implemented without one or more of the following specific details. And in some cases, some well-known structures, materials, or operations are not shown or described in detail to avoid making the embodiments of the present invention too cumbersome.

[0089] Figures 1 - 2 The top view and circuit diagram of a 4×2 array of a specific embodiment of the non-volatile memory of the present invention are respectively shown. Figures 3 - 5 They are respectively the top view of the storage unit in the first group of the first column in the array and the cross-sectional views along the section lines A-A' and B-B'.

[0090] The memory cells in the memory array are of the 1T1C type, i.e., they include a transistor (T) and a capacitor (C) located above and connected to the transistor. The transistor T is a CMOS transistor, which includes a gate, a source, and a drain. The gate of the transistor of the memory cell is connected to the word line WL of the memory array through a wire, and the word line WL is used to control the conduction or cutoff of the transistor; one pole (source or drain) of the transistor T is connected to one electrode (or plate) of the capacitor C, and the other pole (drain or source) of the transistor T is connected to the bit line BL of the memory array. For the sake of convenience, the pole of the transistor T connected to the capacitor C is called the drain D, then the source S of the transistor T is connected to the bit line BL. The other electrode (or plate) of the capacitor C is connected to the plate line PL of the memory array. By controlling the conduction and cutoff of the transistor T through the word line WL, different voltages are applied to the capacitor through the bit line BL and the plate line PL to write data into the memory, and the stored data of the capacitor is detected through the bit line BL to realize data reading.

[0091] As Figures 1 - 2 shown, in this array, the bit lines BL are arranged along columns, and the word lines WL and the plate lines PL are arranged along rows. Each bit line BL connects the sources S of the transistors of the memory cells in each column along that column, each word line WL connects the gates G of the transistors of the memory cells in each row along that row, and each plate line PL connects the electrodes (or plates) of the capacitors of the memory cells in each row along that row that are not connected to the drains of the transistors.

[0092] Two adjacent memory cells in each column form a group. There are four groups of memory cells in this 4×2 array. Figure 1 The first group in the first column as shown is composed of two memory cells 101 and 201 located in the first column and the first - second rows. The second group in the first column is composed of two memory cells 301 and 401 located in the first column and the third - fourth rows. The bit line in the first column is BL1, and the bit line in the second column is BL2. The word line and the plate line in the first row are WL1 and PL1 respectively, and the word line and the plate line in the second row are WL2 and PL2 respectively, and so on.

[0093] Taking Figure 1 the first group in the first column as shown as an example, it is composed of two memory cells 101 and 201 located in the first column and the first - second rows. These two memory cells 101 and 201 respectively contain transistor T 101 and capacitor C 101 , transistor T 201 and capacitor C 201 . The two transistors T 101 and transistor T 201 in these two memory cells in this group share a common drain D 101 / 201 ; and the two capacitors C 101 and C 201Stacked, sharing a plate PC connected to the drain of the transistor in its unit 101 / 201 ( Figures 3 - 5 ), forming a stacked capacitor C 101 / 201 ( Figure 5 The stack capacitor is located at the common drain D with its plate vertically disposed on the substrate surface. 101 / 201 Above, common plate PC 101 / 201 Through the vertical drain conductive via ( Figures 4 - 5 The dot-shaped column in the middle (not marked with a number) is connected to the common drain D below 101 / 201 ( Figures 4 - 5 ). The orientation of the vertical stacked capacitor is: the plate plane is parallel to the direction of the channel between the source and drain of the transistor of the memory cell in its group.

[0094] The transistor T in the memory cell 201 in the first group 201 , and the transistor T of the adjacent memory cell 301 in the adjacent group (group 2) in the first column 301 , share a source S 201 / 301 .

[0095] Capacitor C in stacked capacitors 101 Including side plate P 101 , dielectric layer DL 101 , and common plate PC 101 / 201 , capacitor C 201 Including side plate P 201 , dielectric layer DL 201 , and common plate PC 101 / 201 . Side plate P 101 and P 201 From the entire upper edge, along the normal direction of the plate, there is a narrow strip flange F 101 and F 201 ( Figure 4 ), extending outward, so that the two side plates are inverted positive and negative L shapes, that is, and Side plate P 101 Narrow strip flange F 101 Above, there is an upright conductive via V 101 ( Figures 3 - 5 ), the bottom is connected to the flange, and the top is connected to the plate line PL1 above.

[0096] Figure 1 The manufacturing method of the memory cell array shown comprises the following steps in sequence, wherein the upper edge of the side plate of the stacked capacitor has a flange.

[0097] (1) A transistor array arranged in rows and columns is formed on a substrate (Sub). Each transistor includes a gate G, a source S, and a drain D. Word lines WL connected to the gates of the transistors in each row are formed along each row. Subsequent plate lines PL are also formed in the row direction, and subsequent bit lines BL are formed in the column direction. Two adjacent memory cells in each column form a group. The transistors of the two memory cells within the group share a common drain, and each memory cell within the group shares a common source with the transistor of the adjacent memory cell in the adjacent group in the same column. In the substrate, the active regions where the source and drain of the transistors are located are separated by shallow trench isolation (STI), as Figure 4 shown.

[0098] (2) In each column, a stacked capacitor is formed above the common drain of the two transistors within each group, which successively includes the following steps. Figures 6a - 6u A series of cross-sectional views of the stacked capacitor along the normal direction of its plate during its formation are shown. The position and direction of the cross-hatching are the same as those of the A-A' cross-hatching in Figure 1 .

[0099] (a) Forming conductive vias for the source and the common drain: On the already formed transistor array, a first dielectric layer D 1 is deposited. Conductive vias for the source and the common drain are respectively formed at positions corresponding to the source and the common drain of the underlying transistors within this dielectric layer. The bottom of each via is connected to the corresponding source and common drain below. After each subsequent deposition of a dielectric layer, a conductive via needs to be formed at the position corresponding to the source below in the deposited dielectric layer, so that the source conductive via extends all the way out to be connected to the upper-layer bit line BL formed finally, as Figure 5 shown. Figure 5 The conductive vias for the common drain and the source in are not labeled and are dot-shaped columns. Figure 6a Only the conductive via for the common drain formed in the dielectric layer D 1 is shown in .

[0100] (b) Forming a rectangular opening: As Figures 6b - 6c shown, on the first dielectric layer D 1 , a second dielectric layer D 2 and a first isolation layer I 1 are successively deposited. Then, at the position corresponding to the conductive via for the common drain below, a rectangular opening is formed by using a photomask and dry etching on the first isolation layer I 1 and the second dielectric layer D 2 , penetrating the isolation layer and reaching inside the second dielectric layer, such that the length of the rectangular opening is the same as the full length of the stacked capacitor, and the vertical distance from the bottom of the rectangular opening to the underlying drain conductive via is equal to the upright height of the stacked capacitor; the second dielectric layer D 2 is preferably an isolation dielectric layer.

[0101] (c) Forming a trench: As Figures 6d - 6e shown, on the first isolation layer I 1 and on the bottom and side walls of the rectangular opening, deposit a second isolation layer I 2 , such that the thickness of the second isolation layer I deposited on the side walls of the rectangular opening 2 is equal to the length of the side plate flange F; the preferred materials of the first and second isolation layers are the same, both preferably SiN; then, perform anisotropic dry etching on the second isolation layer until the bottom of the rectangular opening, and the length of the exposed part at the bottom of the opening is the length of the stacked capacitor. At the upper end of the side wall of the etched rectangular opening, a gentle slope is presented;

[0102] Then, simultaneously perform dry etching on the first isolation layer material remaining on the second dielectric layer, the second isolation layer material remaining on the side walls of the rectangular opening, and the second dielectric layer material below the exposed part at the bottom of the rectangular opening until the top surface of the common drain conductive via in the first dielectric layer is exposed, and at the same time completely remove the remaining first isolation layer material and second isolation layer material. Thus, a trench is formed in the second dielectric layer and on the top surface of the common drain conductive via in the first dielectric layer. The remaining side walls and the two bottom corners of the rectangular opening form the outward-expanded steps on the top surface of the trench; As Figure 6f shown. According to the etching ratio of the isolation layer material SiN to the second dielectric layer material with respect to the etchant, and their height ratio, a fluorine-containing gas is preferably used as the etchant to complete this step.

[0103] (d) Forming the two side plates and the intermediate dielectric layer of the stacked capacitor: As Figure 6g shown, deposit the materials of the two side plates P of the stacked capacitor on the second dielectric layer, on the side walls and bottom of the trench and the outward-expanded steps. The materials of the two side plates are the same; then use a photomask and dry etching to only remove the side plate material deposited on the bottom of the trench and the side plate material deposited on the side walls parallel to the normal direction of the plate in the trench, as Figure 6h shown. Then, as Figure 6i shown, deposit the material of the intermediate dielectric layer DL of the stacked capacitor. The materials of the intermediate dielectric layers of the two capacitors are the same. Then use a photomask and dry etching to remove the dielectric layer material deposited on the bottom of the trench and the dielectric layer material deposited on the side walls parallel to the normal direction of the plate in the trench, as Figure 6j shown;

[0104] (e) Spin-coating photoresist and its etching: As Figure 6k shown, spin-coat a layer of photoresist PR, and after curing, perform dry etching to remove the photoresist above the outward-expanded steps on the top surface of the trench, as Figure 6lAs shown, the outwardly expanding step and the dielectric layer material covering the side walls thereof and the second dielectric layer and the materials of the two side plates are exposed; the exposed dielectric layer material and the materials of the two side plates are removed by dry etching again, as Figure 6m shown;

[0105] (f) Forming a groove for accommodating the flange of the side plate of the stacked capacitor: From the bottom of the outwardly expanding step on the top surface of the trench, dry etching is performed on the second dielectric layer below it, so that the bottom of the outwardly expanding step moves down below the top surface of the trench, and the moving distance is equal to the flange height of the two side plates of the stacked capacitor; thus, a sunken groove is formed downward from the outer edge of the top surface of the trench for accommodating and forming the flange of the side plate of the stacked capacitor, as Figure 6n shown; then the remaining organic photoresist in the trench is removed by dry etching, as Figure 6o shown;

[0106] (g) Forming a common electrode plate and forming a stacked capacitor: As Figure 6p shown, on the second dielectric layer and the formed structure, the material of the common electrode plate PC of the stacked capacitor is deposited, and the material of the common electrode plate can be the same as or different from the material of the side plate; then a sacrificial metal, such as tungsten, is deposited, as Figure 6q shown, and the black area in the figure is the deposited sacrificial metal; then, by chemical mechanical polishing, all the structures and deposits above the top surface of the trench are removed to form a stacked capacitor, as Figure 6r shown, and for the two side plates of this stacked capacitor, a narrow strip flange F extending outward is formed respectively from its entire upper edge along the normal direction of the electrode plate;

[0107] (3) Forming a plate line connecting the side plates of the stacked capacitor: As Figures 6s - 6t shown, on the formed stacked capacitor, a SiN protective layer is deposited, and then the third dielectric layer D 3 is deposited; as Figure 6u shown, in the third dielectric layer and the SiN protective layer, at the positions corresponding to the two side plate flanges of the capacitor below, two flange conductive vias V 101 and V 201 are formed, and the bottoms are respectively connected to the two flanges; then the fourth dielectric layer D 4 is deposited, and two plate lines PL1 and PL2 are formed in this dielectric layer, so that the top surfaces of the two flange conductive vias are respectively connected to the two plate lines; at the same time, in this fourth dielectric layer, at the position corresponding to the source conductive via below, a conductive contact block of the source is formed, and the bottom is connected to the source conductive via below.

[0108] (4) Forming a bit line: Depositing the fifth dielectric layer D 5, within the dielectric layer, at a position corresponding to the source conductive contact block below, a source conductive via is formed, with its bottom connected to the conductive contact block below; then, above the fifth dielectric layer, a bit line BL is formed, such that the top surface of the source conductive via is connected to the bit line.

[0109] When the lower edge of the side plate of the vertical stacked capacitor has a flange and other structures and features are the same as those of the above Figure 1 storage unit and its memory array, a preferred specific preparation method for this memory array is as described below, successively including the following steps.

[0110] (1) Form a transistor array and word lines: On a substrate, an array of transistors arranged in rows and columns is formed, where each transistor T includes a gate G, a source S, and a drain D. In each column, two adjacent transistors form a group. Word lines WL are arranged along the row direction, and in each row, a word line WL connected to the gates of the transistors in that row is formed. The subsequent plate lines PL and bit lines BL are arranged along the row and column directions respectively. In each column, two adjacent storage units form a group. The transistors of the two storage units within the group share a drain, and each storage unit within the group shares a source with the transistor of the adjacent storage unit in the adjacent group in that column. Within the substrate, the active regions where the source and drain of the transistors are located are separated by shallow trench isolation (STI).

[0111] (2) Form a stacked capacitor: In each column, above the shared drain of the two transistors within each group, one of the above-mentioned stacked capacitors is formed, successively including the following steps. Figures 7a - 7l Shows a series of cross-sectional views of the stacked capacitor along the normal direction of its plates during its formation process, with the position and direction of the cross-sectional lines the same as those of the Figure 1 A - A' cross-sectional line in.

[0112] (a) Form conductive vias for the source and shared drain, plate lines, and conductive vias for the side plate flanges:

[0113] On the already formed transistor array, a bottom dielectric layer is deposited, and within this dielectric layer, at positions corresponding to the source and shared drain of the underlying transistors respectively, vertical conductive vias for the source and shared drain are formed, with their bottoms respectively connected to the corresponding source and shared drain below. After each subsequent deposition of the dielectric layer, a conductive via needs to be formed again at the position corresponding to the source below in the deposited dielectric layer, so that the source conductive via extends all the way out to be connected to the upper-layer bit line BL formed finally.

[0114] Then, another bottom dielectric layer is deposited, and two plate lines arranged along the row are formed on this dielectric layer. The two plate lines are subsequently connected to the two side plate flanges of the stacked capacitor respectively. At the same time, at the position corresponding to the shared drain conductive via below in this dielectric layer, a drain conductive contact block is formed, with its bottom connected to the shared drain conductive via below.

[0115] Subsequently, deposit the first dielectric layer D 1 , at the position corresponding to the conductive contact block of the shared drain in the first dielectric layer, form a drain conductive via, so that the conductive via of the shared drain extends out, and the bottom of the conductive via is connected to the drain conductive contact block below; at the same time, in the first dielectric layer D 1 , at the positions corresponding to the two side-plate flanges of the stacked capacitor to be formed above it, respectively form two vertical conductive vias for the two flanges, so that the bottoms of the two flange conductive vias are respectively connected to the two plate lines below; Figure 7a shows the conductive via of the shared drain formed in the dielectric layer D 1 , and the conductive vias of the two flanges. The top surfaces of the three conductive vias are in a plane. Figure 7a The conductive via of the shared drain in is not marked with an identifier and is a dot column. The conductive vias V 1 and V 2 in Figure 7a are shown by dotted lines because they are staggered in the front-back direction with the conductive via of the shared drain in the column direction, as shown in the top views of Figure 1 and Figure 3 .

[0116] (b) Form the two side-plate flanges of the stacked capacitor: Deposit the material of the side-plate of the stacked capacitor on the first dielectric layer D 1 and the formed conductive via of the shared drain and the conductive vias of the flanges, as shown in Figure 7b ; then use a photomask and dry etching to form a deposited layer of such side-plate material: make its length in the normal direction of the plate of the stacked capacitor to be formed later equal to the full length of the stacked capacitor, as shown in Figure 7c .

[0117] (c) Form a trench for accommodating the stacked capacitor: Then deposit the second dielectric layer D 2 , as shown in Figure 7d . The second dielectric layer D 2 is preferably an isolation dielectric layer. On this second dielectric layer, above the deposited layer of the side-plate material, centered on the position corresponding to the conductive via of the shared drain below, use a photomask and dry etching to etch downward to form a deep trench until the top of the conductive via of the shared drain is exposed, so that the length and height of the trench are respectively equal to the length and height of the stacked capacitor; at the same time, form two flanges F 1 and F 2 on the top surfaces of the two flange conductive vias, as shown in Figure 7e ;

[0118] ​​​​​​​(d) Forming the side plates and the intermediate dielectric layer of the stacked capacitor: On the second dielectric layer, and on the side walls and bottom of the trench, deposit the materials for the two side plates of the stacked capacitor. Then, use dry etching to remove the materials deposited on the second dielectric layer and at the bottom of the trench, leaving only the side plate material layer on the side walls of the trench, as Figures 7f - 7g shown. Next, on the second dielectric layer, and on the side walls and bottom of the trench, deposit the material for the intermediate dielectric layer of the stacked capacitor. Then, use a photomask and dry etching to remove the dielectric layer material deposited at the bottom of the trench, and the dielectric layer material and side plate material deposited on the side walls parallel to the normal direction of the plate in the trench, forming two side plates P 1 and P 2 , and two dielectric layers DL 1 and DL 2 , as Figures 7h - 7i shown;

[0119] (e) Forming the common plate and the stacked capacitor: As Figure 7j shown, on the dielectric layer material outside the trench and at the bottom of the trench, deposit the material for the common plate to form the common plate PC. Then deposit a sacrificial metal (preferably tungsten), as Figure 7k shown, and the black area in the figure is the deposited sacrificial metal. Then, use chemical mechanical polishing to remove all the structures and deposits above the top surface of the trench to form the stacked capacitor. The two side plates each have a flange that extends outward in the normal direction of the plate along their entire lower edge, as Figure 7l shown.

[0120] (3) Forming the bit line: Deposit another dielectric layer and form the bit line BL to connect the top surface of the extended source conductive vias to the bit line.

[0121] The above description of the embodiments is for the convenience of those of ordinary skill in the art to more easily understand the present invention. Those skilled in the art can obviously make various modifications to these embodiments easily and apply the general principles described herein to other embodiments without creative efforts. Therefore, the protection scope of the present invention is not limited to the embodiments here. Improvements and modifications made by those skilled in the art based on the content disclosed in this application without departing from the scope and spirit of the present invention are within the scope of the present invention.

Claims

1. A non-volatile memory including stacked capacitors, which includes an array of non-volatile memory cells, wherein the memory cells are arranged in rows and columns, each memory cell includes a transistor and a capacitor, the transistor is located on a substrate and includes a source, a drain, and a gate, the capacitor is located above the transistor and includes two electrodes and a dielectric layer therebetween, and one electrode of the capacitor is connected to the drain of the transistor; In each row or column, two adjacent memory cells form a group, and the capacitors of the two memory cells in the group are stacked and share an electrode connected to the drain of the transistor of each respective cell.

2. The non-volatile memory according to claim 1, wherein the stacked capacitors in the group are located above the drains of the two transistors in the group in an upright manner with their electrodes perpendicular to the surface of the substrate, and the shared electrode of the stacked capacitors is connected to the drains of the two transistors.

3. The non-volatile memory according to claim 1 or 2, wherein the transistors of the two memory cells in the group share a drain.

4. The non-volatile memory according to claim 3, wherein the transistor of each memory cell in the group shares a source with the transistor of an adjacent memory cell in the adjacent group.

5. The non-volatile memory according to claim 2, wherein two side electrodes of the stacked capacitors in the group extend outwardly with a flange in a direction normal to the electrode away from the shared electrode from the lower edge or the upper edge of each electrode.

6. The non-volatile memory according to claim 5, wherein each of the upper edges of the two side plates of the stacked capacitors within the group has a flange, such that the two side plates are respectively in a positive upright reverse L shape, i.e., and shape, or are respectively in an inverted reverse L shape, i.e., and 7. The non-volatile memory according to claim 1 or 2, wherein the array includes: bit lines arranged along each column, and word lines and plate lines arranged along each row; wherein the bit lines of each column are connected to the sources of the transistors of the memory cells in that column, the word lines of each row are connected to the gates of the transistors of the memory cells in that row, and the plate lines of each row are connected to the electrodes of the capacitors of the memory cells in that row that are not connected to the transistor drains; wherein in each column, two adjacent memory cells form a group.

8. The non-volatile memory according to claim 7, wherein in each column, the transistors of the two memory cells in the group share a drain, and in each column, the transistor of each memory cell in the group shares a source with the transistor of an adjacent memory cell in the adjacent group.

9. The non-volatile memory according to claim 1 or 2, wherein the memory is selected from: ferroelectric memory, resistive random access memory, phase change memory, or magnetic random access memory.

10. A method for manufacturing the non-volatile memory according to claim 5, wherein two side electrodes of the stacked capacitors in the group extend outwardly with a flange in a direction normal to the electrode away from the shared electrode from the upper edge of each electrode, and the method sequentially includes the following steps: (1) Forming an array of transistors arranged in rows and columns on a substrate, (2) Forming a stacked capacitor between the two transistors in the group in each row or column, located above the drains of the two transistors in the group, and sequentially including the following steps: (a) Forming a vertical drain conductive via perpendicular to the surface of the substrate above the transistor drain, with the bottom connected to the drain; (b) A rectangular opening is formed above the drain conductive via, such that the length of the rectangular opening is the same as the full length of the stacked capacitor, and the vertical distance from the bottom of the rectangular opening to the underlying drain conductive via is equal to the upright height of the stacked capacitor; (c) From the middle of the bottom of the rectangular opening, etching downward to the top surface of the drain conductive via to form a trench, the length and height of the trench being respectively equal to the length and height of the stacked capacitor, and the sidewalls and the two bottom corners of the rectangular opening remaining after etching constitute the outward-expanded steps on the top surface of the trench; (d) Sequentially depositing the materials of the two side plates and the material of the intermediate dielectric layer of the stacked capacitor on the trench, and etching and removing the deposited material at the bottom inside the trench; (e) Etching and removing the dielectric layer material and the materials of the two side plates deposited on the part above the top surface of the trench and the part outside the trench; (f) Etching from the bottom of the outward-expanded step on the top surface of the trench, such that the bottom of the outward-expanded step moves downward below the top surface of the trench, and the downward movement distance is equal to the height of the flange on the upper edges of the two side plates of the stacked capacitor; (g) Depositing the common plate material of the stacked capacitor, then depositing the sacrificial metal, and then removing all the structures and deposits above the top surface of the trench to form the stacked capacitor, and each of the upper edges of the two side plates of the stacked capacitor has a flange extending outward in the normal direction of the plate away from the common plate; (3) Above the two flanges of the two side plates of the stacked capacitor in each group, respectively form two conductive vias, the bottoms of which are respectively connected to the two flanges, and form two plate lines above the two flange conductive vias, such that the top surfaces of the two flange conductive vias are respectively connected to the two plate lines.

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