High-voltage Diode structure and process method

Abstract

A reverse injection region is additionally arranged between an injection region on one side and a DTI, the injection region and the DTI structure are separated, the influence of random potential in the DTI on a PN junction is prevented, and it is guaranteed that positive and negative breakdown voltages are the same during positive and reverse application. A deep trench isolation (DTI) structure serves as isolation between devices, and the DTI penetrates through an epitaxial layer and a buried layer to penetrate into a substrate, so that the integration level of the devices can be improved, and the layout area of a chip is reduced. Only one injection region is added in the process, and the injection process shares the original process and is highly matched with the original process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device design and manufacturing, and particularly to a high-voltage Diode structure and a manufacturing process thereof. Background Art

[0002] High-voltage diode (Diode) devices have the characteristics of high voltage and large current of discrete devices, and also absorb the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can achieve functions that originally required multiple chips, greatly reducing the area, lowering the cost, improving the energy efficiency, and conforming to the development trend of miniaturization, intelligence, and low energy consumption of modern power electronic devices. Diode devices will have forward and reverse applications, that is, being connected in the forward and reverse directions. The forward and reverse breakdown voltages are particularly important as key parameters for measuring high-voltage Diode devices.

[0003] An existing Diode device structure is as Figure 1 shown. From the cross-sectional structure, the entire structure includes a DTI deep isolation trench filled with polysilicon. The right P-type region (including P-type epitaxy 103, P-type implantation region 108, P-well 107, and P-type heavily doped region 110) is connected to the right DTI structure, and the left N-type region (N-type implantation region 104) is connected to the left DTI structure. The potential of the polysilicon filled in the DTI is floating. During forward and / or reverse applications, the potential in the DTI is different, which will cause the position of the PN junction breakdown point to change, transferring from the lateral PN junction breakdown to the DTI sidewall breakdown, resulting in different forward and reverse breakdown voltages. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-voltage Diode structure and a manufacturing process thereof, which can ensure the same forward and reverse breakdown voltages during forward and reverse applications.

[0005] To solve the above problems, the present invention provides a manufacturing process for a high-voltage Diode structure, including the following process steps: Providing a semiconductor substrate of a first conductivity type, and forming a buried layer of a second conductivity type on the semiconductor substrate; Forming another layer of an epitaxial layer of the first conductivity type on the semiconductor substrate; Performing ion implantation to form a second conductivity type implantation region in the epitaxial layer; the second conductivity type implantation region is divided into independent left and right parts; Forming a shallow trench isolation structure on the surface layer of the epitaxial layer; Performing deep trench etching and filling processes to form a deep trench isolation structure; Performing photolithography and etching to open an implantation window, forming a first conductivity type implantation region and a well region.

[0006] Further, the semiconductor substrate includes a silicon substrate, a silicon germanium substrate, or a wide bandgap semiconductor substrate such as gallium nitride or silicon carbide.

[0007] Further, the buried layer is formed by an ion implantation process.

[0008] Further, the epitaxial layer is formed by a deposition process.

[0009] Further, the second conductivity type implantation region is divided into two independent implantation regions on the left and right, which are respectively located beside the subsequently formed deep trench isolation structure, and one side of each is connected to the deep trench isolation structure; the depth of the second conductivity type implantation region penetrates the entire epitaxial layer, and the bottom contacts the buried layer.

[0010] Further, the shallow trench isolation structure is formed by using active region photolithography, etching and filling processes to form a shallow trench isolation structure; the shallow trench isolation structure is filled with an insulating medium.

[0011] Further, the aspect ratio of the deep trench is greater than 20; the deep trench is located outside the independent second conductivity type implantation region and surrounds the second conductivity type implantation region; the deep trench is filled with polysilicon to form a deep trench isolation structure; the polysilicon in the deep trench is in a floating state, and the bottom of the deep trench exceeds the depth where the buried layer is located.

[0012] Further, in the first conductivity type implantation region and the well region, the first conductivity type implantation region is located in the epitaxial layer against the second conductivity type implantation region on the right, and the well region is located in the first conductivity type implantation region.

[0013] Further, the process steps further include performing a selective source and drain ion implantation process to form a heavily doped region of the first conductivity type and a heavily doped region of the second conductivity type.

[0014] Further, the first conductivity type is P-type, and the second conductivity type is N-type; the implanted impurity for P-type during ion implantation is boron, and the implanted impurity for N-type is phosphorus or arsenic; Or it can be changed to the first conductivity type being N-type and the second conductivity type being P-type.

[0015] The present invention provides a high-voltage Diode structure, which has an epitaxial layer of the first conductivity type on a semiconductor substrate of the first conductivity type; a deep trench isolation structure is provided in the epitaxial layer, and the high-voltage Diode is formed in the isolation region formed by the deep trench isolation structure; In the isolation region formed by the deep trench isolation structure, a buried layer is provided in the semiconductor substrate; Separate second-conductive-type implantation regions are respectively against the deep trench isolation structures on both sides in the isolation regions, and the first-conductive-type implantation region is against the second-conductive-type implantation region on the right side; a well region is further provided in the first-conductive-type implantation region, and a heavily doped region of the first conductive type is further provided in the well region; The surface of the epitaxial layer has a shallow trench isolation structure.

[0016] The depth of the second-conductive-type implantation region is the thickness of the epitaxial layer, and its bottom contacts the buried layer.

[0017] The deep trench isolation structure includes deep trenches and polysilicon filled in the deep trenches, and the polysilicon is in a floating state.

[0018] The surface layer of the epitaxial layer further has a heavily doped region of the first conductive type and a heavily doped region of the second conductive type.

[0019] The first conductive type is P type, and the second conductive type is N type; the implanted impurity for P type during ion implantation is boron, and the implanted impurities for N type are phosphorus or arsenic; Or it can be changed to the first conductive type being N type and the second conductive type being P type.

[0020] For the high-voltage Diode structure and process method of the present invention, in order to improve the phenomenon that the forward and reverse breakdown voltages of the PN junction are different, an additional N-type implantation region is added between the right P-type region and the DTI to isolate the P-type region from the DTI structure and prevent the random potential in the DTI from affecting the PN junction. During forward and reverse applications, it ensures that the forward and reverse breakdown voltages are the same. The deep trench isolation structure DTI is used as the isolation between devices. The DTI penetrates through the epitaxial layer and the buried layer and deep into the substrate, which can improve the device integration and reduce the chip layout area. Description of the Drawings

[0021] Figure 1 is a schematic diagram of the high-voltage Diode structure of the traditional structure.

[0022] Figure 2 is a schematic diagram of forming the buried layer in the process steps of the present invention.

[0023] Figure 3 is a schematic diagram of forming the epitaxial layer in the process steps of the present invention.

[0024] Figure 4 is a schematic diagram of forming an independent N-type implantation region in the process steps of the present invention.

[0025] Figure 5 is a schematic diagram of forming the shallow trench isolation structure in the process steps of the present invention.

[0026] Figure 6It is a schematic diagram of the process steps of the present invention for forming a deep trench isolation structure.

[0027] Figure 7 It is a schematic diagram of the process steps of the present invention for forming a P-well and a P-type implantation region.

[0028] Figure 8 It is a schematic diagram of the source / drain implantation in the process steps of the present invention.

[0029] Figure 9 It is a simulation diagram of the internal electric field of the traditional structure connected in forward and reverse.

[0030] Figure 10 It is a simulation diagram of the internal electric field of the structure of the present invention connected in forward and reverse.

[0031] Figure 11 It is a breakdown voltage curve graph of the traditional structure connected in forward and reverse.

[0032] Figure 12 It is a breakdown voltage curve graph of the structure of the present invention connected in forward and reverse.

[0033] Figure 13 It is a process flow chart of the present invention.

[0034] 101 - P-type substrate, 102 - N-type buried layer, 103 - P-type epitaxy, 104 - N-type implantation, 105 - shallow trench isolation structure, 106 - deep trench isolation structure (polysilicon filling), 107 - P-well, 108 - P-type implantation, 109 - N-type heavily doped region, 110 - P-type heavily doped region. Specific embodiments

[0035] The following presents specific embodiments of the present invention in conjunction with the accompanying drawings, clearly and completely describing the technical solutions in the present invention, but the present invention is not limited to the following embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0036] The present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals throughout the drawings denote the same elements. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0037] The present invention provides a high-voltage Diode structure, and in a specific embodiment, its structure is as Figure 6 shown. There is a P-type epitaxial layer 103 on a P-type semiconductor substrate 101; a deep trench isolation structure DTI 106 is provided in the epitaxial layer, and the high-voltage Diode is formed within the isolation region formed by the deep trench isolation structure.

[0038] In the isolation region formed by the deep trench isolation structure, an N-type buried layer 102 is provided in the semiconductor substrate. The buried layer 102 and the deep trench isolation structures DTI 106 on both sides together form a basin-shaped isolation region.

[0039] Independent N-type implantation regions 104 respectively abut against the deep trench isolation structures on both sides in the isolation region, and a P-type implantation region 108 abuts against the N-type implantation region 104 on the right; a P-type well region 107 is further provided in the P-type implantation region, and a P-type heavily doped region 110 is further provided in the well region 107 as the contact lead-out region of the P-type well region 107.

[0040] A shallow trench isolation structure 105 is provided on the surface of the epitaxial layer, and the shallow trench isolation structure 105 is a conventional isolation structure, and the medium filled therein is an insulating medium such as silicon oxide or silicon nitride.

[0041] The depth of the N-type implantation region 104 is the thickness of the epitaxial layer 103, and its bottom contacts the buried layer 102.

[0042] The deep trench isolation structure 106 includes deep trenches and polysilicon filled in the deep trenches, and the polysilicon is in a floating state, that is, not connected to any external potential.

[0043] The surface layer of the epitaxial layer also has a heavily doped P-type region 110 and a heavily doped N-type region 109, forming a contact lead-out region or a source / drain region.

[0044] The process method of the above high-voltage Diode structure can refer to the following process steps: As Figure 1 shown, provide a P-type silicon substrate 101, and form an N-type buried layer 102 on the silicon substrate 101. The buried layer can be formed by implanting N-type impurity ions, such as phosphorus or arsenic, etc. The implantation region of the buried layer also determines the range and size of the isolation region.

[0045] On the silicon substrate 101, form a P-type epitaxial layer 103 through a deposition process, as Figure 3 shown. The thickness and doping concentration of the epitaxial layer have an important impact on the breakdown voltage of the device.

[0046] Perform N-type ion implantation to form an N-type implantation region 104 in the epitaxial layer, as Figure 4 shown. The N-type implantation region 104 is divided into two independent left and right parts. The implantation regions of the two parts are defined by one-time photolithography and etching, and are formed synchronously in one-time ion implantation. The implantation depth of the N-type implantation region 104 penetrates the entire thickness of the epitaxial layer 103, and the bottom reaches the buried layer 102.

[0047] Perform active region photolithography, etching and silicon oxide filling processes on the surface layer of the epitaxial layer to form a shallow trench isolation structure 105. As Figure 5 shown.

[0048] Perform deep trench etching and filling processes, as Figure 6 shown, to form a deep trench isolation structure 106. The deep trench etching is located at the edge of the N-type buried layer, outside the two independent N-type implantation regions 104. The deep trench isolation structure 106 and the underlying layer 102 together form an isolation region. The material filled in the deep trench isolation structure 106 is polysilicon, which is in a floating state and not connected to a potential.

[0049] Perform photolithography and etching to open the implantation window to form a P-type implantation region 108 and a P-type well region 107, as Figure 7 shown. The well region 107 is located in the middle of the P-type implantation region 108, and its implantation region and implantation depth do not exceed those of the P-type implantation region 108.

[0050] Subsequently, conventional source / drain ion implantation can be selectively performed to form a heavily doped N-type region 109 and a heavily doped P-type region 110, as Figure 8 shown, and the entire device fabrication is completed.

[0051] For the high-voltage Diode structure and process method of the present invention, in order to improve the phenomenon that the forward and reverse breakdown voltages of the PN junction are different, an additional N-type implantation region 104 with opposite conductivity type is added between the right P-type implantation region 108 and the DTI. The implantation process is carried out synchronously with the original N-type implantation region 104 on the left, isolating the right P-type implantation region 108 from the DTI structure on the right, preventing the random potential in the DTI from affecting the PN junction, and ensuring the same forward and reverse breakdown voltages during forward and reverse applications. The deep trench isolation structure DTI is used as the isolation between devices. The DTI penetrates through the epitaxial layer and the buried layer and deep into the substrate, which can improve the device integration and reduce the chip layout area.

[0052] Figure 9 and Figure 10 are respectively the simulation diagrams of the electric field distribution when the traditional structure and the structure of the present invention are applied in the forward and reverse connections. It can be seen that Figure 9 for the traditional structure, whether in the forward or reverse connection, the breakdown point is located on the sidewall of the DTI, and the positions are slightly different. While Figure 10 the simulation of

[0053] Figure 11 and Figure 12 shows that for the structure of the present invention, whether in the forward or reverse connection, the breakdown point is located at the lateral PN junction and is in the same position, and the breakdown voltage is more stable and has better consistency. Figure 11 For the traditional structure shown in Figure 12 , when in the forward and reverse connections, the breakdown voltages are 113V and 137V respectively, showing an obvious difference. While for the structure of the present invention shown in

[0054] , when in the forward and reverse connections, the breakdown voltages are almost the same and are significantly higher than those of the traditional structure, demonstrating a significant performance improvement. It should be noted that P connected to negative and N connected to positive respectively represent that when the P end of the PN junction sweeps the breakdown voltage BV of the PN junction towards the negative voltage, and when the N end of the PN junction sweeps the breakdown voltage BV of the PN junction towards the positive voltage. For example, when P is connected to negative and sweeps BV, it is -150V, and when N is connected to positive and sweeps BV, it is 150V. Both are the BV of this PN junction, so the absolute values are the same. However, the BV of the PN junction measured by these two methods for the original structure is different. Therefore, the present invention proposes a new structure. Because there will be situations where a negative voltage is applied to P and a positive voltage is applied to N in the circuit, the BV of these two situations needs to be consistent.

[0054] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A process method for a high voltage diode structure, characterized in that: The process steps include: Providing a semiconductor substrate of a first conductivity type, and forming a buried layer of a second conductivity type on the semiconductor substrate; forming an epitaxial layer of the first conductivity type on the semiconductor substrate; Performing ion implantation to form a second conductive type implantation region in the epitaxial layer; the second conductive type implantation region is divided into two independent left and right parts; forming a shallow trench isolation structure on the surface of the epitaxial layer; Performing deep trench etching and filling processes to form a deep trench isolation structure; Photolithography and etching are performed to open an implantation window to form a first conductive type implantation region and a well region.

2. The process of the high voltage diode structure according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate, a germanium silicon substrate, or a wide bandgap semiconductor substrate of gallium nitride or silicon carbide.

3. The process of the high voltage diode structure according to claim 1, characterized in that: The buried layer is formed by ion implantation process.

4. The process of the high voltage diode structure according to claim 1, characterized in that: The epitaxial layer is formed by a deposition process.

5. The process of the high voltage diode structure according to claim 1, characterized in that: The second conductive type injection region is divided into two independent injection regions connected to the left and right, which are respectively located next to the deep trench isolation structure formed subsequently, and one side of each is connected to the deep trench isolation structure; the depth of the second conductive type injection region is enough to penetrate the entire epitaxial layer, and the bottom is in contact with the buried layer.

6. The process of the high voltage diode structure according to claim 1, characterized in that: The shallow trench isolation structure is formed by utilizing active area photolithography, etching and filling processes; the shallow trench isolation structure is filled with insulating medium.

7. The process of high voltage diode structure according to claim 1, characterized in that: The deep trench has a depth-to-width ratio greater than 20; the deep trench is located outside the independent second conductivity type injection area and surrounds the second conductivity type injection area; the deep trench is filled with polysilicon to form a deep trench isolation structure; the polysilicon in the deep trench is in a floating state, and the bottom of the deep trench exceeds the depth of the buried layer.

8. The process of the high voltage diode structure according to claim 1, characterized in that: The first conductive type injection region and the well region, the first conductive type injection region is located in the epitaxial layer close to the second conductive type injection region on the right side, and the well region is located in the first conductive type injection region.

9. The process of high voltage diode structure according to claim 1, characterized in that: The process steps also include performing a selective source and drain ion implantation process to form a heavily doped region of the first conductivity type and a heavily doped region of the second conductivity type.

10. The process of the high voltage diode structure according to any one of claims 1 to 9, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; during ion implantation, the implanted impurity of the P type is boron, and the implanted impurity of the N type is phosphorus or arsenic; Alternatively, the first conductivity type may be changed to N type and the second conductivity type may be changed to P type.

11. A high voltage diode structure, characterized in that: An epitaxial layer of the first conductivity type is provided on a semiconductor substrate of the first conductivity type; a deep trench isolation structure is provided in the epitaxial layer, and the high-voltage diode is formed in an isolation region formed by the deep trench isolation structure; In the isolation region formed by the deep trench isolation structure, a buried layer is provided in the semiconductor substrate; The independent second conductive type injection region abuts against the deep trench isolation structures on both sides in the isolation region, and the first conductive type injection region abuts against the second conductive type injection region on the right side; the first conductive type injection region also has a well region, and the well region also has a heavily doped region of the first conductive type; The surface of the epitaxial layer has a shallow trench isolation structure.

12. The high voltage diode structure according to claim 11, characterized in that: The depth of the second conductive type implantation region is equal to the thickness of the epitaxial layer, and the bottom of the second conductive type implantation region is in contact with the buried layer.

13. The high voltage diode structure according to claim 11, wherein: The deep trench isolation structure comprises a deep trench and polysilicon filled in the deep trench, and the polysilicon is in a floating state.

14. The high voltage diode structure according to claim 11, wherein: The epitaxial layer surface also has a heavily doped region of the first conductivity type and a heavily doped region of the second conductivity type.

15. The high voltage diode structure according to any one of claims 11 to 14, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; during ion implantation, the implanted impurity of the P type is boron, and the implanted impurity of the N type is phosphorus or arsenic; Alternatively, the first conductivity type may be changed to N type and the second conductivity type may be changed to P type.

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