Dielectric structure, semiconductor device structure and preparation method thereof
By doping Al on the surface of the SiC substrate of the SiC MOS device and forming a SiAlO dielectric layer, the interface defects caused by the traditional SiO2 gate dielectric layer are solved, and the channel mobility and forward conduction capability of the SiC MOS device are improved.
Patent Information
- Application Number
- CN202311685105.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-08
- Publication Date
- 2025-06-10
AI Technical Summary
During the preparation of SiC MOS devices, the lower quality gate dielectric layer limits the performance of SiC MOS devices, especially because there are many interface defects at the interface between the SiO2 gate dielectric layer and SiC, resulting in a decrease in channel mobility.
By doping Al on the first surface of the SiC substrate, an Al-containing SiC layer is formed, and the layer is oxidized by a thermal oxidation process, a dielectric layer including at least a SiAlO layer is formed to replace the conventional SiO2 gate dielectric layer.
This method reduces the interface state density at the SiC/SiO2 interface, improves the quality of the dielectric layer, and enhances the channel mobility and the forward conduction capability of the device.
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Figure CN120129262A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a dielectric structure, a semiconductor device structure and a method for manufacturing the same. Background Art
[0002] Due to its high breakdown strength, high electron drift velocity and high thermal conductivity, SiC material is suitable for high-power devices. As a typical representative of the third-generation semiconductors, SiC material has become an ideal material for manufacturing high-temperature, high-power, high-frequency and high-radiation-resistant devices with its excellent physical and chemical properties. Although SiC power MOSFETs have been commercialized, the research on its gate dielectrics is still of great significance. The gate dielectric is crucial in SiC MOS devices because it needs to maintain a high electric field and a low gate leakage current.
[0003] However, during the manufacturing process of SiC MOS devices, the relatively low-quality gate dielectric layer has greatly limited the performance of SiC MOS devices. For example, for the SiO 2 gate dielectric layer directly thermally oxidized on SiC, there are often inevitably many interface defects at the interface between it and SiC, resulting in a significant decrease in the channel mobility. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a dielectric structure, a semiconductor device structure and a method for manufacturing the same to improve the quality of the gate dielectric layer in SiC MOS devices.
[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a dielectric structure, characterized by including the following steps:
[0006] S1. Provide a SiC substrate, where the SiC substrate has a corresponding first surface and a second surface;
[0007] S2. Dope Al in at least a partial area of the first surface of the SiC substrate to form an Al-containing SiC layer;
[0008] S3. Through a thermal oxidation process, oxidize the Al-containing SiC layer to form a dielectric layer on the SiC substrate, and the dielectric layer at least includes a SiAlO layer.
[0009] As an optional embodiment, a groove recessed inward from the first surface is provided on the first surface of the SiC substrate, and in step S2, doping Al in at least a partial area of the first surface of the SiC substrate to form an Al-containing SiC layer is to dope Al on the side wall and the bottom surface of the groove to form an Al-containing SiC layer.
[0010] As an alternative embodiment, the method of doping Al on the first surface of the SiC substrate in step S2 is ion implantation.
[0011] As an alternative embodiment, before step S3, it further includes:
[0012] S21. Form an AlN layer or a SiCAlN layer on the Al-containing SiC layer.
[0013] As an alternative embodiment, in step S3, through a thermal oxidation process, the Al-containing SiC layer and the AlN layer or SiCAlN are simultaneously oxidized to form a dielectric layer on the SiC substrate, and the dielectric layer includes a SiAlO layer and an AlO X N layer or a SiAlO X N layer.
[0014] As an alternative embodiment, the method of doping Al on the first surface of the SiC substrate in step S2 is to form an Al diffusion layer on the first surface of the SiC substrate, and Al in the Al diffusion layer diffuses into the SiC substrate.
[0015] As an alternative embodiment, the material of the Al diffusion layer includes an Al alloy or an AlN alloy.
[0016] As an alternative embodiment, the material of the Al diffusion layer includes SiCAlN.
[0017] According to another aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor device structure, characterized in that
[0018] It includes the method for manufacturing the dielectric structure described in any one of the above, and step S1 includes:
[0019] S101. Provide a SiC substrate of a first conductivity type, and the SiC substrate has a corresponding first surface and a second surface;
[0020] S102. Form a well region of a second conductivity type at both ends inside the first surface of the SiC substrate;
[0021] S103. Form a source region of a first conductivity type inside the first surface of the well region;
[0022] S104. Form a heavily doped drain region of a first conductivity type on the second surface of the SiC substrate,
[0023] After step S3, it further includes:
[0024] S301. Etch the dielectric layer in the non-gate region to expose the source region;
[0025] S302. Set a source electrode in the source region, set a drain electrode in the drain region, and set a gate electrode on the dielectric layer.
[0026] As an optional embodiment, the method for forming the well region, the source region, and the drain region is ion implantation or secondary epitaxy after selective etching.
[0027] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure, characterized in that
[0028] including the method for manufacturing the dielectric structure described in any one of the above, step S1 includes:
[0029] S105. Provide a SiC substrate of a first conductivity type, the SiC substrate having a corresponding first surface and a second surface;
[0030] S106. Etch a trench in the first surface of the SiC substrate,
[0031] In step S2, Al is doped on the sidewalls and the bottom surface of the trench to form an Al-containing SiC layer,
[0032] After step S3, it further includes:
[0033] S303. Form a well region of a second conductivity type in the first surface of the SiC substrate;
[0034] S304. Form a source region of a first conductivity type in the first surface of the well region close to the dielectric layer;
[0035] S305. Form a heavily doped drain region of a first conductivity type on the second surface of the SiC substrate;
[0036] S306. Set a gate electrode in the groove of the dielectric layer, set a source electrode in the source region, and set a drain electrode in the drain region.
[0037] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a dielectric structure, characterized in that
[0038] including the dielectric structure obtained by manufacturing the dielectric structure described in any one of the above, including a SiC substrate and a dielectric layer stacked, and the dielectric layer at least includes a SiAlO layer.
[0039] As an optional embodiment, the dielectric layer further includes an AlO X N layer or a SiAlO X N layer on the side away from the SiC substrate of the SiAlO layer.
[0040] According to another aspect of the present application, an embodiment of the present application provides a semiconductor device structure, characterized in that it includes a semiconductor device structure obtained by using the preparation method of the above-mentioned semiconductor device structure, and the semiconductor device structure includes:
[0041] A SiC substrate of the first conduction type, the SiC substrate having a corresponding first surface and a second surface;
[0042] A well region of the second conduction type located at both ends inside the first surface of the SiC substrate;
[0043] A source region of the first conduction type located inside the first surface of the well region and a source electrode in contact with the source region;
[0044] A heavily doped drain region of the first conduction type located on the second surface of the SiC substrate and a drain electrode in contact with the drain region;
[0045] A dielectric layer and a gate located in the gate region on the first surface of the SiC substrate, the dielectric layer including at least a SiAlO layer.
[0046] According to another aspect of the present application, an embodiment of the present application provides a semiconductor device structure, characterized in that it includes a semiconductor device structure obtained by using the preparation method of the above-mentioned semiconductor device structure, and the semiconductor device structure includes:
[0047] A SiC substrate of the first conduction type, the SiC substrate having a corresponding first surface and a second surface, and the first surface of the SiC substrate having grooves;
[0048] A well region of the second conduction type located inside the first surface of the SiC substrate;
[0049] A source region of the first conduction type located inside the first surface of the well region close to the groove side and a source electrode in contact with the source region;
[0050] A heavily doped drain region of the first conduction type located on the second surface of the SiC substrate and a drain electrode in contact with the drain region;
[0051] A dielectric layer located on the sidewall and bottom surface of the groove and a gate in the dielectric layer groove, the dielectric layer including at least a SiAlO layer.
[0052] The present disclosure provides a method for preparing a dielectric layer. Al is doped on the surface of a SiC substrate to form an Al-containing SiC layer, and then the Al-containing SiC layer is oxidized to form a dielectric layer including at least a SiAlO layer. By doping Al on the surface of the SiC substrate, on the one hand, it can reduce the thermal oxidation temperature required for the SiC material to be oxidized into SiO 2 material, thereby reducing the SiC / SiO2 At the interface, there are high - density interface states, which improve the quality of the dielectric layer. On the other hand, Al in SiO 2 substitutes the original Si, which can form a more stable structure and further improve the quality of the dielectric layer. The dielectric layer provided by the present disclosure reduces the large number of interface states existing between the SiO 2 grown by the traditional direct thermal oxidation method and SiC, improves the channel mobility, and improves the forward conduction ability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] Figure 1 The flowchart of the preparation method of the dielectric structure provided by an embodiment of the present disclosure is shown.
[0054] Figures 2 to 4 As shown Figure 1 The schematic diagram of the intermediate structure corresponding to the shown process is shown.
[0055] Figure 5 The schematic diagram of the structure of the dielectric structure provided by an embodiment of the present disclosure is shown.
[0056] Figure 6 The schematic diagram of the structure of the dielectric structure before oxidation provided by an embodiment of the present disclosure is shown.
[0057] Figure 7 The schematic diagram of the structure of the dielectric structure after oxidation provided by an embodiment of the present disclosure is shown.
[0058] Figure 8 The schematic diagram of the structure of the dielectric structure before oxidation provided by an embodiment of the present disclosure is shown.
[0059] Figure 9 The flowchart of the preparation method of the semiconductor device structure provided by an embodiment of the present disclosure is shown.
[0060] Figures 10 to 16 As shown Figure 9 The schematic diagram of the intermediate structure corresponding to the shown process is shown.
[0061] Figure 17 The flowchart of the preparation method of the semiconductor device structure provided by an embodiment of the present disclosure is shown.
[0062] Figures 18 to 25 As shown Figure 17 The schematic diagram of the intermediate structure corresponding to the shown process is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0063] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.
[0064] To reduce the large number of interface states existing between SiO grown by the traditional direct thermal oxidation method 2 and SiC, improve the channel mobility, and improve the forward conduction ability of the device, the present disclosure provides a dielectric structure, a semiconductor device structure, and a preparation method thereof. Al is doped on the surface of the SiC substrate to form an Al-containing SiC layer, and then the Al-containing SiC layer is oxidized to form a dielectric layer including at least a SiAlO layer. By doping Al on the surface of the SiC substrate in the present disclosure, on the one hand, the thermal oxidation temperature required for oxidizing the SiC material into SiO 2 material can be reduced, thereby reducing the relatively high-density interface states existing at the interface of SiC / SiO 2 and improving the quality of the dielectric layer; on the other hand, Al in SiO 2 replaces the original Si, which can form a more stable structure and further improve the quality of the dielectric layer. The dielectric layer provided by the present disclosure reduces the large number of interface states existing between SiO grown by the traditional direct thermal oxidation method 2 and SiC, improves the channel mobility, and improves the forward conduction ability of the device.
[0065] Next, a dielectric structure, a semiconductor device structure, and a preparation method thereof mentioned in the present disclosure will be further illustrated by examples. Figures 1 to 25 The following further illustrates a dielectric structure, a semiconductor device structure, and a preparation method thereof mentioned in the present disclosure.
[0066] Figure 1 The flowchart of the preparation method of the dielectric structure provided by an embodiment of the present disclosure is shown; Figures 2 to 4 Shown as Figure 1 The corresponding intermediate structure schematic diagram of the shown process.
[0067] Step S1: Provide a SiC substrate, and the SiC substrate has a corresponding first surface and a second surface.
[0068] Step S2: Dope Al in at least a part of the first surface of the SiC substrate to form an Al-containing SiC layer.
[0069] Step S3: Through a thermal oxidation process, oxidize the Al-containing SiC layer to form a dielectric layer on the SiC substrate, and the dielectric layer includes at least a SiAlO layer.
[0070] Specifically, as Figure 2As shown, a SiC substrate 10 is provided. The SiC substrate 10 has corresponding first and second surfaces, as Figure 3 shown, Al is doped in at least a partial region of the first surface of the SiC substrate 10 to form an Al-containing SiC layer 20, and the doped Al ion concentration is greater than 1E15 / cm 3 , as Figure 4 shown, through a thermal oxidation process, the Al-containing SiC layer 20 is oxidized to form a dielectric layer 100 on the SiC substrate 10. The dielectric layer 100 at least includes a SiAlO layer 21.
[0071] Generally, due to the high chemical stability of SiC (high atomic density and short chemical bond length), its thermal oxidation temperature (1200 - 1400 °C) is very high. The relatively high thermal oxidation temperature brings process-introduced defects, including problems such as deep-level traps and surface quality deterioration, thus resulting in a relatively high density of interface states at the SiC / SiO 2 interface. In this embodiment, sufficient Al is ion-doped on the surface of the SiC substrate 10, and the doped Al ion concentration is greater than 1E15 / cm 3 , which can reduce the thermal oxidation temperature required for the oxidation of SiC material into SiO 2 material, thereby reducing the relatively high density of interface states existing at the SiC / SiO 2 interface, improving the quality of the dielectric layer 100. At the same time, the Al in SiO 2 replaces the original Si, which can form a more stable structure and further improve the quality of the dielectric layer 100. The dielectric layer 100 prepared in this embodiment reduces the large number of interface states existing between the SiO 2 grown by the traditional direct thermal oxidation method and SiC, improves the channel mobility, and improves the forward conduction ability of the device.
[0072] In one embodiment, Figure 5 shown is a schematic structural diagram of a dielectric structure provided by an embodiment of the present disclosure. As Figure 5 shown, a groove 101 recessed inward from the first surface is provided on the first surface of the SiC substrate 10. In step S2, Al is doped in at least a partial region of the first surface of the SiC substrate 10 to form an Al-containing SiC layer 20 by doping Al on the sidewalls and bottom surface of the groove 101. Then, through a thermal oxidation process, a SiAlO layer 21 on the sidewalls and bottom surface of the groove 101 of the SiC substrate 10 is formed. The dielectric structure provided in this embodiment can be used to form a trench-type MOS device.
[0073] In one embodiment, Figure 6 shown is a schematic structural diagram of the dielectric structure before oxidation provided by an embodiment of the present disclosure. Figure 7The following is a schematic diagram of the structure after oxidation of the dielectric structure provided by an embodiment of the present disclosure. In step S2, the method of doping Al on the first surface of the SiC substrate 10 is ion implantation. As Figure 6 shown, after ion implantation of Al on the first surface of the SiC substrate 10, before step S3, it further includes: step S21: forming an AlN layer 30 or a SiCAlN layer 40 on the Al-containing SiC layer 20. In step S3, through a thermal oxidation process, the Al-containing SiC layer 20 and the AlN layer 30 or the SiCAlN layer 40 are simultaneously oxidized to form as Figure 7 shown, a dielectric layer 100 on the SiC substrate 10, and the dielectric layer 100 includes a SiAlO layer 21 and an AlO X N layer 31 or a SiAlO X N layer 41. By forming an AlN layer 30 or a SiCAlN layer 40 on the Al-containing SiC layer 20, the SiAlO layer 21 after oxidation of the Al-containing SiC layer 20 will contain nitrogen diffused from the AlN layer 30 or the SiCAlN layer 40, and the nitrogen background concentration in the SiAlO layer 21 can further improve the interface characteristics between the SiAlO layer 21 and the SiC substrate 10, and further reduce the higher density of interface states existing at the 2 SiC / SiO interface, thereby improving the quality of the dielectric layer 100.
[0074] In one embodiment, Figure 8 the following is a schematic diagram of the structure of the dielectric structure before oxidation provided by an embodiment of the present disclosure. As Figure 8 shown, in step S2, the method of doping Al on the first surface of the SiC substrate 10 is to form an Al diffusion layer 11 on the first surface of the SiC substrate 10. The material of the Al diffusion layer 11 includes an Al alloy or an AlN alloy. Further, the material of the Al diffusion layer 11 includes SiCAlN. The Al in the Al diffusion layer 11 diffuses into the SiC substrate 10. The method of doping Al on the first surface of the SiC substrate 10 by diffusion can reduce the damage to the lattice of the SiC substrate 10. The Al diffusion layer 11 in this embodiment can be etched away or retained and oxidized simultaneously with the Al-containing SiC layer 20. The present disclosure does not make specific limitations.
[0075] According to another aspect of the present disclosure, the present disclosure also provides a method for manufacturing a semiconductor device structure, Figure 9 the following is a flowchart of the method for manufacturing a semiconductor device structure provided by an embodiment of the present disclosure; Figures 10 to 16 shown as Figure 9 the intermediate structure schematic diagram corresponding to the shown process.
[0076] Step S101: Provide a SiC substrate of a first conductivity type, and the SiC substrate has a corresponding first surface and a second surface.
[0077] Step S102: Form a well region of the second conductivity type at both ends inside the first surface of the SiC substrate.
[0078] Step S103: Form a source region of the first conductivity type inside the first surface of the well region.
[0079] Step S104: Form a heavily doped drain region of the first conductivity type on the second surface of the SiC substrate.
[0080] Step S2: Dope Al on the first surface of the SiC substrate to form an Al-containing SiC layer.
[0081] Step S3: Oxidize the Al-containing SiC layer through a thermal oxidation process to form a dielectric layer on the SiC substrate, and the dielectric layer at least includes a SiAlO layer.
[0082] Step S301: Etch the dielectric layer in the non-gate region to expose the source region.
[0083] Step S302: Set a source electrode in the source region, set a drain electrode in the drain region, and set a gate on the dielectric layer.
[0084] Specifically, as Figure 10 shown, provide a SiC substrate 10 of the first conductivity type, the SiC substrate 10 has corresponding first and second surfaces, as Figure 11 shown, form a well region 51 of the second conductivity type at both ends inside the first surface of the SiC substrate 10, as Figure 12 shown, form a source region 52 of the first conductivity type inside the first surface of the well region 51 and form a heavily doped drain region 53 of the first conductivity type on the second surface of the SiC substrate 10, as Figure 13 shown, dope Al on the first surface of the SiC substrate 10 to form an Al-containing SiC layer 20, and oxidize the Al-containing SiC layer 20 through a thermal oxidation process, as Figure 14 shown, form a dielectric layer 100 on the SiC substrate 10, and the dielectric layer 100 at least includes a SiAlO layer 21, as Figure 15 shown, etch the dielectric layer 100 in the non-gate region to expose the source region 52, set a source electrode 61 in the source region 52, set a drain electrode 62 in the drain region 53, and set a gate 63 on the dielectric layer 100 to form a semiconductor device structure as Figure 16 shown. The methods for forming the well region 51, the source region 52, and the drain region 53 are ion implantation or secondary epitaxy after selective etching, and the present disclosure does not make specific limitations. When the semiconductor device structure prepared by the method provided in this embodiment is used for a SiC MOS device, the leakage current of the SiC MOS gate dielectric layer can be reduced, the interface state density between SiC and SiO 2 can be reduced, the breakdown voltage of the SiCMOS can be increased, and the reliability of the SiC MOS in high-temperature and high-power applications can be improved.
[0085] According to another aspect of the present disclosure, the present disclosure further provides a method for manufacturing a semiconductor device structure. Figure 17 The flowchart of the method for manufacturing a semiconductor device structure provided by an embodiment of the present disclosure is shown; Figures 18 to 25 As shown Figure 17 The schematic diagram of the intermediate structure corresponding to the shown process.
[0086] Step S105: Provide a SiC substrate of a first conductivity type, the SiC substrate having a corresponding first surface and a second surface.
[0087] Step S106: Etch trenches in the first surface of the SiC substrate.
[0088] Step S2: Dope Al on the sidewalls and bottom surface of the trenches to form an Al-containing SiC layer.
[0089] Step S3: Oxidize the Al-containing SiC layer through a thermal oxidation process to form a dielectric layer on the SiC substrate, the dielectric layer at least including a SiAlO layer.
[0090] Step S303: Form a well region of a second conductivity type in the first surface of the SiC substrate.
[0091] Step S304: Form a source region of a first conductivity type in the first surface of the well region close to the dielectric layer.
[0092] Step S305: Form a heavily doped drain region of a first conductivity type on the second surface of the SiC substrate.
[0093] Step S306: Set a gate in the groove of the dielectric layer, set a source electrode in the source region, and set a drain electrode in the drain region.
[0094] Specifically, as Figure 18 shown, provide a SiC substrate 10 of a first conductivity type, the SiC substrate 10 having a corresponding first surface and a second surface, etch trenches 101 in the first surface of the SiC substrate 10, the depth of the trenches 101 being less than the thickness of the SiC substrate 10, the cross-sectional shape of the trenches 101 including a rectangle (as Figure 18 shown), a V shape (as Figure 19 shown), or a trapezoid (as Figure 20 shown), the trenches 101 can be formed with a bottom rounded corner structure through secondary etching (as Figure 21 shown) to reduce the electric field strength at the bottom of the trenches 101, thereby increasing the breakdown voltage, as Figure 22 shown, dope Al on the sidewalls and bottom surface of the trenches 101 to form an Al-containing SiC layer 20, and oxidize the Al-containing SiC layer 20 through a thermal oxidation process, as Figure 23As shown, a dielectric layer 100 is formed on the SiC substrate 10. The dielectric layer 100 at least includes a SiAlO layer 21, such as Figure 24 As shown, a well region 51 of the second conductivity type is formed in the first surface of the SiC substrate 10. The thickness of the well region 51 is less than the depth of the trench 101. A source region 52 of the first conductivity type is formed in the first surface of the well region 51 close to the dielectric layer 100, and a heavily doped drain region 53 of the first conductivity type is formed on the second surface of the SiC substrate 10. Finally, a gate 63 is disposed in the groove of the dielectric layer 100, a source electrode 61 is disposed in the source region 52, and a drain electrode 62 is disposed in the drain region 53 to form a semiconductor device structure as shown in Figure 25 When the semiconductor device structure prepared by the method provided in this embodiment is used for a trench-type SiC MOS device, the leakage current of the SiC MOS gate dielectric layer can be reduced, the interface state density between SiC and SiO 2 can be reduced, the breakdown voltage of the SiCMOS can be increased, and the reliability of the SiC MOS in high-temperature and high-power applications can be improved.
[0095] According to another aspect of the present disclosure, the present disclosure further provides a dielectric structure, such as Figure 4 As shown, the dielectric structure is a dielectric structure obtained by the preparation method of the above dielectric structure, including a stacked SiC substrate 10 and a dielectric layer 100. The dielectric layer 100 at least includes a SiAlO layer 21. The Al ion concentration in the SiAlO layer 21 is greater than 1E15 / cm 3 . The Al in the SiAlO layer 21 can reduce the interface states at the interface between the SiC substrate 10 and the dielectric layer 100, and replace Si to form a more stable structure, thereby improving the quality of the dielectric layer 100.
[0096] In one embodiment, as shown in Figure 7 the dielectric layer 100 further includes an AlO X N layer 31 or a SiAlO X N layer 41 on the side of the SiAlO layer 21 away from the SiC substrate 10. The setting of the AlO X N layer 31 or the SiAlO X N layer 41 can increase the Al content in the SiAlO layer 21 while introducing a nitrogen background concentration, thereby reducing the interface states and improving the quality of the dielectric layer 100.
[0097] According to another aspect of the present disclosure, the present disclosure further provides a semiconductor device structure, such as Figure 16As shown, the semiconductor device structure includes: a SiC substrate 10 of a first conductivity type, the SiC substrate 10 having a corresponding first surface and a second surface; a well region 51 of a second conductivity type located inside both ends of the first surface of the SiC substrate 10; a source region 52 of a first conductivity type located inside the first surface of the well region 51 and a source electrode 61 in contact with the source region 52; a heavily doped drain region 53 of a first conductivity type located on the second surface of the SiC substrate 10 and a drain electrode 62 in contact with the drain region 53; a dielectric layer 100 and a gate electrode 63 located in the gate region on the first surface of the SiC substrate 10, the dielectric layer 100 including at least a SiAlO layer 21.
[0098] According to another aspect of the present disclosure, the present disclosure also provides a semiconductor device structure, as Figure 25 shown, the semiconductor device structure includes: a SiC substrate 10 of a first conductivity type, the SiC substrate 10 having a corresponding first surface and a second surface, and the first surface of the SiC substrate 10 having a trench 101; a well region 51 of a second conductivity type located inside the first surface of the SiC substrate 10; a source region 52 of a first conductivity type located inside the first surface of the well region 51 near the trench 101 and a source electrode 61 in contact with the source region 52; a heavily doped drain region 53 of a first conductivity type located on the second surface of the SiC substrate 10 and a drain electrode 62 in contact with the drain region 53; a dielectric layer 100 located on the sidewall and bottom surface of the trench 101 and a gate electrode 63 in a groove of the dielectric layer 100, the dielectric layer 100 including at least a SiAlO layer 21.
[0099] The present disclosure provides a method for preparing a dielectric layer. Al is doped on the surface of a SiC substrate to form a SiC layer containing Al, and then the SiC layer containing Al is oxidized to form a dielectric layer including at least a SiAlO layer. By doping Al on the surface of the SiC substrate, on the one hand, the thermal oxidation temperature required for oxidizing the SiC material into SiO 2 material can be reduced, thereby reducing the relatively high density of interface states existing at the interface of SiC / SiO 2 , and improving the quality of the dielectric layer; on the other hand, Al in SiO 2 replaces the original Si, which can form a more stable structure and further improve the quality of the dielectric layer. The dielectric layer provided by the present disclosure reduces the large number of interface states existing between the SiO 2 grown by the traditional direct thermal oxidation method and SiC, improves the channel mobility, and improves the forward conduction ability of the device.
[0100] It should be understood that the term "including" and its variations used in this disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0101] The above are only the preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.
Claims
1. A method for preparing a dielectric structure, characterized in that, it comprises the following steps: S1. Provide a SiC substrate (10), and the SiC substrate (10) has a corresponding first surface and a second surface; S2. Dope Al in at least a partial region of the first surface of the SiC substrate (10) to form an Al-containing SiC layer (20); S3. Through a thermal oxidation process, oxidize the Al-containing SiC layer (20) to form a dielectric layer (100) on the SiC substrate (10), and the dielectric layer (100) at least includes a SiAlO layer (21).
2. The method for preparing a dielectric structure according to claim 1, characterized in that, a groove (101) recessed inward from the first surface is provided on the first surface of the SiC substrate (10), and in step S2, doping Al in at least a partial region of the first surface of the SiC substrate (10) to form an Al-containing SiC layer (20) is to dope Al on the side wall and the bottom surface of the groove (101) to form an Al-containing SiC layer (20).
3. The method for preparing a dielectric structure according to claim 1, characterized in that, in step S2, the way of doping Al on the first surface of the SiC substrate (10) is ion implantation.
4. The method for preparing a dielectric structure according to claim 3, characterized in that, before step S3, it further includes: S21. Form an AlN layer (30) or a SiCAlN layer (40) on the Al-containing SiC layer (20).
5. The method for preparing a dielectric structure according to claim 4, characterized in that, In the step S3, through a thermal oxidation process, the SiC layer (20) containing Al and the AlN layer (30) or SiCAlN (40) are simultaneously oxidized to form the dielectric layer (100) on the SiC substrate (10), and the dielectric layer (100) includes a SiAlO layer (21) and an AlO X N layer (31) or SiAlO X N layer (41).
6. The method for preparing a dielectric structure according to claim 1, characterized in that, in step S2, the way of doping Al on the first surface of the SiC substrate (10) is to form an Al diffusion layer (11) on the first surface of the SiC substrate (10), and Al in the Al diffusion layer (11) diffuses into the SiC substrate (10).
7. The method for preparing a dielectric structure according to claim 6, characterized in that, the material of the Al diffusion layer (11) includes an Al alloy or an AlN alloy.
8. The method for preparing a dielectric structure according to claim 6, characterized in that, the material of the Al diffusion layer (11) includes SiCAlN.
9. A method for preparing a semiconductor device structure, characterized in that, it includes the method for preparing a dielectric structure according to any one of claims 1-8, and step S1 includes: S101. Provide a SiC substrate (10) of a first conductivity type, and the SiC substrate (10) has a corresponding first surface and a second surface; S102. Form a well region (51) of a second conductivity type at both ends inside the first surface of the SiC substrate (10); S103. Form a source region (52) of a first conductivity type inside the first surface of the well region (51); S104. Form a heavily doped drain region (53) of a first conductivity type on the second surface of the SiC substrate (10), after step S3, it further includes: S301. Etch the dielectric layer (100) in the non-gate region to expose the source region (52). S302. Set a source electrode (61) in the source region (52), set a drain electrode (62) in the drain region (53), and set a gate electrode (63) on the dielectric layer (100).
10. The method for manufacturing the semiconductor device structure according to claim 9, characterized in that the method for forming the well region (51), the source region (52), and the drain region (53) is ion implantation or secondary epitaxy after selective etching.
11. A method for manufacturing a semiconductor device structure, characterized in that it includes the method for manufacturing the dielectric structure according to any one of claims 1-8, and step S1 includes: S105. Provide a SiC substrate (10) of a first conductivity type, and the SiC substrate (10) has a corresponding first surface and a second surface; S106. Etch a trench (101) on the first surface of the SiC substrate (10), in step S2, dope Al on the sidewalls and bottom surface of the trench (101) to form an Al-containing SiC layer (20), after step S3, it further includes: S303. Form a well region (51) of a second conductivity type in the first surface of the SiC substrate (10); S304. Form a source region (52) of a first conductivity type in the first surface of the well region (51) close to the dielectric layer (100); S305. Form a heavily doped drain region (53) of the first conductivity type on the second surface of the SiC substrate (10); S306. Set a gate electrode (63) in the groove of the dielectric layer (100), set a source electrode (61) in the source region (52), and set a drain electrode (62) in the drain region (53).
12. A dielectric structure, characterized in that it includes the dielectric structure obtained by the method for manufacturing the dielectric structure according to any one of claims 1-8, and includes a SiC substrate (10) and a dielectric layer (100) arranged in layers, and the dielectric layer (100) at least includes a SiAlO layer (21).
13. The dielectric structure according to claim 12, characterized in that The dielectric layer (100) further includes an AlO layer (31) or a SiAlO layer (41) on a side of the SiAlO layer (21) away from the SiC substrate (10). X N layer (31) or SiAlO X N layer (41).
14. A semiconductor device structure, characterized in that it includes the semiconductor device structure obtained by the method for manufacturing the semiconductor device structure according to claim 9, and the semiconductor device structure includes: a SiC substrate (10) of a first conductivity type, and the SiC substrate (10) has a corresponding first surface and a second surface; a well region (51) of a second conductivity type located at both ends in the first surface of the SiC substrate (10); a source region (52) of a first conductivity type located in the first surface of the well region (51) and a source electrode (61) in contact with the source region (52); a heavily doped drain region (53) of the first conductivity type located on the second surface of the SiC substrate (10) and a drain electrode (62) in contact with the drain region (53); a dielectric layer (100) and a gate electrode (63) in the gate region on the first surface of the SiC substrate (10), and the dielectric layer (100) at least includes a SiAlO layer (21).
15. A semiconductor device structure, characterized in that, it includes a semiconductor device structure obtained by using the preparation method of the semiconductor device structure described in claim 11, and the semiconductor device structure includes: a SiC substrate (10) of a first conductivity type, the SiC substrate (10) having a corresponding first surface and a second surface, and the first surface of the SiC substrate (10) having a trench (101); a well region (51) of a second conductivity type located in the first surface of the SiC substrate (10); a source region (52) of a first conductivity type located in the first surface of the well region (51) close to the trench (101) and a source electrode (61) in contact with the source region (52); a heavily doped drain region (53) of a first conductivity type located in the second surface of the SiC substrate (10) and a drain electrode (62) in contact with the drain region (53); a dielectric layer (100) located on the side wall and bottom surface of the trench (101) and a gate electrode (63) in a groove of the dielectric layer (100), and the dielectric layer (100) at least includes a SiAlO layer (21).