Semiconductor device and method of manufacturing the same
By patterning the N-type doped layer with electron beam micrograph and eliminating the annealing step, the problems of semiconductor layer damage and ohmic contact resistance increase in the existing AlGaN/GaN HEMT process are solved, and good component performance and low path resistance are achieved.
Patent Information
- Application Number
- CN202311793182.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-08
- Filing Date
- 2023-12-25
- Publication Date
- 2025-06-10
AI Technical Summary
In the existing AlGaN/GaN high-electron mobility transistor process, chemical liquid may damage the semiconductor layer below when removing the shielding layer, resulting in poor component performance. At the same time, the annealing step of the metal electrode will cause the surface of the ohmic contact metal to be rough and increase the resistance value.
The N-type doped layer is patterned by electron beam micro-film to form the source and drain N-type doped parts, eliminating the additional step of forming a silicon oxide or silicon nitride layer, and avoiding the etching liquid from damaging the semiconductor layer. At the same time, the annealing step of the source electrode and drain electrode is cancelled to avoid surface roughness.
It effectively avoids damage to the semiconductor layer by the etching liquid, ensures good component performance, and reduces path resistance and improves the overall performance of the semiconductor device.
Smart Images
Figure CN120129263A_ABST
Abstract
Description
[0001] Cross - reference to related applications
[0002] This invention claims the priority of Taiwan, China Patent Application No. 112147897 filed on December 8, 2023. For all purposes, the above - mentioned patent application is incorporated herein by reference as if fully set forth herein. Technical field
[0003] This invention relates to a semiconductor device and a method for manufacturing the same. Background art
[0004] Aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high - electron - mobility transistors (HEMTs) have become a popular research topic in the application of high - power electronic components due to advantages such as low on - resistance, high current density, and large breakdown voltage. The polarization effect of gallium nitride enables the formation of two - dimensional electron gases (2DEGs) near the hetero - interface in the AlGaN / GaN heterostructure, which allows AlGaN / GaN HEMTs to output large currents for operation.
[0005] With the development of mobile communication technologies such as 5G, the application of AlGaN / GaN HEMTs in microwave electronic components and power electronic components has received extensive attention. Existing AlGaN / GaN HEMT processes usually involve forming a silicon oxide layer or a silicon nitride layer on the surface of the semiconductor layer as a shield, then epitaxially growing gallium nitride components and removing the aforementioned shield with a chemical solution. However, the chemical solution may also damage the underlying semiconductor layer while removing the shield, thereby adversely affecting the performance of AlGaN / GaN HEMTs.
[0006] In addition, excellent ohmic contact is also one of the conditions for realizing high - performance AlGaN / GaN HEMTs, including low ohmic contact resistivity and good flatness of the ohmic contact metal surface. Existing AlGaN / GaN HEMT processes usually involve an annealing step for metal electrodes, resulting in a rough surface of the metal electrodes and making the ohmic contact metal have a high resistance value. Summary of the invention
[0007] In view of the above problems, this invention provides a semiconductor device and a method for manufacturing the same, which helps to solve the problem that the performance of existing AlGaN / GaN high - electron - mobility transistors cannot meet market demands.
[0008] A manufacturing method of a semiconductor device disclosed by an embodiment of the present invention includes the following steps: forming a semiconductor stack on a substrate; forming an N-type doped layer on the semiconductor stack; patterning the N-type doped layer by electron beam lithography to form a source N-type doped region and a drain N-type doped region; forming a source electrode on the source N-type doped region; forming a drain electrode on the drain N-type doped region; and forming a gate electrode on the semiconductor stack between the source N-type doped region and the drain N-type doped region.
[0009] A semiconductor device disclosed by an embodiment of the present invention includes a substrate, a semiconductor stack, a source N-type doped region, a drain N-type doped region, a source electrode, a drain electrode, and a gate electrode. The semiconductor stack is formed on the substrate. The source N-type doped region is formed on the semiconductor stack. The drain N-type doped region is formed on the semiconductor stack. The source electrode is formed on the source N-type doped region. The drain electrode is formed on the drain N-type doped region. The gate electrode is formed on the semiconductor stack, and the gate electrode is between the source N-type doped region and the drain N-type doped region. The gap width between the source N-type doped region and the drain N-type doped region is more than ten times the width of the gate electrode.
[0010] According to the disclosed semiconductor device and its manufacturing method of the present invention, the N-type doped layer is patterned by electron beam lithography to form a source N-type doped region and a drain N-type doped region. In this way, compared with the existing manufacturing method, there is no need to additionally form a silicon oxide layer or a silicon nitride layer between the N-type doped layer and the semiconductor stack as a shield in the epitaxial process of forming the N-type doped layer, so that the subsequent step of removing the silicon oxide layer or the silicon nitride layer with a chemical solution is not required. Thereby, it is beneficial to avoid the etching solution from damaging the semiconductor stack, and further ensure that the semiconductor device has good device performance. The patterning by electron beam lithography can shorten the gap width between the source N-type doped region and the drain N-type doped region, which is beneficial to reducing the path resistance from the source electrode through the semiconductor layer (such as the semiconductor stack and the N-type doped layer) to the drain electrode.
[0011] In addition, compared with the existing manufacturing method that requires an annealing step for the source electrode and the drain electrode, the present embodiment provides the source N-type doped region and the drain N-type doped region in contact with the semiconductor stack, which is beneficial to omitting the annealing step for the source electrode and the drain electrode, and further avoiding the surface roughness of the source electrode and the drain electrode caused by annealing.
[0012] The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the principle of the present invention, and provide a further explanation of the patent application scope of the present invention. Description of the Drawings
[0013] Figure 1Schematic diagram of a semiconductor device according to Embodiment 1 of the present invention;
[0014] Figures 2 to 10 For manufacturing Figure 1 Flow schematic diagram of the semiconductor device;
[0015] Figure 11 Schematic diagram of a semiconductor device according to Embodiment 2 of the present invention;
[0016] Figure 12 For Figure 11 Cross-sectional schematic diagram of the semiconductor device along line 12-12;
[0017] Figure 13 Cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention;
[0018] Figure 14 Cross-sectional schematic diagram of a semiconductor device according to yet another embodiment of the present invention.
[0019] Wherein, reference numerals:
[0020] 1A, 1B: Semiconductor device
[0021] 10: Substrate
[0022] 20: Semiconductor stack
[0023] 201: Source trench
[0024] 202: Drain trench
[0025] 210: Buffer layer
[0026] 220: Channel layer
[0027] 221: Two-dimensional electron gas
[0028] 230: Barrier layer
[0029] 240: Cap layer
[0030] 30: N-type doped layer
[0031] 31, 31B: Source N-type doped region
[0032] 310, 310B: Leg
[0033] 311: Head
[0034] 32, 32B: Drain N-type doped region
[0035] 320, 320B: Leg
[0036] 321: Head
[0037] 41: Source electrode
[0038] 42: Drain electrode
[0039] 50: Gate electrode
[0040] 60: Protective layer
[0041] 610: First opening
[0042] 620: Second opening
[0043] 630: Third opening
[0044] A1, A2: Central axis
[0045] D: Stacking direction
[0046] d: Gap width
[0047] W: Width. Detailed implementation manners
[0048] In the following implementation manners, the detailed features and advantages of the present invention are described in detail. The content is sufficient for those of ordinary skill in the art to understand the technical content of the present invention and implement it accordingly. And according to the content disclosed in this specification, the scope of the patent application and the drawings, those of ordinary skill in the art can easily understand the related purposes and advantages of the present invention. The following embodiments further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.
[0049] Please refer to Figure 1 , which is a schematic diagram of a semiconductor device according to Embodiment 1 of the present invention. In this embodiment, the semiconductor device 1A includes a substrate 10, a semiconductor stack 20, a source N-type doping region 31, a drain N-type doping region 32, a source electrode 41, a drain electrode 42, and a gate electrode 50.
[0050] The substrate 10 may include silicon, sapphire, other suitable crystalline materials, or any combination of the foregoing. In some embodiments where the semiconductor stack 20 includes III-V compounds, the substrate 10 may be a semiconductor wafer.
[0051] A semiconductor stack 20 is formed on a substrate 10. In this embodiment, the semiconductor stack 20 may include a buffer layer 210, a channel layer 220, a barrier layer 230, and a cap layer 240. Further, the buffer layer 210, the channel layer 220, the barrier layer 230, and the cap layer 240 are sequentially stacked on the substrate 10 along the stacking direction D. More specifically, the buffer layer 210 is formed on the substrate 10. The channel layer 220 is formed on the buffer layer 210. The barrier layer 230 is formed on the channel layer 220, and the channel layer 220 contacts the barrier layer 230 at the heterointerface. The cap layer 240 is formed on the barrier layer 230. The channel layer 220 may have a two-dimensional electron gas 221 adjacent to the barrier layer 230.
[0052] In this embodiment, the semiconductor device 1A may be a high electron mobility transistor (HEMT). Further, the semiconductor device 1A may be a gallium nitride heterostructure field effect transistor. More specifically, the channel layer 220 and the cap layer 240 may include gallium nitride (GaN), and the barrier layer 230 may include at least one of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and indium aluminum nitride (InAlN).
[0053] A source N-type doped region 31 and a drain N-type doped region 32 are formed on the semiconductor stack 20. Specifically, the source N-type doped region 31 may be disposed corresponding to the source region of the semiconductor device 1A, and the drain N-type doped region 32 may be disposed corresponding to the drain region of the semiconductor device 1A. Further, both the source N-type doped region 31 and the drain N-type doped region 32 may be N-type gallium nitride doped layers. More specifically, the doping concentration of the N-type gallium nitride doped layer may be 1×10 19 Above. In this embodiment, the source N-type doped region 31 includes a single leg 310, and the leg 310 extends from the cap layer 240 to the channel layer 220. The leg 310 may not penetrate the channel layer 220 and may penetrate the two-dimensional electron gas 221. Further, in this embodiment, the drain N-type doped region 32 includes a single leg 320, and the leg 320 extends from the cap layer 240 to the channel layer 220. The leg 320 may not penetrate the channel layer 220 and may penetrate the two-dimensional electron gas 221.
[0054] A source electrode 41 is formed on the source N-type doped region 31, and a drain electrode 42 is formed on the drain N-type doped region 32. Specifically, both the source electrode 41 and the drain electrode 42 may be ohmic contact metals. Further, both the source electrode 41 and the drain electrode 42 may include titanium, aluminum, nickel, gold, other suitable metal materials, or any combination of the foregoing. In some embodiments, the source electrode 41 and / or the drain electrode 42 may have a stacked structure including multiple metal layers.
[0055] The gate electrode 50 is formed on the semiconductor stack 20, and the gate electrode 50 is interposed between the source N-type doped region 31 and the drain N-type doped region 32 in a lateral direction perpendicular to the stacking direction D. During the use of the semiconductor device 1A, the gate electrode 50 is selectively biased to generate an electric field, which can affect the continuity of the two-dimensional electron gas 221 from the source N-type doped region 31 to the drain N-type doped region 32. For example, when the gate electrode 50 is applied with a bias voltage less than the threshold voltage, the gate electrode 50 can generate an electric field to turn off the continuity of the two-dimensional electron gas 221.
[0056] In this embodiment, the source N-type doped region 31 further includes a head 311 connected to the foot 310, and the head 311 is biased toward the gate electrode 50 with respect to the central axis A1 of the foot 310. As Figure 1 shown, a relatively large volume of the head 311 is located in the left half of the source N-type doped region 31. In addition, the drain N-type doped region 32 further includes a head 321 connected to the foot 320, and the head 321 is biased toward the gate electrode 50 with respect to the central axis A2 of the foot 320. As Figure 1 shown, a relatively large volume of the head 321 is located in the right half of the drain N-type doped region 32.
[0057] In this embodiment, the semiconductor device 1A further includes a protective layer 60 formed on the semiconductor stack 20. The protective layer 60 covers the source N-type doped region 31 and the drain N-type doped region 32, and the source electrode 41, the drain electrode 42, and the gate electrode 50 protrude from the protective layer 60. The protective layer 60 can be silicon oxide or silicon nitride.
[0058] In this embodiment, the gap width d between the source N-type doped region 31 and the drain N-type doped region 32 is more than ten times the width W of the gate electrode 50. As Figure 1 shown, the gap width d between the head 311 of the source N-type doped region 31 and the head 321 of the drain N-type doped region 32 can be from 100.0 nm to 200.0 nm, and the width W of the gate electrode 50 (which can also be referred to as the gate length) can be from 10.0 nm to 20.0 nm.
[0059] The manufacturing method of the semiconductor device 1A will be described below. Figures 2 to 10 For manufacturing Figure 1 is a schematic flow chart of the process of manufacturing the semiconductor device. As Figure 2 shown, a semiconductor stack 20 is formed on the substrate 10. The semiconductor stack 20 includes a buffer layer 210, a channel layer 220, a barrier layer 230, and a cap layer 240 stacked in sequence. In this embodiment, the semiconductor stack 20 can be grown on the substrate 10 by an epitaxial process. The barrier layer 230 can be a single aluminum gallium nitride layer or a double-layer structure composed of an aluminum gallium nitride layer and an aluminum nitride layer.
[0060] Next, an N-type doped layer 30 is formed on the semiconductor stack 20. As Figure 3 shown, a source trench 201 and a drain trench 202 are formed within the semiconductor stack 20. Both the source trench 201 and the drain trench 202 penetrate through the barrier layer 230 and the cap layer 240, and do not penetrate through the channel layer 220. As Figure 4 shown, an N-type doped layer 30 is formed within the source trench 201, within the drain trench 202, and on the cap layer 240. The N-type doped layer 30 can be an N-type gallium nitride doped layer. In this embodiment, a part of the semiconductor stack 20 can be removed through a dry etching process to form the source trench 201 and the drain trench 202, and the N-type doped layer 30 can be grown through an epitaxial process. The N-type doped layer 30 can be in direct contact with the cap layer 240 of the semiconductor stack 20.
[0061] As Figure 5 shown, the N-type doped layer 30 is patterned by electron beam lithography to form a source N-type doped region 31 and a drain N-type doped region 32. Further, a part of the N-type doped layer 30 corresponding to the region between the source region and the drain region is removed by electron beam, thereby forming the source N-type doped region 31 and the drain N-type doped region 32. Both the source N-type doped region 31 and the drain N-type doped region 32 can be in direct contact with the cap layer 240 of the semiconductor stack 20.
[0062] As Figure 6 shown, a protective layer 60 is formed on the source N-type doped region 31, the drain N-type doped region 32, and the semiconductor stack 20. In this embodiment, the protective layer 60 can be formed on the source N-type doped region 31, the drain N-type doped region 32, and the cap layer 240 of the semiconductor stack 20 through atomic layer deposition (ALD). The thickness scale of the protective layer 60 can be several tens of nanometers.
[0063] As Figure 7 and Figure 8 shown, a source electrode 41 is formed on the source N-type doped region 31, and a drain electrode 42 is formed on the drain N-type doped region 32. Further, referring to Figure 7 , a first opening 610 and a second opening 620 are formed within the protective layer 60. The first opening 610 exposes the source N-type doped region 31, and the second opening 620 exposes the drain N-type doped region 32. Next, referring to Figure 8, a source electrode 41 located within the first opening 610 is formed on the source N-type doping region 31, and a drain electrode 42 located within the second opening 620 is formed on the drain N-type doping region 32. The source electrode 41 and the drain electrode 42 may protrude from the protective layer 60 or be flush with the top surface of the protective layer 60. In this embodiment, a dry etching process may be used to remove a portion of the protective layer 60 to form the first opening 610 and the second opening 620, and the source electrode 41 and the drain electrode 42 may be formed by sputtering, physical vapor deposition (PVD), or chemical vapor deposition (CVD).
[0064] As Figure 9 and Figure 10 shown, a gate electrode 50 is formed on the semiconductor stack 20 between the source N-type doping region 31 and the drain N-type doping region 32. Further, referring to Figure 9 , a third opening 630 exposing the cap layer 240 of the semiconductor stack 20 may be formed within the protective layer 60 by atomic layer etching (ALE). The width dimension of the third opening 630 may be several tens of nanometers. Then, referring to Figure 10 , the gate electrode 50 is formed within the third opening 630.
[0065] After the gate electrode 50 is formed, the protective layer 60 may be selectively thinned to completely expose the source electrode 41 and the drain electrode 42.
[0066] According to this embodiment, the N-type doping layer 30 is patterned by electron beam lithography to form the source N-type doping region 31 and the drain N-type doping region 32. In this way, compared with the existing manufacturing method, an additional silicon oxide layer or silicon nitride layer does not need to be formed between the N-type doping layer 30 and the semiconductor stack 20 as a shield in the epitaxial process for forming the N-type doping layer 30, and thus the subsequent step of removing the silicon oxide layer or silicon nitride layer with a chemical solution is not required. Thereby, it is beneficial to avoid the etching solution from damaging the semiconductor stack 20, and further ensure that the semiconductor device 1A has good device performance. In addition, the patterning by electron beam lithography can shorten the gap width d between the source N-type doping region 31 and the drain N-type doping region 32, which is beneficial to reducing the path resistance from the source electrode 41 through the semiconductor layer (such as through the channel layer 220 and the N-type doping layer 30) to the drain electrode 42.
[0067] According to this embodiment, using atomic layer deposition to form the protective layer 60 is beneficial to obtaining a protective layer 60 with a thin thickness and low parasitic capacitance. Using atomic layer etching to form the gate electrode 50 is beneficial to obtaining a gate electrode 50 with a high aspect ratio (such as above 30:1). In addition, using atomic layer etching is beneficial to forming a gate electrode 50 with a very small gate length, thereby improving the cutoff frequency of the semiconductor device 1A to meet the high-frequency application requirements.
[0068] In addition, compared with the existing manufacturing methods that require annealing steps for the source electrode and the drain electrode at a temperature of 800 °C or higher, the present embodiment provides the source N-type doping region 31 and the drain N-type doping region 32 of the contact channel layer 220, which helps to eliminate the annealing steps for the source electrode 41 and the drain electrode 42, thereby avoiding the surface roughness of the source electrode 41 and the drain electrode 42 caused by annealing.
[0069] In Figure 1 , the source N-type doping region 31 includes a single foot 310 and the drain N-type doping region 32 includes a single foot 320, but the present invention is not limited thereto. Please refer to Figure 11 , which is a schematic diagram of a semiconductor device according to Embodiment 2 of the present invention. In the present embodiment, the semiconductor device 1B includes a substrate 10, a semiconductor stack 20, a source N-type doping region 31B, a drain N-type doping region 32B, a source electrode 41, a drain electrode 42, and a gate electrode 50. The structure of the semiconductor device 1B is similar to that of the semiconductor device 1A in Figure 1 , so only the differences will be described below.
[0070] In the present embodiment, the source N-type doping region 31B includes a head 311 and a plurality of feet 310B, and the drain N-type doping region 32B includes a head 321 and a plurality of feet 320B. The feet 310B, 320B extend from the cap layer 240 of the semiconductor stack 20 to the channel layer 220. The feet 310B, 320B may not penetrate the channel layer 220 and may penetrate the two-dimensional electron gas 221. The plurality of feet 310B, 320B helps to increase the contact area between the source N-type doping region 31B and the drain N-type doping region 32B and the channel layer 220, thereby reducing the on-resistance. In some embodiments, the plurality of feet 310B, 320B also helps to increase the contact area between the source N-type doping region 31B and the barrier layer 230 or the cap layer 240, and the contact area between the drain N-type doping region 32B and the barrier layer 230 or the cap layer 240.
[0071] As Figure 11 shows, the head 311 of the source N-type doping region 31B is biased toward the gate electrode 50 with respect to the central axis A1 of the whole of these feet 310B. In addition, the head 321 of the drain N-type doping region 32B is biased toward the gate electrode 50 with respect to the central axis A2 of the whole of these feet 320B.
[0072] In the present embodiment, these feet 310B are arranged at intervals below the head 311, and these feet 320B are arranged at intervals below the head 321. Please refer to Figure 12 , which is Figure 11Cross-sectional schematic view of the semiconductor device along line 12-12. The cross-sectional shapes of the respective feet 310B and 320B are not limited to Figure 12 the rectangle shown.
[0073] The formation of the feet 310B and 320B can be, for example, forming a plurality of source trenches 201 as shown in Figure 3 and a plurality of drain trenches 202 as shown in Figure 3 within the semiconductor stack 20.
[0074] The arrangement of the feet 310B and 320B is also not limited to Figure 12 the state shown. Figure 13 Cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention, wherein a plurality of feet 310B can be arranged in a matrix, and a plurality of feet 320B can also be arranged in a matrix. Figure 14 Cross-sectional schematic view of a semiconductor device according to yet another embodiment of the present invention, wherein a plurality of feet 310B can be arranged in a honeycomb pattern, and a plurality of feet 320B can also be arranged in a honeycomb pattern. The cross-sectional shapes of the respective feet 310B and 320B are not limited to Figure 13 the square shown in Figure 14 and the hexagon shown.
[0075] In summary, according to the semiconductor device and its manufacturing method disclosed in the present invention, an N-type doped layer is patterned by electron beam lithography to form a source N-type doped region and a drain N-type doped region. In this way, compared with the existing manufacturing method, there is no need to additionally form a silicon oxide layer or a silicon nitride layer between the N-type doped layer and the semiconductor stack as a shield in the epitaxial process for forming the N-type doped layer, and thus there is no need to perform a step of removing the silicon oxide layer or the silicon nitride layer with a chemical solution subsequently. Thereby, it is beneficial to avoid damage to the semiconductor stack by the etching solution, and further ensure that the semiconductor device has good device performance. The patterning by electron beam lithography can shorten the gap width between the source N-type doped region and the drain N-type doped region, which is beneficial to reducing the path resistance from the source electrode through the semiconductor layer to the drain electrode.
[0076] In addition, in some embodiments, atomic layer deposition is used to form a protective layer, which is beneficial to obtaining a protective layer with a thin thickness and low parasitic capacitance. Atomic layer etching is used to form the gate electrode, which is beneficial to obtaining a gate electrode with a high aspect ratio. In addition, atomic layer etching is beneficial to forming a gate electrode with a very small gate length, thereby improving the cut-off frequency of the semiconductor device to meet the requirements of high-frequency applications.
[0077] In addition, compared with the existing manufacturing methods that require an annealing step for the source electrode and the drain electrode, this embodiment provides the source N-type doping region and the drain N-type doping region of the contact channel layer, which helps to eliminate the annealing step for the source electrode and the drain electrode, thereby avoiding the surface roughness of the source electrode and the drain electrode caused by annealing.
Claims
1. A manufacturing method of a semiconductor device, characterized in that, comprising: forming a semiconductor stack on a substrate; forming an N-type doping layer on the semiconductor stack; patterning the N-type doping layer by electron beam lithography to form a source N-type doping portion and a drain N-type doping portion; forming a source electrode on the source N-type doping portion; forming a drain electrode on the drain N-type doping portion; and forming a gate electrode on the semiconductor stack between the source N-type doping portion and the drain N-type doping portion.
2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, the semiconductor stack includes a buffer layer, a channel layer, a barrier layer, and a cap layer stacked in sequence, and the channel layer contacts the barrier layer at a heterointerface.
3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, the channel layer and the cap layer include gallium nitride, and the barrier layer includes at least one of aluminum nitride, aluminum gallium nitride, and indium aluminum nitride.
4. The manufacturing method of the semiconductor device according to claim 2, characterized in that, forming the N-type doping layer on the semiconductor stack includes: forming at least one source trench and at least one drain trench in the semiconductor stack, wherein the at least one source trench and the at least one drain trench both penetrate the barrier layer and the cap layer and do not penetrate the channel layer; and forming the N-type doping layer in the at least one source trench, the at least one drain trench, and on the cap layer.
5. The manufacturing method of the semiconductor device according to claim 4, characterized in that, the number of the at least one source trench and the at least one drain trench is plural.
6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, further comprising: forming a protective layer on the source N-type doping portion, the drain N-type doping portion, and the semiconductor stack; wherein, forming the source electrode on the source N-type doping portion includes forming the source electrode in a first opening of the protective layer exposing the source N-type doping portion; wherein, forming the drain electrode on the drain N-type doping portion includes forming the drain electrode in a second opening of the protective layer exposing the drain N-type doping portion; wherein, forming the gate electrode on the semiconductor stack includes forming the gate electrode in a third opening of the protective layer exposing the semiconductor stack.
7. The manufacturing method of the semiconductor device according to claim 6, characterized in that, forming the protective layer on the source N-type doping portion, the drain N-type doping portion, and the semiconductor stack by atomic layer deposition.
8. The manufacturing method of the semiconductor device according to claim 6, characterized in that, forming the third opening of the protective layer by atomic layer etching.
9. The manufacturing method of the semiconductor device according to claim 1, characterized in that, the N-type doping layer is an N-type gallium nitride doping layer.
10. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The gap width between the source N-type doped region and the drain N-type doped region is more than ten times the width of the gate electrode.
11. A semiconductor device, characterized in that, comprising: a substrate; a semiconductor stack formed on the substrate; a source N-type doped region formed on the semiconductor stack; a drain N-type doped region formed on the semiconductor stack; a source electrode formed on the source N-type doped region; a drain electrode formed on the drain N-type doped region; and a gate electrode formed on the semiconductor stack, and the gate electrode is between the source N-type doped region and the drain N-type doped region; wherein, the gap width between the source N-type doped region and the drain N-type doped region is more than ten times the width of the gate electrode.
12. The semiconductor device according to claim 11, characterized in that, the semiconductor stack includes a buffer layer, a channel layer, a barrier layer, and a cap layer stacked in sequence, and the channel layer contacts the barrier layer at a heterointerface.
13. The semiconductor device according to claim 12, characterized in that, the channel layer and the cap layer include gallium nitride, and the barrier layer includes at least one of aluminum nitride, aluminum gallium nitride, and indium aluminum nitride.
14. The semiconductor device according to claim 12, characterized in that, the source N-type doped region and the drain N-type doped region each include a plurality of feet, and the plurality of feet extend from the cap layer to the channel layer and do not penetrate the channel layer.
15. The semiconductor device according to claim 11, characterized in that, the source N-type doped region and the drain N-type doped region each include a head and at least one foot, and the head is biased towards the gate electrode with respect to the central axis of the at least one foot.
16. The semiconductor device according to claim 11, characterized in that, further includes a protective layer formed on the semiconductor stack, the protective layer covers the source N-type doped region and the drain N-type doped region, and the source electrode and the drain electrode protrude from the protective layer.
17. The semiconductor device according to claim 11, characterized in that, the gap width between the source N-type doped region and the drain N-type doped region is 100.0 nm to 200.0 nm, and the width of the gate electrode is 10.0 nm to 20.0 nm.
18. The semiconductor device according to claim 11, characterized in that, both the source N-type doped region and the drain N-type doped region are doped with N-type gallium nitride.