A method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate

Abstract

The application discloses a manufacturing method of a high-power nitride semiconductor microwave transistor on a gallium nitride substrate, and mainly solves the problems of existing devices, i.e., a parasitic leakage channel at a homoepitaxial interface and low breakdown voltage. The method comprises the following steps: first, selecting a p-type gallium nitride single crystal substrate, and performing surface pretreatment to obtain a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer; then, sequentially growing a GaN channel layer, an AlN insertion layer and a barrier layer on the pretreated substrate; finally, preparing an insulating gate dielectric layer and a gate electrode on the barrier layer, and manufacturing source and drain electrodes on both sides to complete the device manufacturing. Through in-situ compensation of donor impurities based on the p-type AlN leakage isolation layer and ion implantation, the application realizes complete isolation of a parasitic leakage channel at a homoepitaxial interface and a 2DEG conductive channel at a homoepitaxial GaN heterojunction interface, effectively inhibits the lateral leakage of the device, and improves the withstand voltage and output power of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride single crystal substrate, which can be used to fabricate high-efficiency solid-state microwave power amplifiers and radio frequency terminal components, etc. Background Technology

[0002] Gallium nitride (GaN) materials possess wide bandgap, high electron saturation velocity, high temperature resistance, and radiation resistance. GaN heterojunctions contain a two-dimensional electron gas (2DEG) with high electron mobility and high areal density, formed by polarization effects. Therefore, GaN semiconductor materials have become a research hotspot in the field of microelectronics, especially in solid-state microwave power devices. High electron mobility transistors (HEMTs) based on GaN heterostructures are the core structure of nitride semiconductor microwave transistors. Currently, mainstream GaNHEMT devices are mainly fabricated on silicon (Si), silicon carbide (SiC), and sapphire substrates via heteroepitaxial growth. The large coefficient of thermal expansion and lattice mismatch in heteroepitaxial materials generate extremely high density dislocation defects, which not only deteriorates the 2DEG transport characteristics but also significantly reduces the device's breakdown voltage, severely hindering the improvement of device output power and operational reliability.

[0003] In recent years, with the development of gallium nitride (GaN) single-crystal substrate fabrication technology and the expansion of market demand, the quality and process stability of GaN single crystals have been significantly improved, leading to increased wafer size and reduced fabrication costs. Therefore, homoepitaxial technology for GaN semiconductor microwave transistors has become a research focus.

[0004] In existing literature with publication number CN113555431A, entitled "Homogeneous Epitaxial Gallium Nitride High Electron Mobility Transistor Based on P-type GaN Leakage Isolation Layer and Fabrication Method Thereof", a transistor is disclosed with a self-supporting gallium nitride substrate or a thick-film gallium nitride substrate material as the substrate. A P-type GaN leakage isolation layer and a GaN buffer layer are disposed between the substrate and the channel layer. An insulating gate dielectric layer and a gate electrode are sequentially disposed on the upper part of the barrier layer. There are ohmic contact regions on both sides, and source and drain electrodes are respectively disposed on the ohmic contact regions. Although the problem of parasitic leakage of Si impurities at the homogeneous epitaxial interface is solved to some extent, this structure has problems such as poor uniformity and high process difficulty, and it is difficult to reproduce in its fabrication process.

[0005] Traditional homoepitaxial GaN HEMT device structures on gallium nitride substrates consist of a gallium nitride substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, and a barrier layer, from bottom to top. In this structure, the surface of the gallium nitride single-crystal substrate readily adsorbs shallow-level donor impurities such as silicon (Si) and oxygen (O), forming parasitic conductive channels at the interface between the GaN epitaxial layer and the gallium nitride single-crystal substrate. This results in high off-state leakage current in the homoepitaxial GaN HEMT device, causing a significant discrepancy between the device's breakdown voltage and output power and theoretically expected values. This severely restricts the realization of the performance advantages of gallium nitride single-crystal substrates and their application in nitride semiconductor microwave transistors. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method for fabricating high-power nitride semiconductor microwave transistors on gallium nitride (GaN) substrates. This method utilizes a pretreatment approach based on a p-type AlN leakage isolation layer and ion-implanted self-compensating donor impurities in the GaN single-crystal substrate. This achieves in-situ compensation of donor impurities such as Si and O adsorbed on the surface of the GaN single-crystal substrate, eliminating parasitic leakage channels at the homoepitaxial interface, reducing the off-state leakage current and RF loss of the homoepitaxial GaN RF transistor, and improving the device's breakdown voltage and output power. Simultaneously, the p-type AlN leakage isolation layer exhibits self-organizing nucleation characteristics after high-temperature annealing, which can suppress dislocation growth in the homoepitaxial GaN RF transistor material, ensuring that the quality of the homoepitaxial GaN material is comparable to that of the GaN single-crystal substrate, thereby improving the operational reliability of the homoepitaxial GaN RF transistor.

[0007] To achieve the above objectives, the technical solution proposed by this invention is as follows:

[0008] A method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate, wherein the transistor comprises, from bottom to top, a gallium nitride single-crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer, wherein the gallium nitride single-crystal substrate is a p-type gallium nitride single-crystal substrate containing a p-type AlN leakage isolation layer obtained by surface pretreatment. The implementation steps of the method of the present invention include the following:

[0009] 1) Select a p-type gallium nitride single crystal substrate and pretreat it:

[0010] 1.1) A polycrystalline GaN sacrificial layer is grown on a p-type gallium nitride single-crystal substrate;

[0011] 1.2) Ion implantation into a p-type gallium nitride single-crystal substrate via a polycrystalline GaN sacrificial layer;

[0012] 1.3) The polycrystalline GaN sacrificial layer was removed by hydrogen atom etching technology to obtain a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface;

[0013] 1.4) A p-type AlN leakage isolation layer is grown on a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface, and the surface of the p-type gallium nitride single crystal substrate is flattened.

[0014] 1.5) Annealing is performed on the p-type gallium nitride single crystal substrate with the p-type AlN leakage isolation layer grown thereon to achieve self-organized nucleation of the p-type AlN leakage isolation layer, thereby obtaining a patterned substrate and completing the pretreatment process.

[0015] 2) On a patterned substrate, i.e. a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer after surface pretreatment, GaN channel layer, AlN insertion layer and barrier layer are grown sequentially.

[0016] 3) Etch the barrier layer down to the channel layer, and form the source electrode and drain electrode on both sides of it, respectively;

[0017] 4) An insulating gate dielectric layer is deposited on the upper surface of the barrier layer, and a gate electrode is formed on the dielectric layer to complete the device fabrication.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] First, because the present invention sets up a polycrystalline GaN sacrificial layer, the irregular crystal orientation in this layer can regulate the path of the injected high-energy ions, so that the concentration peak is located at the parasitic leakage channel on the surface of the gallium nitride single crystal substrate, ensuring that the injected ions compensate for the Si and O impurities adsorbed on the surface of the gallium nitride single crystal substrate, thereby achieving the purpose of isolating the parasitic leakage channel.

[0020] Secondly, the p-type AlN leakage isolation layer used in this invention can self-organize and nucleate after annealing, forming a patterned substrate effect, which can significantly improve the crystal quality of its homoepitaxial GaN material and avoid dislocation growth in the homoepitaxial GaN material.

[0021] Third, the p-type AlN leakage isolation layer used in this invention forms island-shaped nucleation points after annealing. These points simultaneously enter the irregularly distributed pit defects left on the surface of the gallium nitride single crystal substrate after hydrogen atom etching of the polycrystalline GaN sacrificial layer. The p-type AlN leakage isolation layer material within the island-shaped nucleation points and pit defects is distributed in a sawtooth pattern, densely covering the entire surface of the gallium nitride single crystal substrate. This achieves spatial isolation between the parasitic leakage channels of Si impurities on the surface of the gallium nitride substrate and the 2DEG conductive channels at the interface of the homoepitaxial GaN heterojunction, and prevents the lateral conduction of the parasitic leakage channels of Si impurities on the surface of the gallium nitride substrate, thereby improving the overall lateral withstand voltage capability of the device.

[0022] Fourth, the p-type AlN leakage isolation layer used in this invention is an ultra-wide bandgap material, which can act as a back barrier, improve the confinement and transport characteristics of 2DEG in the channel layer of the heterojunction interface in the active region of gallium nitride devices, suppress vertical leakage current, and improve the longitudinal withstand voltage capability of the device.

[0023] Fifth, the pretreatment process for gallium nitride single crystal substrates in this invention is cost-controllable and simple to operate, providing a high degree of freedom and feasibility for the fabrication of homoepitaxial nitride semiconductor radio frequency transistors on gallium nitride single crystal substrates. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a gallium nitride single crystal substrate pretreatment method provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the overall structure of the high-power nitride semiconductor microwave transistor on a gallium nitride substrate in this invention;

[0026] Figure 3 This is a schematic diagram of the fabrication process of the high-power nitride semiconductor microwave transistor on a gallium nitride substrate in this invention;

[0027] Figure 4 This is a transmission electron microscope image of the material cross-section as shown in the embodiment of the present invention. Detailed Implementation

[0028] The present invention will now be further described with reference to the accompanying drawings.

[0029] Example 1. Refer to Appendix Figure 1-3 This invention proposes a method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate. The transistor comprises, from bottom to top, a gallium nitride single-crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer. The gallium nitride single-crystal substrate is a p-type gallium nitride single-crystal substrate containing a p-type AlN leakage isolation layer, obtained through surface pretreatment. The method for fabricating the high-power nitride semiconductor microwave transistor on the gallium nitride substrate specifically includes the following steps:

[0030] Step 1) Select a p-type gallium nitride single crystal substrate, with any one of C, Fe, or Mn as the doping element; and pretreat it:

[0031] 1.1) A polycrystalline GaN sacrificial layer is grown on a p-type gallium nitride single crystal substrate, using any one of the following growth methods: PVD, MOCVD, MBE, HVPE, PLD, and ALD. In this embodiment, PVD or MOCVD is preferred.

[0032] 1.2) Ion implantation into a p-type gallium nitride single-crystal substrate via a polycrystalline GaN sacrificial layer; In this embodiment, this step is specifically performed using an ion implantation process, implanting one or more of C, Fe, and Mg ions into the p-type gallium nitride single-crystal substrate via a polycrystalline GaN sacrificial layer, with an implantation dose of 1 × 10⁻⁶. 12 cm -2 ~1×1014 cm -2 The injection energy is 40keV to 60keV, and the injection method is vertical injection.

[0033] 1.3) The polycrystalline GaN sacrificial layer was removed by hydrogen atom etching technology to obtain a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface;

[0034] 1.4) A p-type AlN leakage isolation layer is grown on a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface, and the surface of the p-type gallium nitride single crystal substrate is flattened.

[0035] In this embodiment, any one of the following growth methods is used when growing the p-type AlN leakage isolation layer: PVD, MOCVD, MBE, HVPE, PLD, and ALD. Preferably, PVD or MOCVD is used to grow the p-type AlN leakage isolation layer with a thickness of 3nm-15nm. The p-type doping element is any one or more of Mn, Fe, and Mg.

[0036] 1.5) Annealing is performed on the p-type gallium nitride single crystal substrate with the p-type AlN leakage isolation layer grown thereon. In this embodiment, the annealing temperature is preferably set to 800℃-1200℃ and the annealing time is 40s-60s. The p-type AlN leakage isolation layer exhibits self-organized nucleation phenomenon, realizing a patterned substrate and completing the pretreatment process.

[0037] Step 2) On a patterned substrate, i.e., a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer after surface pretreatment, a GaN channel layer, an AlN insertion layer, and a barrier layer are grown sequentially; the growth methods are MOCVD or MBE; the thicknesses are 500nm-2000nm, 1nm-2nm, and 3nm-30nm respectively. The barrier layer is any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN.

[0038] Step 3) Etch the barrier layer down to the channel layer, forming source and drain electrodes on both sides respectively; specifically, it is formed as follows: First, use photoresist as a mask on the barrier layer to define the source and drain electrode patterns; then, use a dry etching method to etch the barrier layer down to the channel layer to form the source and drain electrode regions; finally, use an electron beam evaporation process to deposit a Ti / Al / Ni / Au metal combination in the source and drain electrode regions, and anneal it to form the source and drain electrodes.

[0039] Step 4) Deposit an insulating gate dielectric layer on the upper surface of the barrier layer and form a gate electrode on the dielectric layer. Specifically, deposit the insulating gate dielectric on the surface of the barrier layer using the ALD process, define the gate electrode pattern on the surface of the insulating gate dielectric layer using the photolithography process, and then deposit a Ni / Au metal combination on the insulating gate dielectric layer using the electron beam evaporation process to form the gate electrode; finally, the device fabrication is completed.

[0040] Example 2. The preparation method provided in this example is implemented in the same way as in Example 1. Refer to the appendix below. Figure 3 Sections (a)-(e) further describe in detail the gallium nitride single-crystal substrate pretreatment method involved in this invention; the pretreatment involves a C-doped p-type gallium nitride single-crystal substrate, with a C ion implantation quantification of 1 × 10⁻⁶. 14 cm -2 The injection energy was 60 keV; the p-type AlN leakage isolation layer was doped with Mg and had a thickness of 3 nm; the annealing temperature was 800℃ and the annealing time was 60 s. The implementation steps are as follows:

[0041] Step 1. Deposit a polycrystalline GaN sacrificial layer, such as... Figure 3 (a).

[0042] A polycrystalline GaN sacrificial layer was deposited on a C-doped p-type gallium nitride single-crystal substrate using PVD. The thickness of the polycrystalline GaN sacrificial layer was 10 nm.

[0043] Step 2. C-ion implantation, such as Figure 3 (b)

[0044] High-energy ions, specifically C ions, were implanted into a p-type gallium nitride single-crystal substrate using a polycrystalline GaN sacrificial layer. The ion implantation conditions were: an implantation dose of 1 × 10⁻⁶. 14 cm -2 The injected energy is 60keV.

[0045] Step 3. Hydrogen atom etching, such as Figure 3 (c)

[0046] The polycrystalline GaN sacrificial layer was removed by etching using hydrogen atom etching technology.

[0047] Step 4. Deposit a p-type AlN leakage isolation layer, such as... Figure 3 (d)

[0048] A p-type AlN leakage isolation layer was deposited on a p-type gallium nitride single-crystal substrate with the polycrystalline GaN sacrificial layer removed using the PVD method. The thickness of the p-type AlN leakage isolation layer was 3 nm, and the p-type doping element was Mg.

[0049] Step 5. Annealing treatment, such as... Figure 3 (e).

[0050] The p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer was annealed. The annealing conditions were: annealing temperature of 800℃ and annealing time of 60s.

[0051] Example 3. The preparation method provided in this example is implemented in the same way as in Example 1. Refer to the appendix below. Figure 3 Sections (a)-(e) further describe in detail the gallium nitride single crystal substrate pretreatment method involved in this invention; the pretreatment involves a Mn-doped p-type gallium nitride single crystal substrate, with an Fe ion implantation metric of 1 × 10⁻⁶. 13 cm -2 The injection energy is 50 keV; the p-type AlN leakage isolation layer is doped with Fe and has a thickness of 10 nm; the annealing temperature is 1000℃ and the annealing time is 50 s. The implementation steps are as follows:

[0052] Step 1. Deposit a polycrystalline GaN sacrificial layer using MOCVD technology, such as... Figure 3 (a).

[0053] A polycrystalline GaN sacrificial layer was deposited on a Mn-doped p-type gallium nitride single-crystal substrate using MOCVD technology. The thickness of the polycrystalline GaN sacrificial layer was 20 nm.

[0054] Step 2. Fe ion implantation treatment, such as Figure 3 (b)

[0055] A p-type gallium nitride single-crystal substrate with a polycrystalline GaN sacrificial layer deposited was placed in an ion implantation chamber. The implanted ion type was set to Fe ions, and the implantation dose was 1×10⁻⁶. 13 cm -2 The injected energy is 50keV.

[0056] Step 3. Hydrogen atom etching, such as Figure 3 (c)

[0057] The polycrystalline GaN sacrificial layer was removed by etching using hydrogen atom etching technology.

[0058] Step 4. Deposit a p-type AlN leakage current isolation layer using MOCVD technology, such as... Figure 3 (d)

[0059] A 10 nm thick p-type AlN leakage isolation layer was deposited on a p-type gallium nitride single crystal substrate with the polycrystalline GaN sacrificial layer removed, with the process conditions set at a temperature of 800℃, a pressure of 40 Torr, an ammonia flow rate of 1500 sccm, a nitrogen flow rate of 1000 sccm, an aluminum source flow rate of 3 sccm, and an iron source flow rate of 10 sccm.

[0060] Step 5. Annealing treatment, such as... Figure 3 (e).

[0061] The p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer was annealed using a process condition of 1000℃ and 50s.

[0062] Example 4. The preparation method provided in this example is implemented in the same way as in Example 1. Refer to the appendix below. Figure 3 Sections (a)-(e) further describe in detail the gallium nitride single crystal substrate pretreatment method involved in this invention; the pretreatment involves Fe-doped p-type gallium nitride single crystal substrates, with Mn ion implantation quantification of 1 × 10⁻⁶. 12 cm -2 The injection energy is 40 keV; the p-type AlN leakage isolation layer is doped with Mn and has a thickness of 15 nm; the annealing temperature is 1200℃ and the annealing time is 40 s. The implementation steps are as follows:

[0063] Step A. Deposit a polycrystalline GaN sacrificial layer, such as Figure 3 (a).

[0064] A 30 nm thick polycrystalline GaN sacrificial layer was deposited on an Fe-doped p-type gallium nitride single-crystal substrate using the MBE technique.

[0065] Step B. Mn ion implantation treatment, such as Figure 3 (b)

[0066] A p-type gallium nitride single-crystal substrate with a polycrystalline GaN sacrificial layer deposited was placed in an ion implantation chamber at an implantation dose of 1×10⁻⁶. 12 cm -2 Mn ion implantation was performed vertically at an implantation energy of 40 keV.

[0067] Step C. Hydrogen atom etching, such as Figure 3 (c)

[0068] The polycrystalline GaN sacrificial layer was removed by etching using hydrogen atom etching technology.

[0069] Step D. Deposit a p-type AlN leakage isolation layer, such as Figure 3 (d)

[0070] Using MBE technology, at a temperature of 600℃, a nitrogen flow rate of 1.6 sccm, and an aluminum beam equivalent equilibrium vapor pressure of 6.5 × 10⁻⁶, the optimal conditions were achieved. -7 Torr, the equivalent equilibrium vapor pressure of the manganese beam is 2.5 × 10⁻⁶. -8 Under Torr's process conditions, a 15nm thick p-type AlN leakage isolation layer is deposited on a p-type gallium nitride single crystal substrate with the polycrystalline GaN sacrificial layer removed.

[0071] Step E. Annealing treatment, such as Figure 3(e).

[0072] Under the process conditions of annealing temperature of 1200℃ and annealing time of 40s, p-type gallium nitride single crystal substrates with p-type AlN leakage isolation layers were annealed.

[0073] Example 5. The preparation method provided in this example is implemented in the same way as in Example 1. Refer to the appendix below. Figure 3 (f)-(k) further details the process of sequentially growing a GaN channel layer, an AlN insertion layer, and a barrier layer on a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer after surface pretreatment, ultimately completing the device fabrication:

[0074] Step (1): Deposit GaN channel layer, such as Figure 3 (f).

[0075] Using MOCVD technology, a GaN channel layer with a thickness of 500 nm was deposited on a p-type AlN isolation layer under the following process conditions: temperature of 1200℃, pressure of 40 Torr, ammonia flow rate of 3500 sccm, hydrogen flow rate of 3000 sccm, and gallium source flow rate of 200 sccm.

[0076] Step (2): Deposit an AlN insertion layer, such as Figure 3 (g)

[0077] Using MOCVD technology, a 2nm AlN insertion layer was deposited on the GaN channel layer under the following process conditions: temperature 1200℃, pressure 40 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, and aluminum source flow rate 20 sccm.

[0078] Step (3): Deposition of Al 0.25 Ga 0.75 N-barrier layer, such as Figure 3 (h).

[0079] Using MOCVD technology, under the following process conditions: temperature 1200℃, pressure 40 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, gallium source flow rate 200 sccm, and aluminum source flow rate 20 sccm, a 25 nm thick Al layer was deposited on the AlN insertion layer. 0.25 Ga 0.75 N-barrier layer.

[0080] Step (4): Dry etching to form grooves in the source and drain electrode regions, such as Figure 3 (i).

[0081] In Al 0.25 Ga 0.75On the N-type barrier layer, source and drain electrode patterns are defined using photoresist as a mask. Using dry etching technology, under process conditions of 18 sccm Cl2 flow rate, 12 mTorr reaction chamber pressure, and 160 W electrode power, Al in the source and drain electrode regions of the GaN channel layer surface is removed. 0.25 Ga 0.75 An N-type barrier layer and an AlN insertion layer are used to form grooves in the source and drain electrode regions.

[0082] Step (5): Fabricate the source and drain electrodes, such as Figure 3 (j).

[0083] Electron beam evaporation was employed at a vacuum level of less than 1.2 × 10⁻⁶. -3 Pa, power 500W, evaporation rate is Under the specified process conditions, Ti / Al / Ni / Au metal composites with thicknesses of 0.02μm / 0.14μm / 0.05μm / 0.04μm are deposited on the grooves in the source and drain electrode regions, and then annealed at 860℃ in a nitrogen atmosphere to form the source and drain electrodes.

[0084] Step (6): Fabricate the gate electrode, such as Figure 3 (k).

[0085] An insulating gate dielectric was deposited using ALD (Alternating Discharge) technology, and the gate electrode pattern was defined on the surface of the insulating gate dielectric layer using photolithography. Electron beam evaporation was employed at a vacuum level of less than 1.2 × 10⁻⁶. -3 Pa, power is 500W, evaporation rate is Under the specified process conditions, a Ni / Au metal combination with a thickness of 0.05μm / 0.15μm is deposited on the insulating gate dielectric layer to form the gate and complete the device fabrication.

[0086] The parts of this invention not described in detail are common knowledge to those skilled in the art.

[0087] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, in addition to the materials mentioned in the above embodiments, the p-type AlN leakage isolation layer may use any one of p-type InAlN, p-type AlN, p-type InAlGaN, p-type BAlN, p-type ScAlN, p-type AlPN, and p-type BPN. However, these modifications and changes based on the concept of the present invention are still within the scope of the claims of the present invention.

Claims

1. A method for fabricating a high-power gallium nitride semiconductor microwave transistor on a gallium nitride substrate, the transistor comprising, from bottom to top, a gallium nitride single-crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer, characterized in that the substrate undergoes surface pretreatment to obtain a p-type gallium nitride single-crystal substrate containing a p-type AlN leakage isolation layer; the implementation steps of the method include the following: 1) Select a p-type gallium nitride single crystal substrate and pretreat it: 1.1) Growing a polycrystalline GaN sacrificial layer on a p-type gallium nitride single-crystal substrate; 1.2) Implanting one or more of C, Fe, and Mg ions into a p-type gallium nitride single crystal substrate through a polycrystalline GaN sacrificial layer; 1.3) The polycrystalline GaN sacrificial layer was removed by hydrogen atom etching technology to obtain a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface; 1.4) A p-type AlN leakage isolation layer is grown on a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface, and the surface of the p-type gallium nitride single crystal substrate is flattened; 1.5) Annealing is performed on the p-type gallium nitride single crystal substrate with the p-type AlN leakage isolation layer grown thereon to achieve the self-organized nucleation of the p-type AlN leakage isolation layer, thereby obtaining a patterned substrate and completing the pretreatment process. 2) On a patterned substrate, i.e. a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer after surface pretreatment, GaN channel layer, AlN insertion layer and barrier layer are grown sequentially. 3) Etch the barrier layer down to the channel layer, and form the source electrode and drain electrode on both sides of it, respectively; 4) An insulating gate dielectric layer is deposited on the upper surface of the barrier layer, and a gate electrode is formed on the dielectric layer to complete the device fabrication.

2. The method according to claim 1, characterized in that: Step 1) The p-type gallium nitride single crystal substrate is doped with any one of C, Fe, and Mn.

3. The method according to claim 1, characterized in that: In step 1.1), a polycrystalline GaN sacrificial layer is grown on a p-type gallium nitride single crystal substrate, using any one of the following growth methods: PVD, MOCVD, MBE, HVPE, PLD, and ALD.

4. The method according to claim 1, characterized in that: Step 1.2) The implanted ions are specifically implanted using an ion implantation process, with an implantation dose of 1×10⁻⁶. 12 cm -2 ~1×10 14 cm -2 The injected energy is 40 keV~60 keV.

5. The method according to claim 1, characterized in that: In step 1.4), a p-type AlN leakage isolation layer is grown using any one of the following growth methods: PVD, MOCVD, MBE, HVPE, PLD, and ALD. The p-type doping element is any one or more of Mn, Fe, and Mg.

6. The method according to claim 1, characterized in that: In step 2), the GaN channel layer, AlN insertion layer, and barrier layer are all grown using MOCVD or MBE; their thicknesses are 500 nm-2000 nm, 1 nm-2 nm, and 3 nm-30 nm, respectively.

7. The method according to claim 6, characterized in that: The barrier layer is any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN.

8. The method according to claim 1, characterized in that: Step 3) The source and drain electrodes are formed as follows: First, the source and drain electrode patterns are defined on the barrier layer using photoresist as a mask; then, the barrier layer is etched down to the channel layer using a dry etching method to form the grooves in the source and drain electrode regions; finally, an electron beam evaporation process is used to deposit a Ti / Al / Ni / Au metal combination in the grooves in the source and drain electrode regions, and then annealing is performed to form the source and drain electrodes.

9. The method according to claim 1, characterized in that: Step 4) involves depositing an insulating gate dielectric layer on the upper surface of the barrier layer and forming a gate electrode on the dielectric layer. Specifically, an insulating gate dielectric is deposited on the surface of the barrier layer using an ALD process, a gate electrode pattern is defined on the surface of the insulating gate dielectric layer using a photolithography process, and then a Ni / Au metal combination is deposited on the insulating gate dielectric layer using an electron beam evaporation process to form the gate electrode.

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