Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The method includes forming a nanostructured layer on a substrate, forming a gate structure surrounding the nanostructured layer, forming an S / D region adjacent to the nanostructured layer, forming a contact opening on the S / D region, depositing a first conductive layer in the contact opening using a first deposition process, performing a plasma etching process on the first conductive layer, and forming a second conductive layer on the substrate. A second conductive layer is deposited on the first conductive layer using a second deposition process different from the first deposition process and a metal layer is deposited on the second conductive layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a contact structure of a semiconductor device. Background Art

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost has been increasing continuously. To meet these demands, the semiconductor industry has been continuously reducing the size of semiconductor devices. For example, metal oxide semiconductor field effect transistors (MOSFETs) include planar MOSFETs and fin field effect transistors (finFETs). Reducing the size of semiconductor devices increases the complexity of the semiconductor manufacturing process. Summary of the Invention

[0003] In one aspect of the present disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes forming a nanostructured layer on a substrate, forming a gate structure surrounding the nanostructured layer, forming source / drain (S / D) regions adjacent to the nanostructured layer, forming contact openings in the S / D regions, depositing a first conductive layer in the contact openings using a first deposition process, performing a plasma etching process on the first conductive layer, depositing a second conductive layer on the first conductive layer using a second deposition process different from the first deposition process, and depositing a metal layer on the second conductive layer.

[0004] In another aspect of the present disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes forming a gate structure on a substrate, forming S / D regions adjacent to the gate structure, and forming a contact structure. The formation of the contact structure includes forming contact openings in the S / D regions, depositing a first nitride layer in the contact openings, removing a native oxide layer from the surface of the first nitride layer, depositing a second nitride layer on the first nitride layer, and depositing a metal layer on the second nitride layer.

[0005] In yet another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, source / drain (S / D) regions disposed adjacent to the nanostructured channel region, and a contact structure. The contact structure includes a first diffusion barrier layer disposed on the S / D region, a second diffusion barrier layer disposed on the first diffusion barrier layer, and a metal layer disposed on the second diffusion barrier layer. The oxygen atom concentration at the interface between the first diffusion barrier layer and the second diffusion barrier layer is less than 5 atomic %. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A Isometric view of a semiconductor device having a contact structure according to some embodiments;

[0008] Figure 1B And Figure 1C Cross-sectional views of a semiconductor device having a contact structure according to some embodiments;

[0009] Figure 2 Flowchart of a method for manufacturing a semiconductor device having a contact structure according to some embodiments;

[0010] Figures 3 to 11 And Figures 13 to 18 Cross-sectional views of a semiconductor device having a contact structure at various stages of its manufacturing process according to some embodiments;

[0011] Figure 12 Oxygen concentration distribution in the contact structure of a semiconductor device at various stages of a manufacturing process according to some embodiments.

[0012] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements.

[0013]

Symbol Description

[0014] 100: FET / GAA FET / finFET

[0015] 104: Substrate

[0016] 106: Fin substrate / sheet substrate / fin structure

[0017] 108: Nanostructured channel region / nanostructured layer

[0018] 110A, 110B, 110C: S / D regions

[0019] 112A, 112B, 112C: Gate structures

[0020] 114: Gate spacers

[0021] 115: Inner spacers

[0022] 116: STI regions

[0023] 117A, 117B: Etch stop layer / ESL

[0024] 118A, 118B, 118C, 119: Interlayer dielectric layer / ILD layer

[0025] 120: S / D Contact Structure

[0026] 120A: Silicide Layer

[0027] 120B: First Diffusion Barrier Layer / First Conductance Barrier Layer

[0028] 120C: Second Diffusion Barrier Layer / Second Conductance Barrier Layer

[0029] 120D: Contact Plug

[0030] 122: S / D Contact Structure

[0031] 122A: Silicide Layer

[0032] 122B: First Diffusion Barrier Layer

[0033] 122C: Second Diffusion Barrier Layer

[0034] 122D: Contact Plug

[0035] 124A, 124B: Dielectric Barrier Layer

[0036] 126: Via Structure

[0037] 128: Gate Stack

[0038] 128A: Interface Oxide Layer / IL Layer

[0039] 128B: High-K Gate Dielectric Layer / HK Gate Dielectric Layer

[0040] 128C: Work Function Metal Layer / WFM Layer

[0041] 128D: Gate Metal Fill Layer

[0042] 130: Gate Overlay Structure

[0043] 130A: Conductive Gate Overlay

[0044] 130B: Insulating Gate Overlay

[0045] 132: Gate Contact Structure

[0046] 132A: Pad

[0047] 132B: Contact Plug

[0048] 134: Via Contact Structure

[0049] 134A: Pad

[0050] 134B: Contact Plug

[0051] 200: Method

[0052] 205, 210, 215, 220, 225, 230: Operations

[0053] 307: Superlattice Structure

[0054] 308: Nanostructure Layer / Sacrificial Layer

[0055] 312: Polysilicon Structure

[0056] 540: Gate Overlay Opening

[0057] 742: S / D Contact Opening

[0058] 824: Dielectric Layer

[0059] 920: Residual Metal Layer

[0060] 1020: First Conductive Nitride Layer

[0061] 1044: Native Oxide Layer

[0062] 1146: Gas Mixture

[0063] 1248: Concentration Profile

[0064] 1320: Second Conductive Nitride Layer

[0065] 1420: First Metal Layer

[0066] 1520: Second Metal Layer

[0067] A - A, C - C, D - D: Lines

[0068] X, Y, Z: Axes Detailed Description of the Embodiments

[0069] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature hereinafter may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0070] In addition, for descriptive purposes, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0071] Note that references in the specification to "one embodiment", "an embodiment", "exemplary embodiment", "exemplary", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment does not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, implementation of such feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly described.

[0072] It should be understood that the terminology or phrasing herein is for the purpose of description and not intended to be limiting, such that those skilled in the relevant art can interpret the terminology or phrasing herein according to the teachings herein.

[0073] In some embodiments, the terms "about" and "substantially" may indicate that a given value varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of a numerical value). These values are merely exemplary and not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a numerical value as interpreted by those skilled in the relevant art according to the teachings herein.

[0074] The gate all around (GAA) transistor structure can be patterned through any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the structure. Double patterning or multi-patterning processes can combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Next, the sacrificial layer is removed, and the remaining spacers can be used to pattern the GAA transistor structure.

[0075] The present disclosure provides exemplary methods for minimizing contact resistance between a contact structure and a source / drain (S / D) region in a FET (e.g., finFET and GAA FET). In some embodiments, the S / D region may be formed on a fin substrate, and the contact structure may be formed on the S / D region. In some embodiments, forming the contact structure may include depositing a first diffusion barrier layer in a contact opening on the S / D region, depositing a second diffusion barrier layer on the first diffusion barrier layer, and depositing a conductive layer on the second diffusion barrier layer. In some embodiments, forming the contact structure may further include performing an oxide removal process (also referred to as a "cleaning process") on the first diffusion barrier layer before depositing the second diffusion barrier layer. The oxide removal process may remove a native oxide layer and / or oxygen atoms from the top surface of the first diffusion barrier layer to reduce the concentration of oxygen atoms on the top surface of the first diffusion barrier layer to less than about 5 atomic % (e.g., from about 0.1 atomic % to about 4.9 atomic %). Due to the reaction between oxygen in the atmosphere and the material of the first diffusion barrier layer, a native oxide layer and / or oxygen atoms may be introduced on the top surface of the first diffusion barrier layer during a vacuum break between depositing the first diffusion barrier layer and the second diffusion barrier layer. The presence of the native oxide layer and / or oxygen atoms at the interface between the first diffusion barrier layer and the second diffusion barrier layer reduces the conductivity between the contact structure and the S / D region. Thus, the oxide removal process may minimize the contact resistance between the contact structure and the S / D region.

[0076] Figure 1A An isometric view of a FET 100 is shown in accordance with some embodiments. Figure 1B With Figure 1C Shown along Figure 1A Line A-A of different cross-sectional views of the FET 100. In some embodiments, Figure 1B The cross-sectional view of the FET 100 in Figure 1C May be represented as a GAA FET 100, and Figure 1B With Figure 1C Shown a cross-sectional view of the FET 100 with additional structures, for simplicity, the additional structures are not shown in Figure 1A Unless otherwise noted, Figures 1A to 1C The discussion of elements with the same reference numerals in

[0077] The FET 100 may be formed on a substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed on the substrate 104. In some embodiments, the substrate 104 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, the substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).

[0078] Reference Figure 1A and Figure 1B , in some embodiments, the FET 100 may include (i) a fin or sheet substrate 106 disposed on the substrate 104, (ii) a nanostructured channel region 108, (iii) S / D regions 110A - 110C (S / D region 110C is visible in Figure 1A ; S / D regions 110A - 110B are visible in Figure 1B ), (iv) gate structures 112A - 112C surrounding the nanostructured channel region 108, (v) gate spacers 114, (vi) inner spacers 115, (vii) etch stop layers (ESL) 117A - 117B (for simplicity, ESL 117B is not shown in Figure 1A and ESL 117A is not shown in Figure 1B ), (viii) interlayer dielectric (ILD) layers 118A - 118C and 119 (for simplicity, ILD layers 118B and 118C are not shown in Figure 1A ; and are shown in Figure 1B ), (ix) S / D contact structures 120 and 122, (x) dielectric barrier layers 124A and 124B, (xi) via structures 126, (xii) gate contact structures 132, and (xiii) combined via contact structures 134. Depending on the context, each of the S / D regions 110A - 110C may refer to the source or drain independently or collectively.

[0079] In some embodiments, the fin or sheet substrate 106 may include a material similar to the substrate 104. The fin or sheet substrate 106 may have elongated sides extending along the X-axis. In some embodiments, the substrate 104 and the fin or sheet substrate 106 may be replaced with S / D contact structures 122 and ILD layer 119, as referenced below in Figure 1B , Figure 17 and Figure 18 described.

[0080] In some embodiments, the nanostructured channel region 108 may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes. The nanostructured channel region 108 may include a semiconductor material similar to or different from the substrate 104.

[0081] In some embodiments, the nanostructured channel region 108 may include silicon (Si), silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbide phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. Although a rectangular cross-section of the nanostructured channel region 108 is shown, the nanostructured channel region 108 may have a cross-section of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). As used herein, the term "nanostructured" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm.

[0082] For the n-type FET 100, each of the S / D regions 110A-110C may include an epitaxially grown semiconductor material (e.g., Si) and an n-type dopant (e.g., phosphorus and other suitable n-type dopants). For the p-type FET 100, each of the S / D regions 110A-110C may include an epitaxially grown semiconductor material (e.g., Si and SiGe) and a p-type dopant (e.g., boron and other suitable p-type dopants).

[0083] The S / D contact structure 120 may be disposed on the front surface of the S / D regions 110A - 110C. In some embodiments, each S / D contact structure 120 may have a width of about 10 nm to about 20 nm and a height of about 35 nm to about 50 nm to provide a structure with sufficient conductivity between the S / D regions 110A - 110C and the overlying interconnects, such as the via structure 126 and the merged via contact structure 134. In some embodiments, each S / D contact structure 120 may include (i) a silicide layer 120A, (ii) a first diffusion barrier layer 120B (also referred to as the "first conduction resistance barrier layer 120B") disposed on the silicide layer 120A, (iii) a second diffusion barrier layer 120C (also referred to as the "second conduction resistance barrier layer 120C") disposed on the first diffusion barrier layer 120B, and (iv) a contact plug 120D disposed on the second diffusion barrier layer 120C. The silicide layer 120A may be set in the S / D regions 110A - 110C and may have a thickness of about 1 nm to about 8 nm along the Z - axis. In some embodiments, the silicide layer 120A in the n - type FET 100 may include titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), hafnium silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Si), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 120A in the p - type FET 100 may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y) Tungsten silicide (W x Si y ) Iron silicide (Fe x Si y ) Rhodium silicide (Rh x Si y ) Palladium silicide (Pd x Si y ) Ruthenium silicide (Ru x Si y ) Platinum silicide (Pt x Si y ) Iridium silicide (Ir x Si y ) Osmium silicide (Os x Si y ) Other suitable metal silicide materials or combinations thereof.

[0084] In some embodiments, the first diffusion barrier layer 120B can be directly disposed on the silicide layer 120A, and the second diffusion barrier layer 120C can be directly disposed on the first diffusion barrier layer 120B. In some embodiments, the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can be configured to prevent or minimize the diffusion of oxygen atoms from the ILD layer 118B to the contact plug 120D. Oxygen atoms can oxidize the material of the contact plug 120D and reduce the conductivity of the S / D contact structure 120. Additionally, the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can be configured to prevent or minimize the diffusion of metal atoms (e.g., cobalt atoms) from the contact plug 120D to the gate structures 112A - 112C. The diffusion of metal atoms can degrade the performance of the gate structures 112A - 112C. In some embodiments, the silicide layer 120A, the first diffusion barrier layer 120B, and the second diffusion barrier layer 120C can include the same metal, such as titanium and tantalum. In some embodiments, the silicide layer 120A can include TiSi 2 or TaSi 2 , the first diffusion barrier layer 120B can include titanium silicon nitride (TiSiN) or tantalum silicon nitride (TaSiN), and the second diffusion barrier layer 120C can include titanium nitride (TiN) or tantalum nitride (TaN). The first diffusion barrier layer 120B and the second diffusion barrier layer 120C can be conductive.

[0085] In some embodiments, for sufficient performance of the FET 100, the oxygen atom concentration at the interface between the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can be less than about 5 atomic % (e.g., from about 0.1 atomic % to about 4.9 atomic %). An oxygen concentration above 5 atomic % at the interface between the first diffusion barrier layer 120B and the second diffusion barrier layer 120C increases the resistance between the contact plug 120D and the S / D regions 110A - 110C and degrades the performance of the FET 100. In some embodiments, the sidewall portions of each of the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can have a thickness of about 0.5 nm to about 1.5 nm along the X-axis and the Y-axis, and the bottom of each of the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can have a thickness of about 0.5 nm to about 1.5 nm along the Z-axis. Within these thickness ranges, the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can sufficiently prevent or minimize the diffusion of oxygen atoms and metal atoms while minimizing the resistance of the S / D contact structure 120. In some embodiments, the bottom portions of each of the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can be thicker than the sidewall portions of each of the first diffusion barrier layer 120B and the second diffusion barrier layer 120C.

[0086] In some embodiments, the contact plug 120D can be directly disposed on the second diffusion barrier layer 120C, and the first diffusion barrier layer 120B and the second diffusion barrier layer 120C can surround the contact plug 120D. In some embodiments, the contact plug 120D can include a conductive material having a low resistivity (e.g., a resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), other suitable conductive materials having low resistivity, and combinations thereof.

[0087] In some embodiments, the S / D contact structure 122 can be disposed on the backside surface of the S / D regions 110A - 110C. In some embodiments, each S / D contact structure 122 can have a width of about 10 nm to about 20 nm and a height of about 35 nm to about 50 nm to provide sufficient conductivity (not shown) between the S / D regions 110A - 110C and the underlying backside power rail.

[0088] In some embodiments, each S / D contact structure 122 may include (i) a silicide layer 122A, (ii) a first diffusion barrier layer 122B disposed on the silicide layer 120A, (iii) a second diffusion barrier layer 122C disposed on the first diffusion barrier layer 122B, and (iv) a contact plug 122D disposed on the second diffusion barrier layer 122C. Unless otherwise specified, the discussion of the silicide layer 120A, the first diffusion barrier layer 120B, the second diffusion barrier layer 120C, and the contact plug 120D applies to the silicide layer 122A, the first diffusion barrier layer 122B, the second diffusion barrier layer 122C, and the contact plug 122D. The first diffusion barrier layer 122B and the second diffusion barrier layer 122C may be configured to prevent or minimize the diffusion of oxygen atoms from the ILD layer 119 to the contact plug 122D.

[0089] In some embodiments, a dielectric barrier layer 124A may surround each S / D contact structure 120, and a dielectric barrier layer 124B surrounds each S / D contact structure 122. Similar to the first diffusion barrier layer 120B and the second diffusion barrier layer 120C, the dielectric barrier layer 124A may be configured to prevent or minimize the diffusion of oxygen atoms from the ILD layer 118B to the contact plug 120D, and to prevent or minimize the diffusion of metal atoms from the contact plug 120D to the gate structures 112A - 112C. Similar to the first diffusion barrier layer 122B and the second diffusion barrier layer 122C, the dielectric barrier layer 124B may be configured to prevent or minimize the diffusion of oxygen atoms from the ILD layer 119 to the contact plug 122D. In some embodiments, the dielectric barrier layers 124A and 124B may include an oxygen-free dielectric nitride layer (e.g., a SiN layer), an oxygen-free dielectric carbide layer (e.g., a silicon carbide (SiC) layer), or an oxygen-free carbonitride layer (e.g., a silicon carbonitride (SiCN) layer).

[0090] The S / D contact structure 120 on the S / D region 110A can be electrically connected to an overlying interconnect structure (not shown), a power supply (not shown), and / or other components of the FET 100 through the via structure 126. The via structure 126 can be disposed in the S / D contact structure 120 and can include a conductive material such as Ru, W, Ni, Al, Mo, Ir, Os, and other suitable conductive materials. In some embodiments, the conductive material of the via structure 126 is formed by a bottom-up method, and thus, the via structure 126 can be formed without an adhesion layer (also referred to as a "liner" or "glue layer") along the sidewalls of the via structure 126. In some embodiments, the bottom surface of the via structure 126 can have a curved profile to increase the contact area between the via structure 126 and the contact plug 120D, and thus reduce the contact resistance between the via structure 126 and the contact plug 120D. In some embodiments, the via structure 126 can have a diameter (or width) of about 11 nm to about 17 nm along the X-axis and a height of about 15 nm to about 35 nm along the Z-axis to provide sufficient contact area and good conductivity between the S / D contact structure 120 and the overlying interconnect structure (not shown) without affecting the device size and manufacturing cost.

[0091] Each of the gate structures 112A - 112C can be a multi-layer structure and can surround the nanostructure channel region 108, and for the nanostructure channel region 108, the gate structures 112A - 112C can be referred to as "GAA structures". In some embodiments, each of the gate structures 112A - 112C can include a gate stack 128 and a gate capping structure 130. In some embodiments, the gate stack 128 can include (i) an interfacial oxide layer (IL) 128A, (ii) a high-k (HK) gate dielectric layer 128B disposed on the IL layer 128A, (iii) a work function metal (WFM) layer 128C disposed on the HK gate dielectric layer 128B, and (iv) a gate metal fill layer 128D disposed on the WFM layer 128C.

[0092] In some embodiments, the IL layer 128A can include silicon oxide (SiO 2 ), silicon germanium oxide (SiGeO x ), germanium oxide (GeO x ), or other suitable oxide materials. In some embodiments, the HK gate dielectric layer 128B can include a high-k dielectric material such as hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 3) Hafnium silicate (HfSiO 4 ) Zirconium oxide (ZrO 2 ) Zirconium silicate (ZrSiO 2 ) or other suitable high-k dielectric materials. In some embodiments, the WFM layer 128C for the n-type FET 100 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped titanium nitride, or other suitable aluminum-based materials. In some embodiments, the WFM layer 128C for the p-type FET 100 may include titanium-based or tantalum-based nitrides or alloys that are substantially aluminum-free (e.g., no aluminum), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the gate metal fill layer 128D may include a conductive material such as W, Ti, Ru, Mo, Co, Al, Ir, Ni, metal alloys, and combinations thereof.

[0093] In some embodiments, the gate capping structure 130 may include a conductive gate cap 130A disposed on the gate stack 128 and an insulating gate cap 130B disposed on the conductive gate cap 130A.

[0094] The conductive gate cap 130A may provide a conductive interface between the gate metal fill layer 128D and the overlying contact structures (e.g., the gate contact structure 132 and the combined via contact structure 134) without directly forming a contact structure above or within the gate metal fill layer 128D. The contact structure is not directly formed above or within the gate metal fill layer 128D to prevent contamination by any processing materials used to form the contact structure. Contamination of the gate metal fill layer 128D can lead to a degradation in device performance. Thus, by using the conductive gate cap 130A, the gate structures 112A-112C can be electrically connected to the contact structures without compromising the integrity of the gate structures 112A-112C. In some embodiments, the conductive gate cap 130A may include a conductive material such as W, Ru, Mo, Co, or other suitable conductive materials.

[0095] The insulating gate cap 130B may protect the underlying conductive gate cap 130A and the gate stack 128 from structural and / or compositional degradation during subsequent processing of the FET 100. In some embodiments, the insulating gate cap 130B may include a nitride material such as SiN and may have a thickness of about 2 nm to about 10 nm to adequately protect the underlying conductive gate cap 130A and the gate stack 128.

[0096] In some embodiments, the gate structures 112A - 112C can be electrically isolated from adjacent S / D regions 110A - 110C and the S / D contact structures 120 through the gate spacers 114 and the inner spacers 115. In some embodiments, the gate spacers 114 and the inner spacers 115 can include insulating materials such as SiO x , SiN, silicon oxynitride (SiON), silicon oxycarbide (SiOC), SiCN, silicon oxycarbonitride (SiOCN), and other suitable insulating materials.

[0097] In some embodiments, the gate contact structure 132 can include a liner 132A and a contact plug 132B disposed on the liner 132A. In some embodiments, the liner 132A can include a nitride material such as TiN, and the contact plug 132B can include a conductive material similar to the via structure 126. In some embodiments, the liner 132A can include TiN and the contact plug 132B can include W. In some embodiments, the liner 132A can include TaN and the contact plug 132B can include Ru.

[0098] In some embodiments, the merged via contact structure 134 can be disposed on the S / D region 110B and the gate structure 112C. When the FET 100 is formed in the logic element region and / or the static random access memory (SRAM) element region of an integrated circuit (not shown), the merged via contact structure 134 can electrically connect the S / D region 110B and the gate structure 112C to each other and to an overlying interconnect structure (not shown). The merged via contact structure 134 can include a liner 134A and a contact plug 134B disposed on the liner 134A. In some embodiments, the liner 134A and the contact plug 134B can include materials similar to the liner 132A and the contact plug 132B, respectively.

[0099] In some embodiments, the STI regions 116, the ESLs 117A and 117B, and the ILD layers 118A - 118C and 119 can include insulating materials such as SiO 2 , SiN, SiON, SiOC, SiCN, SiOCN, and SiGeO x .

[0100] Reference Figure 1C, in some embodiments, the FET 100 can be a finFET instead of a GAA FET, and can have a fin structure 106 instead of a nanostructured channel region 108 and a fin substrate 106. The finFET can have gate structures 112A-112C disposed on the fin structure 106, where the fin regions can serve as channel regions.

[0101] Figure 2 A flowchart illustrating an exemplary method 200 for manufacturing the FET 100 is shown according to some embodiments. For illustrative purposes, reference will be made to an exemplary manufacturing process for manufacturing the FET 100 as Figures 3 to 18 shown to describe Figure 2 the operations shown. Figures 3 to 11 and Figures 13 to 18 are cross-sectional views of the FET 100 along Figure 1A line A-A at various manufacturing stages according to some embodiments. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that the method 200 may not result in a complete FET 100. Therefore, it should be understood that additional processes can be provided before, during, and after the method 200, and some other processes may only be briefly described herein. Unless otherwise specified, Figure 1A , Figure 1B and Figures 3 to 18 the discussion of elements with the same reference numerals in

[0102] Reference is made to Figure 2 , in operation 205, a superlattice structure is formed on the fin substrate, and a polysilicon structure and S / D regions are formed on the superlattice structure. For example, as described with reference to Figure 3 , a superlattice structure 307 is formed on the fin substrate 106, a polysilicon structure 312 is formed on the superlattice structure 307, and S / D regions 110A-110C are formed in the superlattice structure 307. The superlattice structure 307 can include nanostructured layers 108 and nanostructured layers 308 arranged in an alternating configuration. In some embodiments, the nanostructured layer 108 and the nanostructured layer 308 include different materials from each other. The nanostructured layer 308 is also referred to as the "sacrificial layer 308". During subsequent processing, the polysilicon structure 312 and the sacrificial layer 308 can be replaced in a gate replacement process to form the gate structures 112A-112C. In some embodiments, an internal spacer 115 can be formed after the polysilicon structure 312 is formed and before the S / D regions 110A-110C are formed. After the S / D regions 110A-110C are formed, an ESL 117A (as shown in Figure 1A ; not shown for simplicity in Figures 3 to 11 and Figures 13 to 18 ) and an ILD layer 118A, as shown in Figure 3as shown

[0103] Reference Figure 2 , in operation 210, a gate structure replaces the sacrificial layers of the polysilicon structure and the superlattice structure. For example, as described in reference Figures 4 to 6 , gate structures 112A - 112C replace the polysilicon structure 312 and the sacrificial layer 308. The formation of the gate structures 112A - 112C may include the following sequential operations: (i) removing the polysilicon structure 312 and the sacrificial layer 308, (ii) forming a gate stack 128 on the nanostructure layer 108, as Figure 4 shown, (iii) etching the gate stack 128 to form a gate capping opening 540, as Figure 5 shown, and (iv) forming a gate capping structure 130 on the gate stack 128, as Figure 6 shown. After forming the gate structures 112A - 112C, an ILD layer 118B may be formed, as Figure 7 shown.

[0104] Reference Figure 2 , in operation 215, an S / D contact structure is formed on the front - side surface of the S / D region. For example, as described in reference Figures 7 to 16 , an S / D contact structure 120 is formed on the S / D regions 110A and 110B. The formation of the S / D contact structure may include the following sequential operations: (i) forming an S / D contact opening 742, as Figure 7 shown, (ii) depositing a dielectric layer 824 on the Figure 7 structure to form the Figure 8 structure, (iii) performing a chemical mechanical polishing (CMP) process on the dielectric layer 824 to form a dielectric barrier layer 124A, as Figure 9 shown, (iv) forming a silicide layer 120A, as Figure 9 shown, (v) depositing a first conductive nitride layer 1020 (e.g., a TiN layer or a TaN layer) on the Figure 9 structure to form the Figure 10 structure, (vi) performing an oxide removal process (also referred to as an "oxygen removal process" or a "cleaning process") on the Figure 10 structure to remove the native oxide layer 1044 and / or oxygen atoms from the exposed surface of the first conductive nitride layer 1020 to form the Figure 11 structure, (vii) depositing a second conductive nitride layer 1320 (e.g., a TiN layer or a TaN layer) on the Figure 11 structure to form the Figure 13 structure, (viii) using a CVD or ALD process on the Figure 13A first metal layer 1420 (eg, a Co layer) is deposited on the structure to form Figure 14 (ix) using electroplating technology on Figure 14 A second metal layer 1520 (eg, a Co layer) is deposited on the structure to form Figure 15 The structure of (x) Figure 15 The structure is subjected to a CMP process to form an S / D contact structure 120, such as Figure 16 shown.

[0105] In some embodiments, depositing the first conductive nitride layer 1020 may include using a chemical vapor deposition (CVD) process using a Ti or Ta precursor gas and ammonia (NH 3 ) gas to deposit a TiN layer or TaN. A CVD process may be used to form the first conductive nitride layer 1020, because NH 3 The gas may react with the Ti or Ta precursor gas to form a TiN or TaN layer as the first conductive nitride layer 1020, and at the same time, a residual metal (eg, Ti) layer 920 (eg, Figure 9 1020). The residual metal layer 920 may be part of a metal layer (not shown) deposited during the formation of the metal silicide layer 120A. In some embodiments, silicon atoms of the dielectric barrier layer 124A may diffuse into or react with the TiN or TaN layer of the first conductive nitride layer 1020 to form TiSiN or TaSiN. The first conductive nitride layer 1020 may form a first diffusion barrier layer 120B in a subsequent process.

[0106] In some embodiments, depositing the second conductive nitride layer 1320 may include depositing a TiN layer or TaN using an atomic layer deposition (ALD) process. The second conductive nitride layer 1320 may form a second diffusion barrier layer 120C in a subsequent process. The deposition processes of the first conductive nitride layer 1020 and the second conductive nitride layer 1320 are performed ex situ, so a vacuum break is introduced between the deposition processes of the first conductive nitride layer 1020 and the second conductive nitride layer 1320. Due to the vacuum break, the native oxide layer 1044 and / or oxygen atoms may be introduced onto the exposed surface of the first conductive nitride layer 1020.

[0107] In some embodiments, the oxide removal process for removing the native oxide layer 1044 and / or oxygen atoms may include performing a plasma etching process using hydrogen radicals in a processing chamber at a high temperature of about 350 °C to about 450 °C and at a bias power of about 0.5 W to about 5 W in a gas mixture 1146 having hydrogen and nitrogen. In some embodiments, the concentration ratio of hydrogen to nitrogen in the gas mixture 1146 may be about 4:1 to about 6:1 to sufficiently remove the native oxide layer 1044 and / or oxygen atoms and reduce the concentration of oxygen atoms on the exposed surface of the first conductive nitride layer 1020 to less than about 5 atomic % (e.g., about 0.1 atomic % to about 4.9 atomic %). In some embodiments, the oxide removal process may include supplying hydrogen at a flow rate of about 30 sccm to about 50 sccm and supplying nitrogen at a flow rate of about 5 sccm to about 20 sccm to achieve a concentration ratio of hydrogen to nitrogen in the gas mixture 1146 of about 4:1 to about 6:1.

[0108] Figure 12 Shows a reduction in the concentration of oxygen atoms on the exposed surface of the first conductive nitride layer 1020 after performing the oxide removal process. Figure 12 Shows along before performing the oxide removal process Figure 10 the concentration profile 1248 of oxygen atoms along line C-C of, and along after performing the oxide removal process Figure 11 the concentration profile 1250 of oxygen atoms along line D-D of. In some embodiments, the peak concentration of the concentration profile 1250 may be less than about 5 atomic %, and may be about 80% to about 90% lower than the peak concentration of the concentration profile 1248.

[0109] In some embodiments, the oxide removal process, the deposition process of the second conductive nitride layer 1320, and the deposition process of the first metal layer 1420 are performed in-situ, without introducing a vacuum break between performing each process. After forming the S / D contact structure 120, the ESL 117B and the ILD layer 118C may be formed, as Figure 17 shown.

[0110] Referring to Figure 2 , in operation 220, a via structure is formed on one of the S / D contact structures. For example, as Figure 17 shown, a via structure 126 is formed through the ILD layer 118C and the ESL 117B and in the S / D contact structure 120 on the S / D region 110A.

[0111] Referring to Figure 2 , in operation 225, a gate contact structure is formed on the first gate structure, and a combined via contact structure is formed on the second S / D contact structure and the second gate structure. For example, as Figure 17As shown, a gate contact structure 132 is formed on a gate structure 112A, and a merged via contact structure 134 is simultaneously formed on the S / D regions 110B and the gate structure 112C.

[0112] Refer to Figure 2 , in operation 230, an S / D contact structure is formed on the back surface of the S / D region. For example, as Figure 18 shown, an S / D contact structure 122 is formed on the backside surfaces of the S / D regions 110A and 110B. The formation of the S / D contact structure 122 may include the following sequential operations: (i) removing portions of the fin substrate 106 and the substrate 104 below the S / D regions 110A and 110B to form an opening (not shown), (ii) forming a dielectric barrier layer 124B in the opening, and (iii) forming the S / D contact structure 122 in the opening. The operations of forming the silicide layer 122A, the first diffusion barrier layer 122B, the second diffusion barrier layer 122C, and the contact plug 122D of the S / D contact structure 122 and the dielectric barrier layer 124B may be similar to those of forming the silicide layer 120A, the first diffusion barrier layer 120B, the second diffusion barrier layer 120C, and the contact plug 120D and the dielectric barrier layer 124A of the S / D contact structure 120, as described in operation 215. After forming the S / D contact structure 122, the substrate 104 may be replaced with an ILD layer 119, as Figure 18 shown.

[0113] The present disclosure provides exemplary methods (e.g., method 200) for minimizing contact resistance between a contact structure and a source / drain (S / D) region in a FET (e.g., FET 100). In some embodiments, the S / D regions (e.g., S / D regions 110A - 110C) may be formed on a fin substrate (e.g., fin substrate 106), and contact structures (e.g., S / D contact structures 120 and 122) may be formed on the S / D regions. In some embodiments, forming the contact structures may include depositing a first diffusion barrier layer (e.g., first diffusion barrier layer 1020) in a contact opening (e.g., contact opening 742) on the S / D region, depositing a second diffusion barrier layer (e.g., second diffusion barrier layer 1320) on the first diffusion barrier layer, and depositing a conductive layer (e.g., metal layer 1520) on the second diffusion barrier layer. In some embodiments, forming the contact structures may further include performing an oxide removal process (also referred to as a “cleaning process”) on the first diffusion barrier layer before depositing the second diffusion barrier layer. The oxide removal process may remove a native oxide layer (e.g., native oxide layer 1044) and / or oxygen atoms from the top surface of the first diffusion barrier layer to reduce the oxygen atom concentration on the top surface of the first diffusion barrier layer to less than about 5 atomic % (e.g., from about 0.1 atomic % to about 4.9 atomic %). The native oxide layer and / or oxygen atoms on the top surface of the first diffusion barrier layer are introduced due to the reaction between atmospheric oxygen and the material of the first diffusion barrier layer during vacuum break between depositing the first and second diffusion barrier layers. The presence of the native oxide layer and / or oxygen atoms at the interface between the first and second diffusion barrier layers reduces the conductivity between the contact structure and the S / D region. Thus, the oxide removal process may minimize the contact resistance between the contact structure and the S / D region.

[0114] In some embodiments, a method of manufacturing a semiconductor device includes forming a nanostructured layer on a substrate, forming a gate structure surrounding the nanostructured layer, forming S / D regions adjacent to the nanostructured layer, forming contact openings in the S / D regions, depositing a first conductive layer in the contact openings using a first deposition process, performing a plasma etching process on the first conductive layer, depositing a second conductive layer on the first conductive layer using a second deposition process different from the first deposition process, and depositing a metal layer on the second conductive layer.

[0115] In some embodiments, depositing the first conductive layer includes depositing a conductive nitride layer by a chemical vapor deposition process. In some embodiments, depositing the second conductive layer includes depositing a conductive nitride layer by an atomic layer deposition process. In some embodiments, performing a plasma etching process includes etching a native oxide layer from the surface of the first conductive layer. In some embodiments, performing a plasma etching process includes etching a native oxide layer from the surface of the first conductive layer with hydrogen radicals. In some embodiments, performing a plasma etching process includes etching a native oxide layer from the surface of the first conductive layer using a gas mixture having a hydrogen to nitrogen concentration ratio of from about 4:1 to about 6:1. In some embodiments, performing a plasma etching process includes etching a native oxide layer from the surface of the first conductive layer at a temperature of from about 350 °C to about 450 °C. In some embodiments, depositing the first conductive layer and depositing the second conductive layer are performed ex-situ. In some embodiments, the plasma etching process, depositing the second conductive layer, and depositing the metal layer are performed in-situ. In some embodiments, further includes depositing an oxygen-free nitride layer in the contact opening before depositing the first conductive layer.

[0116] In some embodiments, a method of manufacturing a semiconductor device includes forming a gate structure on a substrate, forming source / drain (S / D) regions adjacent to the gate structure, and forming a contact structure. Forming the contact structure includes forming a contact opening in the S / D region, depositing a first nitride layer in the contact opening, removing a native oxide layer from the surface of the first nitride layer, depositing a second nitride layer on the first nitride layer, and depositing a metal layer on the second nitride layer.

[0117] In some embodiments, depositing the first nitride layer includes depositing titanium nitride by a chemical vapor deposition process. In some embodiments, depositing the second nitride includes depositing titanium nitride by an atomic layer deposition process. In some embodiments, removing the native oxide layer includes performing an etching process with a gas mixture having a hydrogen to nitrogen concentration ratio of from about 4:1 to about 6:1. In some embodiments, removing the native oxide layer is performed at a temperature of from about 350 °C to about 450 °C. In some embodiments, removing the native oxide layer, depositing the second nitride layer, and depositing the metal layer are performed in-situ.

[0118] In some embodiments, a semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, source / drain (S / D) regions disposed adjacent to the nanostructured channel region, and a contact structure. The contact structure includes a first diffusion barrier layer disposed on the S / D region, a second diffusion barrier layer disposed on the first diffusion barrier layer, and a metal layer disposed on the second diffusion barrier layer. The oxygen atom concentration at the interface between the first diffusion barrier layer and the second diffusion barrier layer is less than about 5 atomic %.

[0119] In some embodiments, it further includes an oxygen-free nitride layer surrounding the contact structure. In some embodiments, the first diffusion barrier layer includes a titanium silicon nitride layer. In some embodiments, the second diffusion barrier layer includes a titanium nitride layer.

[0120] The foregoing outlines the features of several embodiments such that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may readily be utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made therein within the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a nanostructure layer on a substrate; forming a gate structure surrounding the nanostructure layer; forming a source / drain region adjacent to the nanostructure layer; forming a contact opening on the source / drain region; Depositing a first conductive layer in the contact opening by a first deposition process; performing a plasma etching process on the first conductive layer; Depositing a second conductive layer on the first conductive layer by a second deposition process different from the first deposition process; and A metal layer is deposited on the second conductive layer.

2. The method according to claim 1, characterized in that Depositing the first conductive layer and depositing the second conductive layer are performed ex-situ.

3. The method according to claim 1, characterized in that The plasma etching process, the deposition of the second conductive layer, and the deposition of the metal layer are performed in situ.

4. A method for manufacturing a semiconductor device, characterized in that: include: forming a gate structure on a substrate; forming a source / drain region adjacent to the gate structure; and A contact structure is formed, comprising: forming a contact opening on the source / drain region; depositing a first nitride layer in the contact opening; removing a native oxide layer from a surface of the first nitride layer; depositing a second nitride layer on the first nitride layer; and A metal layer is deposited on the second nitride layer.

5. The method according to claim 4, characterized in that Depositing the first nitride layer includes depositing titanium nitride using a chemical vapor deposition process.

6. The method according to claim 4, characterized in that Depositing the second nitride includes depositing titanium nitride using an atomic layer deposition process.

7. A semiconductor device, characterized in that: include: a substrate; a nanostructure channel region, disposed on the substrate; a gate structure surrounding the nanostructure channel region; a source / drain region disposed adjacent to the nanostructure channel region; and A contact structure comprising: a first diffusion barrier layer disposed on the source / drain region; a second diffusion barrier layer disposed on the first diffusion barrier layer, wherein an oxygen atomic concentration at an interface between the first diffusion barrier layer and the second diffusion barrier layer is less than 5 atomic %; and A metal layer is disposed on the second diffusion barrier layer.

8. The semiconductor device according to claim 7, wherein: Further included is an oxygen-free nitride layer surrounding the contact structure.

9. The semiconductor device according to claim 7, wherein: The first diffusion barrier layer includes a titanium silicon nitride layer.

10. The semiconductor device according to claim 7, wherein: The second diffusion barrier layer includes a titanium nitride layer.

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