Device for manufacturing side wall at preset position in vertical direction and manufacturing process thereof

Abstract

The invention discloses a device for manufacturing a side wall at a preset position in the vertical direction and a manufacturing process thereof. According to an embodiment, a semiconductor device may include a first constituent device on a substrate and a second constituent device stacked on the first constituent device. Each of the first constituent device and the second constituent device includes: a first source / drain layer; a second source / drain layer over the first source / drain layer; the channel layer vertically extends from the side wall of the first source / drain layer to the side wall of the second source / drain layer; and a gate stack on one side of the channel layer back to the side wall of the first source / drain layer and the side wall of the second source / drain layer. Between the gate stack of the first constituent device and the gate stack of the second channel device, the dielectric layer vertically extends from the sidewall of the second source / drain layer of the first constituent device to the sidewall of the first source / drain layer of the second constituent device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly, to a device for fabricating sidewalls at a preset position in the vertical direction and a manufacturing process thereof. Background Art

[0002] Vertical channel transistor (VCT) technology is considered to be one of the key technologies for future improvement of integration density and continuation of Moore's Law. The vertical structure device poses many new requirements for thin film deposition and etching processes, making the manufacturing and structural improvement of vertical devices difficult. The current method is to reduce the manufacturing difficulty by adding some self-alignment structures in the structural design.

[0003] In addition, VCT currently lacks a corresponding sidewall process in the vertical direction, and there are certain technical difficulties in realizing the vertical device structure. Summary of the Invention

[0004] In view of this, at least part of the purpose of the present disclosure is to provide a device for fabricating sidewalls at a preset position in the vertical direction and a manufacturing process thereof.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided, including a first constituent device on a substrate and a second constituent device stacked on the first constituent device. Each of the first constituent device and the second constituent device includes: a first source / drain layer; a second source / drain layer above the first source / drain layer; a channel layer vertically extending from the sidewall of the first source / drain layer to the sidewall of the second source / drain layer; and a gate stack on one side of the sidewalls of the channel layer facing away from the sidewalls of the first source / drain layer and the second source / drain layer. Between the gate stack of the first constituent device and the gate stack of the second channel device, a dielectric layer vertically extends from the sidewall of the second source / drain layer of the first constituent device to the sidewall of the first source / drain layer of the second constituent device.

[0006] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a vertical stack on a substrate including the following layers sequentially arranged: a first source / drain defining layer of a first constituent device, a channel defining layer, and a second source / drain defining layer, a first dopant source layer, a first source / drain defining layer of a second constituent device, a channel defining layer, and a second source / drain defining layer, and a second dopant source layer; forming a spacer defining layer on sidewalls of the vertical stack; driving dopants from the first dopant source layer and the second dopant source layer into the spacer defining layer respectively, thereby forming doping regions corresponding to the first dopant source layer and the second dopant source layer respectively in the spacer defining layer; selectively etching the spacer defining layer to retain the doping regions therein and removing the remaining portions; forming a channel layer extending between the spacers on sidewalls of the vertical stack; and forming a gate stack on a side of the channel layer facing away from the sidewalls, wherein the spacers between vertically adjacent gate stacks are defined by the doping regions.

[0007] According to another aspect of the present disclosure, there is provided an electronic device including the above semiconductor device.

[0008] According to an embodiment of the present disclosure, vertical spacers are realized, making it easier to fabricate vertical devices, especially stacked vertical devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent. In the drawings:

[0010] Figures 1(a) to 21 Schematically illustrated are some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0011] Figures 22(a) to 26 Schematically illustrated is a process using a support structure according to an embodiment of the present disclosure.

[0012] Throughout the drawings, the same or similar reference numerals denote the same or similar components. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0014] Schematic diagrams of various structures according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where certain details are enlarged for the purpose of clear illustration, and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual requirements.

[0015] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0016] The present disclosure can be presented in various forms, and some examples will be described below. In the following description, the selection of various materials is involved. In addition to considering its function (e.g., semiconductor materials are used to form active regions, and dielectric materials are used to form electrical isolation), the etching selectivity is also considered when selecting materials. In the following description, the required etching selectivity may or may not be indicated. Those skilled in the art should be clear that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or other layers are not shown as being etched in the figures, then this etching can be selective, and the material layer can have etching selectivity with respect to other layers exposed to the same etching recipe.

[0017] Figures 1(a) to 21 Some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure are schematically shown.

[0018] As Figure 1(a) and 1(b) (a top view and a cross-sectional view along line AA', respectively) show, a substrate 1001 is provided. The substrate 1001 can be various forms of substrates, including but not limited to a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, etc. In the following description, for the convenience of explanation, a bulk Si substrate is taken as an example for description. Here, a silicon wafer is provided as the substrate 1001.

[0019] On a substrate 1001, the following can be sequentially formed: a first source / drain definition layer 1003 for a first constituent device, a channel definition layer 1005, and a second source / drain definition layer 1007, a first dopant source layer 1009, a first source / drain definition layer 1011 for a second constituent device, a channel definition layer 1013, and a second source / drain definition layer 1015, and a second dopant source layer 1017.

[0020] Each of the source / drain definition layers 1003, 1007, 1011, 1015 can be used to form or define the source / drain layers of the first and second constituent devices respectively, and can include a material having an etching selectivity with respect to the channel definition layers 1005, 1013 and the dopant source layers 1009, 1017.

[0021] The channel definition layers 1005, 1013 can respectively define the positions of the channels of the first and second constituent devices, and can include a material having an etching selectivity with respect to each of the source / drain definition layers 1003, 1007, 1011, 1015 and the dopant source layers 1009, 1017.

[0022] The first dopant source layer 1009 and the second dopant source layer 1017 contain a dopant such as boron (B) for use as a diffusion source of the dopant in subsequent processes.

[0023] According to an embodiment of the present disclosure, a non-single crystal device or a single crystal device can be formed.

[0024] In one example, an indium gallium zinc oxide (IGZO) transistor can be formed. In this case, each of the source / drain definition layers 1003, 1007, 1011, 1015 can include a metal such as tungsten (W), and each thickness is, for example, about 20 nm - 200 nm. Considering the etching selectivity, the channel definition layers 1005, 1013 can include an oxide (e.g., silicon oxide), and the thickness is, for example, about 20 nm - 50 nm. The first dopant source layer 1009 and the second dopant source layer 1017 can be formed as an amorphous structure, such as a polycrystalline film or an amorphous film. For example, the first dopant source layer 1009 and the second dopant source layer 1017 can include a silicon (Si) film with a thickness of, for example, about 20 nm - 200 nm and containing, for example, about 0.1% - 5% of the dopant. These layers can be formed by, for example, deposition such as chemical vapor deposition (CVD), etc.

[0025] Here, using a silicon film can facilitate processing with a sidewall definition layer in subsequent processes. However, the present disclosure is not limited thereto. For example, the first dopant source layer 1009 or the second dopant source layer 1017 can also include a dielectric material containing a dopant such as an oxide.

[0026] In another example, the above-described layers may be, for example, single-crystalline layers formed by epitaxial growth, and each layer may include materials selected according to the etching selectivity as described above. For example, non-Si-based transistors such as GaAs transistors may be formed, and each layer may have a desired etching selectivity by element ratio and / or including different elements. Alternatively, Si-based transistors may be formed, and each layer may include, for example, Si or SiGe to have a desired etching selectivity.

[0027] Above the above-described material layer, a hard mask for assisting in patterning may be formed. In this example, an etch stop layer 1019, a core mold layer 1021, and a hard mask layer 1023 may be formed by deposition. For example, the etch stop layer 1019 may include an oxide with a thickness of about 1 nm - 10 nm; the core mold layer 1021 may include polysilicon with a thickness of about 50 nm - 150 nm; the hard mask layer 1023 may include a nitride (e.g., silicon nitride) with a thickness of about 30 nm - 100 nm. Note that according to the patterning process, the hard mask may have different numbers of layers and may have different materials.

[0028] An active region may be defined from the above-described layers. According to an embodiment of the present disclosure, the definition of the active region may be based on sidewall image transfer (SIT) technology to improve pattern size control.

[0029] For example, as Figure 2(a) and 2(b) (a top view and a cross-sectional view along line AA′, respectively) shown, a photoresist (not shown) may be formed on the hard mask layer 1023 and patterned by photolithography into a strip extending in a first direction (e.g., the vertical direction in the plane of the paper in the top view of FIG. 2(a)). The photoresist thus patterned is used as an etch mask, and by, for example, reactive ion etching (RIE) in the vertical direction, the hard mask layer 1023 and the core mold layer 1021 are anisotropically etched in sequence to transfer the pattern of the photoresist into the hard mask layer 1023 and the core mold layer 1021. The etching may stop at the etch stop layer 1019. Here, the etch stop layer 1019 may also be further anisotropically etched. After that, the photoresist may be removed.

[0030] Sidewalls may be formed on the sidewalls of the core mold layer 1021 on opposite sides in a second direction (e.g., the horizontal direction in the plane of the paper in the top view of FIG. 2(a)) intersecting (e.g., perpendicular) to the first direction. For example, as Figure 3 shown, on the resulting structure, a preliminary sidewall layer 1025p may be formed by deposition. The preliminary sidewall layer 1025p may be formed in a substantially conformal manner (in Figure 3In [description], merely for the convenience of illustration, for example, to more clearly show the subsequently formed sidewalls and the active regions defined thereby, the film thickness of the vertical extension portion of the preliminary sidewall layer 1025p is magnified, so that in the illustration, the film thickness of the vertical extension portion of the sidewall layer 1025p appears to be greater than that of the horizontal extension portion, but they can be substantially equal to each other). Considering the etching selectivity, the preliminary sidewall layer 1025p can include nitride. As Figure 4 shown, the preliminary sidewall layer 1025p can be anisotropically etched, for example, by RIE in the vertical direction. The etching depth can be substantially equal to (or slightly greater than) the film thickness of its horizontal extension portion. Thus, the vertical extension portion of the preliminary sidewall layer 1025p can be left to form the sidewall 1025. Note that due to the control of the etching depth, the hard mask layer 1023, which is also nitride in this example, can be retained.

[0031] An isolation process can be performed, for example, forming trenches in the above layers to separate the above layers into several vertical stacks, thereby defining device active regions. For example, as Figure 5 shown, the hard mask layer 1023 and the sidewall 1025 can be used as etching masks to anisotropically etch the layers on the substrate 1001 in sequence, for example, by RIE in the vertical direction. Figure 5 The vertical stacks isolated in the second direction (for example, the horizontal direction in the plane of the paper) are shown in [description].

[0032] It should be noted that in the first direction (for example, the direction perpendicular to the plane of the paper), isolation can be performed here together. For example, in the process described in combination with Figure 2(a) and 2(b) the hard mask layer 1023 and the core mold layer 1021 can be patterned into patterns whose sizes are defined in both the first direction and the second direction, such as rectangles or squares, rather than strips extending along the first direction. In this case, the sidewall 1025 can be formed as a closed figure surrounding the outer periphery of the pattern, such as a rectangular ring or a square ring. In the isolation process described in combination with Figure 5 using the thus formed hard mask layer 1023 and sidewall 1025 as etching masks, vertical stacks whose sizes are defined in both the first direction and the second direction can be obtained. Alternatively, isolation can be performed later. Different orders of the isolation process do not affect the fabrication of the device, but may result in different channel forms.

[0033] On the sidewalls of the vertical stacks, a sidewall defining layer can be formed to subsequently define sidewalls on the sidewalls of the vertical stacks. For example, as Figure 6As shown, the sidewall defining layer 1027 can be formed in a substantially conformal manner. As described above, in this embodiment, the sidewall defining layer 1027 can include a silicon film so as to be processed together with the dopant source layer in subsequent processes. The silicon film can be a non-single-crystalline silicon film such as a polysilicon film or an amorphous silicon film (e.g., in the case of forming a non-single-crystalline transistor), and can be formed by deposition. Alternatively, the silicon film can be a single-crystalline silicon film (e.g., in the case of forming a single-crystalline transistor), and can be formed by (selective) epitaxial growth. In the process of selective epitaxial growth, the silicon film may not be formed on the hard mask layer 1023 and the sidewall 1025. The formed silicon film may not be intentionally doped, and the thickness is, for example, about 40 nm - 80 nm. Here, the reason for using the silicon film is mainly that the silicon film can have an etching selectivity due to different doping concentrations. Alternatively, other materials that can have an etching selectivity due to different doping concentrations can also be selected, and even dielectric materials can be used.

[0034] The sidewall defining layer 1027 formed in this way extends on the vertical sidewalls (and the top surface) of the vertical stack. The sidewall self-aligned to the dopant source layer can be defined by diffusion doping. For example, as Figure 7 shown, an annealing process can be performed to drive or diffuse the dopants in the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027. Specifically, the dopants can laterally diffuse from the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027, and the dopants entering the sidewall defining layer 1027 can diffuse upward and downward, thereby defining a certain range of doped regions 1029 in the vertical direction in the sidewall defining layer 1027.

[0035] Here, the upward and downward diffusion conditions can be substantially the same, so the upward and downward diffusion ranges can be substantially the same. Therefore, the doped regions 1029 at the respective ends of the first dopant source layer 1009 and the second dopant source layer 1017 can be vertically symmetric with respect to the corresponding dopant source layer, that is, the height from the end of the corresponding dopant source layer upward can be substantially equal to the height from the end of the corresponding dopant source layer downward.

[0036] In the case where the materials and thicknesses of the first dopant source layer 1009 and the second dopant source layer 1017 and the types and concentrations of the dopants therein are all substantially the same, the diffusion from the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027 can also be substantially the same. Therefore, the doped regions at the ends of the first dopant source layer 1009 and the doped regions at the ends of the second dopant source layer 1017 can have substantially the same height.

[0037] The doped region 1029 can be self-aligned with the first dopant source layer 1009 and the second dopant source layer 1017 because it is defined by diffusion from the first dopant source layer 1009 and the second dopant source layer 1017. Additionally, the degree of diffusion can be controlled by controlling the annealing process parameters. Thus, the position and height of the doped region 1029 (and the sidewall defined thereby) can be well controlled.

[0038] Here, although each source / drain defining layer may also include dopants, the type and / or concentration of the dopants in the dopant source layer can be appropriately selected such that even if there is diffusion from the source / drain defining layer in the sidewall defining layer, the doped region 1029 caused by the diffusion from the dopant source layer still has an etching selectivity with respect to the rest of the sidewall defining layer due to the doping type and / or concentration. Thus, although the doped region 1029 can extend on a partial sidewall of each source / drain defining layer, it may not extend to the entire sidewall of each source / drain defining layer.

[0039] As Figure 8 shown, the sidewall defining layer 1027 in which the doped region 1029 is formed can be selectively etched. An etching recipe can be selected such that the doped region 1029 can be substantially retained while the other parts of the sidewall defining layer 1027 are removed. This can be due to different etching rates caused by different doping concentrations in the sidewall defining layer 1027.

[0040] Then, the doped region 1029 can remain on the vertically stacked sidewalls (self-aligned with the dopant source layers 1009, 1017). In the case where the sidewall defining layer 1027 is a dielectric material, such a doped region 1029 can directly form the sidewall. Or, in the case where the sidewall defining layer 1027 is, for example, a silicon film, the sidewall can be defined by the doped region 1029 through an oxidation process or a replacement process as described below. Hereinafter, for convenience, the doped region 1029 remaining on the vertically stacked sidewalls is referred to as the sidewall.

[0041] The sidewall 1029 defines a channel layer formation region on the vertically stacked sidewalls. More specifically, the channel layer can be formed on the vertically stacked sidewalls between the sidewalls 1029 adjacent in the vertical direction.

[0042] For example, as Figure 9As shown, a preliminary channel layer 1031p can be formed in a substantially conformal manner. The preliminary channel layer 1031p can include a suitable semiconductor material. In this embodiment, the preliminary channel layer 1031p can include a silicon film. Similarly, the preliminary channel layer 1031p can include a single crystal material (e.g., in the case of forming a single crystal transistor) and can be formed by, for example, epitaxial growth; or, can include a non-single crystal material (e.g., in the case of forming a non-single crystal transistor) and can be formed by, for example, deposition. The formed silicon film can be unintentionally doped or lightly doped to adjust the threshold voltage (V t ).

[0043] On the preliminary channel layer 1031p, a sacrificial gate can be formed for subsequent formation of a self-aligned gate stack. For example, a preliminary sacrificial gate layer 1033p can be formed by deposition such as CVD. The preliminary sacrificial gate layer 1033p can include an oxide and can be formed in a substantially conformal manner, and the portion thereof extending between the sidewalls 1029 can cover the preliminary channel layer 1031p and at least partially fill or even substantially completely fill the void between the vertically adjacent sidewalls 1029 (after forming the preliminary channel layer 1031p).

[0044] The continuously extending preliminary channel layer 1031p can be separated into portions extending between the first source / drain defining layer and the second source / drain defining layer of each device. For example, as Figure 10 shown, the preliminary sacrificial gate layer 1033p and the preliminary channel layer 1031p formed as described above can be anisotropically etched, for example, by RIE in the vertical direction. Thus, the preliminary sacrificial gate layer 1033p and the preliminary channel layer 1031p can remain below each sidewall 1029 and can (substantially completely) overlap the sidewall 1029 in a top view. The remaining preliminary channel layer 1031p can constitute the channel layer 1031, and the remaining preliminary sacrificial gate layer 1033p can constitute the sacrificial gate 1033, which extend between adjacent sidewalls 1029.

[0045] In the case where the sidewall 1029 is not a dielectric as described above (e.g., a silicon film in this embodiment), the sidewall 1029 can be further processed here to have electrical insulation properties.

[0046] For example, at least the surface portion of the sidewall 1029 can be oxidized to an oxide by an oxidation process. In the case where the dopant source layers 1009, 1017 are also silicon films, since the dopant source layers 1009, 1017 are inside the stack, they may not be fully oxidized in the oxidation process. If electrical isolation is required between the first constituent device and the second constituent device, then as combined above Figure 1(a) and 1(b)In the described process, a dielectric layer can be additionally formed between the dopant source layers 1009, 1017 and the source / drain definition layer. For example, as shown in FIG. 11(a), a dielectric layer 1035 can be formed between the source / drain definition layer 1007 and the first dopant source layer 1009, a dielectric layer 1037 can be formed between the first dopant source layer 1009 and the source / drain definition layer 1011, and a dielectric layer 1039 can be formed between the source / drain definition layer 1015 and the second dopant source layer 1017. However, electrical isolation between the first constituent device and the second constituent device is not necessary. According to the device design, the first constituent device and the second constituent device can be electrically connected to each other. In this case, the doped silicon films 1009, 1017 can even remain between the first constituent device and the second constituent device. As shown in FIG. 11(b), the oxidation process can convert at least the surface portion or even the entire sidewall 1029 into an oxide 1041 to achieve electrical isolation from the adjacent channel layer. Additionally, the ends of the channel layer may also be oxidized due to the oxidation process. The process parameters in the oxidation process can be controlled such that the vertical portion of the channel layer 1031 extending on the vertically stacked sidewalls can remain unoxidized.

[0047] According to another embodiment, the sidewall 1029 (as well as the dopant source layers 1009, 1017) can be replaced with a dielectric material. For example, as shown in FIG. 12(a), a photoresist 1043 can be formed on the resulting structure, and the photoresist 1043 can be patterned to mask a part of the structure. Using the patterned photoresist 1043 as an etching mask, the sidewall 1029 and the dopant source layers 1009, 1017 (both silicon films in this embodiment) are selectively etched, for example, by wet etching. Thus, a part of the sidewall 1029 (e.g., the sidewall on the right sidewall of the vertically stacked sidewalls in FIG. 12(a)) and a part of the dopant source layers 1009, 1017 can be removed. Here, the reason for not removing all of the dopant source layers 1009, 1017 is at least partially to avoid the collapse of the vertical stack. After that, the photoresist 1043 can be removed. As shown in FIG. 12(b), in the void left due to the partial removal of the dopant source layers 1009, 1017, a dielectric material such as an oxide can be filled by deposition such as CVD and then etch-back such as RIE in the vertical direction, and the dielectric material can be filled between the vertically adjacent channel layers (and the sacrificial gates formed thereon) to form the sidewall 1045. Note that the sidewall above the uppermost channel layer may not be formed again, but this does not affect the subsequent processes. After that, the remaining sidewall 1029 and the dopant source layers 1009, 1017 can be processed in a similar manner. For example, as shown in FIG. 12(c), they can be removed by selective etching, and then as shown in FIG. 12(d), the sidewall 1047 can be formed by filling a dielectric material such as an oxide. In FIG. 12(d), the dielectric materials filled twice are shown as a whole.

[0048] Since the sidewalls may take different forms, for convenience hereinafter, the sidewall 1029 previously obtained from the sidewall defining layer is still taken as an example for illustration.

[0049] Returning to Figure 10 , the device fabrication can be completed by replacing the sacrificial gate 1033 with a gate stack through an alternative gate process. The gate stack thus formed can be self-aligned to the channel layer. If the vertical stack is isolated in both directions (e.g., the horizontal direction in the plane of the paper and the direction perpendicular to the plane of the paper) in the isolation process described above in combination with Figure 5 , then the channel layer can be formed in a form surrounding the sidewalls of the vertical stack, and the gate stack can surround the channel layer outside the channel layer. If in the above combination with Figure 5In the described isolation process, the vertical stack is isolated only in one direction (e.g., the horizontal direction within the plane of the paper). Then, isolation in another direction (e.g., the direction perpendicular to the plane of the paper) can be performed here (before or after the replacement gate process). In this case, the channel layer can be formed on one side wall of the vertical stack, and the gate stack can extend over the channel layer so as to be opposite to the side wall of the vertical stack via the channel layer.

[0050] According to other embodiments, a multi-gate structure can be formed.

[0051] To avoid excessive loss of thickness of the masking layer (see 1051 in Figure 14 ) during subsequent etching processes, for example as shown in Figure 13 , a protective layer 1049 having the same material (in this example, nitride) as the sidewall 1025 can be formed first, for example, by deposition such as CVD. The protective layer 1049 can be formed in a substantially conformal manner.

[0052] As shown in Figure 14 , on the substrate 1001, a masking layer 1051 can be formed, for example, by deposition such as CVD, to mask and protect the channel layer and the sacrificial gate already formed on the side walls of the vertical stack during subsequent processes. In this embodiment, the masking layer 1051 can include an oxide. The masking layer 1051 can be planarized, such as by chemical mechanical polishing (CMP), and the planarization process can stop at the core mold layer 1021 (and thus the hard mask layer 1023 is removed during the planarization process). Subsequently, an opening can be made inside the vertical stack based on the core mold layer 1021 to form another gate stack inside the channel layer.

[0053] If the vertical stack is isolated only in one direction (e.g., the horizontal direction within the plane of the paper) in the isolation process described above in combination with Figure 5 , then isolation in another direction (e.g., the direction perpendicular to the plane of the paper) can be performed here before forming the filling layer 1051.

[0054] As shown in Figure 15(a) and 15(b) (a top view and a cross-sectional view along the line AA' respectively), the core mold layer 1021 can be removed by selective etching, for example, wet etching using a TMAH solution. In this way, the sidewalls 1025 are left on the vertical stack. Here, the sidewalls 1025 present two strips opposite to each other and extending along the first direction. As described above, the sidewalls 1025 may also be annular.

[0055] The sidewall 1025 can be used as an etching mask, and anisotropic etching can be sequentially performed on each layer on the substrate 1001, for example, by RIE in the vertical direction. The etching can stop at the substrate 1001. Thus, the vertical stack can be separated into two sub-stacks corresponding to two bars opposite to each other of the sidewall 1025. Alternatively, the vertical stack can be formed into an annular structure corresponding to the sidewall 1025. Thus, the inner sides of the channel defining layers are exposed. In an example where the channel defining layers 1005 and 1013 include oxides, a certain thickness of the masking layer 1051, which is also an oxide here, can also be etched away.

[0056] Here, each source / drain defining layer is separated into parts corresponding to each device. Hereinafter, the parts of the source / drain defining layer in the final device will be collectively referred to as the source / drain layer.

[0057] Next, an alternative gate process can be performed.

[0058] For example, as Figure 16 shown, the masking layer 1051 can be removed by selective etching, such as wet etching (in this example, the channel defining layers 1005 and 1013, which are also oxides, can also be removed), the sidewall 1025 and the protective layer 1049 can be removed, and the sacrificial gate 1033, such as an oxide, can be removed. In this example, when removing the masking layer 1051, the sidewalls 1045 and 1047 (and the sidewall defining layers 1009 and 1017) can be retained. This is, for example, by selecting a material with appropriate etching selectivity for them (although they are all described as including oxides in the above embodiments, this is only an example), or by retaining the sidewalls 1045 and 1047 (and the sidewall defining layers 1009 and 1017) as silicon films and replacing them later, which will be described in further detail below.

[0059] A gate stack 1053 can be formed on the resulting structure. For example, by deposition such as CVD, the gate dielectric layer, the work function adjustment layer, and the gate conductor layer can be sequentially formed in a substantially conformal manner. For example, the gate dielectric layer can include a high-k gate dielectric such as HfO 2 , with a thickness of, for example, about 3 nm - 5 nm; the work function adjustment layer can include (in combination with the gate dielectric layer) a material with an appropriate work function, such as a conductive metal nitride like TiN, etc., with a thickness of, for example, about 3 nm - 5 nm; the gate conductor layer can include a conductive material, such as a metal like W, etc. The gate stack 1053 including the gate dielectric layer, the work function adjustment layer, and the gate conductor layer can extend along the surface of the structure, as Figure 17 shown.

[0060] As Figure 18As shown, the gate stack 1053 can be anisotropically etched, for example, by RIE in the vertical direction. Thus, the gate stack 1053 can remain in the region defined by the original sidewalls 1025 and be self-aligned with the channel layer. In particular, the gate stack 1053 can include two parts that sandwich the channel layer from opposite sides.

[0061] So far, the device fabrication has been basically completed. Next, the fabrication of the contact portions can be carried out.

[0062] If the sidewalls 1045, 1047 and the sidewall defining layers 1009, 1017 have not been oxidized or replaced as described above (see the description in conjunction with Figure 11(a) and 11(b) or the description in conjunction with Figures 12(a) to 12(d) ), such replacement treatment can be carried out here.

[0063] For example, as Figure 19 shown, in the case of forming a support structure on the vertical stack side, the sidewalls 1045, 1047 and the sidewall defining layers 1009, 1017 can be removed by selective etching. The support structure will be further described in detail below.

[0064] As Figure 20 shown, an interlayer dielectric layer 1055 can be formed on the substrate 1001, for example, by deposition such as CVD and planarization treatment such as CMP. In this embodiment, the interlayer dielectric layer 1055 can include an oxide. The interlayer dielectric 1055 can be filled into the voids left due to the removal of the sidewalls 1045, 1047 and the sidewall defining layers 1009, 1017.

[0065] In the interlayer dielectric layer 1055, various contact portions can be formed. Figure 21 The contact portion of one of the devices is schematically shown in Figure 21 . As

[0066] shown, the contact portion can include a contact portion 1057-1 electrically connected to the first source / drain layer, a contact portion 1057-2 electrically connected to one gate stack, a contact portion 1057-3 electrically connected to the second source / drain layer, and a contact portion 1057-4 electrically connected to the other gate stack. The contact portions of other devices can be formed similarly. There are various ways in the art to form the contact portions for vertical devices, which will not be elaborated here. Figure 21 As Figure 21(in the dashed circle). The first constituent device may include a first source / drain layer 1003, a second source / drain layer 1007 above the first source / drain layer 1003, and a channel layer 1031 vertically extending from the sidewall of the first source / drain layer 1003 to the sidewall of the second source / drain layer 1007. Similarly, the second constituent device may include a first source / drain layer 1011, a second source / drain layer 1015 above the first source / drain layer 1011, and a channel layer 1031 vertically extending from the sidewall of the first source / drain layer 1011 to the sidewall of the second source / drain layer 1015. On the side of the channel layer 1031 facing away from the source / drain layer, a gate stack 1053 is formed. As described above, the gate stack 1053 may be self-aligned with the channel layer 1031. Additionally, on the other side of the channel layer 1031, a gate stack may also be formed, and this gate stack may also be self-aligned with the channel layer 1031.

[0067] Between the gate stacks 1053 of the first and second constituent devices respectively, a spacer 1029′ may be formed (as Figure 21 shown by the dashed box in). As described above, such a spacer may be formed separately or be a part of the interlayer dielectric layer 1055. The position and size of the gate stack 1053 may be defined by the spacer, so the gate stack 1053 and the spacer may be self-aligned with each other. In a top view, the gate stack 1053 may overlap with the spacer. The sidewalls of the gate stack 1053 may be substantially coplanar with the sidewalls of the spacer.

[0068] As described above, the degree of upward and downward diffusion of the dopant in the spacer defining layer may be substantially the same. Therefore, the extension height of the spacer defined by diffusion on the sidewall of the second source / drain layer 1007 of the first constituent device (the range extending downward from the first dopant source layer 1009 in the spacer defining layer) may be substantially equal to the extension height on the sidewall of the first source / drain layer 1011 of the second constituent device (the range extending upward from the first dopant source layer 1009 in the spacer defining layer).

[0069] The portion of the dopant source layer remaining between the second source / drain layer 1007 of the first constituent device and the first source / drain layer 1011 of the second constituent device (or replaced by a dielectric material as described above) may constitute an isolation layer between the first and second constituent devices. The spacer may be vertically symmetric with respect to the isolation layer.

[0070] Figures 22(a) to 26 Schematically shows a process using a support structure according to an embodiment of the present disclosure.

[0071] For example, after forming the masking layer 1051 in the process described above in conjunction with Figure 14 , as Figure 22(a) , 22(b)As shown in FIGS. 22(c) (top view, cross-sectional view along line BB′, and cross-sectional view along line CC′ respectively), a photoresist 1059 can be formed on the resulting structure and patterned by lithography to occupy a certain range in a first direction (e.g., the vertical direction in the plane of FIG. 22(a)), such as a strip extending along a second direction (e.g., the horizontal direction in the plane of FIG. 22(a)). As Figure 23(a) , 23(b) and FIGS. 23(c) (top view, cross-sectional view along line BB′, and cross-sectional view along line CC′ respectively), the photoresist 1059 that can be patterned in this way is used as an etching mask, and the layers on the substrate are anisotropically etched, for example, by RIE in the vertical direction. After that, the photoresist 1059 can be removed. In the trenches (between the vertical stacks) formed on the substrate due to etching, a support layer 1061 can be filled. For example, the support layer 1061 can be formed by depositing a dielectric material and planarizing the deposited dielectric material, such as CMP, and CMP can stop at the sidewall 1025. Considering the etching selectivity in subsequent processes, the support layer 1061 can include, for example, nitrogen oxides (e.g., silicon oxynitride).

[0072] After that, the process can proceed similarly. For example, as described above in connection with FIGS. 15(a) and 15(b), openings can be made inside the vertical stack to obtain a structure as shown in Figure 24(a) , 24(b) and FIGS. 24(c). Then, as described above in connection with Figures 16 to 18 , a gate stack can be formed to obtain a structure as shown in Figure 25(a) and 25(b) . After that, as described above, the sidewalls 1045, 1047 and the sidewall defining layers 1009, 1017 can be removed. As shown in Figure 26 , due to the presence of the support layer 1061, the vertical stack can be maintained.

[0073] The semiconductor device according to an embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and possibly other devices (e.g., other forms of transistors, etc.), an integrated circuit (IC) can be formed, and an electronic device can be constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above semiconductor device. The electronic device may further include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such electronic devices include, for example, smart phones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, mobile power supplies, etc.

[0074] According to an embodiment of the present disclosure, a method for manufacturing a system-on-chip (SoC) is also provided. The method may include the above-described method. Specifically, a variety of devices may be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

[0075] In the above description, technical details such as the layout and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0076] The above embodiments of the present disclosure have been described. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a first constituent device on a substrate and a second constituent device stacked on the first constituent device, wherein each of the first constituent device and the second constituent device comprises: a first source / drain layer, a second source / drain layer above the first source / drain layer, a channel layer vertically extending from a sidewall of the first source / drain layer to a sidewall of the second source / drain layer, and a gate stack on a side of the channel layer facing away from the sidewalls of the first source / drain layer and the second source / drain layer, wherein, between the gate stack of the first constituent device and the gate stack of the second channel device, a dielectric layer vertically extends from a sidewall of the second source / drain layer of the first constituent device to a sidewall of the first source / drain layer of the second constituent device.

2. The semiconductor device according to claim 1, wherein, the dielectric layer comprises a material having an etching selectivity with respect to the surrounding interlayer dielectric layer, and further comprises a portion between the second source / drain layer of the first constituent device and the first source / drain layer of the second constituent device.

3. The semiconductor device according to claim 2, wherein, a portion of the dielectric layer between the gate stack of the first constituent device and the gate stack of the second channel device overlaps with the gate stack in a top view.

4. The semiconductor device according to claim 2, wherein, sidewalls of a portion of the dielectric layer between the gate stack of the first constituent device and the gate stack of the second channel device are substantially coplanar with sidewalls of the gate stack.

5. The semiconductor device according to claim 1, wherein, the dielectric layer is a part of the interlayer insulating layer of the semiconductor device.

6. The semiconductor device according to claim 1, wherein, a height of the extension of the dielectric layer on a sidewall of the second source / drain layer of the first constituent device is substantially equal to a height of the extension of the sidewall on a sidewall of the first source / drain layer of the second constituent device.

7. The semiconductor device according to claim 1, further comprising: an isolation layer between the second source / drain layer of the first constituent device and the first source / drain layer of the second constituent device, wherein the dielectric layer is substantially vertically symmetric with respect to the isolation layer.

8. The semiconductor device according to claim 7, wherein, the isolation layer includes a dopant.

9. The semiconductor device according to claim 1, further comprising: another gate stack on a side of the channel layer facing the sidewalls of the first source / drain layer and the second source / drain layer.

10. The semiconductor device according to claim 1, wherein, sidewalls of the first source / drain layer and the second source / drain layer of the first constituent device are substantially coplanar with sidewalls of the first source / drain layer and the second source / drain layer of the second constituent device.

11. The semiconductor device according to claim 10, wherein, the channel layer has substantially flat sidewalls.

12. The semiconductor device according to claim 1, wherein, The first source / drain layer and the second source / drain layer comprise a metal, and the channel layer comprises an amorphous or polycrystalline semiconductor material.

13. The semiconductor device according to claim 1, wherein, the first source / drain layer, the second source / drain layer, and the channel layer comprise single-crystalline semiconductor materials.

14. The semiconductor device according to claim 1, wherein, the gate stack is self-aligned with the channel layer.

15. A method of manufacturing a semiconductor device, comprising: forming on a substrate a vertical stack including the following layers sequentially disposed: a first device-forming first source / drain defining layer, a channel defining layer, and a second source / drain defining layer, a first dopant source layer, a second device-forming first source / drain defining layer, a channel defining layer, and a second source / drain defining layer, and a second dopant source layer; forming a spacer defining layer on sidewalls of the vertical stack; driving dopants from the first dopant source layer and the second dopant source layer into the spacer defining layer respectively, thereby forming doping regions corresponding to the first dopant source layer and the second dopant source layer respectively in the spacer defining layer; selectively etching the spacer defining layer to retain the doping regions therein and removing the remaining portions; forming a channel layer extending between the spacers on the sidewalls of the vertical stack; and forming a gate stack on a side of the channel layer facing away from the sidewalls, wherein the spacers between vertically adjacent gate stacks are defined by the doping regions.

16. The method according to claim 15, wherein, the dopant diffuses upward and downward in the spacer defining layer from the first dopant source layer to substantially the same extent, and diffuses upward and downward in the spacer defining layer from the second dopant source layer to substantially the same extent.

17. The method according to claim 15, wherein, the vertical stack is formed by deposition, the first source / drain defining layer and the second source / drain defining layer comprise a metal, the first dopant source layer and the second dopant source layer comprise an amorphous or polycrystalline film containing a dopant or a dielectric layer, and the channel layer comprises an amorphous or polycrystalline semiconductor material.

18. The method according to claim 17, wherein, forming the spacer defining layer comprises: depositing an amorphous or polycrystalline silicon film in a substantially conformal manner.

19. The method according to claim 15, wherein, the vertical stack is formed by epitaxial growth, the first source / drain defining layer, the channel defining layer, the second source / drain defining layer, and the channel layer comprise single-crystalline semiconductor materials, and the first dopant source layer and the second dopant source layer comprise single-crystalline films containing a dopant.

20. The method according to claim 19, wherein, forming the spacer defining layer comprises: epitaxially growing a single-crystalline film.

21. The method according to claim 15, further comprising: oxidizing at least a surface portion of the remaining doping regions into an oxide, or replacing the doping regions with a dielectric material to define the spacers.

22. The method according to claim 15, wherein, forming the channel layer comprises: Form a preliminary channel layer in a substantially conformal manner; Form a sacrificial gate material layer on the preliminary channel layer; Using the sidewall as a mask, anisotropically etch the preliminary channel layer and the sacrificial gate material layer in the vertical direction. After etching, the preliminary channel layer forms the channel layer, and the etched sacrificial gate material layer constitutes the sacrificial gate.

23. The method according to claim 22, wherein, By means of an alternative gate process, replace the sacrificial gate with a gate stack that is self-aligned to the channel layer.

24. The method according to claim 15, further comprising: Form an opening in the vertical stack to expose the interior of the vertical stack; Via the opening, remove the channel defining layer; and Form another gate stack opposite to the channel layer in the void left due to the removal of the channel defining layer.

25. The method according to claim 15, further comprising: Form an opening in the vertical stack to expose the interior of the vertical stack; Via the opening, remove the first dopant source layer and the second dopant source layer and the remaining doped regions; Fill a dielectric layer in the space left due to the removal.

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