Partial silicon-on-insulating-layer LDMOS device with double-sided variable-high-K dielectric structure
By adopting a double-sided high K dielectric structure in silicon LDMOS devices on some insulating layers, the problem of early breakdown caused by excessive voltage across the source and drain is solved, and a higher breakdown voltage and lower on-resistance are achieved, which improves the stability of the device.
Patent Information
- Application Number
- CN202510305266.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-06-10
AI Technical Summary
Existing high-K dielectric LDMOS devices have the problem of early breakdown due to excessive voltage across the source and drain.
Using a double-sided high-K dielectric structure, the first high-K dielectric and the second high-K dielectric with the same width but different K values are arranged side by side on both sides of the silicon material body to guide the electric flux and modulate the device's electric field distribution.
By uniformizing the electric field distribution on the surface of the device, the breakdown voltage is increased, and the specific on-resistance is reduced by consuming electrons in the drift region, the autothermal effect is alleviated and the device stability is improved.
Smart Images
Figure CN120129277A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor high-voltage power integrated circuit special devices, and particularly relates to a partially silicon-on-insulator LDMOS device with a double-sided variable high-K dielectric structure. Background Art
[0002] One advantage of a laterally diffused metal oxide semiconductor (LDMOS) device is that its gate, source, and drain electrodes are all on the surface of the device, so it is convenient for integration. Therefore, the LDMOS device is a commonly used power device in intelligent power integrated circuits. Especially in power management chips, such as DC / DC chips, AC / DC chips, DC / AC chips, etc., in these chips, the LDMOS device occupies most of the chip area. Therefore, to achieve high performance, low power consumption, and miniaturization of the chip, improving the LDMOS device in the chip is a very important link. Because the on-resistance of the LDMOS is much larger than that of the vertical transistor (VDMOS) in practice, and a larger device size is required under the rated breakdown voltage, resulting in an increase in production cost. Therefore, in the device design process, while increasing the breakdown voltage of the lateral LDMOS device, reducing its on-state on-resistance, that is, alleviating the contradictory relationship between the breakdown voltage (BV) and the specific on-resistance (Ron,sp) of the LDMOS device has practical significance. The LDMOS device based on silicon-on-insulator (SOI) occupies an important position in the field of power devices due to its fast conversion rate and low power consumption. The partially silicon-on-insulator (PSOI) structure solves its pain points while retaining the advantages of the silicon-on-insulator structure. The structure of the partially silicon-on-insulator enables the internal heat of the device to be dissipated to the substrate through the silicon window, and at the same time, the substrate undertakes part of the breakdown voltage, alleviating the self-heating effect of the device and increasing the breakdown voltage of the device. The high-K dielectric effectively increases the breakdown voltage of the device and reduces its specific on-resistance by guiding the electric flux and optimizing the electric field distribution of the device; however, in the existing solutions, the LDMOS device with a high-K dielectric has the problem of premature breakdown due to too high voltage at both ends of the source and drain. Summary of the Invention
[0003] The purpose of the present invention is to provide a partially silicon-on-insulator LDMOS device with a double-sided variable high-K dielectric structure. The LDMOS device is based on a partially silicon-on-insulator substrate and has a variable high-K dielectric structure on both the front and back sides of the silicon material in the silicon film layer.
[0004] The present invention provides a partially silicon-on-insulator LDMOS device with a double-sided variable high-K dielectric structure, including a substrate layer, a buried oxide layer, a silicon film layer, and a device top layer stacked in sequence; the silicon film layer includes a silicon material main body and a high-K dielectric region; the silicon material main body includes a drain region, a source region, a silicon body, and a drift region; the device top layer includes a drain electrode, a gate electrode, and a source electrode; the drain electrode, the gate electrode, and the source electrode are respectively located above the drain region, the silicon body, and the source region;
[0005] High-K dielectric regions are provided on both sides of the silicon material body; the high-K dielectric regions include a first high-K dielectric and a second high-K dielectric arranged in parallel; the first high-K dielectric is in contact with the drain region; the second high-K dielectric is in contact with the source region and the silicon body; the K value of the first high-K dielectric is less than the K value of the second high-K dielectric; the widths of the first high-K dielectric and the second high-K dielectric are equal.
[0006] Preferably, the widths of the first high-K dielectric and the second high-K dielectric are both in the range of 0.2 μm to 0.6 μm; the K value of the first high-K dielectric is 20 to 100; the K value of the second high-K dielectric is 150 to 500.
[0007] Preferably, the widths of the first high-K dielectric and the second high-K dielectric are both 0.6 μm; the K value of the first high-K dielectric is 50; the K value of the second high-K dielectric is 250.
[0008] Preferably, the buried oxide layer is made of silicon dioxide material with a length of 20 μm to 40 μm.
[0009] Preferably, the length of the buried oxide layer is 30 μm.
[0010] Preferably, the doping type of the drift region is N-type, and the doping concentration is 1×10 15 cm -3 ~1.8×10 16 cm -3 。
[0011] Preferably, the source region includes a source region N+ part and a source region P+ part; the drain region, the source region N+ part, and the source region P+ part are arranged in sequence along the length direction of the LDMOS device; the source region N+ part is separated from the second high-K dielectric by the silicon body.
[0012] Preferably, the gate electrode is separated from the source region N+ part, the silicon body, and the drift region by a gate oxide layer; the drain electrode is in direct contact with the top surface of the drain region; the source electrode is in direct contact with the top surface of the source region.
[0013] Preferably, the source region is completely separated from the drift region by the silicon body.
[0014] Preferably, the substrate layer is made of silicon material, the doping type is P-type, and the doping concentration is 1×10 14 ~1×10 15 cm -3 。
[0015] The beneficial effects of the present invention are:
[0016] 1. On both sides of the silicon material main body, the present invention juxtaposes a first high-K dielectric and a second high-K dielectric with the same width but different K values, which helps to guide the electric flux, modulate the distribution of the device electric field, reduce the electric field at both ends of the source and drain, make the surface electric field distribution of the device more uniform, and prevent the device from being prematurely broken down due to too high voltage at both ends of the source and drain, thereby increasing the breakdown voltage of the device.
[0017] 2. The high-K dielectric region provided in the silicon film layer of the present invention helps to consume electrons in the drift region and assist in depleting the drift region, thereby increasing the doping concentration of the drift region and greatly reducing the specific on-resistance of the device; at the same time, the partially silicon-on-insulator structure adopted by the present invention enables the substrate to bear part of the voltage and conduct heat from the window to the substrate, which can relieve the self-heating effect of the device while increasing the breakdown voltage of the device and improve the device stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a device structure diagram of Embodiment 1 of the present invention.
[0019] Figure 2 It is a device cross-sectional view of Embodiment 1 of the present invention at z = 1.
[0020] Figure 3 It is a device structure diagram of Comparative Example 1.
[0021] Figure 4 It is a comparison diagram of the surface electric field of the silicon film layer of Embodiment 1 and Comparative Example 1 changing with position.
[0022] Figure 5 It is a comparison diagram of the influence of the K values of the first high-K dielectric and the second high-K dielectric on the FOM of the device in Embodiment 1 of the present invention.
[0023] Figure 6 It is a comparison diagram of the influence of the K value of the second high-K dielectric on the breakdown voltage of the device in the present invention.
[0024] Figure 7 It is a comparison diagram of the influence of the K value of the second high-K dielectric on the on-resistance of the device in the present invention.
[0025] Figure 8 It is a comparison diagram of the influence of the K value of the second high-K dielectric on the FOM value of the device in the present invention.
[0026] Figure 9 It is a comparison diagram of the influence of the width of the high-K dielectric and the K value of the first high-K dielectric on the breakdown voltage of the device in the present invention.
[0027] Figure 10 It is a comparison diagram of the influence of the width of the high-K dielectric and the K value of the first high-K dielectric on the on-resistance of the device in the present invention.
[0028] Figure 11 This is a comparison chart of the influence of the high-K dielectric width and the K value of the first high-K dielectric on the FOM value of the device in the present invention.
[0029] Figure 12 This is a comparison chart of the influence of the high-K dielectric width and the K value of the second high-K dielectric on the breakdown voltage of the device in the present invention.
[0030] Figure 13 This is a comparison chart of the influence of the high-K dielectric width and the K value of the second high-K dielectric on the on-resistance of the device in the present invention.
[0031] Figure 14 This is a comparison chart of the influence of the high-K dielectric width and the K value of the second high-K dielectric on the FOM value of the device in the present invention.
[0032] Figure 15 This is a relationship chart of the breakdown voltage and specific on-resistance for comparison between the present invention and other devices in the related field.
[0033] Reference numerals: 1, drain region; 2, N+ part of source region; 3, P+ part of source region; 4, silicon body; 5, drift region; 6, buried oxide layer; 7, substrate layer; 8, drain electrode; 9, gate electrode; 10, source electrode; 11, first high-K dielectric; 12, second high-K dielectric. Detailed implementation manners
[0034] The present invention will be further described below with reference to the accompanying drawings.
[0035] Example 1
[0036] As Figure 1 and 2 shown, a partially-depleted silicon-on-insulator (PD-SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device with a double-sided variable high-K dielectric structure includes a substrate layer 7, a buried oxide layer 6, a silicon film layer, and a device top layer stacked in sequence from bottom to top. The overall length of the LDMOS transistor device is 50 μm, the overall thickness is 108 μm, and the width is 2 μm. The substrate layer 7 is disposed at the bottom, with a P-type doping type and a doping concentration of 1×10 14 cm -3 ~1×10 15 cm -3 silicon material, and the thickness of the substrate layer 7 is 99 μm; the buried oxide layer 6 uses a silicon dioxide material with a length of 20 μm to 40 μm, a thickness of 3 μm to 5 μm, and a width of 2 μm.
[0037] In this embodiment, the doping concentration of the substrate layer 7 is 7×10 14 cm -3 ; the length of the buried oxide layer 6 is 30 μm and the thickness is 4 μm.
[0038] The silicon film layer includes a silicon material main body and high-K dielectric regions covering both sides of the silicon material main body; the silicon material main body includes a drain region 1, a source region, a silicon body 4, and a drift region 5. The source region includes a source region N+ portion 2 and a source region P+ portion 3; the drain region 1, the source region N+ portion 2, and the source region P+ portion 3 are all disposed above the drift region 5 and are arranged in sequence along the length direction of the LDMOS device; the silicon body 4 is disposed between the source region and the drift region 5.
[0039] The silicon body 4 is made of silicon material with a length of 3 μm, a thickness of 3 μm, a doping type of P-type, and a doping concentration of 1×10 17 cm -3 .
[0040] The silicon film layer has a length of 50 μm, a width ranging from 0.4 μm to 1.8 μm, and a thickness of 5 μm; the drain region 1 is made of silicon material with a length of 2 μm, a thickness of 1 μm, a doping type of N-type, and a doping concentration of 1×10 20 cm -3 .
[0041] The source region N+ portion 2 is made of silicon material, with a doping type of N-type, a doping concentration of 1×10 20 cm -3 , and both the length and thickness are 1 μm; the source region P+ portion 3 is made of silicon material, with a doping type of P-type, a doping concentration of 1×10 20 cm -3 , and both the length and thickness are 1 μm.
[0042] The doping type of the drift region 5 is N-type, and the doping concentration is 1×10 15 cm -3 ~1.8×10 16 cm -3 ; in this embodiment, the doping concentration of the drift region 5 is 1.02×10 16 cm -3 .
[0043] The high-K dielectric region includes a first high-K dielectric 11 and a second high-K dielectric 12 arranged in parallel. The first high-K dielectric 11 is in contact with the drain region 1; the second high-K dielectric 12 is in contact with the source region P+ portion 3 and the silicon body 4; the source region N+ portion 2 is separated from the second high-K dielectric 12 by the silicon body; the bottom surface of the first high-K dielectric 11 is in complete contact with the top surface of the buried oxide layer 6; the K values of the first high-K dielectrics 11 in the high-K dielectric regions on both sides of the silicon material main body are equal; the K values of the second high-K dielectrics 12 in the high-K dielectric regions on both sides of the silicon material main body are equal. The first high-K dielectric 11 and the second high-K dielectric 12 have the same width, and the value range is 0.2 μm to 0.6 μm; the K value of the first high-K dielectric 11 is 20 to 100; the K value of the second high-K dielectric 12 is 150 to 500.
[0044] In this embodiment, the width t of the first high-K dielectric 11 is 0.6 μm, and the K value is 50; the width t of the second high-K dielectric 12 is 0.6 μm, and the K value is 250.
[0045] The top layer of the device includes a drain electrode 8, a gate electrode 9, and a source electrode 10; the drain electrode 8 is located above the drain region 1 and is in direct contact with the top surface of the drain region 1; the gate electrode 9 is disposed above the silicon body 4 and is separated from the source region N+ part 2, the silicon body 4, and the drift region 5 by a gate oxide layer; the source electrode 10 is located above the source region and is in direct contact with the top surface of the source region.
[0046] Comparative Example 1
[0047] As Figure 3 shown, a high-K dielectric on insulator silicon LDMOS transistor (HK PSOI LDMOS) with double-sided high-K dielectrics. The difference between this comparative example and Example 1 is that high-K dielectrics 11 are only provided on both sides of the silicon material body, and the K values of the high-K dielectrics 11 on both sides are equal, and the other parameters are the same as those in Example 1. After testing, under the structure of this embodiment, the optimal doping concentration of the drift region 5 is 1.02×10 16 cm -3 .
[0048] Set the device length direction as the X-axis direction, the device thickness direction as the Y-axis direction, and the device width direction as the Z-axis direction. Based on three-dimensional TCAD software simulation, the following tests are carried out to obtain the performance of the LDMOS transistors provided by Example 1 and Comparative Example 1. In the simulation study, the substrate layer 7 is grounded.
[0049] Explanation of the significant superiority of Example 1 compared to Comparative Example 1:
[0050] The comparison chart of the surface electric field change curves of the LDMOS transistors provided by Example 1 (VHK PSOI LDMOS), Comparative Example 1 (HKPSOI LDMOS), and traditional PSOI LDMOS is as Figure 4 shown. As can be seen from Figure 4 , in Example 1, variable high-K dielectric regions exist on both sides of the silicon material in the silicon film layer, which can guide the electric flux (i.e., more electric flux flows to the high-K dielectric), and make the surface electric field of the silicon film layer more uniform, improving the RESURF (Reduced Surface Field) effect of the device. The structure of double-sided variable high-K dielectrics forms an electric field peak in the middle of the drift region, which is beneficial to uniform the surface electric field and prevent the device from premature breakdown caused by excessive voltage at both ends of the source and drain.
[0051] Determination process of the optimal values of each key parameter in Example 1:
[0052] The doping concentration of the drift region 5, the length of the buried oxide layer 6, and the width and K value of the first high-K dielectric region 11 and the second high-K dielectric of the LDMOS transistor provided in Example 1 are changed to study the influence of key parameters on the performance of the device such as breakdown voltage, on-resistance and FOM value.
[0053] Figure 5 The influence of the K value of the first high-K dielectric 11 and the second high-K dielectric 12 on the FOM value of the device is described. The corresponding optimal high-K dielectric width is 0.2μm to 0.7μm, the optimal silicon window length is 10μm to 25μm, and the other related parameters remain unchanged. In the figure, K1 is the K value of the first high-K dielectric 11, and K2 is the K value of the second high-K dielectric 12. When K1 is 50 and K2 is 250, the highest FOM value is obtained.
[0054] Figure 6 , Figure 7 and Figure 8 Describe the effect of the K value of the second high-K dielectric 12 on the device breakdown voltage, specific on-resistance, and FOM value. At this time, the K value of the first high-K dielectric 11 is 50, the width of the high-K dielectric is 0.6μm, the corresponding optimal silicon window length is 10μm~25μm, and the other related parameters remain unchanged. In the figure, K2 is the K value of the second high-K dielectric 12; when the K value of the second high-K dielectric 12 is 150, the concentration of the drift region 5 is 9×10 15 cm 3 When the K value of the second high-K dielectric 12 is 250, the breakdown voltage decreases slightly and the on-resistance decreases significantly. At this time, the highest FOM value of 4.556MW / cm is obtained. 2 , showing the best overall performance.
[0055] Figure 9 , Figure 10 and Figure 11 Describe the influence of the K value of the first high-K dielectric 11 and the width of the high-K dielectric on the device breakdown voltage, specific on-resistance and FOM value. At this time, the K value of the second high-K dielectric 12 is 250, and the corresponding optimal silicon window length is 10μm~25μm, and the other related parameters remain unchanged. In the figure, K1 is the K value of the first high-K dielectric 11, K2 is the K value of the second high-K dielectric 12, t HK is the width of the high-K dielectric. As can be seen from the figure, when K2 is 250, as K1 increases, the breakdown voltage of the device first increases and then decreases, and the FOM value of the device first increases and then decreases; as t HK As K1 increases, the device breakdown voltage first increases and then decreases, and the device on-resistance first decreases and then increases. HKWhen it is 0.6μm, the device achieves a relatively high breakdown voltage and the lowest on-resistance, and the comprehensive performance reaches the best.
[0056] Figure 12 , Figure 13 and Figure 14 Describe the influence of the K value of the second high-K dielectric 12 and the width of the high-K dielectric on the breakdown voltage, specific on-resistance, and FOM value of the device. At this time, the K value of the first high-K dielectric 11 is 50, and the corresponding optimal silicon window length is 10μm - 25μm, and the other relevant parameters remain unchanged. In the figure, K1 is the K value of the first high-K dielectric 11, and K2 is the K value of the second high-K dielectric 12. It can be seen from the figure that as K2 increases, the falling edge of the device breakdown voltage gradually shifts to the left, and the on-resistance decreases as K2 increases; as t HK increases, the device breakdown voltage first rises and then falls, and the device on-resistance first falls and then rises. When K2 is 250 and t HK is 0.6μm, the device achieves a relatively high breakdown voltage and a relatively low on-resistance, and the device has the highest FOM value.
[0057] Combined with the above figures, it can be seen that when the widths of the high-K dielectrics are both 0.6μm, the K value of the first high-K dielectric 11 is 50, and the K value of the second high-K dielectric 12 is 250, the device has a relatively high breakdown voltage and a relatively low on-resistance, and the structure set with these parameters can exhibit the best performance.
[0058] Figure 15 This is a graph showing the relationship between the breakdown voltage and on-resistance of the present invention compared with other devices Pseudo LDMOS, MR LDMOS, and SCDT LDMOS in the related field. It can be seen from the figure that the design concept of the present invention has superiority, and its performance exceeds the traditional Double RESURF curve. Compared with other devices in the related field, it has a relatively high breakdown voltage and a relatively low on-resistance, and has more excellent performance.
Claims
1. A partially insulating silicon-on-silicon LDMOS device with a double-sided variable high-K dielectric structure, comprising a substrate layer (7), a buried oxide layer (6), a silicon film layer and a device top layer stacked in sequence; the silicon film layer comprises a silicon material body and a high-K dielectric region; the silicon material body comprises a drain region (1), a source region, a silicon body (4) and a drift region (5); the device top layer comprises a drain electrode (8), a gate electrode (9) and a source electrode (10); the drain electrode (8), the gate electrode (9) and the source electrode (10) are respectively located above the drain region (1), the silicon body (4) and the source region; characterized in that: High-K dielectric regions are provided on both sides of the silicon material body; the high-K dielectric regions include a first high-K dielectric (11) and a second high-K dielectric (12) arranged in parallel; the first high-K dielectric (11) is in contact with the drain region (1); the second high-K dielectric (12) is in contact with the source region and the silicon body (4); the K value of the first high-K dielectric (11) is smaller than the K value of the second high-K dielectric (12); and the widths of the first high-K dielectric (11) and the second high-K dielectric (12) are equal.
2. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The widths of the first high-K medium (11) and the second high-K medium (12) are both in the range of 0.2 μm to 0.6 μm; the K value of the first high-K medium (11) is 20 to 100; and the K value of the second high-K medium (12) is 150 to 500.
3. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 2, characterized in that: The widths of the first high-K dielectric (11) and the second high-K dielectric (12) are both 0.6 μm; the K value of the first high-K dielectric (11) is 50; and the K value of the second high-K dielectric (12) is 250.
4. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The buried oxide layer (6) is made of silicon dioxide material with a length of 20 μm to 40 μm.
5. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 4, characterized in that: The length of the buried oxide layer (6) is 30 μm.
6. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The doping type of the drift region (5) is N-type, and the doping concentration is 1×10 15 cm -3 ~1.8×10 16 cm -3 .
7. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The source region comprises a source region N+ part (2) and a source region P+ part (3); the drain region (1), the source region N+ part (2) and the source region P+ part (3) are arranged in sequence along the length direction of the LDMOS device.
8. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 7, characterized in that: The gate electrode (9) is separated from the source region N+ part (2), the silicon body (4) and the drift region (5) by a gate oxide layer; the drain electrode (8) is in direct contact with the top surface of the drain region (1); and the source electrode (10) is in direct contact with the top surface of the source region.
9. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The source region and the drift region (5) are completely separated by the silicon body (4).
10. The partial silicon-on-insulator LDMOS device with a double-sided high-K dielectric structure according to claim 1, characterized in that: The substrate layer (7) is made of silicon material, the doping type is P type, and the doping concentration is 1×10 14 ~1×10 15 cm -3 .