Electric field clamping structure and trench gate transistor
By designing an electric field clamping structure in a trench transistor, the space charge region of the PN junction and doped region is used to reduce the electric field strength, and the problem of breakdown at the corner of the trench is solved, achieving the effect of reducing costs and improving reliability.
Patent Information
- Application Number
- CN202311654288.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-04
- Publication Date
- 2025-06-10
AI Technical Summary
The trench corners of the trench type transistor are prone to withstand huge electric field strength, which leads to breakdown and affects the reliability of the transistor. The existing electric field shielding structure has complex production processes and high costs.
An electric field clamping structure is designed, by providing a plurality of spaced PN junctions in the trench gate transistor, and a space charge region formed by stacking the first doped region, the second doped region and the third doped region are reduced. The breakdown voltage of this structure is smaller than the breakdown voltage at the corner of the gate trench structure in the trench gate transistor.
It effectively reduces the breakdown at the trench corner of the trench gate transistor, reduces the production cost, and is simple in process.
Smart Images
Figure CN120129284A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to an electric field clamping structure and a trench gate transistor. Background Art
[0002] According to different gate layout directions, transistors can be divided into planar structures and trench structures. Due to a higher cell density, the trench structure has more obvious advantages in terms of conduction performance. However, for trench transistors, the biggest challenge is that the trench corners are extremely vulnerable to huge electric field intensities, which affects the reliability of the transistors.
[0003] In related technologies, an electric field shielding structure can be set to reduce the electric field intensity at the trench corners to reduce the occurrence of breakdown at the trench corners. However, the manufacturing process of the electric field shielding structure is relatively complex, resulting in a high manufacturing cost. Summary of the Invention
[0004] The present disclosure provides an electric field clamping structure and a trench gate transistor, mainly aiming to reduce the occurrence of breakdown at the trench corners of the trench gate transistor, and having a simple manufacturing process and a low manufacturing cost.
[0005] According to one aspect of the present disclosure, there is provided an electric field clamping structure applied to a trench gate transistor, including:
[0006] A plurality of PN junctions arranged at intervals, the PN junctions being formed by a first doped region and a second doped region stacked, and a third doped region is arranged between adjacent PN junctions;
[0007] The first doped region is of a first doping type, and both the second doped region and the third doped region are of a second doping type;
[0008] The breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure in the trench gate transistor.
[0009] Optionally, in an embodiment of the present disclosure, the breakdown voltage of the electric field clamping structure is determined by at least one of the doping concentration of the first doped region, the doping concentration of the second doped region, the doping concentration of the third doped region, and the spacing between adjacent PN junctions.
[0010] Optionally, in an embodiment of the present disclosure, when the voltage range of the breakdown voltage of the electric field clamping structure is from 400V to 3000V, the doping concentration range of the first doped region is from 1E16 cm-3 to 1E20 cm-3; the doping concentration range of the second doped region is from 1E15 cm-3 to 8E17 cm-3; the doping concentration range of the third doped region is from 1E16 cm-3 to 1E19 cm-3; the spacing range between adjacent PN junctions is from 0.2um to 10.0um.
[0011] Optionally, in an embodiment of the present disclosure, the first doping type is P-type and the second doped region type is N-type; or,
[0012] the first doping type is N-type and the second doped region type is P-type.
[0013] Optionally, in an embodiment of the present disclosure, the first surface of the first doped region and the first surface of the third doped region are in the same plane, and the second surface of the first doped region is in contact with the first surface of the second doped region.
[0014] Optionally, in an embodiment of the present disclosure, the electric field clamping structure further includes a first oxide layer; wherein,
[0015] the first oxide layer covers the first surface of the third doped region and extends to both sides and at least covers part of the first surface of the first doped region.
[0016] Optionally, in an embodiment of the present disclosure, the electric field clamping structure further includes a first metal structure; wherein,
[0017] the first metal structure at least covers part of the first surface of the first doped region.
[0018] According to another aspect of the present disclosure, there is provided a trench gate transistor, including:
[0019] a plurality of cell structures, the cell structures including a plurality of trench sub-cells distributed in an array, and each of the trench sub-cells includes a gate trench structure;
[0020] An electric field clamping structure as shown in any one of the foregoing aspects is provided in the peripheral region of each of the cell structures.
[0021] Optionally, the cell structure includes at least one row of sub-cells, and each row of sub-cells includes a plurality of trench sub-cells arranged in parallel;
[0022] The electric field clamping structure is provided at the periphery of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells respectively.
[0023] Optionally, the cell structure includes at least one column of sub-cells, and each column of sub-cells includes a plurality of trench sub-cells arranged side by side;
[0024] The electric field clamping structure is disposed at the periphery of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells respectively.
[0025] Optionally, the trench gate transistor further includes:
[0026] A silicon carbide substrate, an epitaxial layer is disposed on a first surface of the silicon carbide substrate, and both the silicon carbide substrate and the epitaxial layer are of the second doping region type;
[0027] The cell structure and the electric field clamping structure are disposed in the epitaxial layer, and the resistance value corresponding to the epitaxial layer is higher than the epitaxial resistance threshold.
[0028] Optionally, the trench sub-cell further includes:
[0029] A fourth doping region disposed on both sides of the end of the gate trench structure away from the silicon carbide substrate, and the fourth doping region is of the second doping region type;
[0030] A sixth doping region disposed on a side of the fourth doping region away from the gate trench structure, the sixth doping region is of the first doping region type and the doping concentration of the sixth doping region is the same as the doping concentration of the first doping region;
[0031] A second oxide layer covering a first surface of the gate trench structure and extending to both sides and covering a part of the first surface of the fourth doping region;
[0032] A second metal structure covering a first surface of the sixth doping region and covering a part of the first surface of the fourth doping region;
[0033] A well region disposed on a second surface of the fourth doping region, and the well region is of the first doping region type.
[0034] Optionally, the gate trench structure includes:
[0035] A gate oxide layer trench disposed in the epitaxial layer;
[0036] A gate layer disposed in the gate oxide layer trench.
[0037] In summary, for the electric field clamping structure and the trench gate transistor provided by the embodiments of the present disclosure, since the breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure in the trench gate transistor, when the blocking voltage borne by the transistor reaches the breakdown voltage of the lower electric field clamping structure, the electric field clamping structure is broken down, and the transistor is broken down in advance, so that the electric field strength at the corner of the gate trench structure can be clamped below the safe value, and the breakdown at the trench corner of the trench gate transistor can be reduced. In addition, the manufacturing process of the electric field clamping structure is simple, and the first doped region, the second doped region, and the third doped region can be formed only by a simple ion implantation process, which can reduce the manufacturing cost of the transistor.
[0038] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. Description of the Drawings
[0039] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, in which:
[0040] Figure 1 is a schematic structural diagram of an existing planar gate type silicon carbide MOSFET;
[0041] Figure 2 is a schematic structural diagram of another existing trench gate type silicon carbide MOSFET;
[0042] Figure 3 is a schematic structural diagram of an existing trench gate type silicon carbide MOSFET with a designed shielding structure;
[0043] Figure 4 is a schematic structural diagram of another existing trench gate type silicon carbide MOSFET with a designed shielding structure;
[0044] Figure 5 is a schematic cross-sectional view of an electric field clamping structure provided by an embodiment of the present disclosure;
[0045] Figure 6 is a schematic cross-sectional view of a trench gate transistor provided by an embodiment of the present disclosure;
[0046] Figure 7 is a schematic top view of a trench gate transistor provided by an embodiment of the present disclosure;
[0047] Figure 8 is a schematic top view of a trench gate transistor provided by another embodiment of the present disclosure. Detailed Embodiments
[0048] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present disclosure and should not be construed as a limitation of the present disclosure. On the contrary, the embodiments of the present disclosure include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.
[0049] It should be noted that a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a voltage-type control device, with a simple drive circuit, low drive power, fast switching speed, and high operating frequency.
[0050] Among them, Figure 1 is a schematic structural diagram of an existing planar-gate silicon carbide MOSFET. Figure 2 is a schematic structural diagram of another existing trench-gate silicon carbide MOSFET. As Figure 1 and Figure 2 shown, in the trench-gate silicon carbide MOSFET, since its channel is in the vertical direction, the silicon carbide surface in this direction has a higher channel mobility. At the same time, the cell size is small and the on-state current density is large. Therefore, the trench-gate silicon carbide MOSFET has more performance advantages than the planar-gate silicon carbide MOSFET.
[0051] However, the trench-gate silicon carbide MOSFET has relatively serious reliability problems: when a relatively high voltage is blocked at the corner in the trench-gate structure of the trench-gate silicon carbide MOSFET, the electric field here is extremely high, far exceeding that of the planar-gate silicon carbide MOSFET. Therefore, the gate oxide layer at this corner is very easy to be broken down, resulting in poor reliability of the trench-gate silicon carbide MOSFET.
[0052] In the related art, various technical solutions of trench-gate silicon carbide MOSFETs will design special shielding structures to protect this corner and avoid reliability problems at this corner.
[0053] For example, Figure 3 is a schematic structural diagram of an existing trench-gate silicon carbide MOSFET with a designed shielding structure. As Figure 3 shown, a shielding structure is implanted by high-energy ions under the gate oxide layer of this trench-gate silicon carbide MOSFET.
[0054] Again, for example, Figure 4 is a schematic structural diagram of another existing trench-gate silicon carbide MOSFET with a designed shielding structure. As Figure 4As shown, it designs the shielding structure by adopting a deep trench process.
[0055] It should be noted that the above shielding structure requires a complex process flow and extremely high capabilities of process equipment. In addition, during the operation of the trench-gated silicon carbide MOSFET with the above-designed shielding structure, the forward conduction current will flow through the shielding structure. Therefore, this shielding structure will introduce an obvious Junction Field-Effect Transistor (JFET) resistance, thereby increasing the on-resistance of the trench-gated silicon carbide MOSFET and resulting in a decline in the performance of the trench-gated silicon carbide MOSFET. Additionally, it is also difficult to adjust the reduction level of the electric field intensity for the shielding structure.
[0056] The following will specifically describe the present disclosure with reference to specific embodiments.
[0057] Figure 5 It is a cross-sectional schematic diagram of an electric field clamping structure provided by an embodiment of the present disclosure.
[0058] As Figure 5 shown, the electric field clamping structure includes:
[0059] A plurality of PN junctions arranged at intervals, the PN junction is formed by a first doping region 11 and a second doping region 12 arranged in a stacked manner, and a third doping region 13 is arranged between adjacent PN junctions;
[0060] The first doping region 11 is of the first doping type, and both the second doping region 12 and the third doping region 13 are of the second doping region type.
[0061] According to some embodiments, a PN junction refers to the contact surface of two semiconductors of different doping types. For example, the first doping type is P-type and the second doping region type is N-type; or the first doping type is N-type and the second doping region type is P-type. In the embodiments of the present disclosure, the PN junction specifically refers to the contact surface between the first doping region 11 and the second doping region 12.
[0062] In some embodiments, the spacing between adjacent PN junctions may refer to the width of the third doping region 13, for example.
[0063] According to some embodiments, when the electric field clamping structure is applied in a trench gate transistor, the breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure in the trench gate transistor. Therefore, during the operation of the trench gate transistor, space charge regions are formed inside the first doped region 11, the second doped region 12, and the third doped region 13. As the blocking voltage borne by the transistor gradually increases to approach the breakdown voltage of the electric field clamping structure, carriers with higher energy in the space charge region collide with neutral atoms in the space charge region and generate impact ionization, producing new electron-hole pairs. These newly generated electrons and holes will, under the action of the electric field, regain energy, collide with other neutral atoms to ionize them, and generate more electron-hole pairs. This chain reaction continues, causing the number of carriers in the space charge region to increase exponentially, just like an avalanche, causing the reverse current to increase exponentially. Eventually, the electric field clamping structure undergoes avalanche breakdown, so that the blocking voltage borne by the transistor also stops increasing, that is, the electric field strength at the corner of the gate trench structure stops increasing, thereby being able to clamp the electric field strength at the corner of the gate trench structure below a safe value and reducing the occurrence of breakdown at the trench corner of the trench gate transistor. In addition, the manufacturing process of the electric field clamping structure is simple, and the first doped region, the second doped region, and the third doped region can be formed only through a simple ion implantation process, which can reduce the manufacturing cost of the transistor.
[0064] Optionally, the breakdown voltage of the electric field clamping structure is determined by at least one of the doping concentration of the first doped region 11, the doping concentration of the second doped region 12, the doping concentration of the third doped region 13, and the spacing between adjacent PN junctions.
[0065] It should be noted that when designing the electric field clamping structure, first, the breakdown voltage at the corner of the gate trench structure in the trench gate transistor can be determined; then, the breakdown voltage of the electric field clamping structure can be determined according to the breakdown voltage at the corner; finally, the doping concentration of the first doped region 11, the doping concentration of the second doped region 12, the doping concentration of the third doped region 13, and the spacing between adjacent PN junctions can be determined according to the breakdown voltage of the electric field clamping structure. According to some embodiments, when determining the doping concentration of the first doped region 11, the doping concentration of the second doped region 12, the doping concentration of the third doped region 13, and the spacing between adjacent PN junctions according to the breakdown voltage of the electric field clamping structure, the spacing between adjacent PN junctions can be determined first according to the breakdown voltage of the electric field clamping structure, and then the doping concentration of the first doped region 11, the doping concentration of the second doped region 12, and the doping concentration of the third doped region 13 can be determined according to the breakdown voltage of the electric field clamping structure.
[0066] In some embodiments, when the spacing between adjacent PN junctions has been determined, the doping concentrations of the first doping region 11, the second doping region 12, and the third doping region 13 can be determined according to the breakdown voltage of the electric field clamping structure by the following formula:
[0067]
[0068] where N D is the doping concentration (including the doping concentrations of the first doping region 11, the second doping region 12, and the third doping region 13), V B is the breakdown voltage of the electric field clamping structure, ε is the dielectric constant, q is the electric charge amount, and E c is the electric field strength.
[0069] Taking a scenario as an example, for the industrial and automotive application fields, the breakdown voltage of semiconductor devices is generally 400V to 3000V, that is, the breakdown voltage at the corner of the trench-gate transistor is generally 400V to 3000V. According to the high critical electric field strength characteristics of the silicon carbide material, the magnitude of the doping concentration determines the electric field strength borne by the structure under the blocking condition and also affects the on-resistance. Therefore, the doping concentration range of the first doping region corresponding to the breakdown voltage at the corner of 400V to 3000V can be selected as 1E16 cm-3 to 1E20 cm-3, the doping concentration range of the second doping region can be selected as 1E15 cm-3 to 8E17 cm-3; the doping concentration range of the third doping region can be selected as 1E16 cm-3 to 1E19 cm-3; the spacing range between adjacent PN junctions can be selected as 0.2 um to 10.0 um. Based on the above concentration intervals and spacing intervals, on the basis of meeting the breakdown voltage of the trench-gate transistor, the forward on-resistance of the electric field clamping structure is low.
[0070] It should be noted that the PN junction can form a space charge region (depletion layer) under the action of the built-in potential. At the blocking voltage, the space charge regions of adjacent PN junctions will assist in sharing a part of the voltage to reduce the concentration of power lines, reduce the electric field strength of the PN junction, and increase the breakdown voltage of the PN junction. However, if the spacing distance between PN junctions is larger, the effect of sharing voltage will be weaker, and the breakdown voltage of the PN junction will decrease.
[0071] Similarly, the doping concentration between PN junctions will affect the width of the space charge region of the PN junction. According to Poisson's equation, the higher the doping concentration between PN junctions, the smaller the width of the space charge region, the weaker the effect of sharing voltage, and the lower the breakdown voltage.
[0072] That is to say, the higher the spacing between adjacent PN junctions, the lower the breakdown voltage of the clamping structure. Or, the higher the doping concentration of the second doping region 12, the lower the breakdown voltage of the clamping structure. Or, the higher the doping concentration of the third doping region 13, the lower the breakdown voltage of the clamping structure.
[0073] For example, when the first doping type is P-type, the second doping region type is N-type, the doping concentration of the first doping region 11 is 1E18 cm-3, the doping concentration of the second doping region 12 is 5E16 cm-3, the doping concentration of the third doping region 13 is 3E17 cm-3, and the spacing between adjacent PN junctions is 1.0 um, the breakdown voltage of this electric field clamping structure can be 1800V.
[0074] At this time, the spacing between adjacent PN junctions can be increased to reduce the breakdown voltage of the electric field clamping structure. For example, when the first doping type is P-type, the second doping region type is N-type, the doping concentration of the first doping region 11 is 1E18 cm-3, the doping concentration of the second doping region 12 is 5E16 cm-3, the doping concentration of the third doping region 13 is 3E17 cm-3, and the spacing between adjacent PN junctions is 2.0 um, the breakdown voltage of this electric field clamping structure can drop to 1300V.
[0075] Or, the doping concentration of the second doping region 12 can also be increased to reduce the breakdown voltage of the electric field clamping structure. For example, when the first doping type is P-type, the second doping region type is N-type, the doping concentration of the first doping region 11 is 1E18 cm-3, the doping concentration of the second doping region 12 is 1E17 cm-3, the doping concentration of the third doping region 13 is 3E17 cm-3, and the spacing between adjacent PN junctions is 1.0 um, the breakdown voltage of this electric field clamping structure can drop to 1300V.
[0076] Or, the doping concentration of the third doping region 13 can also be increased to reduce the breakdown voltage of the electric field clamping structure. For example, when the first doping type is P-type, the second doping region type is N-type, the doping concentration of the first doping region 11 is 1E18 cm-3, the doping concentration of the second doping region 12 is 5E16 cm-3, the doping concentration of the third doping region 13 is 6E17 cm-3, and the spacing between adjacent PN junctions is 1.0 um, the breakdown voltage of this electric field clamping structure can drop to 1300V.
[0077] It should be noted that the doping concentration of the second doping region 12 and the doping concentration of the third doping region 13 can be adjusted by adjusting the dose and energy injected during ion implantation, and the spacing between adjacent PN junctions can also be adjusted by adjusting the relevant dimensions during the manufacturing process. The adjustment of these two methods is simple and easy for the electric field shielding structure. That is to say, the adjustment difficulty of the breakdown voltage of the electric field clamping structure is low.
[0078] Optionally, as Figure 5 shown, the first surface of the first doped region 11 and the first surface of the third doped region 13 are in the same plane, and the second surface of the first doped region 11 is in contact with the first surface of the second doped region 12.
[0079] According to some embodiments, the width of the first doped region 11 may be the same as the width of the second doped region 12, for example.
[0080] In some embodiments, the depth of the third doped region 13 may be higher than the sum of the depths of the first doped region 11 and the second doped region 12.
[0081] It should be noted that when the second surface of the first doped region 11 is in contact with the first surface of the second doped region 12, this contact surface is the PN junction.
[0082] Optionally, as Figure 5 shown, the electric field clamping structure further includes a first oxide layer 14; wherein,
[0083] The first oxide layer 14 covers the first surface of the third doped region 13 and extends to both sides and at least covers a part of the first surface of the first doped region 11.
[0084] According to some embodiments, the first oxide layer 14 can be used as a mask to protect the sensitive PN junction in the silicon from contamination, improving the reliability of the electric field clamping structure. The first oxide layer 14 can also be used as an effective insulating layer for depositing metal interconnects thereon.
[0085] Optionally, as Figure 5 shown, the electric field clamping structure further includes a first metal structure 15; wherein,
[0086] The first metal structure 15 covers at least a part of the first surface of the first doped region 11.
[0087] According to some embodiments, the first metal structure 15 can conduct electricity as an electrode.
[0088] In some embodiments, the first metal structure 15 can be in contact with the first oxide layer 14 and jointly cover the first surface of the first doped region 11.
[0089] In summary, for the electric field clamping structure provided in the embodiments of the present disclosure, since the breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure, when the blocking voltage borne by the transistor reaches the breakdown voltage of the lower electric field clamping structure, the electric field clamping structure is broken down, and the transistor breaks down in advance, so that the electric field strength at the corner of the gate trench structure can be clamped below the safe value, and the breakdown at the trench corner of the trench gate transistor can be reduced. In addition, the manufacturing process of the electric field clamping structure is simple, and the first doping region, the second doping region, and the third doping region can be formed only by a simple ion implantation process, which can reduce the manufacturing cost of the transistor.
[0090] The embodiments of the present disclosure also provide a trench gate transistor.
[0091] Specifically, Figure 6 is a cross-sectional schematic diagram of a trench gate transistor provided in the embodiments of the present disclosure. As Figure 6 shown, the trench gate transistor includes:
[0092] A plurality of cell structures 2, the cell structure 2 includes a plurality of trench small cells 21 distributed in an array, and an electric field clamping structure 1 as shown in any of the above embodiments is provided in the peripheral region of each cell structure 2;
[0093] Each trench small cell 21 includes a gate trench structure 211, and the breakdown voltage of the electric field clamping structure 1 is less than the breakdown voltage at the corner of the gate trench structure 211.
[0094] According to some embodiments, the breakdown voltage of the electric field clamping structure 1 is less than the breakdown voltage at the corner of the gate trench structure 211. Thus, when the blocking voltage borne by the trench gate transistor reaches the breakdown voltage of the lower electric field clamping structure 1, the PN junction between the first doping region 11 and the second doping region 12 in the electric field clamping structure 1 will be broken down, and the trench gate transistor will break down in advance, and the blocking voltage borne by the transistor will also stop increasing. That is, the electric field strength at the corner of the gate trench structure will stop increasing. Therefore, the electric field strength at the corner of the gate trench structure 211 can be clamped below the safe value, and the breakdown at the trench corner of the trench gate transistor can be reduced. In addition, the electric field clamping structure 1 is independent of the trench small cell 21, and the forward conduction current during the operation of the trench small cell 21 will not flow through the electric field clamping structure 1, so that no additional JFET resistance will be introduced, and the performance of the transistor can be improved.
[0095] According to some embodiments, Figure 7 is a top view schematic diagram of a trench gate transistor provided in the embodiments of the present disclosure. As Figure 7As shown, the trench cell 21 and the electric field clamping structure 1 are both square. The trench gate transistor includes four cell structures 2, and one row or one column of sub-cells are shared between adjacent cell structures 2. Each cell structure 2 includes six rows of sub-cells. The cell structure 2 and the electric field clamping structure 1 can jointly form a 6*6 grid array, and the four electric field clamping structures 1 are respectively located at the four corners of the 6*6 grid array.
[0096] In some embodiments, Figure 8 is a top view schematic diagram of a trench gate transistor provided by another embodiment of the present disclosure. As Figure 8 shown, the trench cell 21 and the electric field clamping structure 1 are both strip-shaped. The trench gate transistor includes one cell structure 2, and the cell structure 2 includes one row of sub-cells. An electric field clamping structure 1 is respectively arranged on the periphery of the first column and the last column of the sub-cells, and a total of two electric field clamping structures 1 are arranged.
[0097] It should be noted that the distribution manners of the trench cell 21 and the electric field clamping structure 1 are not limited to Figure 7 and Figure 8 these two distribution manners. The distribution manners of the trench cells 21 arranged in an array include but are not limited to parallel arrangement, parallel arrangement, etc.
[0098] For example, the cell structure 2 may include at least one row of sub-cells, and each row of sub-cells includes a plurality of trench cells 21 arranged in parallel;
[0099] Electric field clamping structures are respectively arranged on the periphery of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells.
[0100] For example, the cell structure 2 may further include at least one column of sub-cells, and each column of the sub-cells includes a plurality of trench cells 21 arranged side by side;
[0101] The electric field clamping structure 1 is respectively arranged on the periphery of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells.
[0102] It should be noted that the shapes and sizes of the trench cell 21 and the electric field clamping structure 1 can be adjusted according to actual situations and are not limited herein. For example, both the trench cell 21 and the electric field clamping structure 1 can be square; or, both the trench cell 21 and the electric field clamping structure 1 can be strip-shaped; or, the trench cell 21 is square and the electric field clamping structure 1 is strip-shaped.
[0103] Optionally, as Figure 6 shown, the trench gate transistor further includes:
[0104] A silicon carbide substrate 22 is provided with an epitaxial layer 23 on a first surface thereof, and both the silicon carbide substrate 22 and the epitaxial layer 23 are of a second doping region type;
[0105] The cell structure 2 and the electric field clamping structure 1 are disposed within the epitaxial layer 23.
[0106] According to some embodiments, the epitaxial layer 23 adopts a high-resistance specification, that is, the resistance value corresponding to the epitaxial layer 23 is higher than the epitaxial resistance threshold. For example, a trench gate transistor with a breakdown voltage withstand of 1200V may adopt an epitaxial layer 23 with a breakdown voltage withstand of 2200V. Therefore, when the breakdown voltage of the electric field clamping structure is 1300V, the electric field strength at the corner of the gate trench structure is still within a safe range, so the electric field strength at the corner of the gate trench structure can always not exceed the safe value.
[0107] Optionally, as Figure 6 shown, the trench gate transistor includes two trench small cells 21, and the trench small cell 21 further includes:
[0108] A fourth doping region 212 disposed on both sides of the end of the gate trench structure 211 far from the silicon carbide substrate 22, and the fourth doping region 212 is of a second doping region type;
[0109] A sixth doping region 213 disposed on the side of the fourth doping region 212 far from the gate trench structure, the sixth doping region 213 is of a first doping region type and the doping concentration of the sixth doping region 213 is the same as the doping concentration of the first doping region 11;
[0110] A second oxide layer 214 covering the first surface of the gate trench structure and extending to both sides and covering a part of the first surface of the fourth doping region 212;
[0111] A second metal structure 215 covering the first surface of the sixth doping region 213 and covering a part of the first surface of the fourth doping region 212;
[0112] A well region 216 disposed on the second surface of the fourth doping region 212, and the well region 216 is of a first doping region type.
[0113] According to some embodiments, the functions of the materials used for the second oxide layer 214 and the first oxide layer 14 can be the same.
[0114] In some embodiments, the functions of the materials used for the second metal structure 215 and the first metal structure 15 can also be the same. Therefore, when the electric field clamping structure 1 and the trench small cell 21 are in contact settings, the first metal structure 15 and the second metal structure 215 are in contact connection. Similarly, the sixth doping region 213 can also be in contact connection with the first doping region 11.
[0115] According to some embodiments, when adjacent trench cells 21 are in contact with each other, the two second metal structures 215 between the two trench cells 21 are in contact connection, and the two sixth doped regions 213 are in contact connection.
[0116] In some embodiments, the total width of the two sixth doped regions 213 between the two trench cells 21 in contact connection, and the width of one sixth doped region 213 between the trench cell 21 in contact connection and the electric field clamping structure 1 can be the same, for example.
[0117] Optionally, the gate trench structure 211 includes:
[0118] A gate oxide layer trench 2111 disposed in the epitaxial layer 23;
[0119] A gate layer 2112 disposed in the gate oxide layer trench 2111.
[0120] According to some embodiments, the corner of the gate trench structure 211 can refer to the corner 21121 of the gate oxide layer trench 2111, for example.
[0121] It should be noted that as the voltage between the epitaxial layer 23 and the metal structure (including the second metal structure 215 and the first metal structure 15) gradually increases to the breakdown voltage of the electric field clamping structure 1, the PN junction between the first doped region 11 and the second doped region 12 in the electric field clamping structure 1 will be broken down, resulting in the breakdown between the epitaxial layer 23 and the metal structure, and the voltage between the epitaxial layer 23 and the metal structure will also stop increasing. That is, the voltage between the gate layer 2112 and the epitaxial layer 23 will also stop increasing, and the voltage at the corner 21121 of the gate oxide layer trench 2111 will also stop increasing. Therefore, the electric field strength at the corner of the gate trench structure can be clamped below the safe value, and the breakdown at the trench corner of the trench gate transistor can be reduced.
[0122] In summary, for the trench gate transistor provided by the embodiments of the present disclosure, since the breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure, when the blocking voltage borne by the transistor reaches the breakdown voltage of the lower electric field clamping structure, the electric field clamping structure is broken down, and the transistor is broken down in advance. The electric field strength at the corner of the gate trench structure can be clamped below the safe value, and the breakdown at the trench corner of the trench gate transistor can be reduced. In addition, the manufacturing process of the electric field clamping structure is simple, and the first doped region, the second doped region, and the third doped region can be formed only by a simple ion implantation process, which can reduce the manufacturing cost of the transistor. In addition, the electric field clamping structure is independent of the trench cell, and the forward conduction current during the operation of the trench cell does not flow through the electric field clamping structure, so that no additional JFET resistance is introduced, and the performance of the transistor can be improved.
[0123] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms may be directed to different embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0124] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0125] Although the embodiments of the present disclosure have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.
Claims
1. An electric field clamping structure, characterized in that, applied to a trench gate transistor, comprising: a plurality of PN junctions arranged at intervals, the PN junctions being formed by a first doped region and a second doped region arranged in a stacked manner, and a third doped region being arranged between adjacent PN junctions; the first doped region is of a first doping type, and the second doped region and the third doped region are both of a second doping type; the breakdown voltage of the electric field clamping structure is less than the breakdown voltage at the corner of the gate trench structure in the trench gate transistor.
2. The electric field clamping structure according to claim 1, characterized in that, the breakdown voltage of the electric field clamping structure is determined by at least one of the doping concentration of the first doped region, the doping concentration of the second doped region, the doping concentration of the third doped region, and the spacing between adjacent PN junctions.
3. The electric field clamping structure according to claim 2, characterized in that, when the voltage range of the breakdown voltage of the electric field clamping structure is 400V to 3000V, the doping concentration range of the first doped region is 1E16 cm-3 to 1E20 cm-3; the doping concentration range of the second doped region is 1E15 cm-3 to 8E17 cm-3; the doping concentration range of the third doped region is 1E16 cm-3 to 1E19 cm-3; the spacing range between adjacent PN junctions is 0.2 um to 10.0 um.
4. The electric field clamping structure according to claim 1, characterized in that, the first doping type is P-type and the second doping type is N-type; or, the first doping type is N-type and the second doping type is P-type.
5. The electric field clamping structure according to claim 1, characterized in that, the first surface of the first doped region and the first surface of the third doped region are located on the same plane, and the second surface of the first doped region is in contact with the first surface of the second doped region.
6. The electric field clamping structure according to claim 5, characterized in that, the electric field clamping structure further includes a first oxide layer; wherein, the first oxide layer covers the first surface of the third doped region and extends to both sides and at least covers part of the first surface of the first doped region.
7. The electric field clamping structure according to claim 5, characterized in that, the electric field clamping structure further includes a first metal structure; wherein, the first metal structure at least covers part of the first surface of the first doped region.
8. A trench gate transistor, characterized in that, comprising: a plurality of cell structures, the cell structures including a plurality of trench sub-cells distributed in an array, and each trench sub-cell includes a gate trench structure; an electric field clamping structure as described in any one of claims 1 to 7 is arranged in the peripheral region of each cell structure.
9. The trench gate transistor according to claim 8, characterized in that, the cell structure includes at least one row of sub-cells, and each row of sub-cells includes a plurality of trench sub-cells arranged in parallel; the electric field clamping structure is arranged at the periphery of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells respectively.
10. The trench gate transistor according to claim 8, characterized in that, the cell structure includes at least one column of sub-cells, and each column of the sub-cells includes a plurality of trench sub-cells arranged side by side; the electric field clamping structures are respectively arranged at the peripheries of the first column and the last column of the first row of sub-cells and the first column and the last column of the last row of sub-cells.