Ring gate field effect transistor, preparation method thereof and dynamic random access memory

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to a gate-all-around field effect transistor, a preparation method thereof and a dynamic random access memory. According to the gate-all-around field effect transistor, required stress is introduced into a channel to relieve the short-channel effect of a device, and the carrier mobility is improved.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor devices, and particularly relates to a gate-all-around field effect transistor, a preparation method thereof, and a dynamic random access memory. Background Art

[0002] Dynamic random access memory (DRAM) is a volatile, capacitor-based, destructive read-form semiconductor memory. It currently occupies more than 50% of the memory market size.

[0003] Dynamic random access memory (DRAM) is composed of memory cells. Each memory cell contains a transistor. When writing data, the transistor is turned on, and charges are pushed into the capacitor (1) or removed from the capacitor (0); when reading data, the charges are extracted and measured.

[0004] Gate-all-around Field Effect Transistor (GAAFET) is an advanced semiconductor device technology. This technology enhances the gate's control ability over the channel by surrounding the entire channel with the gate on all four sides, thereby improving the performance of the transistor.

[0005] However, the carrier mobility of the existing structure of the gate-all-around field effect transistor still needs to be improved. Summary of the Invention

[0006] The technical objective of this application is to at least solve the technical problem that the carrier mobility of the existing structure of the gate-all-around field effect transistor is not ideal.

[0007] The first aspect of this application is to provide a gate-all-around field effect transistor, which includes:

[0008] A substrate;

[0009] A nanosheet stack portion: disposed on one surface of the substrate; the nanosheet stack portion includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence;

[0010] A gate stack: disposed around the nanosheet stack portion;

[0011] A source and a drain: located outside the nanosheet stack portion.

[0012] In some embodiments, in the direction parallel to the plane where the substrate is located, the end of the first semiconductor layer is retracted inward relative to the end of the second semiconductor layer.

[0013] In some embodiments, in the direction parallel to the plane where the substrate is located, the end of the third semiconductor layer is retracted inward relative to the end of the second semiconductor layer.

[0014] In some embodiments, in a direction parallel to the plane of the substrate, the ends of the first semiconductor layer are flush with the ends of the third semiconductor layer.

[0015] In some embodiments, the transistor further includes sidewalls,

[0016] The sidewalls are disposed between the gate stack and the source and drain;

[0017] The sidewalls extend along the stacking direction of the semiconductor layers and separate the first semiconductor layer and the third semiconductor layer from the source and drain.

[0018] In some embodiments, the material of the first semiconductor layer is the same as the material of the third semiconductor layer.

[0019] In some embodiments, the material of the second semiconductor layer is different from the materials of the first semiconductor layer and the third semiconductor layer.

[0020] In some embodiments, the materials of the first semiconductor layer and the third semiconductor layer include silicon-germanium compounds.

[0021] In some embodiments, the material of the second semiconductor layer includes any one or more of elemental silicon, elemental germanium, or silicon-germanium compounds.

[0022] In some embodiments, the orthographic projection shape of the nanosheet stack portion on the first plane is any one of a rectangle, a cross, a T shape, a triangle, a trapezoid, a sigma shape, and a fan shape;

[0023] The first plane is perpendicular to the second plane, and the second plane is the plane of the substrate.

[0024] The second aspect of the present application is to provide a dynamic random access memory, which includes the transistor described in the first aspect.

[0025] The third aspect of the present application is to provide a method for manufacturing a surround field effect transistor, the method including:

[0026] Providing a substrate;

[0027] Forming at least one stacked structure on one side surface of the substrate, the stacked structure including a first sacrificial layer, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence;

[0028] Etching the at least one stacked structure to form a fin structure;

[0029] The first sacrificial layer, the first semiconductor layer and the third semiconductor layer are etched concave relative to the second semiconductor layer to form a nanosheet stack portion;

[0030] Forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer;

[0031] forming a source region and a drain region on both sides of the second semiconductor layer;

[0032] Etching the first sacrificial layer to form a vacancy;

[0033] A gate stack is formed in the vacancy.

[0034] In some embodiments, the step of etching the at least one stacked structure to form a fin structure includes:

[0035] A first sidewall is formed on a surface of the stacked structure that is away from the substrate, and the stacked structure is etched along an extension direction of the first sidewall to a surface of the substrate to form a fin structure.

[0036] In some embodiments, the step of etching the first sacrificial layer, the first semiconductor layer, and the third semiconductor layer recessed relative to the second semiconductor layer to form a nanosheet stack portion comprises:

[0037] The first sacrificial layer, the first semiconductor layer and the third semiconductor layer are selectively partially etched along the stacking direction of each conductor layer.

[0038] In some embodiments, the step of forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer, and the third semiconductor layer includes:

[0039] Forming a spacer material layer on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer, and forming a third spacer by anisotropic etching;

[0040] The third sidewall spacer is selectively partially etched along the extension direction of the third sidewall spacer to the surface of the substrate to expose the bottom of the substrate.

[0041] In some embodiments, the step of forming a gate stack in the vacancy includes:

[0042] An interface layer, a high dielectric constant material layer, a barrier layer, a work function layer and a gate metal layer are sequentially formed in the above vacancies.

[0043] In some embodiments, the material of the first sacrificial layer includes a first silicon-germanium compound; the material of the first semiconductor layer includes a second silicon-germanium compound;

[0044] The mass percentage of germanium in the first silicon-germanium compound is greater than that in the second silicon-germanium compound.

[0045] In some embodiments, the material of the third semiconductor layer is the same as that of the first semiconductor layer.

[0046] In some embodiments, the material of the second semiconductor layer includes any one or more of elemental silicon, elemental germanium, or silicon-germanium compounds.

[0047] Advantages of the present application:

[0048] The transistor provided by the present application introduces a stacked structure in the channel, and this stacked structure can provide biaxial tensile stress, thereby being used to improve the carrier mobility. Description of the drawings

[0049] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0050] Figure 1 、 Figure 2 Schematically shows the schematic diagrams of some embodiments of the present application;

[0051] Figure 3 Schematically shows the flowcharts of the transistor manufacturing processes of some embodiments of the present application;

[0052] Figure 4 Schematically shows the partial structural diagrams of the transistors of some embodiments of the present application;

[0053] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B Schematically shows a structural diagram of a method for manufacturing a transistor according to some embodiments of the present application. Among them, in each of the attached drawings, Figure A is a schematic diagram obtained along the X-X' axial direction in Figure 4 , and Figure B is a schematic diagram obtained along the Y-Y' axial direction in Figure 4 ;

[0054] Among them Figure 21C schematically shows a structural diagram of each dielectric layer around the gate metal layer;

[0055] Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 Schematically shows a structural diagram of a partial manufacturing method of another transistor according to some embodiments of the present application, and Figures 25 to 29 is a schematic diagram obtained along the Y-Y' axial direction in Figure 4 ;

[0056] The reference numerals in the attached drawings are represented as follows:

[0057] 110, substrate;

[0058] 120, stacked structure: 121, the first semiconductor layer before etching; 121', the first semiconductor layer after etching;

[0059] 122, the second semiconductor layer; 123, the third semiconductor layer before etching; 123', the third semiconductor layer after etching; 120a, fin structure; 120b, fin structure after selective partial etching; 120c, nanosheet stack part;

[0060] 131, the first sacrificial layer; 131', the first sacrificial layer after etching; 131a, the first vacancy;

[0061] 132, the second sacrificial layer;

[0062] 140a, the first sidewall; 140b, the second sidewall; 140c, the third sidewall; 140c', the third sidewall after etching;

[0063] 150, Shallow Trench Isolation Region;

[0064] 160, Gate Oxide Layer;

[0065] 170, Surrounding False Gate; 170’, Second Vacancy;

[0066] 180a, First Hard Mask Layer;

[0067] 190a, Source Region; 190b, Drain Region;

[0068] 190a’, Source; 190b’, Drain;

[0069] 200a, First Interlayer Dielectric Layer; 200b, Second Interlayer Dielectric Layer; 200, Top Interlayer Dielectric Layer;

[0070] 210, Interface Layer;

[0071] 220, High-k Dielectric Material Layer;

[0072] 230, Barrier Layer;

[0073] 240, Work Function Layer;

[0074] 250, Gate Metal Layer;

[0075] 300, Gate Stack;

[0076] 260, Contact Layer;

[0077] 270, Contact Electrode;

[0078] First Direction: The extending direction of the first sidewall, which can also refer to the stacking direction of the transistors in the drawings or the thickness direction of each layer;

[0079] Second Direction: The length extending direction of the first semiconductor layer or the third semiconductor layer, which can also refer to the Y-Y’ axis direction in the drawings. Detailed Implementation Manner

[0080] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0081] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. And those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0082] In the context of the present application, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.

[0083] The present application may use the term "coupled to" along with its derivatives. "Coupled" can mean one or more of the following. "Coupled" can mean that two or more elements are in direct physical contact or electrical contact. However, "coupled" can also mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other. The term "directly coupled" can mean that two or more elements are in direct contact.

[0084] The Gate-all-around Field Effect Transistor (GAAFET) is an advanced semiconductor device technology. This technology enhances the gate's control ability over the channel by surrounding the channel entirely on all four sides with the gate, thereby improving the performance of the transistor. The stacking of nanosheets or nanowires in GAAFET can increase the effective width, and thus increase the effective drive current. At the same time, GAAFET devices exhibit short-channel effects. The short-channel effect refers to a series of special effects that occur in micron-scale MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) when the channel length is shortened to be comparable to or even shorter than the electron mean free path. For example, as the channel length decreases, the proportion of the depletion region of the source-drain junction in the entire channel increases, resulting in a decrease in the amount of charge required to form an inversion layer, and thus causing the threshold voltage to decrease. This means that in short-channel devices, a higher gate electric field is required to control and form a normal channel, which affects the injection and collection of carriers. Moreover, in short-channel devices, due to the increase in the electric field strength, the carrier mobility becomes related to the electric field, and ultimately the carrier velocity reaches saturation. This means that at high electric fields, the carrier velocity no longer increases with the increase in the electric field, resulting in current saturation and affecting the switching speed and efficiency of the device.

[0085] As the process node size of semiconductor devices shrinks, the impact of device short-channel effects and carrier mobility degradation effects becomes increasingly prominent.

[0086] To suppress the device short-channel effect, currently adopted methods include introducing stress into the channel to improve the carrier mobility in the channel and the performance of transistor devices, as shown in the Figure 1 and Figure 2 schematic diagrams. The principle includes: through device structure, material, and process design, introducing stress into the transistor channel region to change the crystal lattice structure, thereby causing a change in carrier mobility. Under appropriate stress, the carrier mobility can be improved. For example, tensile stress along the channel direction can increase electron mobility, while compressive stress in the channel direction can increase hole mobility.

[0087] How to introduce the required stress into the channel is a technical problem to be solved in this field.

[0088] To solve the above technical problem, this application discloses a gate-all-around field effect transistor, which includes a substrate and a nanosheet stack portion located on one surface of the substrate. Among them, the nanosheet stack portion includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence; it also includes a gate stack, a source electrode, and a drain electrode, where the gate stack surrounds the nanosheet stack portion, and the source electrode and the drain electrode are located outside the nanosheet stack portion.

[0089] The transistor provided by this application includes a stacked structure, which can provide biaxial tensile stress and is thus used to improve the carrier mobility.

[0090] In some embodiments, in the direction parallel to the plane of the substrate, the end of the first semiconductor layer is recessed inward relative to the end of the second semiconductor layer.

[0091] In some embodiments, in the direction parallel to the plane of the substrate, the end of the third semiconductor layer is recessed inward relative to the end of the second semiconductor layer.

[0092] In some embodiments, in the direction parallel to the plane of the substrate, the end of the first semiconductor layer is flush with the end of the second semiconductor layer.

[0093] In some embodiments, the transistor further includes sidewalls.

[0094] The sidewalls are disposed between the gate stack and the source and drain.

[0095] The sidewalls extend along the stacking direction of the semiconductor layers and separate the first semiconductor layer and the third semiconductor layer from the source and drain.

[0096] In some embodiments, the material of the first semiconductor layer is the same as that of the third semiconductor layer.

[0097] In some embodiments, the material of the second semiconductor layer is different from that of the first semiconductor layer and the third semiconductor layer.

[0098] In some embodiments, the material of the first semiconductor layer and the third semiconductor layer includes silicon germanium compound.

[0099] In some embodiments, the material of the second semiconductor layer includes any one or more of silicon, germanium, or silicon germanium compound.

[0100] In some embodiments, the orthographic projection shape of the nanosheet stack portion on the first plane is any one of a rectangle, a cross, a T shape, a triangle, a trapezoid, a sigma shape, and a fan shape.

[0101] The first plane is perpendicular to the second plane, and the second plane is the plane of the substrate.

[0102] The second aspect of this application is to provide a dynamic random access memory, which includes the transistor described in the first aspect.

[0103] The dynamic random access memory includes the above transistor and a capacitor. The dynamic random access memory has good application prospects in personal computers (PCs), smart phones, servers, embedded devices, game consoles and communication equipment (such as DVB, DVD, LCD TV, monitoring and other electronic systems).

[0104] The third aspect of the present application is to provide a method for preparing a gate-all-around field effect transistor, the method comprising:

[0105] providing a substrate;

[0106] At least one stacked structure is formed on one side surface of the substrate, wherein the stacked structure includes a first sacrificial layer, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are stacked in sequence;

[0107] Etching the at least one stacked structure to form a fin structure;

[0108] The first sacrificial layer, the first semiconductor layer and the third semiconductor layer are etched concave relative to the second semiconductor layer to form a nanosheet stack portion;

[0109] Forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer;

[0110] forming a source region and a drain region on both sides of the second semiconductor layer;

[0111] Etching the first sacrificial layer to form a vacancy;

[0112] A gate stack is formed in the vacancy.

[0113] In some embodiments, the step of etching the at least one stacked structure to form a fin structure includes:

[0114] A first sidewall is formed on a surface of the stacked structure that is away from the substrate, and the stacked structure is etched along an extension direction of the first sidewall to a surface of the substrate to form a fin structure.

[0115] In some embodiments, the step of etching the first sacrificial layer, the first semiconductor layer, and the third semiconductor layer recessed relative to the second semiconductor layer to form a nanosheet stack portion comprises:

[0116] The first sacrificial layer, the first semiconductor layer and the third semiconductor layer are selectively partially etched along the stacking direction of each conductor layer.

[0117] In some embodiments, the step of forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer, and the third semiconductor layer includes:

[0118] Forming a spacer material layer on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer, and forming a third spacer by anisotropic etching;

[0119] The third sidewall spacer is selectively partially etched along the extension direction of the third sidewall spacer to the surface of the substrate to expose the bottom of the substrate.

[0120] In some embodiments, the step of forming a gate stack in the vacancy includes:

[0121] An interface layer, a high dielectric constant material layer, a barrier layer, a work function layer and a gate metal layer are sequentially formed in the above vacancies.

[0122] In some embodiments, the material of the first sacrificial layer includes a first silicon-germanium compound; the material of the first semiconductor layer includes a second silicon-germanium compound;

[0123] The mass percentage of germanium in the first silicon-germanium compound is greater than the mass percentage of germanium in the second silicon-germanium compound.

[0124] In some embodiments, a material of the third semiconductor layer is the same as a material of the first semiconductor layer.

[0125] In some embodiments, the material of the second semiconductor layer includes any one or more of silicon, germanium, or silicon-germanium compounds.

[0126] The present application describes the transistor protected by the present application in combination with a specific preparation method as follows. The preparation method includes Figure 3 The process flow shown is as follows:

[0127] S100, providing a substrate;

[0128] S101, forming a stacked structure on one side surface of the substrate, the stacked structure comprising a first sacrificial layer, a first semiconductor layer before etching, a second semiconductor layer, and a third semiconductor layer before etching;

[0129] S102, forming a first side wall on a surface of the stacked structure facing away from the substrate, and etching the stacked structure along an extension direction of the first side wall to the surface of the substrate to form a fin structure, wherein the extension direction of the first side wall is a first direction, and the first direction is perpendicular to a direction of a plane where the substrate is located;

[0130] S103, forming a surrounding dummy gate outside the fin structure;

[0131] S104, etching the fin structure along the first direction to the surface of the substrate to form a source region and a drain region, wherein the source region and the drain region are located on both sides of the fin structure;

[0132] S105, selectively partially etching the first sacrificial layer, the first semiconductor layer and the third semiconductor layer in the fin structure; the first semiconductor layer after the selective partial etching, the third semiconductor layer after the selective partial etching and the second semiconductor layer constitute a nanosheet stacking part;

[0133] S106, removing the surrounding false gate to form a second vacancy;

[0134] S107, removing the first sacrificial layer after selective partial etching to form a first vacancy;

[0135] S108, forming a gate stack in the first vacancy and the second vacancy; the gate stack is disposed around the nanosheet stack portion;

[0136] S109, forming a top interlayer dielectric layer on a surface of the gate stack facing away from the substrate;

[0137] S110, opening a contact hole on the top interlayer dielectric layer, and leading out a contact electrode through the contact hole.

[0138] Example

[0139] A method for preparing a gate-all-around field effect transistor is provided. Figure 4 Taking the gate-all-around field-effect transistor as an example, the specific process includes:

[0140] S100, providing a substrate 110; Figure 5A , 5B As shown, the substrate 110 is a portion of a semiconductor wafer suitable for forming one or more IC devices, and can be a silicon substrate, including but not limited to silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-on-nothing (SON), silicon-on-insulator (SOI), or silicon-on-replacement insulator (SRI), or silicon-germanium substrate, and the like. The substrate 110 may additionally or alternatively include various isolation, doping and / or device features. For example, the present embodiment uses high-purity single crystal silicon as the substrate 110, and also includes forming a highly doped well region by injecting impurities into the high-purity single crystal silicon, diffusing, and annealing to achieve the desired well depth.

[0141] S101, removing silicon dioxide from the surface of the substrate 110, and epitaxially growing a plurality of stacked structures 120 on one side of the substrate 110, the stacked structures 120 comprising a first sacrificial layer 131, a first semiconductor layer 121 before etching, a second semiconductor layer 122, and a third semiconductor layer 123 before etching, which are stacked in sequence;Figure 6A , 6B In the embodiment, the material of the first sacrificial layer 131 includes a first silicon-germanium compound; the material of the first semiconductor layer 121 before etching includes a second silicon-germanium compound; the mass percentage of the germanium element in the first silicon-germanium compound is greater than the mass percentage of the germanium element in the second silicon-germanium compound; for example, the chemical formula of the first silicon-germanium compound is Si 1-y Ge y The chemical formula of the second silicon germanium compound is Si 1-x Ge x , x and y are each independently any one of greater than zero and less than 1, and y>x, in this embodiment, y is selected to be 0.85 and x is selected to be 0.50. The material of the third semiconductor layer 123 before etching in this embodiment is the same as the material of the first semiconductor layer 121 before etching. The material of the second semiconductor layer 122 in this embodiment includes silicon element. In this embodiment, the thickness of the first sacrificial layer 131, the first semiconductor layer 121 before etching, the second semiconductor layer 122 and the third semiconductor layer 123 before etching are each independently selected from any one of 1nm to 10nm. In this embodiment, the thickness of each semiconductor layer and sacrificial layer is each independently selected from 5nm.

[0142] S102a, such as Figure 7A , 7B As shown, a self-aligned spacer image transfer process (SIT, Spacer Image Transfer) is often used to form a first side wall 140a on the side surface of the above-mentioned stacked structure 120 away from the above-mentioned substrate 110, and the material of the first side wall 140a includes silicon nitride (SiNx); the specific formation process includes: forming a second sacrificial layer 132 with a strip by etching on the stacked structure 120, and the second sacrificial layer 132 can specifically be polycrystalline silicon (Poly Si, p-si) or amorphous silicon (α-si), and the deposition of this application includes first forming a side wall material layer of silicon nitride material, and then using anisotropic etching to form the first side wall 140a, and then removing the remaining second sacrificial layer 132.

[0143] like Figure 8A , 8B As shown in the figure, the stacked structure 120 is etched along the extension direction of the first sidewall 140a to the surface of the substrate 110 to form a fin structure 120a. The extension direction of the first sidewall 140a is perpendicular to the plane where the substrate 110 is located. The epitaxially grown stacked structure 120 is made into a plurality of periodically distributed fin structures 120a through an etching process. The first sidewall 140a is used as a mask for etching to form a fin structure 120a with the stacked structure 120. The upper part of the fin structure 120a includes a conductive channel region formed by the stacking, and the lower part is the substrate, forming a fin structure 120a. Figure 8A and8B The fin structure 120a is shown. The etching process is dry etching or wet etching. In this embodiment, reactive ion etching (RIE) can be used. The fin structure 120a will be used to form one or more horizontal nanosheets of n-type field effect transistors and / or p-type field effect transistors. Although Figure 8A , 8B Only one fin structure 120a is shown, and it should be understood that any suitable number and shape of fins may be used. The height of the fin structure 120a is about 100nm to 400nm (the distance between two surfaces oppositely disposed along the first direction), and 200nm is selected in this embodiment.

[0144] S102b, such as Figure 9A , 9B As shown in FIG. 1 , a shallow trench isolation region (STI) 150 is formed between adjacent fin structures 120a disposed on the substrate 110. The shallow trench isolation region (STI) 150 may be formed of a suitable dielectric material, such as silicon dioxide (SiO 2 ), Silicon Nitride (SiN x ), etc., the shallow trench isolation region 150 serves to separate transistors on adjacent fin structures 120a.

[0145] S103a, such as Figure 10A , 10B As shown, a gate oxide layer 160 and a wraparound dummy gate 170 are formed outside the fin structure 120a; a first hard mask layer 180a is formed on a surface of the wraparound dummy gate 170 that is away from the substrate 110; wherein, Figure 10B It can be seen that the gate oxide layer 160 and the surrounding dummy gate 170 are both arranged around the fin structure 120a, and the first hard mask layer 180a is located on the surface of the surrounding dummy gate 170 that is away from the substrate 110. The formation method of the surrounding dummy gate 170 includes thermal oxidation, chemical vapor deposition, sputtering and other processes, and the material of the surrounding dummy gate 170 includes polysilicon or non-polysilicon. The material of the gate oxide layer 160 includes silicon dioxide or some high dielectric constant materials, such as hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc., and the material of the first hard mask layer includes silicon dioxide, silicon nitride, silicon nitride, etc.

[0146] S103b, such as Figure 11A , 11B As shown, a second sidewall 140b is formed outside the above-mentioned surrounding dummy gate 170; the second sidewall 140b is located on both sides of the surrounding dummy gate 170 and is symmetrically distributed, and the height of the second sidewall 140b in the first direction is lower than the height of the first hard mask layer 180a to facilitate exposure of the first hard mask layer 180a.

[0147] S104, as shown in Figure 12A , 12B , etch the fin structure 120a along the extending direction of the second sidewall 140b to the surface of the substrate 110 to form a source region 190a and a drain region 190b. The source region 190a and the drain region 190b are located on both sides of the fin structure 120a. Use the surrounding dummy gate 170 and the second sidewall 140b as a hard mask to etch the fin structure 120a to reserve positions for the source and the drain.

[0148] S105a, as shown in Figure 13A , 13B , selectively etch the first sacrificial layer 131, the first semiconductor layer 121 before etching, and the third semiconductor layer 123 before etching in the fin structure 120a to form the etched first sacrificial layer 131', the etched first semiconductor layer 121', and the etched third semiconductor layer 123'; combined with Figure 13A , it can be seen that the orthographic projection of the etched first semiconductor layer 121' on the second semiconductor layer 122 overlaps with the second semiconductor layer 122 at least partially, and the orthographic projection of the etched third semiconductor layer 123' on the second semiconductor layer 122 overlaps with the second semiconductor layer 122 at least partially. When it is partial overlap, that is, in the direction parallel to the plane where the substrate is located (the second direction), the end of the etched first semiconductor layer 121' retracts inward relative to the end of the second semiconductor layer 122; similarly, in the direction parallel to the plane where the substrate is located, the end of the etched third semiconductor layer 123' retracts inward relative to the end of the second semiconductor layer 122. This design method is beneficial to introduce the required biaxial tensile stress.

[0149] In this embodiment, in the direction perpendicular to the plane where the substrate is located, the ends of the etched first semiconductor layer 121' and the etched third semiconductor layer 123' are basically flush, that is, the lengths are equal. This design method is beneficial to ensure the consistency of the stress on both sides of the first semiconductor layer.

[0150] In this embodiment, the length of the etched first semiconductor layer 121' and / or the etched third semiconductor layer 123' extending along the second direction is L1; the length of the second semiconductor layer 122 extending along the second direction is L2; it satisfies that L1 / L2 is greater than or equal to 0.5 and less than 1; the second direction is perpendicular to the first direction, and the first direction is parallel to the plane where the substrate 110 is located. In this embodiment, L1 / L2 = 0.85 is selected. In addition, 0.5 ≤ L1 / L2 ≤ 0.85 can also be selected.

[0151] The first semiconductor layer 121' after the above-mentioned selective partial etching, the third semiconductor layer 123' after the selective partial etching, and the second semiconductor layer 122 form a nanosheet stack portion 120c; the shape of the orthographic projection of the above-mentioned nanosheet stack portion 120c on the first plane is any one of a rectangle, a cross, a T shape, a triangle, a trapezoid, a sigma shape, and a fan shape; the first plane is perpendicular to the second plane, and the second plane is the plane where the substrate 110 is located. As Figure 13A , 13B shown, the shape of the orthographic projection of the above-mentioned nanosheet stack portion 120c on the first plane is a rectangle. Among them, this design method introduces a stacked structure into the channel, and this stacked structure can provide biaxial tensile stress, thereby being used to improve the carrier mobility.

[0152] The above-mentioned selective etching refers to etching according to the selectivity ratio selected according to the actual semiconductor process. For example, the selectivity ratio can be 1:10, other values higher than 1:10, such as 1:20, 1:100, 1:200, 1:500, or any one of 1:1000 or any one that satisfies the range values of any two of the above. The selectivity ratio here includes any conventional meaning in the art: for example, under the same etching conditions, the relative etching rate of one material to another material. Specifically, the selectivity ratio is defined as the ratio of the etching rate of the material to be etched to the etching rate of another material layer such as the masking layer material. The formula is as follows: Selectivity ratio = etching rate of the material to be etched / etching rate of other material layers such as masking layer material. The design method of selective etching selected in this application is beneficial to forming semiconductor layers of the required sizes.

[0153] As Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29Schematically shows another schematic diagram of the nanosheet stack portion 120c. The shape of the orthographic projection of the above-mentioned nanosheet stack portion 120c on the first plane is a cross. On the one hand, this design method introduces a stacked structure in the channel, and this stacked structure can provide biaxial tensile stress, thereby being used to improve the carrier mobility. On the other hand, the cross-sectional shape can also reduce the short-channel effect and further improve the carrier mobility. Here, the short-channel effect refers to a series of effects that occur in a metal-oxide-semiconductor field-effect transistor (MOSFET) when the channel length is reduced to be equal to or shorter than the depletion region width of the source and drain junctions. These effects include changes in the scattering mechanisms of carriers in the channel. For example, at high electric fields, Coulomb scattering, phonon scattering, and surface roughness scattering of carriers will increase. These scattering mechanisms will reduce the effective mobility of carriers. For example, in a silicon-on-insulator (SOI) device with an ultra-thin insulator, due to the reduction of the channel thickness, the interface scattering of carriers is more significant, resulting in a reduction in mobility. The design method provided in this application further improves the carrier mobility by reducing the short-channel effect. For example, by designing with the method of controlling variables, if the stacked structure of this application is not adopted, the hole carrier mobility of the semiconductor device is about 60-100 cm 2 V -1 s -1 or so. By adopting the design method provided in this application, the hole carrier mobility can reach 150-250 cm 2 V -1 s -1 . Therefore, the design method provided in this application is beneficial to improving the carrier mobility.

[0154] S105b. As Figure 14A 、 14B schematically shows, a third sidewall 140c is formed outside the fin structure 120b after selective partial etching. Specifically, a sidewall material layer is deposited on both sides of the etched first sacrificial layer 131', the etched first semiconductor layer 121', and the etched third semiconductor layer 123', and then the third sidewall 140c is formed by anisotropic etching. Here, the anisotropic etching includes any conventional meaning in the art. In this application, it means that the etching rate is different in different directions, and the etching rate in the vertical direction is much greater than that in the horizontal direction, for fabricating the third sidewall 140c with a vertical sidewall and a nanoscale size.

[0155] Combined with Figure 14A it can be seen that the third sidewall 140c is located on both sides of the fin structure 120b after selective partial etching; and the third sidewall 140c extends out of the first hard mask layer 180a. The material of the third sidewall 140c includes any one or more of silicon nitride or silicon oxide.

[0156] As Figure 15A 、15B As shown, the third sidewall 140c is etched to expose the bottom substrate 110 and the top first hard mask layer 180a. At the same time, the etched third sidewall 140c’ is formed from the third sidewall 140c.

[0157] S105c. For example, Figure 16A , 16B As shown, a source electrode 190a’ is formed in the above-mentioned source region 190a, and a drain electrode 190b’ is formed in the above-mentioned drain region 190b. For example, Figure 17A , 17B As shown, the above-mentioned source electrode 190a’ and drain electrode 190b’ can be doped to complete activation. Among them, the formation methods of the source electrode 190a’ and the drain electrode 190b’ include metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth (SEG), similar methods or combinations of the foregoing. For P-type stacked nanosheet devices, the source / drain material is boron (B)-doped SiGe (SiGe:B), and for N-type stacked nanosheet devices, the source / drain material is phosphorus (P)-doped silicon (Si) (Si:P). The height of the source / drain is lower than the height of the third sidewall 140c.

[0158] S105d. For example, Figure 18A , 18B As shown, a first interlayer dielectric layer 200a is formed on the side surface of the above-mentioned source electrode 190a’ and drain electrode 190b’ facing away from the above-mentioned substrate 110. The first interlayer dielectric layer 200a is planarized, and the first hard mask layer 180a is removed, so that the processed first interlayer dielectric layer 200a is flush with the above-mentioned surround gate 170.

[0159] S106. For example, Figure 19A , 19B As shown, the above-mentioned surround gate 170 is removed to form a second vacancy 170’.

[0160] S107. For example, Figure 20A , 20B As shown, the above-mentioned first sacrificial layer 131 is removed to form a first vacancy 131a. Among them, the first vacancy 131a and the second vacancy 170’ are used to form a gate stack 300 subsequently. The remaining first semiconductor layer, second semiconductor layer and third semiconductor layer constitute a nanosheet stack portion 120c. The removal method here includes any conventional etching process in the art.

[0161] S108a. For example, Figure 21A , 21BIt is shown that a gate metal layer 250 is formed in the first vacant position 131a and the second vacant position 170'; the gate metal layer 250 is disposed around the nanosheet stack portion 120c;

[0162] Specifically, as shown in Figure 21C it can be seen that a gate stack 300 is simultaneously formed in the first vacant position 131a and the second vacant position 170'. The gate stack 300 includes an interface layer 210, a high-k dielectric layer 220, a barrier layer 230, a work function layer 240, and a gate metal layer 250. The gate metal layer 250 is disposed around the nanosheet stack portion 120c. The material of the interface layer 210 includes silicon oxide, and the silicon oxide interface layer can be passivated to improve the interface. The material of the high-k dielectric layer 220 can be selected from one or a combination of HfO 2 , HfSiO x , HfON, HfSiON, HfAlO x , HfLaO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 or La 2 O 3 . The work function layer 240 can be a P-type work function layer (P WFL) or an N-type work function layer (N WFL).

[0163] S108b, as shown in Figure 22A , 22B it is shown that the gate metal layer 250 is planarized to expose the first interlayer dielectric layer 200a.

[0164] S109, as shown in Figure 23A , 23B it is shown that a second interlayer dielectric layer 200b is formed on the surface of the gate metal layer 250 facing away from the substrate 110. The second interlayer dielectric layer 200b and the first interlayer dielectric layer 200a constitute the top interlayer dielectric layer 200.

[0165] S110, as shown in Figure 24A , 24B it is shown that contact holes are formed in the top interlayer dielectric layer 200, and the contact electrodes 270 are led out through the contact holes. A contact layer 260 is further provided between the contact holes and the contact electrodes 270. The material of the contact layer 260 includes metal silicide.

[0166] In the above preparation process of the present application, one preparation process of the gate-all-around field-effect transistor will be described in detail with reference to the accompanying drawings. In addition, the present application also includes other methods, and the present application will not elaborate on this preparation process.

[0167] In summary, the gate-all-around field-effect transistor designed in the present application alleviates the short-channel effect of the device and improves the carrier mobility by introducing the required stress into the channel.

[0168] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprising", "including", "containing", and "having" are inclusive and therefore specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is explicitly stated. It should also be understood that alternative or additional steps may be used. As described above, only the preferred specific embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate-all-around field effect transistor, characterized in that: include: substrate; Nanosheet stacking part: arranged on one surface of the substrate; The nanosheet stack portion includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked in sequence; Gate stack: arranged around the nanosheet stack portion; Source and drain: located outside the nanosheet stack.

2. The gate-all-around field effect transistor according to claim 1, characterized in that: In a direction parallel to the plane where the substrate is located, an end portion of the first semiconductor layer is retracted inward relative to an end portion of the second semiconductor layer; and / or; In a direction parallel to the plane where the substrate is located, an end portion of the third semiconductor layer is retracted inward relative to an end portion of the second semiconductor layer.

3. The gate-all-around field effect transistor according to claim 2, characterized in that: In a direction parallel to the plane where the substrate is located, an end of the first semiconductor layer is arranged flush with an end of the third semiconductor layer.

4. The gate-all-around field effect transistor according to any one of claims 1 to 3, characterized in that: The transistor further includes a sidewall spacer. The sidewall is arranged between the gate stack and the source and drain; The sidewalls extend along the stacking direction of the semiconductor layers and separate the first semiconductor layer and the third semiconductor layer from the source and the drain.

5. The gate-all-around field effect transistor according to any one of claims 1 to 3, characterized in that: The material of the first semiconductor layer is the same as that of the third semiconductor layer; and / or; The material of the second semiconductor layer is different from the material of the first semiconductor layer and the material of the third semiconductor layer.

6. The gate-all-around field effect transistor according to claim 5, characterized in that: The material of the first semiconductor layer and the material of the third semiconductor layer include silicon germanium compound; and / or; The material of the second semiconductor layer includes any one or more of silicon, germanium, or silicon-germanium compound.

7. The transistor according to any one of claims 1 to 3, characterized in that: The orthographic projection shape of the nanosheet stack on the first plane is any one of a rectangle, a cross, a T-shape, a triangle, a trapezoid, a sigma shape and a fan shape; The first plane is perpendicular to the second plane, and the second plane is the plane where the substrate is located.

8. A dynamic random access memory, characterized in that: A transistor comprising the transistor according to any one of claims 1 to 7.

9. A method for preparing a gate-all-around field effect transistor, characterized in that: providing a substrate; At least one stacked structure is formed on a surface of one side of the substrate, wherein the stacked structure includes a first sacrificial layer, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are stacked in sequence; Etching the at least one stacked structure to form a fin structure; etching the first sacrificial layer, the first semiconductor layer and the third semiconductor layer to be recessed relative to the second semiconductor layer to form a nanosheet stack portion; Forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer; forming a source region and a drain region on both sides of the second semiconductor layer; Etching the first sacrificial layer to form a vacancy; A gate stack is formed in the vacancy.

10. The preparation method according to claim 9, characterized in that: The step of etching the at least one stacked structure to form a fin structure comprises: A first sidewall spacer is formed on the stacked structure by a sidewall transfer process, and the stacked structure is etched to the surface of the substrate using the first sidewall spacer as a mask to form a fin structure.

11. The preparation method according to any one of claims 9 to 10, characterized in that: The step of etching the first sacrificial layer, the first semiconductor layer and the third semiconductor layer recessed relative to the second semiconductor layer to form a nanosheet stack portion comprises: The first sacrificial layer, the first semiconductor layer and the third semiconductor layer are selectively partially etched along the stacking direction of each conductor layer.

12. The preparation method according to any one of claims 9 to 10, characterized in that: The step of forming sidewalls on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer comprises: Forming a spacer material layer on both sides of the first sacrificial layer, the first semiconductor layer and the third semiconductor layer, and forming a third spacer by anisotropic etching; The third sidewall spacer is selectively partially etched along the extension direction of the third sidewall spacer to the surface of the substrate to expose the bottom substrate.

13. The preparation method according to any one of claims 9 to 10, characterized in that: The step of forming a gate stack in the vacancy includes: An interface layer, a high dielectric constant material layer, a barrier layer, a work function layer and a gate metal layer are sequentially formed in the vacancy.

14. The preparation method according to any one of claims 9 to 10, characterized in that: The material of the first sacrificial layer includes a first silicon-germanium compound; the material of the first semiconductor layer includes a second silicon-germanium compound; The mass percentage of the germanium element in the first silicon-germanium compound is greater than the mass percentage of the germanium element in the second silicon-germanium compound; and / or; The material of the third semiconductor layer is the same as that of the first semiconductor layer; and / or; The material of the second semiconductor layer includes any one or more of silicon, germanium, or silicon-germanium compound.

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