Semiconductor device and preparation method thereof
By forming an epitaxial substrate on the substrate surface of the semiconductor device and setting up a gate structure, the problem of insufficient current in the prior art due to small electronic channel area is solved, a larger electronic channel area and higher current are achieved, and device performance is improved.
Patent Information
- Application Number
- CN202311700095.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-08
- Publication Date
- 2025-06-10
AI Technical Summary
In existing semiconductor devices, the circulation area of the electronic channel is small, resulting in insufficient current and affecting device performance.
By forming an epitaxial substrate on the substrate surface and setting a gate structure at the epitaxial substrate surface and side wall positions, an electronic channel with an approximately "several" shape is formed.
The circulation area of the electronic channel is increased to provide more electrons for circulation, thereby increasing the current and improving the performance of semiconductor devices.
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Figure CN120129291A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] A semiconductor device generally includes a substrate, a gate disposed on the surface of the substrate, and a gate insulating layer located between the gate and the substrate. Among them, the gate is a key part for controlling the MOS transistor, and the current characteristics are adjusted by changing the gate voltage.
[0003] In the related art, a metal oxide (usually silicon dioxide) is usually covered on the surface of a substrate (such as an N-type or P-type semiconductor silicon wafer) as the gate insulating layer, and then a metal or polysilicon is fabricated thereon as the gate. The gate insulating layer between the substrate and the gate is arranged parallel to the surface of the substrate. Therefore, the electron channel in the substrate flows along the vicinity of the gate insulating layer. Summary of the Invention
[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same. Compared with the related art, in the structure of the semiconductor device, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0005] To achieve the above purpose, in the first aspect of the present disclosure, a semiconductor device is provided, including:
[0006] A substrate; an epitaxial substrate is formed on the surface of the substrate; and
[0007] A gate structure, disposed on the surfaces of the epitaxial substrate and the substrate, wherein the gate structure is located on the surface and sidewalls of the epitaxial substrate.
[0008] Optionally, the gate structure includes a gate and a first gate insulating layer;
[0009] The first gate insulating layer is located between the gate and the substrate, and between the gate and the epitaxial substrate.
[0010] Optionally, a second gate insulating layer is formed on the sidewalls of the gate.
[0011] Optionally, the gate is a polysilicon gate; and / or
[0012] The semiconductor device further includes a trench isolation structure formed in the substrate.
[0013] In the second aspect of the present disclosure, a method for manufacturing a semiconductor device is further provided, including:
[0014] Providing a substrate, and forming an epitaxial substrate on the surface of the substrate;
[0015] Form a gate structure on the surface of the epitaxial substrate; wherein, the gate structure is located on the surface and sidewalls of the epitaxial substrate.
[0016] Optionally, forming the gate structure on the surface of the epitaxial substrate includes:
[0017] Form a first gate insulating layer on the surface of the substrate, as well as on the surface and sidewalls of the epitaxial substrate;
[0018] Cover a gate layer on the surface of the first gate insulating layer;
[0019] Etch the gate layer to form a gate.
[0020] Optionally, forming the gate on the surface of the epitaxial substrate further includes:
[0021] Form a second gate insulating layer on the sidewalls of the gate.
[0022] Optionally, etching the gate layer to form a gate includes:
[0023] Form a first photoresist layer on the surface of the gate layer and pattern the first photoresist layer;
[0024] Use the patterned first photoresist layer to etch the gate layer to form a gate.
[0025] Optionally, the gate is a polysilicon gate.
[0026] Optionally, providing the substrate and forming an epitaxial substrate on the surface of the substrate includes:
[0027] Form an epitaxial substrate layer on the surface of the substrate;
[0028] Form a second photoresist layer on the surface of the epitaxial substrate layer and pattern the second photoresist layer;
[0029] Use the patterned second photoresist layer to etch the epitaxial substrate layer to form an epitaxial substrate.
[0030] Through the above technical solution, that is, the semiconductor device of the present disclosure includes a substrate, an epitaxial substrate located on the surface of the substrate, and a gate structure. Among them, because the gate structure is on the surface and sidewalls of the epitaxial substrate, therefore, electrons can not only flow along the surface of the substrate close to the gate structure, but also flow inside the epitaxial substrate along the sidewalls and surface of the epitaxial substrate close to the gate structure, forming an approximately "ji"-shaped electron channel. Compared with the related art, in the structure of the semiconductor device of the present disclosure, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0031] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0033] Figure 1 is a schematic structural diagram of a semiconductor device in the related art.
[0034] Figure 2 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure.
[0035] Figures 3 to 9 is a schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor device provided by some embodiments of the present disclosure.
[0036] Figure 10 is a flowchart of a method for manufacturing a semiconductor device provided by some embodiments of the present disclosure.
[0037] Figure 11 is a flowchart of forming an epitaxial substrate of a method for manufacturing a semiconductor device provided by some embodiments of the present disclosure.
[0038] Figure 12 is a flowchart of forming a gate structure of a method for manufacturing a semiconductor device provided by some embodiments of the present disclosure.
[0039] DESCRIPTION OF REFERENCE NUMERALS
[0040] 100 - Substrate; 110 - Epitaxial substrate; 110a - Epitaxial substrate layer; 200 - Gate; 200a - Gate layer; 210 - First gate insulating layer; 220 - Second gate insulating layer; 310 - First photoresist layer; 320 - Second photoresist layer. DETAILED DESCRIPTION
[0041] The following detailed description of the present disclosure will be made with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the present disclosure, and are not intended to limit the present disclosure.
[0042] In the present disclosure, unless otherwise specified, the directional terms such as "upper, lower, left, right" generally refer to the upper, lower, left, and right of the corresponding drawings; "inner, outer" refer to the inner and outer of the contour of the component or structure itself. "First, second" etc. are used to distinguish one element from another, and do not have sequence and importance. In addition, in the description with reference to the drawings, the same reference numerals in different drawings represent the same elements.
[0043] As Figure 1 shown, in the related art, generally a metal oxide (usually silicon dioxide) is covered on the surface of a substrate 100 (such as an N-type or P-type semiconductor silicon wafer) as a first gate insulating layer 210, then a metal or polysilicon is fabricated thereon as a gate 200, and a second gate insulating layer 220 is formed on the sidewalls of the gate 200. And the first gate insulating layer 210 between the substrate 100 and the gate 200 is arranged parallel to the surface of the substrate 100. Therefore, the electron channel in the substrate 100 flows along the direction close to the first gate insulating layer 210. For example, as Figure 1 shown, the electron channel is a straight channel flowing from left to right.
[0044] The object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof. Compared with the related art, in the structure of the semiconductor device, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0045] To achieve the above object, as Figure 2 shown, an embodiment of the present disclosure provides a semiconductor device, which includes: a substrate 100, wherein a shallow trench isolation structure, a doped region or other well-known semiconductor structures may also be formed in the substrate 100, and the present application does not limit this. In addition, the related structures not marked in the figure may be well-known semiconductor structures (such as the related structures required for forming a shallow trench isolation structure), and the present application does not limit this. An epitaxial substrate 110 is formed on the surface of the substrate 100; and a gate structure is disposed on the surfaces of the epitaxial substrate 110 and the substrate 100, wherein the gate structure is located on the surface and sidewalls of the epitaxial substrate 110.
[0046] Through the above technical solution, that is, the semiconductor device of the present disclosure includes a substrate 100, an epitaxial substrate 110 on the surface of the substrate 100 and a gate structure. Among them, because the gate structure is located on the surface and sidewalls of the epitaxial structure, therefore, the electrons in the substrate 100 can not only flow along the surface of the substrate 100 close to the gate structure, but also flow inside the epitaxial substrate 110 along the sidewalls and surface of the epitaxial substrate 110 close to the gate structure, forming an approximately "ji" - shaped electron channel. Compared with the related art, in the structure of the semiconductor device of the present disclosure, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0047] The semiconductor device provided by the embodiments of the present disclosure is equivalent to adding an epitaxial substrate 110 on the basis of the original substrate 100, increasing the contact length between the substrate 100 and the gate 200, thereby increasing the extension length of the electron channel, realizing an increase in the electron channel area to accommodate more electron flow paths, and thus achieving the purpose of increasing the current.
[0048] In this embodiment, the substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but is not limited thereto.
[0049] It should be noted that the epitaxial substrate 110 may be a new crystal grown on the surface of the substrate 100 through related technologies including the epitaxial process, and its material may be the same as that of the substrate 100. The specific forming method may refer to the manufacturing method of the semiconductor device described below.
[0050] The gate structure can be constructed using any suitable structure, such as Figure 2 and Figure 9 As shown, in some embodiments, the gate structure includes a gate 200 (such as a polysilicon gate) and a first gate insulating layer 210; the first gate insulating layer 210 is located between the gate 200 and the substrate 100, and between the gate 200 and the epitaxial substrate 110. Among them, the gate 200 includes but is not limited to a polysilicon gate. The first gate insulating layer 210 is used to isolate the gate 200 from the epitaxial substrate 110 and the substrate 100, so that electrons can flow in the substrate 100 and the epitaxial substrate 110 along the extension direction of the polysilicon gate 200 to form a "Ji" - shaped or approximately "Ji" - shaped electron channel, so as to increase the extension length of the electron channel, thereby increasing the area of the electron channel and increasing the current.
[0051] It should be noted that the gate structure may also be a metal gate 200, for example, made of tungsten or aluminum.
[0052] In another embodiment, a second gate insulating layer 220 is formed on the sidewall of the gate 200. Among them, by forming the second gate insulating layer 220 on the sidewall of the gate 200, it can play a role in protecting the polysilicon gate 200. In addition, it is also convenient to form an isolation structure on the outer sidewall of the second gate insulating layer 220 to reduce parasitic capacitance.
[0053] It should be noted that the first gate insulating layer 210 and the second gate insulating layer 220 include but are not limited to silicon dioxide, hafnium oxide, etc.
[0054] In some other embodiments, the semiconductor device further includes a trench isolation structure formed on the substrate 100. Among them, the trench isolation structure can be formed using any suitable structure and method known in the related technologies, which will not be elaborated here. As Figure 2As shown, there are two trench isolation structures arranged at intervals, and a P-well is formed in the substrate 100 between the two trench isolation structures. The epitaxial substrate 110 and the gate structure are located on the upper surface of the P-well between the two trench isolation structures.
[0055] It can be understood that the above semiconductor device further includes a source region and a drain region formed on the substrate 100. For the specific structure, reference can be made to related known technologies and will not be elaborated here.
[0056] Reference Figure 10 As shown, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor device, which includes step S100 and step S200.
[0057] In step S100, a substrate 100 is provided, and an epitaxial substrate 110 is formed on the surface of the substrate 100.
[0058] In step S200, a gate structure is formed on the surface of the epitaxial substrate 110; wherein, the gate structure is located on the surface and sidewalls of the epitaxial substrate 110.
[0059] As shown, through the above method, first a substrate 100 is provided, and an epitaxial substrate 110 is formed on the surface of the substrate 100. Then, a gate structure is formed on the surface of the epitaxial substrate 110. Among them, the gate structure is located above a part of the substrate 100 and simultaneously covers the upper surface and the sidewall surface of the epitaxial substrate 110, thereby forming a "ji"-shaped electron channel on the substrate 100, increasing the area of the electron channel, and improving the current intensity.
[0060] Among them, the substrate 100 can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto.
[0061] Reference Figure 11 As shown, in some embodiments, step S100 of providing the substrate 100 and forming the epitaxial substrate 110 on the surface of the substrate 100 includes steps S110 to S130.
[0062] In step S110, an epitaxial substrate 110 layer is formed on the surface of the substrate 100.
[0063] In step S120, a second photoresist layer 320 is formed on the surface of the epitaxial substrate 110 layer, and the second photoresist layer 320 is patterned.
[0064] In step S130, the epitaxial substrate 110 layer is etched using the patterned second photoresist layer 320 to form the epitaxial substrate 110.
[0065] The epitaxial substrate 110 can be formed on the basis of the original substrate 100 by using an epitaxial process. The forming process may include: First, an epitaxial substrate 110 layer is formed on the upper surface of the substrate 100, where the epitaxial substrate 110 layer includes but is not limited to polysilicon; Second, a second photoresist layer 320 is formed above the epitaxial substrate 110 layer, and then the second photoresist layer 320 is patterned, that is, the position of the epitaxial substrate 110 to be formed is defined; Finally, the epitaxial substrate 110 layer is etched by using the patterned second photoresist layer 320 to form the above-mentioned epitaxial substrate 110.
[0066] It should be noted that any suitable process known in the related art can be used to form the epitaxial substrate 110 layer on the upper surface of the substrate 100. For example, chemical vapor deposition or molecular beam epitaxy technology can be used, which will not be elaborated here.
[0067] Reference Figure 12 As shown, in some embodiments, the step S200 of forming a gate structure on the surface of the epitaxial substrate 110 includes step S210 to step S230.
[0068] In step S210, a first gate insulating layer 210 is formed on the surface of the substrate 100, as well as on the surface and sidewalls of the epitaxial substrate 110.
[0069] In step S220, a gate layer 200a is covered on the surface of the first gate insulating layer 210.
[0070] In step S230, the gate layer 200a is etched to form a gate 200.
[0071] After step S100, a first gate insulating layer 210 and a gate layer 200a are deposited on the surfaces of the substrate 100 and the epitaxial substrate 110, and then a gate structure is formed by etching, so that the gate structure covers a part of the substrate 100 and the entire epitaxial substrate 110, thereby forming a "Ji"-shaped electron channel.
[0072] It should be noted that the gate layer 200a in the embodiments of the present disclosure can be made of polysilicon material, and the gate 200 can be a polysilicon gate 200.
[0073] In some embodiments, the step S200 of forming a gate structure on the surface of the epitaxial substrate 110 further includes:
[0074] A second gate insulating layer 220 is formed on the sidewalls of the gate 200.
[0075] Among them, any suitable process can be used to form the second gate insulating layer 220 on the sidewalls of the gate 200. For example, it can be realized by a re-oxidation technique. It should be noted that the first gate insulating layer 210 and the second gate insulating layer 220 include but are not limited to silicon dioxide or hafnium oxide, etc.
[0076] Further, the step of etching the gate layer 200a to form the gate 200 includes:
[0077] Form a first photoresist layer 310 on the surface of the gate layer 200a and pattern the first photoresist layer 310.
[0078] Etch the gate 200 using the patterned first photoresist layer 310.
[0079] As Figure 7 shown, after depositing the gate layer 200a (such as a polysilicon layer), cover the first photoresist layer 310 on the surface of the gate layer 200a and pattern the first photoresist layer 310. Then, etch the gate layer 200a using the patterned first photoresist layer 310 to obtain the gate 200.
[0080] It can be understood that the first photoresist layer 310 and the second photoresist layer 320 can adopt the structures known in the related art, which are prior art and will not be elaborated here.
[0081] It should be noted that after etching the gate layer 200a, a second gate insulating layer 220 can be formed on the sidewalls of the etched gate 200 by any suitable method, and the first gate insulating layer 210 on the surface of the substrate 100 can be removed.
[0082] Through the above technical solution, that is, the semiconductor device of the present disclosure includes a substrate 100, an epitaxial substrate 110 located on the surface of the substrate 100, and a gate structure. Among them, since the gate structure is located on the surface and sidewalls of the epitaxial structure, therefore, the electrons in the substrate 100 can not only flow along the surface of the substrate 100 close to the gate structure, but also flow inside the epitaxial substrate 110 along the sidewalls and surface of the epitaxial substrate 110 close to the gate structure, forming an approximately "ji"-shaped electron channel. Compared with the related art, in the structure of the semiconductor device of the present disclosure, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0083] Next, a specific embodiment will be used to describe in detail the manufacturing method of the semiconductor device.
[0084] As Figure 3 shown, provide a substrate 100.
[0085] As Figure 4 shown, deposit an epitaxial substrate 110 layer on the substrate 100 and form a patterned second photoresist layer 320 above the epitaxial substrate 110 layer.
[0086] As Figure 5 shown, form the epitaxial substrate 110 on the substrate 100 by etching.
[0087] As shown Figure 6 in FIG. 1, a first gate insulating layer 210 is deposited over a substrate 100 and an epitaxial substrate 110.
[0088] As shown Figure 7 in FIG. 2, a gate layer 200a (polysilicon) is deposited over the first gate insulating layer 210, and a first photoresist layer 310 is formed over the gate layer 200a, and the first photoresist layer 310 is patterned.
[0089] As shown Figure 8 in FIG. 3, the gate layer 200a is etched using the patterned first photoresist layer 310 to form a gate 200.
[0090] As shown Figure 9 in FIG. 4, a second gate insulating layer 220 is formed on sidewalls of the gate 200 using a re-oxidation technique.
[0091] The semiconductor device of the embodiment of the present disclosure is obtained through the above steps. As shown Figure 2 in FIG. 5, an approximately "ji" - shaped electron channel is formed on the semiconductor device. Compared with the related art, in the structure of the semiconductor device of the present disclosure, the flow area of the electron channel is larger, which can allow more electrons to flow, increasing the current and improving the performance of the semiconductor device.
[0092] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0093] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, they can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination manners.
[0094] Furthermore, any combination can be made between various different embodiments of the present disclosure as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A semiconductor device, characterized in that, comprising: a substrate; an epitaxial substrate is formed on the surface of the substrate; and a gate structure disposed on the surfaces of the epitaxial substrate and the substrate, wherein the gate structure is located on the surface and sidewalls of the epitaxial substrate.
2. The semiconductor device according to claim 1, characterized in that, the gate structure includes a gate and a first gate insulating layer; the first gate insulating layer is located between the gate and the substrate, and between the gate and the epitaxial substrate.
3. The semiconductor device according to claim 2, characterized in that, a second gate insulating layer is formed on the sidewalls of the gate.
4. The semiconductor device according to any one of claims 1-3, characterized in that, the gate is a polysilicon gate; and / or the semiconductor device further includes a trench isolation structure formed in the substrate.
5. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a substrate, and forming an epitaxial substrate on the surface of the substrate; forming a gate structure on the surface of the epitaxial substrate; wherein the gate structure is located on the surface and sidewalls of the epitaxial substrate.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, the forming a gate structure on the surface of the epitaxial substrate includes: forming a first gate insulating layer on the surface of the substrate, and on the surface and sidewalls of the epitaxial substrate; covering a gate layer on the surface of the first gate insulating layer; etching the gate layer to form a gate.
7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, the forming a gate on the surface of the epitaxial substrate further includes: forming a second gate insulating layer on the sidewalls of the gate.
8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, the etching the gate layer to form a gate includes: forming a first photoresist layer on the surface of the gate layer, and patterning the first photoresist layer; etching the gate layer using the patterned first photoresist layer to form a gate.
9. The method for manufacturing a semiconductor device according to any one of claims 6-8, characterized in that, the gate is a polysilicon gate.
10. The method for manufacturing a semiconductor device according to claim 5, characterized in that, the providing a substrate, and forming an epitaxial substrate on the surface of the substrate includes: forming an epitaxial substrate layer on the surface of the substrate; forming a second photoresist layer on the surface of the epitaxial substrate layer, and patterning the second photoresist layer; etching the epitaxial substrate layer using the patterned second photoresist layer to form an epitaxial substrate.