Method of forming semiconductor device structure

Abstract

A method of forming a semiconductor device structure is disclosed. The method includes preparing a semiconductor substrate having an original surface; forming a group of active regions on the basis of the semiconductor substrate and forming a shallow trench isolation region between two adjacent active regions; asymmetric spacer layers are formed in the shallow trench isolation region between the two adjacent active regions, a first spacer layer in the asymmetric spacer layers is an oxide layer, the first spacer layer covers the side wall of a first active region in the two adjacent active regions, and a second spacer layer in the asymmetric spacer layers is arranged in the narrow trench; and a first interconnection layer formed between the asymmetric spacing layers, wherein the first interconnection layer is in the shallow trench isolation region and below the original surface. Because the interconnection structure / wire which is well isolated is introduced below the silicon surface, the size of the transistor can be effectively reduced, and the performance of the transistor can be effectively improved.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device structure, and more particularly to a method for embedding an under-silicon surface interconnect structure / wire in a silicon substrate and the under-silicon surface interconnect structure / wire being capable of connecting to a transistor at the bottom of the transistor within the silicon substrate. Background Art

[0002] In the most advanced existing integrated circuits, the integrated circuit connects multiple transistors through conductive interconnect structures (e.g., metal wires, polysilicon wires, etc.) to assist in signal transmission between the gates, sources, and drains of the multiple transistors. The metal wires are connected to the gates, sources, and drains of the multiple transistors respectively by many contact holes and connection plugs. This poses great challenges and difficulties to the chip design goals of reducing area, power consumption, and noise and improving the performance of the integrated circuit, especially when the size of the integrated circuit must be significantly reduced on the chip to meet Moore's Law.

[0003] Next, taking the challenges and difficulties caused by area increase as an example, compared with the size of the contact holes used to connect the metal wires to the source or drain, the source or drain in the multiple transistors must be designed with a larger diffusion area so that the inevitable lithography misalignment limited by the lithography tool will not cause the contact holes to be formed outside the lower edge of the source or drain. However, the larger diffusion area will inevitably increase the diffusion area of the multiple transistors and the chip area where the transistors are located. This will result in a larger parasitic capacitance, significantly reducing the alternating current (ac) performance of the circuit containing the transistors, causing the circuit of the transistors to consume higher power and have greater noise.

[0004] Therefore, how to introduce self-aligned contact structures and technologies that use less area to connect a transistor to a first interconnect structure (metal) layer corresponding to the transistor to send and receive signals has become an important topic for further effectively reducing the size of the transistor and improving the performance of the transistor. Summary of the Invention

[0005] The present invention discloses a structural invention of a transistor using new technologies (including new process integration), wherein the technologies achieve the embedding of an underground interconnection structure under the silicon surface in a silicon substrate, and the underground interconnection structure under the silicon surface has both high conductivity and effectively optimized isolation of the silicon substrate. The underground interconnection structure under the silicon surface can be vertically (or bridged) connected to the source or drain of the transistor through a compact self-alignment invention, thereby leading to innovations in many components and circuit designs. For example, the underground interconnection structure under the silicon surface can be vertically connected to many different sources or drains respectively, and the other ends of the underground interconnection structure under the silicon surface can be connected to different signal sources, such as a voltage source or a ground source. Additionally, the chip architecture can further introduce power supply voltages vertically distributed in different layers or different levels in the silicon substrate, wherein necessary isolation must be embedded under the silicon surface to separate the power supply of different layers or different levels, and the chip architecture can correspondingly improve the performance of the transistor and the circuit (such as speed, power, and noise, etc.), and reduce the design complexity on the silicon surface (for example, currently complex chip designs may need to use the tenth layer of the ten-layer interconnection structure on the silicon surface as the power supply, but nine layers of interconnection structures below the tenth layer are required to transmit signals, where the ten-layer interconnection structure stacked up is very complex and will occupy a considerable contact area, etc.). To describe the present invention by way of example: different steps are established between the wires under the silicon surface and the wires above the silicon surface, wherein the wires under the silicon surface can be designed to have different depths to allow the wires under the silicon surface to be distributed in the chip to provide various signals (such as signals of the voltage source or the ground source), without colliding with each other in the silicon substrate in a relatively large or excessive size.

[0006] An embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnection structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located under the silicon surface. The interconnection structure extends outside the transistor and is coupled to the first conduction region of the transistor. The interconnection structure is disposed under the silicon surface and is isolated from the silicon substrate through an isolation region.

[0007] In another embodiment of the present invention, the semiconductor device structure further includes another transistor and a signal line, wherein the signal line is electrically connected to the other transistor, and the signal line is distributed under the silicon surface and separated from the interconnection structure.

[0008] In another embodiment of the present invention, a distance between the silicon surface and an upper surface of the interconnect structure is different from a distance between the silicon surface and an upper surface of the signal line.

[0009] In another embodiment of the present invention, the semiconductor device structure further includes another transistor and a power supply line, wherein the power supply line is electrically connected to the another transistor, and the power supply line is distributed below the silicon surface and separated from the interconnect structure.

[0010] In another embodiment of the present invention, the power supply line is coupled to a voltage source or a ground source.

[0011] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnect structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located below the silicon surface. The interconnect structure extends outside the transistor and is coupled to the gate structure of the transistor. The interconnect structure includes an upper portion above the silicon surface, and sidewalls of the upper portion of the interconnect structure are aligned with sidewalls of the gate structure.

[0012] In another embodiment of the present invention, the semiconductor device structure further includes a first spacer layer and a second spacer layer, wherein the first spacer layer covers a first sidewall of the gate structure and is located above the silicon surface; and the second spacer layer covers a second sidewall of the gate structure and is located above the silicon surface.

[0013] In another embodiment of the present invention, the first spacer layer is adjacent to a sidewall of the upper portion of the interconnect structure.

[0014] In another embodiment of the present invention, the semiconductor device structure further includes a dielectric layer, wherein the dielectric layer is disposed below the first spacer layer, the second spacer layer, and the gate structure.

[0015] In another embodiment of the present invention, at least a portion of the gate structure extends downward from the silicon surface, and at least a portion of the channel is located below a bottom of the dielectric layer and extends along the bottom of the dielectric layer.

[0016] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnect structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located under the silicon surface. The interconnect structure extends outside the transistor and is electrically connected to the first conduction region of the transistor through a bridge contact. A first sidewall of the bridge contact aligns with an edge of the first conduction region and a second sidewall of the bridge contact aligns with an edge of the interconnect structure.

[0017] In another embodiment of the present invention, the bridge contact includes an upper portion and a lower portion, wherein the upper portion of the bridge contact abuts the silicon substrate and the lower portion of the bridge contact is separated from the silicon substrate.

[0018] In another embodiment of the present invention, the semiconductor device structure further includes a first isolation layer, wherein the first isolation layer covers at least the first sidewall, the second sidewall, and the bottom of the lower portion of the bridge contact.

[0019] In another embodiment of the present invention, the first isolation layer further covers a third sidewall of the lower portion of the bridge contact, and a second isolation layer further covers a fourth sidewall of the lower portion of the bridge contact, wherein the third sidewall of the lower portion is parallel to the fourth sidewall of the lower portion, and the width of the second isolation layer is different from the width of the first isolation layer.

[0020] In another embodiment of the present invention, the interconnect structure is disposed under the silicon surface, and the lower portion of the bridge contact abuts the interconnect structure.

[0021] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first transistor, and an interconnect structure. The silicon substrate has a silicon surface. The first transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located under the silicon surface. The interconnect structure is electrically connected to the first conduction region of the first transistor through a bridge contact. The interconnect structure is located below the silicon surface and an isolation cap is disposed on the bridge contact to isolate the bridge contact. The bridge contact includes an upper portion and a lower portion, and at least a first sidewall of the lower portion of the bridge contact abuts an isolation layer, and an edge of the isolation cap aligns with an edge of the isolation layer.

[0022] In another embodiment of the present invention, the semiconductor device structure further includes a first spacer layer, wherein the first spacer layer is disposed between the first conduction region and the gate structure of the first transistor, and the isolation cap contacts the first conduction region of the first transistor.

[0023] In another embodiment of the present invention, the semiconductor device structure further includes a second transistor, wherein the second transistor is adjacent to the first transistor. The second transistor includes a gate structure, a first conduction region, and a second conduction region, and the first conduction region of the second transistor contacts the isolation cap and is electrically connected to the interconnect structure through the bridge contact.

[0024] In another embodiment of the present invention, the semiconductor device structure further includes a third transistor, wherein the third transistor is adjacent to the first transistor. The third transistor includes a gate structure, a first conduction region, and a second conduction region, and the second conduction region of the third transistor is separated from the second conduction region of the first transistor.

[0025] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a trench, and a first spacer layer and a second spacer layer. The silicon substrate has a silicon surface. At least a portion of the trench is formed under the silicon surface. The first spacer layer covers a first side of the trench, and the second spacer layer covers a second side of the trench. The material of the first spacer layer is different from the material of the second spacer layer.

[0026] In another embodiment of the present invention, the first side of the trench is symmetric to the second side of the trench.

[0027] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first interconnect structure, and a second interconnect structure. The silicon substrate has a silicon surface. The first interconnect structure is disposed under the silicon surface. The second interconnect structure is disposed under the silicon surface. The depth from the silicon surface to the first interconnect structure is the same as the depth from the silicon surface to the second interconnect structure, and the first interconnect structure and the second interconnect structure are separated from each other.

[0028] In another embodiment of the present invention, the material of the first interconnect structure is the same as the material of the second interconnect structure.

[0029] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first transistor, a bridge contact, and an interconnect structure. The silicon substrate has a silicon surface. The first transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located under the silicon surface. The bridge contact includes an upper portion and a lower portion, wherein the bridge contact is electrically connected to the first conduction region of the first transistor. The interconnect structure is located under the silicon surface and contacts the lower portion of the bridge contact.

[0030] In another embodiment of the present invention, the first transistor is an n-type metal oxide semiconductor transistor and the first conduction region includes an n+ doped region.

[0031] In another embodiment of the present invention, the first transistor is a p-type metal oxide semiconductor transistor and the first conduction region includes a p+ doped region.

[0032] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor, a bridge contact, and an interconnect structure. The silicon substrate has a silicon surface. The n-type metal oxide semiconductor transistor includes a gate structure, a first conduction region, and a first channel located under the silicon surface. The p-type metal oxide semiconductor transistor includes a gate structure, a second conduction region, and a second channel located under the silicon surface. The bridge contact includes an upper portion and a lower portion, wherein the bridge contact is electrically connected to the first conduction region of the n-type metal oxide semiconductor transistor and the second conduction region of the p-type metal oxide semiconductor transistor. The interconnect structure is located under the silicon surface and contacts the lower portion of the bridge contact.

[0033] In another embodiment of the present invention, the first conduction region of the n-type metal oxide semiconductor transistor includes an n+ doped region and the second conduction region of the p-type metal oxide semiconductor transistor includes a p+ doped region.

[0034] In another embodiment of the present invention, the material of the bridge contact is the same as the material of the interconnect structure.

[0035] Another embodiment of the present invention discloses a method of forming a semiconductor device structure. The method includes preparing a semiconductor substrate having an original surface; forming a set of active regions based on the semiconductor substrate and forming a shallow trench isolation (STI) between two adjacent active regions in the set of active regions; forming an asymmetric spacer layer in the shallow trench isolation between the two adjacent active regions, wherein a first spacer layer in the asymmetric spacer layer is an oxide layer, the first spacer layer covers a sidewall of a first active region in the two adjacent active regions, a second spacer layer in the asymmetric spacer layer is disposed in a narrow trench, and the narrow trench exposes a sidewall of a second active region in the two adjacent active regions; and forming a first interconnect layer between the asymmetric spacer layers, wherein the first interconnect layer is in the shallow trench isolation and under the original surface of the semiconductor substrate.

[0036] In an embodiment of the present invention, the material of the first spacer layer is different from the material of the second spacer layer.

[0037] In an embodiment of the present invention, the second spacer layer is composed of silicon oxynitride carbon (SiOCN).

[0038] In an embodiment of the present invention, the method further includes forming a second interconnect layer and forming a gate region of a transistor in the second active region, wherein the gate region of the transistor is connected to the second interconnect layer; and forming an interconnect plug in the second active region to connect the first interconnect layer.

[0039] In an embodiment of the present invention, forming the second interconnect layer and forming the gate region of the transistor in the second active region includes etching the second active region to form a recess therein; depositing a high-k dielectric insulating layer in the recess; and depositing a first conductive material to form the gate region of the transistor and the second interconnect layer.

[0040] In an embodiment of the present invention, forming the interconnect plug includes etching the second active region to form a hole and forming a dielectric layer in the hole; removing the second spacer layer based on the hole to expose a sidewall of the first interconnect layer; and depositing a second conductive material in the hole to connect the sidewall of the first interconnect layer.

[0041] In an embodiment of the present invention, the semiconductor device structure is a dynamic random-access memory (DRAM) cell, the first interconnect layer is a bit line, the transistor is an access transistor of the dynamic random-access memory cell, and the second interconnect layer is a word line.

[0042] In an embodiment of the present invention, forming the asymmetric spacer layer includes forming the oxide layer to cover the sidewalls of the first active region, and forming a temporary oxide layer to cover the second active region; depositing a sacrificial layer over the shallow trench isolation region to cover the oxide layer and the temporary oxide layer; forming the narrow trench by removing a first portion of the sacrificial layer and the temporary oxide layer to expose the sidewall of the second active region; and depositing the second spacer layer in the narrow trench to cover the sidewall of the second active region.

[0043] In an embodiment of the present invention, the narrow trench is completely filled with the second spacer layer.

[0044] In an embodiment of the present invention, forming the narrow trench includes forming a patterned photoresist layer to expose a first portion of the sacrificial layer; and removing the first portion of the sacrificial layer and the temporary oxide layer covered by the first portion of the sacrificial layer to form the narrow trench.

[0045] In an embodiment of the present invention, the width of the narrow trench is 2 to 5 nanometers (nm). Description of the Drawings

[0046] Figure 1A is a flowchart of a method for manufacturing a dynamic random access memory cell array disclosed in an embodiment of the present invention.

[0047] Figure 1B - 1G is an illustration Figure 1A of

[0048] Figure 2 is an illustration of a top view and a cross-sectional view along the X direction showing the deposition of a liner nitride layer and a liner oxide layer and the formation of a shallow trench isolation.

[0049] Figure 3 is an illustration of depositing the first nitride layer to form the first nitride spacer and depositing the STI-first oxide layer and the photoresist layer.

[0050] Figure 4 is an illustration of etching away the upper-edge first nitride spacer and the photoresist layer not covering the STI-first oxide layer.

[0051] Figure 5 is an illustration of stripping the photoresist layer and the STI-first oxide layer and forming the first oxide layer.

[0052] Figure 6 is an illustration of depositing the metal layer in the trench and planarizing it by chemical mechanical polishing.

[0053] Figure 7 is an illustration of depositing the photoresist layer.

[0054] Figure 8 is an illustration of etching the metal layer corresponding to the end of the active region.

[0055] Figure 9 is an illustration of removing the photoresist layer and etching back the metal layer to form the underlying bit line on the silicon surface.

[0056] Figure 10 is an illustration of depositing the second oxide layer in the trench.

[0057] Figure 11 It is a schematic diagram showing the deposition of the third oxide layer, the second nitride layer, and the photoresist layer, and removing unnecessary portions of the third oxide layer, the second nitride layer, and the photoresist layer.

[0058] Figure 12 It is a schematic diagram showing the etching of the pad nitride layer while retaining the pad oxide layer.

[0059] Figure 13 It is a schematic diagram showing the formation of the U-shaped groove and the formation of the high-k dielectric layer as the gate structure of the access transistor.

[0060] Figure 14 It is a schematic diagram showing the deposition of the third nitride layer and the fourth oxide layer, and then polishing the third nitride layer and the fourth oxide layer.

[0061] Figure 15 It is a schematic diagram showing the etching away of the second nitride layer and the third oxide layer.

[0062] Figure 16 It is a schematic diagram showing the deposition and etching of the fourth nitride layer, the fifth oxide layer, and the fifth nitride layer by the anisotropic etching technique, and the deposition of the sixth oxide layer.

[0063] Figure 17 It is a schematic diagram showing the deposition of the spin-on dielectric material to create the hole.

[0064] Figure 18 It is a schematic diagram showing the deposition of the seventh oxide layer within the hole and the deposition of the spin-on dielectric layer on top of the seventh oxide layer.

[0065] Figure 19 It is a schematic diagram showing the removal of the spin-on dielectric layer, the pad oxide layer, and the silicon material to create another hole.

[0066] Figure 20 It is a schematic diagram showing a cross-sectional view along the Y2 direction.

[0067] Figure 21 It is a schematic diagram showing the removal of the lower-edge first nitride spacer on the other inner wall within the other hole.

[0068] Figure 22 It is a schematic diagram showing the deposition and etching of the n+ polysilicon to leave the n+ polysilicon plug within the other hole.

[0069] Figure 23It is a schematic diagram showing the removal of the upper part of the eighth oxide layer to generate the eighth oxide spacer layer within the other hole.

[0070] Figure 24A It is a schematic diagram showing the generation of the neck-shaped surrounding conductive n+ polysilicon and the n+ polysilicon plug.

[0071] Figure 24B It is a schematic diagram showing another way to implement the vertical connection (bridge) and the W-2 plug.

[0072] Figure 25A It is a schematic diagram showing the thermal growth of the ninth oxide layer on the n+ polysilicon plug.

[0073] Figure 25B It is a schematic diagram showing the local thermal growth of the ninth oxide layer on the W-2 plug.

[0074] Figure 26 It is a schematic diagram showing the removal of the sixth oxide layer and the fifth nitride spacer layer, and then the use of n-type dopant implantation to generate the drain and source of the access transistor.

[0075] Figure 27 It is a schematic diagram showing the principle of implementing the sub-surface silicon interconnect structure.

[0076] Figure 28 It is a schematic diagram showing a top view of the dynamic random access memory cell array. Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36 It is a schematic diagram showing another manufacturing process for forming the asymmetric spacer layer and the sub-surface silicon interconnect line disclosed in another embodiment of the present invention.

[0077] Figure 37 It is a schematic diagram showing Figure 36 the three-dimensional perspective view of the temporary structure of

[0078] Among them, the reference numerals are explained as follows:

[0079] 202 p-type substrate

[0080] 204 Pad oxide layer

[0081] 205 Thermal oxide layer

[0082] 206 Pad nitride layer

[0083] 207 Spin-on dielectric material

[0084] 208, HSS-1 / 2, HSS-1 / 3 semiconductor surface

[0085] 209 silicon oxynitride material

[0086] 210 trench

[0087] 214 oxide layer

[0088] 303 titanium nitride layer

[0089] 304 STI - first oxide layer

[0090] 305 tungsten layer

[0091] 306, 702, 1106 photoresist layer

[0092] 307 silicon nitride layer

[0093] 309 high density plasma oxide layer

[0094] 502 first oxide layer

[0095] 504 first oxide / STI layer

[0096] 602 metal layer

[0097] 902, UGBL silicon surface lower bit line

[0098] 1002, CVD - STI - Oxide2 second oxide layer

[0099] 1102 third oxide layer

[0100] 1104 second nitride layer

[0101] 1302 U - shaped channel

[0102] 1304 high - dielectric - constant insulating layer

[0103] 1402 third nitride layer

[0104] 1404 fourth oxide layer

[0105] 1602 fourth nitride layer

[0106] 1604 fifth oxide layer

[0107] 1606 fifth nitride layer

[0108] 1608 sixth oxide layer

[0109] 1702 spin - on dielectric

[0110] 1802 seventh oxide layer

[0111] 1804 Spin-coated dielectric layer

[0112] 1902 Eighth oxide layer

[0113] 2202 n+ polysilicon plug

[0114] 2402 n+ polysilicon layer

[0115] 2502 Ninth oxide layer

[0116] A, B cutting lines

[0117] AQ1, AQ2, AQ3 access transistors

[0118] Drain-1 First drain

[0119] Drain-2 Second drain

[0120] Drain-3 Third drain

[0121] Hole-1 / 2, Hole-1 / 3 Holes

[0122] NLDD n-type lightly doped drain

[0123] 2602, 2604 Capacitors

[0124] Source-1 First source

[0125] Source-2 Second source

[0126] Source-3 Third source

[0127] STI Shallow trench isolation

[0128] Wordline-1 First word line

[0129] Wordline-2 Second word line

[0130] Wordline-3 Third word line

[0131] Steps 10-80, 102-160 Detailed implementation mode

[0132] To illustrate that the present invention is applicable to integrated circuits including logic, digital, analog, memory, etc., the following description takes a memory as an example to easily grasp the core technology of the present invention. Currently, there are many semiconductor memories using different types of memory cells (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), and nonvolatile flash memories including NOR, NAND, three-dimensional (3D) NAND, etc.) that require bit lines and word lines. Additionally, the present invention discloses a new architecture for arranging the bit lines and the word lines, and the core technology related to the new architecture is considered to be well applicable to the above-mentioned memories. Further, in the embodiments following the present invention, the present invention takes a dynamic random access memory as an example to illustrate the core technology of the present invention and the manufacturing method of the dynamic random access memory can be used as an implementation method of the present invention. One of the memory cells most commonly used in the dynamic random access memory currently is the 1T1C cell, where the gate structure of an access transistor (1T) in the 1T1C cell is connected to a word line, the drain of the access transistor (1T) is connected to a bit line, and the source of the access transistor (1T) is connected to a capacitor (1C) in the 1T1C cell.

[0133] To increase the density of the memory on a chip, the 1T1C cell needs to be minimized as much as possible, that is, all geometric dimensions of the 1T1C cell need to be reduced to a smaller dimension and the design of the capacitor must also progress to a three-dimensional (3D) structure to increase the capacitance value of the capacitor (e.g., forming a stacked capacitor on top of the access transistor (1T) or forming a trench capacitor under the silicon surface of the access transistor (1T)). However, as the 1T1C cell is required to be shrunk, the following difficulties faced by semiconductor process technologies will become more difficult to solve:

[0134] (1) Since the geometric scale of the 1T1C cell is reduced, the total area of the 1T1C cell is decreased, resulting in a much smaller surface area in the 1T1C cell that is used to allow the formation of various necessary contacts (such as the contact between the capacitor and the source of the access transistor (1T), and the contact between the bit line and the drain of the access transistor (1T)). (2) Even if the capacitor (1C) is made of the three-dimensional (3D) structure, the capacitance value of the capacitor (1C) will still decrease. For example, if the stacked capacitor formed above the silicon surface of the access transistor (1T) is too high, the silicon surface of the 1T1C cell will be very rough and have a poor surface appearance, and if the trench capacitor is formed below the silicon surface of the access transistor (1T), the trench capacitor needs to be made very deep so that the related etching and refilling processes become difficult. (3) It is very difficult to layout the three structures of the word line, the bit line, and the capacitor in the same plane. In particular, the geometric conduction mechanism requires that the three structures must be perpendicular or nearly perpendicular to each other, and the formation order of each other in the three structures (such as the order of forming the capacitor after the bit line or the order of forming the bit line after the capacitor) will make the layout more difficult. (4) Because of the above (3), the connection area from the capacitor to the source of the access transistor (1T) is very small, so it is very difficult to achieve some self-alignment between different structures that need to be connected. (5) When the geometric scale of the 1T1C cell continues to shrink, since the shrinkage of the geometric shape of the 1T1C cell will not completely depend on processes such as lithographic scaling and alignment, the integration process for manufacturing the 1T1C cell becomes increasingly difficult to achieve a critical layer and a geometrical pattern with self-alignment characteristics.

[0135] Accordingly, the present invention discloses (1) a new structure in which the bit lines are below the horizontal silicon surface (HSS), (2) a new structure for connecting the gate structure of the access transistor (1T) and the word line to a critical vertical connection with self-alignment possibility, (3) a new structure for connecting the vertical bridge material to the drain of the access transistor (1T) to an underground interconnection structure, (4) a new structure for self-aligning the drain of the access transistor (1T) to a channel at a desired distance through a spacer layer surrounding the word line, where the desired distance is determined by the spacer layer surrounding the word line, (5) a new structure for fabricating an insulating cap over the underground interconnection structure by self-alignment to isolate the underground interconnection structure from all other conductive layers, and (6) all novel process methods for implementing the present invention.

[0136] Next, please refer to Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26 , Figure 27 , Figure 28 , where Figure 1A is a flowchart of a method for manufacturing an array of dynamic random access memory storage cells (1T1C cells) disclosed in an embodiment of the present invention, and the detailed steps are as follows:

[0137] Step 10: Start;

[0138] Step 20: Based on the p-type substrate, define the active region of the dynamic random access memory cell array and form shallow trench isolation (STI).

[0139] Step 30: Form an asymmetric spacer along the sidewalls of the active region.

[0140] Step 40: Form an underground bit line below the silicon surface of the asymmetric spacer and the p-type substrate.

[0141] Step 50: Form the word line and gate structure of the U-shaped transistor (or access transistor) of the dynamic random access memory cell array.

[0142] Step 60: Define and isolate the drain (i.e., the first conduction region) and the source (i.e., the second conduction region) of the U-shaped transistor of the dynamic random access memory cell array.

[0143] Step 16: Form a connection between the underground bit line and the drain of the U-shaped transistor (or the access transistor), and dope the drain and the source.

[0144] Step 80: End.

[0145] Please refer to Figure 1B and Figure 2 , step 20 includes:

[0146] Step 102: Deposit a pad oxide layer 204 and a pad nitride layer 206.

[0147] Step 104: Define the active region of the dynamic random access memory cell array, and remove the silicon material corresponding to the semiconductor surface 208 (i.e., the silicon surface) outside the active region to generate a trench 210.

[0148] Step 106: Deposit and etch back an oxide layer 214 in the trench 210 to form the shallow trench isolation below the semiconductor surface 208.

[0149] Please refer to Figure 1C and Figure 3 , Figure 4 , Figure 5 , step 30 includes:

[0150] Step 108: Deposit and etch back a first nitride layer to form a first nitride spacer.

[0151] Step 110: Deposit the STI-first oxide layer 304 in the trench 210 and planarize it by chemical mechanical polishing (CMP) technology;

[0152] (chemical mechanical polishing,CMP) technology planarization;

[0153] Step 112: Deposit a photoresist layer 306 on the STI-first oxide layer 304 and the liner nitride layer 206;

[0154] Step 114: Completely etch the upper edge of the first nitride spacer layer and the STI-first oxide layer 304 that are not covered by the photoresist layer 306;

[0155] Step 116: Strip the photoresist layer 306 and the STI-first oxide layer 304, and generate the first oxide layer 502. Please refer to Figure 1D and Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 , step 40 includes:

[0156] Step 118: Deposit a metal layer 602 in the trench 210 and planarize it by the chemical mechanical polishing technology;

[0157] Step 120: Deposit a photoresist layer 702;

[0158] Step 122: Etch the metal layer 602 corresponding to the ends of the active regions to separate multiple wires;

[0159] Step 124: Remove the photoresist layer 702 and etch back the metal layer 602 to form the underlying wires 902 on the silicon surface;

[0160] Step 126: Deposit a second oxide layer 1002 in the trench 210 and planarize it by the chemical mechanical polishing technology.

[0161] Please refer to Figure 1E and Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 , step 50 includes:

[0162] Step 128: Deposit a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106, and remove the unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104; Step 130: Remove the patterned photoresist layer 1106, the liner nitride layer 206, and the liner oxide layer 204;

[0163] Step 132: Etch the semiconductor surface 208 to form a U-shaped groove, form a high-k dielectric layer 1304 within the U-shaped groove, and deposit a gate material 1306 and then etch back to form the word line and gate structure of the access transistor;

[0164] Step 134: Deposit a third nitride layer 1402, subsequently deposit a fourth oxide layer 1404, and then etch back the fourth oxide layer 1404;

[0165] Step 136: Etch away the second nitride layer 1104 and the third oxide layer 1102.

[0166] Please refer to Figure 1F and Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 , step 60 includes:

[0167] Step 138: Remove the pad nitride layer 206 and etch back the second oxide layer 1002 to the semiconductor surface 208; Step 140: Deposit and anisotropically etch a fourth nitride layer 1602, a fifth oxide layer 1604, and a fifth nitride layer 1606, and deposit a sixth oxide layer 1608;

[0168] Step 142: Deposit spin-on dielectrics (SOD) 1702, planarize the deposited spin-on dielectrics 1702 by the chemical mechanical planarization technique, deposit a photoresist to expose the spin-on dielectrics 1702 in the area serving as the source, and etch the spin-on dielectrics 1702, the pad oxide layer 204, and the silicon material in the area serving as the drain to create a hole Hole-1 / 3, and remove the photoresist;

[0169] Step 144: Deposit and etch back a seventh oxide layer 1802, and then deposit and etch back a spin-on dielectric layer 1804;

[0170] Step 146: Deposit a photoresist to expose the area serving as the drain, etch the spin-on dielectrics 1702, the pad oxide layer 204, and the silicon material near the area serving as the drain to create a hole Hole-1 / 2, remove the photoresist, and thermally grow an eighth oxide layer 1902.

[0171] Please refer to Figure 1G and Figure 21 、 Figure 22 、 Figure 23 、 Figure 24A 、 Figure 24B 、 Figure 25A 、Figure 25B , Figure 26 , step 70 includes:

[0172] Step 148: Remove the lower edge of the first nitride spacer layer to expose the sidewall of the under-gate bit line 902 (UGBL) on the silicon surface;

[0173] Step 150: Deposit a conductive material (such as n+ polysilicon 2202 or other metal materials (such as tungsten)) to contact the sidewall of the under-gate bit line 902 (UGBL) on the silicon surface, and then etch back the n+ polysilicon 2202 to leave an n+ polysilicon plug;

[0174] Step 152: Remove the upper part of the eighth oxide layer 1902 to expose the sidewall of the drain;

[0175] Step 154: Generate a connection material that allows the drain and the n+ polysilicon 2202 to contact to electrically connect the drain to the under-gate bit line 902 (UGBL) on the silicon surface;

[0176] Step 156: Generate an isolation material (such as a ninth oxide layer 2502) on the connection material;

[0177] Step 158: Remove the spin-on dielectric layer 1804, the sixth oxide layer 1608, and the fifth nitride layer 1606, and then use n-type dopant implantation to fabricate the drain and the source of the access transistor;

[0178] Step 160: End.

[0179] The detailed description of the above manufacturing method is as follows. The above manufacturing method starts from a p-type silicon wafer (i.e., a p-type substrate 202). In step 102, as Figure 2 (a) shows, a pad oxide layer 204 is formed on the semiconductor surface 208 (i.e., the horizontal silicon surface), and then a pad nitride layer 206 is deposited on the pad oxide layer 204.

[0180] In step 104, the photolithographic mask technique can define the active regions of the dynamic random access memory cell array, where as Figure 2As shown in (a), since the active regions of the dynamic random access memory storage cell array correspond to the pad oxide layer 204 and the pad nitride layer 206, the semiconductor surface 208 outside the active region pattern will thus be exposed. Since the semiconductor surface 208 outside the active region pattern is exposed, the silicon material corresponding to the semiconductor surface 208 outside the active region pattern can be removed by an anisotropic etching technique to create trenches (or channels) 210, where, for example, the trenches 210 can reach 250 nanometers deep under the semiconductor surface 208.

[0181] In step 106, an oxide layer 214 is deposited to fill the trenches 210, and then the oxide layer 214 is etched back to form the shallow trench isolation within the trenches 210 that is below the semiconductor surface 208. Additionally, Figure 2 (b) is a top view corresponding to Figure 2 (a), and Figure 2 (a) is a cross-sectional view along the cutting line in the X direction as shown in Figure 2 (b). Additionally, as shown in Figure 2 (a), in an embodiment of the present invention, the shallow trench isolation has a thickness of approximately 50 nanometers, and if the trenches 210 below the semiconductor surface 208 have a depth of 250 nanometers, the upper surface of the shallow trench isolation is approximately 200 nanometers deep from the semiconductor surface 208.

[0182] In step 108, as shown in Figure 3 (a), the first nitride layer is deposited and the first nitride layer is etched back using the anisotropic etching technique to form the first nitride spacer layer along the two edges (i.e., the upper edge and the lower edge) of the trenches 210. In step 110, as shown in Figure 3 (a), an STI-first oxide layer 304 is deposited over the shallow trench isolation within the trenches 210 to fill the trenches 210. Then the STI-first oxide layer 304 is planarized by the chemical mechanical planarization technique so that the upper surface of the STI-first oxide layer 304 is flush with the upper surface of the pad nitride layer 206.

[0183] In step 112, as shown in Figure 3As shown in (a), the first nitride spacer layer (i.e., the lower-edge first nitride spacer layer) along the lower edge of the trench 210 is protected by the photoresist layer 306 using photolithography technology, but the first nitride spacer layer along the upper edge of the trench 210 (i.e., the upper-edge first nitride spacer layer) is removed. That is, after the photoresist layer 306 is deposited on the STI-first oxide layer 304 and the liner nitride layer 206, since the photoresist layer 306 on the upper-edge first nitride spacer layer is removed but the photoresist layer 306 on the lower-edge first nitride spacer layer is retained, the lower-edge first nitride spacer layer is not removed but the upper-edge first nitride spacer layer can be removed. Additionally, Figure 3 (b) is a top view corresponding to Figure 3 (a), and Figure 3 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 3 (b). In step 114, as Figure 4 shown, the upper-edge first nitride spacer layer and the STI-first oxide layer 304 that are not covered by the photoresist layer 306 can be etched away through an etching process.

[0184] In step 116, as Figure 5 shown, the photoresist layer 306 and the STI-first oxide layer 304 are stripped, where the STI-first oxide layer 304 has an etching rate much higher than that of the thermally grown oxide layer and the deposited oxide layer. Then the thermally grown first oxide layer 502 is formed to form the first oxide spacer layer, where the first oxide spacer layer covers the upper edge of the trench 210, the first oxide layer 502 does not grow beyond the liner nitride layer 206, and only a very thin oxide layer (referred to as the first oxide / STI layer 504) is formed on the shallow trench isolation. As Figure 5 shown, step 116 results in the formation of asymmetric spacer layers (i.e., the lower-edge first nitride spacer layer (i.e., the first spacer layer described in claim 20) and the first oxide spacer layer (i.e., the second spacer layer described in claim 20)) on the two symmetrical edges of the trench 210 (i.e., the upper edge and the lower edge of the trench 210). For example, the thickness of the first oxide spacer layer is 4 nanometers and the thickness of the lower-edge first nitride spacer layer is 3 nanometers. On the other hand, the asymmetric spacer layers are also formed along the sidewalls of the active region. The structure of the asymmetric spacer layers (as Figure 5 shown) and the related steps above are the first main technical feature of the present invention, which is called asymmetric spacers on two symmetrical edges of a trench or a canal (ASoSE).

[0185] In step 118, as Figure 6 shown, a metal layer 602 (or a conductive material that needs to withstand subsequent process conditions) is deposited to fill the trench 210 and planarized by the chemical mechanical planarization technique so that the upper surface of the metal layer 602 is flush with the upper surface of the liner nitride layer 206 (as Figure 6 shown). Additionally, in an embodiment of the present invention, the metal layer 602 can be tungsten (abbreviated as W).

[0186] In step 120, as Figure 7 shown, a photoresist layer 702 is deposited to cover the lower edge first nitride spacer layer and the first oxide spacer layer, but exposes the two edges of the lower edge first nitride spacer layer and the first oxide spacer layer corresponding to the ends of the active regions.

[0187] In step 122, as Figure 8 shown, the metal layer 602 corresponding to the ends of the active regions is etched until the upper surface of the first oxide / STI layer 504 is exposed to separate multiple conductive lines (i.e., the metal layer 602).

[0188] In step 124, as Figure 9 (a) shown, after removing the photoresist layer 702, the metal layer 602 in the trench 210 is etched back to a reasonable thickness to form a sub-surface wire 902 on the silicon surface, where the upper surface of the sub-surface wire 902 on the silicon surface is much lower than the semiconductor surface 208 (e.g., the thickness of the sub-surface wire 902 on the silicon surface is about 40 nanometers). Additionally, as Figure 9 (a) shown, the sub-surface wire 902 on the silicon surface is located above the upper surface of the shallow trench isolation and the two sidewalls of the sub-surface wire 902 on the silicon surface are respectively limited by the asymmetric spacer layers (i.e., the lower edge first nitride spacer layer and the first oxide spacer layer). Additionally, Figure 9 (a) is a cross-sectional view along the cutting line in the Y direction as Figure 9 (b) shown.

[0189] In step 126, as Figure 10 (a cross-sectional view along the cutting line in the Y direction as Figure 9 (b) shown), the second oxide layer 1002 (also referred to as CVD-STI-oxide2) needs to have a sufficient thickness to fill the trench 210 above the sub-surface wire 902 on the silicon surface, and then the second oxide layer 1002 is polished by the chemical mechanical planarization technique to retain a part of the second oxide layer 1002, where the height of the retained part of the second oxide layer 1002 is flush with the upper surface of the liner nitride layer 206, limited by the liner nitride layer 206, and covers the lower edge first nitride spacer layer and the first oxide spacer layer. As Figure 10As shown, step 126 can embed the lower bit-line 902 on the silicon surface (i.e., the interconnect structure described in claim 1) into all the insulators (i.e., the isolation region described in claim 1) in the trench 210 and be limited by all the insulators (after which the lower bit-line 902 on the silicon surface will be connected to the drain of the access transistor of the dynamic random access memory storage cell array), where as Figure 10 The structure shown is called an insulator-enclosed lower bit-line on the silicon surface (UGBL), and the lower bit-line on the silicon surface (UGBL) is the second main technical feature of the present invention.

[0190] The following description will introduce how to form the access transistor and the word line of the dynamic random access memory storage cell (1T1C cell) array and form the word line connecting all the relevant gate structures of the access transistor simultaneously through a self-alignment method. In this way, the gate structures of the access transistors of the dynamic random access memory storage cell (1T1C cell) array and the word line will be connected into an integrated metal (such as tungsten (W)).

[0191] In step 128, as Figure 11 (a) shows, first, a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106 are deposited. Then, the unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104 are removed using the photolithography technique. Additionally, a transistor / word line pattern can be defined through the composite layer of the third oxide layer 1102 and the second nitride layer 1104, where the composite layer of the third oxide layer 1102 and the second nitride layer 1104 is composed of multiple strip-shaped third oxide layers 1102 and second nitride layers 1104 in a direction perpendicular to the active region direction. Therefore, as Figure 11 (a) and Figure 11 (b) show, longitudinal (the Y direction) stripes (composed of the third oxide layer 1102 and the second nitride layer 1104) for defining the access transistor and the word line, and cross-point squares for defining the active region will be formed, where the cross-point squares are cross-point spaces located between the two longitudinal stripes, and Figure 11 (a) is a cross-sectional view along the cutting line in the X direction as shown in Figure 11 (b).

[0192] As Figure 11 (b) shows, Figure 11(b) The top view shows a fabric-like checkerboard pattern with longitudinal stripes composed of a third oxide layer 1102 and a second nitride layer 1104 located above the pad nitride layer 206 and the pad oxide layer 204, and also shows the active region (covered by the pad nitride layer 206 and the pad oxide layer 204) and the shallow trench isolation in the horizontal direction (i.e., the X direction as shown in Figure 11 (b)). As shown in Figure 11 (b), the active region allows the access transistor to be fabricated by a self-alignment technique. This fabric-like checkerboard pattern of the gate structure of the access transistor and the self-alignment structure of the word line fabricated in one process step is the third main technical feature of the present invention.

[0193] In step 130, as shown in Figure 12 (a), the photoresist layer 1106 is retained, the pad nitride layer 206 is etched away, and the pad oxide layer 204 is retained, and as shown in Figure 12 (b), the photoresist layer 1106 and the pad oxide layer 204 are removed. Thus, the semiconductor surface 208 is exposed in the cross-point square area as shown in Figure 12 (b), where the cross-point square area corresponds to the active region (the cross-point square shown in Figure 11 (a) and Figure 11 (b)).

[0194] In step 132, as shown in Figure 13 , the semiconductor surface 208 exposed in the cross-point square area is etched by the anisotropic etching technique to form the U-shaped groove, where the U-shaped groove is for forming the U-shaped channel 1302 of the access transistor, and for example, the vertical depth of the U-shaped groove starting from the semiconductor surface 208 can reach about 60 nanometers, that is, the U-shaped channel 1302 is located below the semiconductor surface 208. Since the U-shaped groove of the access transistor is exposed, the U-shaped channel 1302 in the U-shaped groove can be doped by a reasonably designed concentration of boron (p-type dopant) to achieve channel doping, where the channel doping is to enable the access transistor to have the required threshold voltage after the subsequent formation of the high-k metal-gate structure. Then, a high-k insulating layer 1304 is formed on the bottom and sidewalls of the U-shaped groove, where the high-k insulating layer 1304 serves as the gate dielectric layer of the access transistor, and asFigure 13 As shown, the upper surfaces of the two edges of the high-k dielectric layer 1304 are higher than the semiconductor surface 208. Then, a gate material 1306 suitable for the word line conductivity and capable of achieving the targeted work-function performance is selected, so that the access transistor has a lower threshold voltage (the purpose of selecting the gate material 1306 is to reduce the boosted word line voltage to as low as possible while still providing sufficient driving force to complete the sufficient charge amount for restoring the capacitor (1C), and on the other hand, it is beneficial for faster charge transfer for signal detection).

[0195] The gate material 1306 (i.e., the suitable gate material) is deposited, where the gate material 1306 is sufficient to fill the U-shaped groove between two adjacent longitudinal stripes (formed by the third oxide layer 1102 and the second nitride layer 1104) as Figure 13 shown. For example, the gate material 1306 can be tungsten (W) used to form the high-k metal-gate structure. If the U-shaped channel 1302 has a suitable doping concentration, the high-k metal-gate structure allows the access transistor to have the required lower threshold voltage. Then, the gate material 1306 is etched to produce a longitudinal (in the Y direction) word line sandwiched between the two adjacent longitudinal stripes (formed by the third oxide layer 1102 and the second nitride layer 1104).

[0196] The access transistor with the U-shaped channel 1302 (hereinafter referred to as the U-type transistor) disclosed in the present invention is different from the recessed transistor commonly used in the buried word line design disclosed in the prior art. The body of the U-type transistor is restricted by the second oxide layer 1002 (i.e., CVD-STI-Oxide2) on both sides along the Y direction (i.e., the channel width direction), and the channel length of the U-type transistor includes the depth of the side of the U-shaped channel 1302 corresponding to the drain of the U-type transistor, the length of the bottom of the U-shaped channel 1302, and the depth of the side of the U-shaped channel 1302 corresponding to the source of the U-type transistor. For example, if the vertical depth of the U-shaped groove is 60 nanometers and the opening of the U-shaped groove along the X direction (i.e., the channel length direction) is 7 nanometers, the total length of the U-shaped channel 1302 of the U-type transistor can reach 127 nanometers. In contrast, the channel length of the recessed transistor must more depend on the depth at which the gate material of the recessed transistor is embedded and the depth formed by the source junction and the drain junction of the recessed transistor.

[0197] Due to the structural differences between the U-shaped transistor and the embedded transistor, the channel length of the U-shaped channel 1302 can be better controlled (especially when the channel length of the U-shaped channel 1302 does not depend on the gate structure height of the U-shaped transistor). Additionally, since the semiconductor surface 208 is fixed, the doping concentration profiles of the drain and source of the U-shaped transistor have fewer device-design-parameter variations and higher controllability, which will be described in more detail later regarding how to form the drain and source of the U-shaped transistor. Additionally, in the longitudinal direction, forming the gate structure of the U-shaped transistor and the word line simultaneously through self-alignment between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104) is a way to keep the word line not lower than the semiconductor surface 208, where the word line not lower than the semiconductor surface 208 has design and performance parameters quite different from those of the buried word lines commonly used in the prior art. Additionally, the height of the word line (i.e., the gate material 1306) is designed to be lower than the height of the composite layer (composed of the third oxide layer 1102 and the second nitride layer 1104) through etching back. Additionally, the structural design in which the gate structure of the U-shaped transistor is self-aligned to the word line is the fourth main technical feature of the present invention.

[0198] In step 134, as Figure 14 shown, deposit the third nitride layer 1402, and subsequently deposit the fourth oxide layer 1404, where the third nitride layer 1402 and the fourth oxide layer 1404 are stacked together such that their total thickness is sufficient to fill the space between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104). Then, etch back (or polish) the fourth oxide layer 1404 to make the upper surface of the fourth oxide layer 1404 flush with the upper surface of the second nitride layer 1104, thereby forming a composite layer composed of the fourth oxide layer 1404 and the third nitride layer 1402 directly above the word line (i.e., the gate material 1306).

[0199] In step 136, as Figure 15 shown, etch away the second nitride layer 1104 through the anisotropic etching technique, and retain the fourth oxide layer 1404 / third nitride layer 1402 above the word line. Then, also etch away the third oxide layer 1102 through the anisotropic etching technique to expose the pad nitride layer 206. As Figure 15 shown, the gate structure (such as the fourth oxide layer 1404 / third nitride layer 1402 / gate material 1306) simultaneously realizes the gate structure of the U-shaped transistor within the U-shaped groove and the word line in the longitudinal direction (i.e., the Y direction).

[0200] In step 138, as Figure 16 shown, the liner nitride layer 206 is removed to leave the liner oxide layer 204. The second oxide layer 1002 (i.e., the second oxide layer) is etched back so that the upper surface of the second oxide layer 1002 is flush with the upper surface of the liner oxide layer 204.

[0201] In step 140, as Figure 16 shown, the fourth nitride layer 1602 is deposited and the fourth nitride layer 1602 is etched by the anisotropic etching technique to generate a fourth nitride spacer layer with a designed thickness (i.e., the first spacer layer and the second spacer layer as claimed in claim 7). Then, the fifth oxide layer 1604 is deposited and the fifth oxide layer 1604 is etched by the anisotropic etching technique to generate a fifth oxide spacer layer. Then, the fifth nitride layer 1606 is deposited and the fifth nitride layer 1606 is etched by the anisotropic etching technique to generate a fifth nitride spacer layer. Then, the sixth oxide layer 1608 is deposited on the entire surface as Figure 16 shown. Thus, in summary, the sixth oxide layer 1608 is outside the fifth nitride spacer layer, the fifth nitride spacer layer is outside the fifth oxide spacer layer, and the fifth oxide spacer layer is outside the fourth nitride spacer layer, and all the above spacer layers surround and are along the gate structure (the fourth oxide layer 1404 / the third nitride layer 1402 / the gate material 1306).

[0202] As Figure 16 , Figure 17As shown, for the convenience and clear description of the dynamic random access memory storage cell array having the word lines and the bit lines, the word line at the center is labeled as the first word line Wordline-1 (corresponding to the access transistor AQ1), the word line adjacent to the left of the first word line Wordline-1 is labeled as the second word line Wordline-2 (corresponding to the access transistor AQ2 adjacent to the left of the access transistor AQ1), and the pad oxide layer 204 still covers the region as the drain between the first word line Wordline-1 and the second word line Wordline-2 to reserve the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2. The word line adjacent to the right of the first word line Wordline-1 is labeled as the third word line Wordline-3 (corresponding to the access transistor AQ3 adjacent to the right of the access transistor AQ1), and the pad oxide layer 204 still covers the region as the source between the first word line Wordline-1 and the third word line Wordline-3 to reserve the first source Source-1 of the access transistor AQ1 and the third source Source-3 of the access transistor AQ3. Additionally, taking the first word line Wordline-1 and the access transistor AQ1 as an example, as Figure 16 shown, the first word line Wordline-1 is obviously coupled to the gate structure of the access transistor AQ1, wherein the first word line Wordline-1 (i.e., the interconnect structure described in claim 6) includes an upper portion above the semiconductor surface 208 of the p-type substrate 202, and the sidewalls of the upper portion of the first word line Wordline-1 are obviously aligned with the sidewalls of the gate structure of the access transistor AQ1.

[0203] In step 142, as Figure 17As shown, the spin-on dielectric 1702 is deposited, where the thickness of the spin-on dielectric 1702 is sufficient to fill the space (the regions serving as the drain and the source) between the above word lines (the first word line Wordline-1, the second word line Wordline-2, and the third word line Wordline-3), and the spin-on dielectric 1702 is polished by the chemical mechanical planarization technique to make the upper surface of the spin-on dielectric 1702 flush with the upper surface of the fourth oxide layer 1404. Additionally, the sixth oxide layer 1608 is also polished to make the upper surface of the sixth oxide layer 1608 flush with the upper surface of the fourth oxide layer 1404. The photoresist is deposited to cover the spin-on dielectric 1702 in the regions serving as the drain (the first drain Drain-1 and the second drain Drain-2), and the spin-on dielectric 1702 in the regions serving as the source (the first source Source-1 and the third source Source-3) is exposed for subsequent processing. Then, the sixth oxide layer 1608 around the above word lines (the first word line Wordline-1, the second word line Wordline-2, and the third word line Wordline-3) can serve as a self-alignment mask to remove the spin-on dielectric 1702 in the regions serving as the source (the first source Source-1 and the third source Source-3), and the pad oxide layer 204 at the center of the region serving as the source is etched away to expose the semiconductor surface 208. Then, as Figure 17 shown, the silicon material of the semiconductor surface HSS-1 / 3 (a part of the semiconductor surface 208) in the region serving as the source is excavated and removed by the anisotropic etching to generate holes Hole-1 / 3 (for example, the depth of the holes Hole-1 / 3 is 140 nanometers), where two pairs of sides of the holes Hole-1 / 3 are surrounded by the lower-edge first nitride spacer and the first oxide spacer and the other two pairs of sides of the holes Hole-1 / 3 are surrounded by the p-type substrate 202.

[0204] As Figure 17As shown, the semiconductor surface HSS-1 / 2 (a part of the semiconductor surface 208) between the first word line Wordline-1 and the second word line Wordline-2 serves as the region for the first drain Drain-1 (i.e., the drain of the access transistor AQ1) and the second drain Drain-2 (i.e., the drain of the access transistor AQ2), and also serves as the region for vertically connecting the access transistors AQ1 and AQ2 to the lower bit line 902 on the silicon surface. Additionally, the semiconductor surface HSS-1 / 3 (a part of the semiconductor surface 208) between the first word line Wordline-1 and the third word line Wordline-3 serves as the region for the first source Source-1 (i.e., the source of the access transistor AQ1) and the third source Source-3 (i.e., the source of the access transistor AQ3). However, since the first source Source-1 and the third source Source-3 will be connected to the unit storage nodes CSN1 and CSN3 respectively, the first source Source-1 and the third source Source-3 must be separated and not connected. Additionally, since the spin-on dielectric 1702 has a very high etching rate without damaging other existing materials and the spin-on dielectric 1702 can resist other thermal processes other than photoresist, the spin-on dielectric 1702 is used in step 142. Additionally, since the required pattern has been transferred to the spin-on dielectric 1702, all unnecessary photoresist must be removed to planarize the spin-on dielectric 1702 (as Figure 17 shown).

[0205] In step 144, as Figure 18 shown, the seventh oxide layer 1802 is deposited, where the thickness of the seventh oxide layer 1802 is sufficient to fill the hole Hole-1 / 3 and the seventh oxide layer 1802 above the semiconductor surface 208 is accurately removed by an isotropic etch technique to form a seventh oxide vertical isolation within the hole Hole-1 / 3, where the upper surface of the seventh oxide vertical isolation is flush with the semiconductor surface 208. Then a spin-on dielectric layer 1804 is deposited, where the thickness of the spin-on dielectric layer 1804 is sufficient to fill the space on the upper surface of the seventh oxide layer 1802 in the hole Hole-1 / 3, and the spin-on dielectric material at the top of the spin-on dielectric layer 1804 is removed by the chemical mechanical planarization technique until the upper surface of the spin-on dielectric layer 1804 is flush with the upper surface of the fourth oxide layer 1404.

[0206] In step 146, as Figure 19As shown, a deposited and patterned photoresist is used to cover the area serving as the drain and to expose the area serving as the drain. Then, the spin-on dielectric 1702 corresponding to the holes Hole-1 / 2 and the underlying liner oxide 204 are removed to expose the semiconductor surface 208. Then, the silicon material corresponding to the semiconductor surface HSS-1 / 2 (a portion of the semiconductor surface 208) is etched and removed by the anisotropic etching to create the holes Hole-1 / 2 (for example, the depth of the holes Hole-1 / 2 is 200 nanometers), where two opposite sides of the holes Hole-1 / 2 are respectively surrounded by the p-type substrate 202, the third side of the holes Hole-1 / 2 is surrounded by the lower-edge first nitride spacer, and the fourth side of the holes Hole-1 / 2 is surrounded by the first oxide spacer, where the second oxide layer 1002 may additionally externally limit the third and fourth sides of the holes Hole-1 / 2. Then, the photoresist and the thermally generated eighth oxide layer 1902 (i.e., the first isolation layer described in claim 13) are removed to cover three of the four inner sidewalls of the holes Hole-1 / 2 and the bottom of the holes Hole-1 / 2, where the other inner sidewall different from the three inner sidewalls of the four inner sidewalls of the holes Hole-1 / 2 is covered by the lower-edge first nitride spacer. Additionally, Figure 20 is a cross-sectional view of the dynamic random access memory storage cell array along the Y2 direction, where the Y2 direction extends along the center of the holes Hole-1 / 2 and is perpendicular to the X direction. Additionally, as Figure 20 shown, the active region is sandwiched between the second oxide layer 1002 (CVD-STI-Oxide2), the silicon surface lower bit line 902 (UGBL), the first oxide spacer, and the lower-edge first nitride spacer.

[0207] In step 148, as Figure 21 shown, the lower-edge first nitride spacer on the other inner sidewall within the holes Hole-1 / 2 is removed by the isotropic etching technique (since the lower-edge first nitride spacer is very thin and because the sixth oxide layer 1608 is a good protection for the fifth nitride spacer (corresponding to the fifth nitride layer 1606), the isotropic etching technique does not damage other structures above the semiconductor surface 208 and also does not remove the eighth oxide layer 1902 within the holes Hole-1 / 2).

[0208] In step 150, as Figure 22As shown, a very heavily doped n+ polysilicon 2202 (or tungsten) is deposited, where the thickness of the n+ polysilicon 2202 (or tungsten) is sufficient to fill the hole Hole-1 / 2 so as to form a flat surface above the n+ polysilicon 2202 (or tungsten), and then the n+ polysilicon 2202 (or tungsten) on the semiconductor surface 208 is removed by the isotropic etching technique to leave an n+ polysilicon (or tungsten) plug in the hole Hole-1 / 2, where the upper surface of the n+ polysilicon (or tungsten) plug is flush with the semiconductor surface 208. As Figure 22 As shown, within the hole Hole-1 / 2, the n+ polysilicon (or tungsten) plug is connected to the sidewall of the silicon surface lower bit line 902 (UGBL) through its sidewall, and this connection method is the fifth main technical feature of the present invention, where the n+ polysilicon (or tungsten) plug and the silicon surface lower bit line 902 (UGBL) are conductive materials connected in a sidewall self-alignment way, but are completely isolated from the p-type substrate 202 by the eighth oxide layer 1902.

[0209] In step 152, as Figure 23 As shown, an upper part of the eighth oxide layer 1902 is removed by the anisotropic etching technique (for example, the upper part of the eighth oxide layer 1902 below a height 20 nanometers below the semiconductor surface 208 is removed) to generate an eighth oxide spacer layer within the hole Hole-1 / 2, where the height of the eighth oxide spacer layer is lower than the height of the n+ polysilicon (or tungsten) plug (for example, the height of the eighth oxide spacer layer is about 20 nanometers lower than the semiconductor surface 208).

[0210] In step 154, as Figure 24A As shown, when taking the n+ polysilicon plug 2202 (which is the bridge contact described in claim 11) as an example, a thin layer of n+ polysilicon material can be grown by using the silicon seeds provided by the n+ polysilicon plug 2202 and the selective epitaxy growth (SEG) technique, so that the neck-type surrounding conductive n+ polysilicon (i.e., the thin layer of n+ polysilicon material) on the semiconductor surfaces 208 connected to both sides of the hole Hole-1 / 2 can be used as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2 respectively, and can also be used as a conductive bridge contact between the silicon surface lower bit line 902 (UGBL) (which is the interconnect structure described in claim 11) and the access transistors AQ1 and AQ2, where the neck-type surrounding conductive n+ polysilicon is also called the n+ Collar. Then, in step 156, as Figure 25AAs shown, a ninth oxide layer 2502 (i.e., an isolation cap) is thermally grown locally on the n+ polysilicon plug 2202 to cover the semiconductor surface HSS-1 / 2 (a part of the semiconductor surface 208), but leaving the n+ ring as (or in contact with) the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2. The above-described connection method of forming the conductive bridge contact between the underlying bit line 902 (UGBL) on the silicon surface and the first drain Drain-1 (or the second drain Drain-2) is the sixth main technical feature of the present invention, wherein the first drain Drain-1 and the second drain Drain-2 are oxide (i.e., the isolation cap) covered n+ drains.

[0211] In addition, please refer to Figure 24B , Figure 24B which is a schematic diagram illustrating another way of implementing the vertical connection (bridge) and the first drain Drain-1 of the access transistor AQ1 (or the second drain Drain-2 of the access transistor AQ2) disclosed in another embodiment of the present invention, and how the vertical connection (bridge) and the first drain Drain-1 of the access transistor AQ1 (or the second drain Drain-2 of the access transistor AQ2) are connected to the underlying bit line 902 (UGBL) on the silicon surface. By following the above steps to thermally grow the eighth oxide layer 1902 and remove the lower-edge first nitride spacer layer within the hole Hole-1 / 2, but the next step is not to deposit n+ polysilicon 2202 within the hole Hole-1 / 2, but to form a thick layer of tungsten or other metal material to fill the hole Hole-1 / 2 by deposition or any other means, and then etch back the tungsten or other metal material to leave a plug (referred to as a W-2 plug) within the hole Hole-1 / 2. The W-2 plug is connected to the underlying bit line 902 (UGBL) on the silicon surface through an opening on the sidewall of the hole Hole-1 / 2. The height of the W-2 plug is lower than the semiconductor surface 208 by a designed distance (e.g., 20 nanometers). The portion of the eighth oxide layer 1902 within the hole Hole-1 / 2 that is not covered by the W-2 plug is removed by the anisotropic etching technique. Then, an n+ polysilicon layer 2402 is deposited to fill the hole Hole-1 / 2, and then the n+ polysilicon layer 2402 is etched back so that the height of the n+ polysilicon layer 2402 is flush with the semiconductor surface 208, thus resulting in a neck-type surrounding conductive n+ polysilicon (also referred to as an n+ ring) on the semiconductor surface 208 connected to both sides of the hole Hole-1 / 2 that can serve as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2, respectively, and can also serve as the conductive bridge contact between the underlying bit line 902 (UGBL) on the silicon surface and the access transistors AQ1, AQ2. Then, as Figure 25BAs shown, a ninth oxide layer 2502 (i.e., the isolation cap) is thermally grown locally on the W-2 plug to cover the semiconductor surface HSS-1 / 2 (a part of the semiconductor surface 208), but leaving the n+ ring as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2.

[0212] The advantages of using the W-2 plug to connect the underlying bit line 902 (UGBL) on the silicon surface to the n-type doped drain or source (or p-type doped drain or source) respectively are as follows: (1) The same type of vertical bridge material (i.e., the W-2 plug) can be used in a complementary metal-oxide-semiconductor (CMOS) to connect the first conduction region (i.e., the drain) of the n-type metal-oxide-semiconductor (NMOS) included in the complementary metal-oxide-semiconductor and the second conduction region (i.e., the drain) of the p-type metal-oxide-semiconductor included in the complementary metal-oxide-semiconductor; (2) Because the same material is used, the contact between the W-2 plug and the underlying bit line 902 (UGBL) on the silicon surface has a low resistance.

[0213] In step 158, as Figure 26 shown, the sixth oxide layer 1608 and the fifth nitride spacer layer are removed, and then the n-type dopant implantation can generate a drain or source with an n-p junction (i.e., the first drain Drain-1 and the first source Source-1 of the access transistor AQ1, the second drain Drain-2 of the access transistor AQ2, and the third source Source-3 of the access transistor AQ3) in the p-type substrate 202 through the pad oxide layer 204. Additionally, a rapid thermal annealing (RTA) process step is required to activate the n-type dopant to eliminate any defects caused by ion implantation. Additionally, n-type lightly doped drains (NLDD) can be formed under the fifth oxide spacer layer and the fourth nitride spacer layer.

[0214] Figure 27 and Figure 28 are schematic diagrams respectively showing a cross-sectional view and a top view of the dynamic random access memory storage cell array. As Figure 27 and Figure 28 shown, Figure 27 and Figure 28Disclosed is the principle of an underground interconnection structure for connecting to the drains (such as the first drain Drain-1 and the second drain Drain-2) of the access transistors (such as access transistors AQ1 and AQ2) through a self-aligned vertical connector. Additionally, the first source Source-1 and the third source Source-3 are respectively connected to capacitors 2602 and 2604, where the capacitors 2602 and 2604 can be generated using methods commonly used to fabricate stacked capacitors or trench capacitors to complete the dynamic random access memory cells (1T1C cells) in the dynamic random access memory cell array. Additionally, Figure 28 along Figure 20 a cross-sectional view of the dynamic random access memory cell array in the Y2 direction described can show the position of the under-silicon surface bit line 902 (UGBL). Additionally, other transistors included in the dynamic random access memory cell array can be electrically connected to signal lines (not shown in Figure 28 , for example, the signal lines can be power lines coupled to a voltage source or a ground source), where the signal lines are distributed under the semiconductor surface 208 and separated from the under-silicon surface bit line 902 (UGBL), and the distance between the upper surface of the semiconductor surface 208 and the upper surface of the under-silicon surface bit line 902 (UGBL) is different from the distance between the upper surface of the semiconductor surface 208 and the upper surface of the signal lines.

[0215] Similarly, according to the above principle, many other memory cell or component structures can also consider using the under-silicon surface bit line 902 (UGBL) and / or a self-aligned gate structure and word line structure and effectively connecting the access transistors AQ1 and AQ2 to anywhere on the same chip through the underground interconnection structure to achieve the required functions. Such well-isolated interconnection structures / wires in the p-type silicon substrate 202 can also be applied to other types of transistors, such as fin field-effect transistors (FinFETs), tri-gate transistors, and planar transistors, etc.

[0216] As described above, forming an asymmetric spacer layer along the sidewalls of the active region and forming an interconnect under the silicon surface (such as an underground bit-line (UGBL) or a conduction line under the silicon surface) between the asymmetric spacer layers and below the silicon surface are the main technical features of the present invention. Next, another embodiment of the present invention will disclose another process for forming the asymmetric spacer layer and the interconnect under the silicon surface. As Figure 29 shown, first, a pad oxide layer 204 and a pad nitride layer 206 are deposited to define the active region, a portion of the silicon material outside the active region is removed, and then an oxide layer 214 is deposited and etched back to form a shallow trench isolation (STI) region, where Figure 29 (c) is a top view illustrating the temporary structure after the formation of the shallow trench isolation region, Figure 29 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 29 (c), and Figure 29 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 29 (c).

[0217] After that, as Figure 30 shown, a thermal oxide layer 205 is formed along the exposed sidewalls of the active region, where Figure 30 (c) is a top view illustrating the temporary structure after the formation of the thermal oxide layer 205, Figure 30 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 30 (c), and Figure 30 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 30 (c). Then, as Figure 31 shown, a spin-on dielectric material 207 is deposited and planarized by the chemical mechanical polishing (CMP) technique, where Figure 31 (c) is a top view illustrating the temporary structure after the planarization of the spin-on dielectric material 207, Figure 31 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 31 (c), and Figure 31 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 31 (c).

[0218] After that, as Figure 32 shown, a patterned photoresist layer 306 is formed to cover a portion (such as 1 / 2) of the active region and expose a portion of the spin-on dielectric material 207, where Figure 32(c) is a top view showing the temporary structure after the spin-on dielectric material 207 is exposed. Figure 32 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 32 (c), and Figure 32 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 32 (c). Thereafter, as shown in Figure 33 , the exposed spin-on dielectric material 207 and the thermal oxide layer 205 thereunder are removed to form a narrow trench (where when the process node is about 8 - 20 nanometers (nm), the width of the narrow trench is between 2 - 5 nm, for example 3 nm), where Figure 33 (c) is a top view showing the temporary structure after the exposed spin-on dielectric material 207 and the thermal oxide layer 205 thereunder are removed. Figure 33 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 33 (c), and Figure 33 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 33 (c). It should be noted here that after the exposed spin-on dielectric material 207 and the thermal oxide layer 205 thereunder are removed, one sidewall of the active region is exposed by the narrow trench.

[0219] As shown in Figure 34 , after the patterned photoresist layer 306 is removed, silicon oxycarbide nitride (SiOCN) material 209 is deposited in the narrow trench and planarized by the chemical mechanical planarization technique. Thus, the asymmetric spacer layer comprises different materials (such as the oxide layer 205 and the silicon oxycarbide nitride material 209) formed in the shallow trench isolation region. As shown in Figure 34 (a), the asymmetric spacer layer also covers both sidewalls of the active region respectively. Additionally, Figure 34 (c) is a top view showing the temporary structure after the silicon oxycarbide nitride material 209 is deposited and planarized. Figure 34 (a) is a cross-sectional view along the cutting line in the Y direction as shown in Figure 34 (c), and Figure 34 (b) is a cross-sectional view along the cutting line in the X direction as shown in Figure 34 (c).

[0220] Thereafter, as shown in Figure 35 , the spin-on dielectric material 207 is removed, a titanium nitride layer 303 and a tungsten layer 305 are deposited between the oxide layer 205 and the silicon oxycarbide nitride material 209, and then the titanium nitride layer 303 and the tungsten layer 305 are etched back to form the silicon subsurface interconnect line, where Figure 35 (c) is a top view showing the temporary structure after the silicon subsurface interconnect line is formed. Figure 35 (a) is a cross-sectional view along the...Figure 35 The cross-sectional view of the cutting line in the Y direction shown in (c), and Figure 35 (b) is along the Figure 35 The cross-sectional view of the cutting line in the X direction shown in (c). Then, as Figure 36 shown, a silicon nitride layer 307 and a high-density plasma (HDP) oxide layer 309 are formed to cover the interconnect lines under the silicon surface, where Figure 36 (c) is a top view illustrating the temporary structure after the formation of the silicon nitride layer 307 and the high-density plasma oxide layer 309, Figure 36 (a) is the cross-sectional view of the cutting line in the Y direction shown in (c), and Figure 36 (c) is the cross-sectional view of the cutting line in the X direction shown in (c). In addition, Figure 36 (b) is along the Figure 36 The cross-sectional view of the cutting line in the X direction shown in (c). Additionally, Figure 37 is a schematic diagram of the three-dimensional perspective view of the temporary structure illustrating Figure 36 .

[0221] In summary, since the present invention introduces the well-isolated interconnect structure / wire below the silicon surface, in addition to using the interconnect structure only above the semiconductor surface, the interconnect structure / wire can also connect the transistor at the bottom of the transistor within the silicon substrate.

[0222] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device structure, characterized in that Include: preparing a semiconductor substrate having an original surface; Forming a group of active regions based on the semiconductor substrate and forming a shallow trench isolation region between two adjacent active regions in the group of active regions; forming an asymmetric spacer layer in the shallow trench isolation region between the two adjacent active regions, A first spacer layer in the asymmetric spacer layer is an oxide layer, and the first spacer layer covers a side wall of a first active region in the two adjacent active regions. A second spacer layer in the asymmetric spacer layer is disposed in a narrow groove, and the narrow groove exposes a side wall of a second active region in the two adjacent active regions; and A first interconnect layer is formed between the asymmetric spacer layers, wherein the first interconnect layer is in the shallow trench isolation region and below the original surface of the semiconductor substrate.

2. The method according to claim 1, characterized in that A material of the first spacer layer is different from a material of the second spacer layer.

3. The method according to claim 1, characterized in that The second spacer layer is composed of silicon oxycarbon nitride.

4. The method according to claim 1, characterized in that Also includes: forming a second interconnect layer and forming a gate region of a transistor in the second active region, wherein the gate region of the transistor is connected to the second interconnect layer; and An interconnect plug is formed in the second active region to connect the first interconnect layer.

5. The method according to claim 4, characterized in that Forming the second interconnect layer and forming the gate region of the transistor in the second active region includes: etching the second active region to form a recess therein; depositing a high dielectric constant insulating layer in the recess; and A first conductive material is deposited to form the gate region of the transistor and the second interconnect layer.

6. The method according to claim 4, characterized in that Forming the interconnect plug comprises: Etching the second active region to form a hole and forming a dielectric layer in the hole; removing the second spacer layer based on the hole to expose a side wall of the first interconnection layer; and A second conductive material is deposited in the hole to connect the sidewall of the first interconnect layer.

7. The method according to claim 4, characterized in that The semiconductor device structure is a dynamic random access memory cell, the first interconnect layer is a bit line, the transistor is an access transistor of the dynamic random access memory cell, and the second interconnect layer is a word line.

8. The method according to claim 1, characterized in that Forming the asymmetric spacer layer comprises: forming the oxide layer to cover the sidewall of the first active region, and forming a temporary oxide layer to cover the second active region; Depositing a sacrificial layer over the shallow trench isolation region to cover the oxide layer and the temporary oxide layer; forming the narrow trench by removing a first portion of the sacrificial layer and the temporary oxide layer to expose the sidewall of the second active region; and The second spacer layer is deposited in the narrow trench to cover the sidewall of the second active region.

9. The method according to claim 8, characterized in that The narrow trench is completely filled with the second spacer layer.

10. The method according to claim 8, characterized in that Forming the narrow groove comprises: forming a patterned photoresist layer to expose a first portion of the sacrificial layer; and The first portion of the sacrificial layer and the temporary oxide layer covered by the first portion of the sacrificial layer are removed to form the narrow trench.

11. The method according to claim 8, characterized in that The width of the narrow groove is 2 to 5 nanometers.

Images