Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate including adjacent PMOS device regions and NMOS device regions; a channel structure layer suspended on top of the substrate containing the PMOS and NMOS device regions, the channel structure layer including one or more spaced-apart channel layers, wherein the width of the channel layer in the PMOS device region is greater than the width of the channel layer in the NMOS device region; a device gate structure located on top of the substrate and spanning the channel structure layer, the device gate structure surrounding the channel layer; source / drain doped layers located in the channel structure layers on both sides of the device gate structure; and an interlayer dielectric layer located on top of the source / drain doped layers and covering the sidewalls of the device gate structure. This method balances the electrical performance of the PMOS device region and the NMOS device region, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] As device size continues to shrink, improving the performance of fully enclosed gate structure devices becomes increasingly difficult and challenging. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including adjacent PMOS device regions and NMOS device regions; a channel structure layer suspended on top of the substrate of the PMOS device regions and NMOS device regions, the channel structure layer including one or more spaced-apart channel layers, wherein the width of the channel layer in the PMOS device region is greater than the width of the channel layer in the NMOS device region; a device gate structure located on top of the substrate and spanning the channel structure layer, the device gate structure surrounding the channel layer; source / drain doped layers located in the channel structure layers on both sides of the device gate structure; and an interlayer dielectric layer located on top of the source / drain doped layers and covering the sidewalls of the device gate structure.

[0007] Optionally, the width of the channel layer in the PMOS device region is greater than the width of the channel layer in the NMOS device region, and the width difference is 0.5 nanometers to 10 nanometers.

[0008] Optionally, along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, the sidewall of the device gate structure located directly below the channel layer is recessed relative to the sidewall of the channel layer; the semiconductor structure further includes: an inner wall layer located between the sidewall of the device gate structure located directly below the channel layer and the source / drain doped layer.

[0009] Optionally, the device gate structure includes: a gate dielectric layer surrounding the channel layer and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0010] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent PMOS device regions and NMOS device regions, wherein a stacked structure material layer is formed on top of the substrate of the PMOS device regions and NMOS device regions; forming a protruding mask sidewall layer on top of the stacked structure material layer, wherein the width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region; using the mask sidewall layer as a mask, patterning the stacked structure material layer in the PMOS device regions and NMOS device regions to form a protruding stacked structure on top of the substrate, the stacked structure including one or more stacked channel stacks, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer.

[0011] Optionally, in the step of forming the mask sidewall layer, the mask sidewall layer in the PMOS device region includes a first mask sidewall layer and a second mask sidewall layer located on both sides of the first mask sidewall layer, and the mask sidewall layer in the NMOS device region includes the first mask sidewall layer.

[0012] Optionally, the step of forming the mask sidewall layer includes: forming a protruding first mask sidewall layer on top of the stacked structure material layer of the PMOS device region and the NMOS device region; forming a second mask sidewall material layer on top of the substrate, covering the top of the stacked structure material layer, as well as the top and sidewalls of the first mask sidewall layer; removing the second mask sidewall material layer of the NMOS device region; after removing the second mask sidewall material layer of the NMOS device region, removing the second mask sidewall material layer covering the top of the first mask sidewall layer and the top of the stacked structure material layer of the PMOS device region, using the remaining second mask sidewall material layer located on the sidewall of the first mask sidewall layer as the second mask sidewall layer, using the first mask sidewall layer and the second mask sidewall layer in the PMOS device region as the mask sidewall layer in the PMOS device region, and using the first mask sidewall layer in the NMOS device region as the mask sidewall layer in the NMOS device region.

[0013] Optionally, in the step of forming the mask sidewall layer, the material of the mask sidewall layer includes one or more of silicon nitride, silicon carbide, silicon oxide, and silicon oxynitride.

[0014] Optionally, the process for forming the second mask sidewall material layer includes atomic layer deposition.

[0015] Optionally, the step of removing the second mask sidewall material layer of the NMOS device region includes: forming a mask layer covering the second mask sidewall material layer on top of the substrate of the PMOS device region, with the mask layer exposing the second mask sidewall material layer of the NMOS device region; using the mask layer as a mask to remove the second mask sidewall material layer of the NMOS device region exposed by the mask layer.

[0016] Optionally, the process for removing the second mask sidewall material layer of the NMOS device region includes a dry etching process.

[0017] Optionally, in the step of removing the second mask sidewall material layer on top of the first mask sidewall layer and the stacked structure material layer covering the PMOS device region, the etching selectivity ratio between the second mask sidewall material layer and the first mask sidewall layer is greater than 100:1.

[0018] Optionally, in the step of removing the second mask sidewall material layer of the NMOS device region, the etching selectivity ratio between the second mask sidewall material layer and the first mask sidewall layer is greater than 100:1.

[0019] Optionally, in the step of forming the mask sidewalls, the width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region by 1 nanometer to 10 nanometers.

[0020] Optionally, after forming a raised stacked structure on top of the substrate, the method for forming the semiconductor structure further includes: removing the mask sidewall layers in the PMOS device region and the NMOS device region; forming a gate structure across the stacked structure on top of the substrate in the PMOS device region and the NMOS device region, the gate structure covering part of the top and part of the sidewalls of the stacked structure; forming source / drain doped layers in the stacked structures on both sides of the gate structure; forming an interlayer dielectric layer on top of the source / drain doped layers, the interlayer dielectric layer covering the sidewalls of the gate structure; removing the gate structure and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening and forming a through-slot connected to the gate opening below the channel layer; forming a device gate structure in the gate opening and the through-slot, the device gate structure surrounding the channel layer.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0022] This invention provides a semiconductor structure in which the width of the channel layer in the PMOS device region is greater than the width of the channel layer in the NMOS device region. This allows the carrier migration in the channel layer of the PMOS device region to be similar to that in the channel layer of the NMOS device region, thereby balancing the electrical performance of the PMOS device region and the NMOS device region, and thus improving the performance of the semiconductor structure.

[0023] This invention provides a method for forming a semiconductor structure. First, a protruding mask sidewall layer is formed on top of a multilayer material layer. The width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region. Then, during the patterning process of the multilayer material layer in the PMOS and NMOS device regions using the mask sidewall layer as a mask, the width of the mask sidewall layer in the PMOS device region is greater than that in the NMOS device region. This allows the width of the channel layer formed in the PMOS device region to be greater than that in the NMOS device region. Compared to a scheme where the width of the channel layer in the PMOS device region is the same as that in the NMOS device region, this invention, by setting the width of the channel layer in the PMOS device region to be greater than that in the NMOS device region, enables the carrier migration in the channel layer of the PMOS device region to be closer to that in the channel layer of the NMOS device region. This balances the electrical performance of the PMOS and NMOS device regions, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a semiconductor structure.

[0025] Figure 2This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0026] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0027] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a particular semiconductor structure needs further improvement.

[0028] Figure 1 This is a schematic diagram of a semiconductor structure.

[0029] The semiconductor structure includes: a substrate 10, which includes adjacent PMOS device regions 10A and NMOS device regions 10B; a channel structure layer 22, suspended on top of the substrate 10 above the PMOS device regions 10A and NMOS device regions 10B, the channel structure layer 22 including one or more spaced-apart channel layers 12, and the width of the channel layer 12 in the PMOS device region 10A is equal to the width of the channel layer 12 in the NMOS device region 10B; a device gate structure 15, located on top of the substrate 10 and spanning the channel structure layer 22, the device gate structure 15 surrounding the channel layer 12; source / drain doped layers (not shown), located in the channel structure layers 22 on both sides of the device gate structure 15; and an interlayer dielectric layer 13, located on top of the source / drain doped layers and covering the sidewalls of the device gate structure 15.

[0030] Research has revealed that, since hole mobility is much lower than electron mobility, when the width of the channel layer 12 in PMOS device region 10A is equal to the width of the channel layer 12 in NMOS device region 10B, it means that the carrier mobility in the channel layer 12 of PMOS device region 10A is much lower than that in the channel layer 12 of NMOS device region 10B. This results in an imbalance between the electrical performance of PMOS device region 10A and NMOS device region 10B, thus affecting the performance of the semiconductor structure.

[0031] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent PMOS device regions and NMOS device regions, wherein a stacked structure material layer is formed on top of the substrate of the PMOS device regions and NMOS device regions; forming a protruding mask sidewall layer on top of the stacked structure material layer, wherein the width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region; using the mask sidewall layer as a mask, patterning the stacked structure material layer in the PMOS device regions and NMOS device regions to form a protruding stacked structure on top of the substrate, the stacked structure including one or more stacked channel stacks, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer.

[0032] This invention provides a method for forming a semiconductor structure. First, a protruding mask sidewall layer is formed on top of a multilayer material layer. The width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region. Then, during the patterning process of the multilayer material layer in the PMOS and NMOS device regions using the mask sidewall layer as a mask, the width of the mask sidewall layer in the PMOS device region is greater than that in the NMOS device region. This allows the width of the channel layer formed in the PMOS device region to be greater than that in the NMOS device region. Compared to a scheme where the width of the channel layer in the PMOS device region is the same as that in the NMOS device region, this invention, by setting the width of the channel layer in the PMOS device region to be greater than that in the NMOS device region, enables the carrier migration in the channel layer of the PMOS device region to be closer to that in the channel layer of the NMOS device region. This balances the electrical performance of the PMOS and NMOS device regions, thereby improving the performance of the semiconductor structure.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figure 2 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention.

[0035] The semiconductor structure includes: a substrate (not shown) comprising adjacent PMOS device regions 200A and NMOS device regions 200B; a channel structure layer 222 suspended on top of the substrate of the PMOS device regions 200A and NMOS device regions 200B, the channel structure layer 222 comprising one or more spaced-apart channel layers 2222, and the width of the channel layer 2222 in the PMOS device region 200A being greater than the width of the channel layer 2222 in the NMOS device region 200B; a device gate structure 250 located on top of the substrate and spanning the channel structure layer 222, the device gate structure 250 surrounding the channel layer 2222; source / drain doped layers (not shown) located in the channel structure layers 222 on both sides of the device gate structure 250; and an interlayer dielectric layer 231 located on top of the source / drain doped layers and covering the sidewalls of the device gate structure 250.

[0036] It should be noted that by setting the width of the channel layer 2222 in the PMOS device region 200A to be greater than the width of the channel layer 2222 in the NMOS device region 200B, the carrier migration in the channel layer 2222 of the PMOS device region 200A can be made closer to that in the channel layer 2222 of the NMOS device region 200B. This balances the electrical performance of the PMOS device region 200A and the NMOS device region 200B, thereby improving the performance of the semiconductor structure.

[0037] The substrate is used to provide a process platform for setting up gate-all-around (GAA) transistors.

[0038] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate 200 and a fin 280 protruding from the substrate 200.

[0039] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0040] The fin 280 exposes a portion of the substrate 200, thus providing a process basis for setting up the isolation layer.

[0041] In this embodiment, the fin 280 is made of the same material as the substrate 200, which is silicon. In other embodiments, the fin can also be made of semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from that of the substrate.

[0042] PMOS device area 200A is the area where PMOS transistors are set, and NMOS device area 200B is the area where NMOS transistors are set.

[0043] The channel structure layer 222 is used to provide a conductive channel for the transistor.

[0044] In this embodiment, the channel structure layer 222 includes a plurality of spaced-apart channel layers 2222, and the stacking direction of the plurality of stacked channel layers 2222 is perpendicular to the surface of the substrate 200. In this embodiment, the number of channel layers 2222 is two. In other embodiments, the number of channel layers may not be limited to two.

[0045] In this embodiment, the channel structure layer 222 is made of the same material as the fin 280, and the channel structure layer 222 is made of Si.

[0046] It should be noted that the width of the channel layer 2222 in the PMOS device region 200A is greater than the width of the channel layer 2222 in the NMOS device region 200B. This makes the carrier migration in the channel layer 2222 of the PMOS device region 200A and the carrier migration in the channel layer 2222 of the NMOS device region 200B similar, thus balancing the electrical performance of the PMOS device region 200A and the NMOS device region 200B, thereby improving the performance of the semiconductor structure.

[0047] It should also be noted that the width of the channel layer 2222 in PMOS device region 200A should not be too large or too small compared to the width of the channel layer 2222 in NMOS device region 200B. If the width of the channel layer 2222 in PMOS device region 200A is too large or too small compared to the width of the channel layer 2222 in NMOS device region 200B, an imbalance may occur between the carrier migration rates in the channel layer 2222 of PMOS device region 200A and the channel layer 2222 of NMOS device region 200B. This imbalance in electrical performance between PMOS device region 200A and NMOS device region 200B will affect the performance of the semiconductor structure. Therefore, in this embodiment, the width of the channel layer 2222 in PMOS device region 200A is greater than the width of the channel layer 2222 in NMOS device region 200B, and the width difference is between 0.5 nanometers and 10 nanometers.

[0048] The device gate structure 250 is used to control the opening and closing of the conductive channel when the device is working.

[0049] Specifically, the device gate structure 250 is a metal gate structure.

[0050] In this embodiment, the device gate structure 250 includes a gate dielectric layer (not shown) surrounding the channel layer 2222 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0051] Specifically, the gate dielectric layer includes gate oxide layers that conformally cover the top, sidewalls, and bottom of the conformally covered channel layer 2222, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0052] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0053] The gate electrode layer is used for subsequent electrical connection with external structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.

[0054] Source and drain doping layers are used to provide source and drain regions for semiconductor structures.

[0055] Among them, the PMOS device region 200A is used to set up P-type MOS transistors, the stress layer material is Si or SiGe, and the dopant ions in the source / drain doping layer 260 are P-type ions; the NMOS device region 200B is used to set up N-type MOS transistors, the stress layer material is Si or SiC, and the dopant ions in the source / drain doping layer 260 are N-type ions.

[0056] In this embodiment, along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure 250, the sidewall of the device gate structure 250 located directly below the channel layer 2222 is recessed inward relative to the sidewall of the channel layer 2222.

[0057] The sidewall of the device gate structure 250 directly below the channel layer 2222 is recessed inward relative to the sidewall of the channel layer 2222, which facilitates the setting of an inner wall layer directly below the channel layer 2222.

[0058] As an example, the semiconductor structure also includes an inner wall layer (not shown) located between the sidewall of the device gate structure 250 and the source / drain doped layers, directly below the channel layer 2222.

[0059] The inner wall layer, acting as an inner sidewall, increases the distance between the device gate structure 250 and the source / drain doped layer, which helps to reduce the parasitic capacitance between the device gate structure 250 and the source / drain doped layer.

[0060] In this embodiment, the material of the inner wall layer is silicon nitride.

[0061] In this embodiment, the semiconductor structure further includes an isolation layer (not shown) located on the substrate 200 exposed by the fin 280, and the isolation layer covers the sidewall of the fin 280.

[0062] The isolation layer is used to isolate adjacent fins 280.

[0063] In this embodiment, the material of the isolation layer is silicon oxide.

[0064] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 231, which is located on top of the source and drain doped layers and covers the sidewalls of the device gate structure 250.

[0065] Interlayer dielectric layer 231 is used to achieve electrical isolation between adjacent devices.

[0066] In this embodiment, the material of the interlayer dielectric layer 231 is silicon oxide.

[0067] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, wherein, Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step of an embodiment of the semiconductor structure formation method of the present invention.

[0068] refer to Figure 3 A substrate is provided, the substrate including adjacent PMOS device region 100A and NMOS device region 100B, and a stacked structure material layer 103 is formed on the top of the substrate of PMOS device region 100A and NMOS device region 100B.

[0069] The substrate provides a process platform for forming gate-all-around (GAA) transistors.

[0070] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate 100 and a fin 180 protruding from the substrate 100.

[0071] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0072] The fin 180 exposes a portion of the substrate 100, thus providing a process basis for the subsequent formation of the isolation layer.

[0073] In this embodiment, the fin 180 is made of the same material as the substrate 100, which is silicon. In other embodiments, the fin can also be made of semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from that of the substrate.

[0074] PMOS device region 100A is the region where PMOS transistors will be formed subsequently, and NMOS device region 100B is the region where NMOS transistors will be formed subsequently.

[0075] The laminated structure material layer 103 provides a material layer for the subsequent formation of a laminated structure that protrudes from the top of the substrate. Specifically, the subsequently formed laminated structure protrudes from the top of the fin 180.

[0076] In this embodiment, the stacked structure material layer 103 includes one or more stacked stacked material layers 102, each stacked material layer 102 including a sacrificial material layer 1001 and a channel material layer 1002 located on the sacrificial material layer 1001.

[0077] refer to Figures 4 to 8 A protruding mask sidewall layer 116 is formed on top of the stacked structure material layer 103, and the width of the mask sidewall layer 116 in the PMOS device region 100A is greater than the width of the mask sidewall in the NMOS device region 100B.

[0078] Specifically, the mask sidewall layer 116 serves as an etching mask for the subsequent patterning of the stacked structure material layer 103 to form the stacked structure. Since the width of the mask sidewall layer 116 in the PMOS device region 100A is greater than the width of the mask sidewall in the NMOS device region 100B, during the patterning process of the stacked structure material layer 103 in the PMOS device region 100A and NMOS device region 100B using the mask sidewall layer 116 as a mask, the width of the channel layer formed in the PMOS device region 100A can be greater than the width of the channel layer formed in the NMOS device region 100B. Compared to a scheme where the width of the channel layer in PMOS device region 100A is the same as the width of the channel layer in NMOS device region 100B, this embodiment enables the width of the channel layer in PMOS device region 100A to be greater than the width of the channel layer in NMOS device region 100B. This makes the carrier migration in the channel layer of PMOS device region 100A and the carrier migration in the channel layer of NMOS device region 100B similar, thereby balancing the electrical performance of PMOS device region 100A and NMOS device region 100B and improving the performance of the semiconductor structure.

[0079] It should be noted that, in the step of forming the mask sidewall layer 116, the width of the mask sidewall layer 116 in the PMOS device region 100A should not be too large or too small compared to the width of the mask sidewall in the NMOS device region 100B. If the width of the mask sidewall layer 116 in the PMOS device region 100A is too large or too small compared to the width of the mask sidewall in the NMOS device region 100B, it is easy to cause an imbalance between the carrier migration in the channel layer of the PMOS device region 100A and the carrier migration in the channel layer of the NMOS device region 100B. This will result in an imbalance between the electrical performance of the PMOS device region 100A and the NMOS device region 100B, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of forming the mask sidewall, the width of the mask sidewall layer 116 in the PMOS device region 100A is greater than the width of the mask sidewall in the NMOS device region 100B by 1 nanometer to 10 nanometers.

[0080] In this embodiment, the material of the mask sidewall layer 116 includes one or more of silicon nitride, silicon carbide, silicon oxide, and silicon oxynitride.

[0081] Specifically, silicon nitride, silicon carbide, silicon oxide, and silicon oxynitride have a high etching selectivity ratio with the materials selected for the subsequently formed stacked structure, thereby enabling the mask sidewall layer 116 to serve as an etching mask for the patterned stacked structure material layer 103 to form the stacked structure.

[0082] As an example, the mask sidewall layer 116 in the PMOS device region 100A includes a first mask sidewall layer 106 and a second mask sidewall layer 110 located on both sides of the first mask sidewall layer 106, and the mask sidewall layer 116 in the NMOS device region 100B includes the first mask sidewall layer 106.

[0083] Specifically, since the mask sidewall layer 116 in the PMOS device region 100A includes a first mask sidewall layer 106 and second mask sidewall layers 110 located on both sides of the first mask sidewall layer 106, and the mask sidewall layer 116 in the NMOS device region 100B includes the first mask sidewall layer 106, the width of the mask sidewall layer 116 in the PMOS device region 100A is greater than the width of the mask sidewall layer 116 in the NMOS device region 100B, which is the width of the second mask sidewall layers 110 on both sides of the first mask sidewall layer 106. Compared to the PMOS device region 100A and the NMOS device region 100B, this difference is significant. In this embodiment, the mask sidewall layers 116 in region 100B are all single-layer structures, and the mask sidewall layer 116 of PMOS device region 100A is larger than that of NMOS device region 100B. This embodiment is advantageous because by controlling the thickness of the second mask sidewall layer 110, the difference between the width of the mask sidewall layer 116 of PMOS device region 100A and the width of the mask sidewall layer 116 of NMOS device region 100B can be controlled. This facilitates the control of the electrical performance of PMOS device region 100A and NMOS device region 100B to achieve a balance, thereby improving the performance of the semiconductor structure.

[0084] It should be noted that the thickness of the second mask sidewall layer 110 should not be too large or too small. If the thickness of the second mask sidewall layer 110 is too large or too small, during the subsequent patterning process of the stacked structure material layer 103 in the PMOS device region 100A and NMOS device region 100B using the mask sidewall layer 116 as a mask to form the channel layer, the difference between the channel layer in the PMOS device region 100A and the channel layer in the NMOS device region 100B may become too large or too small. This can easily lead to an imbalance in the carrier migration in the channel layer of the PMOS device region 100A and the channel layer of the NMOS device region 100B, thereby causing the electrical performance of the PMOS device region 100A and the NMOS device region 100B to be unbalanced, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second mask sidewall layer 110 is 1 nanometer to 10 nanometers.

[0085] Reference Figures 4 to 8 The steps for forming a protruding mask sidewall layer 116 on top of the laminated structural material layer 103 are described in detail.

[0086] refer to Figure 4 A first mask sidewall layer 106 is formed on top of the stacked structure material layer 103 of the PMOS device region 100A and the NMOS device region 100B.

[0087] Specifically, the first mask sidewall layer 106 is used as an etching mask for the subsequent patterned stacked structure material layer 103. At the same time, by forming the first mask sidewall layer 106 first, it is beneficial to form the second mask sidewall layer 110 on the sidewall of the first mask sidewall layer 106.

[0088] In this embodiment, the step of forming the first mask sidewall layer 106 includes: forming a first mask sidewall material layer (not shown) on top of the stacked structure material layer 103 of the PMOS device region 100A and the NMOS device region 100B; and performing patterning processing on the first mask sidewall material layer to form a first mask sidewall layer 106 protruding from the top of the stacked structure material layer 103.

[0089] In this embodiment, the process for patterning the first mask sidewall material layer includes a dry etching process.

[0090] refer to Figure 5 A second mask sidewall material layer 190 is formed on the top of the substrate covering the top of the laminated structure material layer 103, and the top and sidewalls of the first mask sidewall layer 106.

[0091] Specifically, the second mask sidewall material layer 190 is used as a material layer for the subsequent formation of the second mask sidewall layer 110.

[0092] In this embodiment, the process for forming the second mask sidewall material layer 190 includes atomic layer deposition.

[0093] It should be noted that the atomic layer deposition process involves multiple atomic layer deposition cycles, resulting in high film thickness consistency. This improves the thickness uniformity of the second mask sidewall material layer 190, ensuring that the subsequently formed second mask sidewall layer 110 has a consistent thickness. Furthermore, the second mask sidewall material layer 190 can cover the top of the laminated structure material layer 103, as well as the top and sidewalls of the first mask sidewall layer 106. In other embodiments, chemical vapor deposition (CVD) can also be used to form the first protective layer.

[0094] refer to Figures 6 to 7 Remove the second mask sidewall material layer 190 from the NMOS device region 100B.

[0095] It should be noted that by removing the second mask sidewall material layer 190 of the NMOS device region 100B, the mask sidewall layer 116 in the NMOS device region 100B is reduced to only the first mask sidewall layer 106. Subsequently, after forming the second mask sidewall layer 110 in the PMOS device region 100A, the width of the mask sidewall layer 116 in the PMOS device region 100A can be greater than the width of the mask sidewall in the NMOS device region 100B.

[0096] As an example, the step of removing the second mask sidewall material layer 190 of the NMOS device region 100B includes: forming a mask layer 112 on top of the substrate of the PMOS device region 100A that covers the second mask sidewall material layer 190, with the mask layer 112 exposing the second mask sidewall material layer 190 of the NMOS device region 100B; and removing the second mask sidewall material layer 190 of the NMOS device region 100B exposed by the mask layer 112 by masking it.

[0097] Specifically, the mask layer 112 is used as an etching mask for removing the second mask sidewall material layer 190 of the NMOS device region 100B. At the same time, the mask layer 112 also protects the second mask sidewall material layer 190 in the PMOS device region 100A, reducing the probability of damage to the second mask sidewall material layer 190 in the PMOS device region 100A. This results in high sidewall surface quality of the second mask sidewall layer 110 subsequently formed on both sides of the first mask sidewall layer 106, and improves the formation quality of subsequent patterning processing using the mask sidewall layer 116 as a mask.

[0098] In this embodiment, the material of the mask layer 112 includes a photoresist layer.

[0099] It should be noted that in the step of removing the second mask sidewall material layer 190 of the NMOS device region 100B, the etching selectivity between the second mask sidewall material layer 190 and the first mask sidewall layer 106 should not be too small. If the etching selectivity between the second mask sidewall material layer 190 and the first mask sidewall layer 106 is too small, the etching rate of the second mask sidewall material layer 190 is likely to be close to that of the first mask sidewall layer 106. Consequently, during the removal of the second mask sidewall material layer 190 of the NMOS device region 100B, the probability of damage to the first mask sidewall layer 106 of the NMOS device region 100B increases. This means that the probability of the first mask sidewall layer 106 of the NMOS device region 100B collapsing increases significantly, making the first mask sidewall layer 106 of the NMOS device region 100B unusable as an etching mask for the subsequent patterned stacked structure material layer 103, thereby increasing the probability of semiconductor device failure. Therefore, in this embodiment, in the step of removing the second mask sidewall material layer 190 of the NMOS device region 100B, the etching selectivity ratio between the second mask sidewall material layer 190 and the first mask sidewall layer 106 is greater than 100:1.

[0100] As an example, the process for removing the second mask sidewall material layer 190 of the NMOS device region 100B includes a dry etching process.

[0101] Specifically, the dry etching process is a plasma dry etching process. By using plasma dry etching to remove the second mask sidewall material layer 190 of the NMOS device region 100B, the plasma undergoes physical and chemical reactions with the second mask sidewall material layer 190 of the NMOS device region 100B, thereby achieving the purpose of completely removing the second mask sidewall material layer 190 of the NMOS device region 100B. This reduces the probability of the second mask sidewall material layer 190 remaining in the NMOS device region 100B. In addition, by using plasma dry etching, a higher etching selectivity can be achieved, thereby reducing the probability of accidental etching of other film layers.

[0102] refer to Figure 8 After removing the second mask sidewall material layer 190 of the NMOS device region 100B, the second mask sidewall material layer 190 covering the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 of the PMOS device region 100A is removed. The remaining second mask sidewall material layer 190 located on the sidewall of the first mask sidewall layer 106 is used as the second mask sidewall layer 110. The first mask sidewall layer 106 and the second mask sidewall layer 110 in the PMOS device region 100A are used as the mask sidewall layer 116 in the PMOS device region 100A. The first mask sidewall layer 106 in the NMOS device region 100B is used as the mask sidewall layer 116 in the NMOS device region 100B.

[0103] Specifically, the second mask sidewall material layer 190 covering the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 of the PMOS device region 100A is removed, thereby enabling the formation of the second mask sidewall layer 110 on the sidewall of the first mask sidewall layer 106 of the PMOS device region 100A and exposing the top surface of the stacked structure material layer 103. This facilitates subsequent patterning of the stacked structure material layer 103 using the first mask sidewall layer 106 and the second mask sidewall layer 110.

[0104] It should be noted that in the step of removing the second mask sidewall material layer 190 covering the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 of the PMOS device region 100A, the etching selectivity between the second mask sidewall material layer 190 and the first mask sidewall layer 106 should not be too small. If the etching selectivity between the second mask sidewall material layer 190 and the first mask sidewall layer 106 is too small, the etching rate of the second mask sidewall material layer 190 is likely to be close to that of the first mask sidewall layer 106. Consequently, during the removal of the second mask sidewall material layer 190 from the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 of the PMOS device region 100A, the probability of damage to the first mask sidewall layer 106 of the PMOS device region 100A increases. This means that the probability of the first mask sidewall layer 106 of the PMOS device region 100A collapsing increases significantly, causing the first mask sidewall layer 106 of the PMOS device region 100A to be unusable as an etching mask for the subsequent patterned stacked structure material layer 103, thereby increasing the probability of semiconductor device failure. Therefore, in this embodiment, in the step of removing the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 covering the PMOS device region 100A, the etching selectivity ratio between the second mask sidewall material layer 190 and the first mask sidewall layer 106 is greater than 100:1.

[0105] As an example, the process of removing the second mask sidewall material layer 190 covering the top of the first mask sidewall layer 106 and the top of the stacked structure material layer 103 of the PMOS device region 100A includes an anisotropic dry etching process.

[0106] refer to Figure 9 Using the mask sidewall layer 116 as a mask, the stacked structure material layer 103 in the PMOS device region 100A and NMOS device region 100B is patterned to form a protruding stacked structure 121 on the top of the substrate. The stacked structure 121 includes one or more stacked channel stacks 122. Each channel stack 122 includes a sacrificial layer 1221 and a channel layer 1222 located on the sacrificial layer 1221.

[0107] Specifically, the stacked structure 121 provides a process basis for the subsequent formation of the channel layer 1222 with suspended space separation. At the same time, since the width of the mask sidewall layer 116 in the PMOS device region 100A is greater than the width of the mask sidewall in the NMOS device region 100B, the width of the channel layer 1222 formed in the PMOS device region 100A is greater than the width of the channel layer 1222 formed in the NMOS device region 100B. This makes the carrier migration in the channel layer 1222 of the PMOS device region 100A and the carrier migration in the channel layer 1222 of the NMOS device region 100B similar, so that the electrical performance of the PMOS device region 100A and the NMOS device region 100B are balanced, thereby improving the performance of the semiconductor structure.

[0108] As an example, the stacked structure 121 is located on top of the fin 180, and the extension direction of the stacked structure 121 is the same as the extension direction of the fin 180.

[0109] In this embodiment, there are multiple channel stacks 122, and the stacking direction of the multiple stacked channel stacks 122 is perpendicular to the surface of the substrate 100.

[0110] Each channel stack 122 includes a sacrificial layer 1221 and a channel layer 1222 located on the sacrificial layer 1221. The channel stack 122 provides a process basis for the subsequent formation of the channel layer 1222 with a spaced-out arrangement. Specifically, the sacrificial layer 1221 supports the channel layer 1222, thereby providing a process basis for the subsequent realization of the spaced-out arrangement of the channel layer 1222, and also occupying space for the formation of the gate structure of the subsequent device. The channel layer 1222 is used to provide a conductive channel that fully surrounds the gate transistor.

[0111] Correspondingly, when there are multiple trench stacks 122, there are also multiple trench layers 1222, and the multiple trench layers 1222 are arranged at intervals.

[0112] In this embodiment, taking the number of channel layers 1222 as an example, the multiple channel layers 1222 arranged at intervals constitute a channel structure layer. In other embodiments, the channel structure layer may also include only one channel layer.

[0113] In this embodiment, the channel layer 1222 is made of Si, and the sacrificial layer 1221 is made of SiGe. During the subsequent removal of the sacrificial layer, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 1221 to SiGe and the material of the channel layer 1222 to Si, the impact of the removal process of the sacrificial layer 1221 on the channel layer 1222 can be effectively reduced, thereby improving the quality of the channel layer 1222 and ultimately contributing to improved device performance.

[0114] In this embodiment, there are two channel stacks 122. In other embodiments, the number of channel stacks may be different.

[0115] In this embodiment, an isolation layer (not shown) is also formed on the substrate 100 on the side of the fin 180, and the isolation layer exposes the channel stack 122.

[0116] The isolation layer is used to isolate adjacent fins 180° apart.

[0117] In this embodiment, the material of the isolation layer is silicon oxide.

[0118] refer to Figure 10 Remove the mask sidewall layer 116 in PMOS device region 100A and NMOS device region 100B.

[0119] Specifically, removing the mask sidewall layer 116 in the PMOS device region 100A and the NMOS device region 100B exposes the top of the stacked structure 121 in the PMOS device region 100A and the NMOS device region 100B, which facilitates the subsequent formation of a gate structure spanning the stacked structure 121 on the top of the substrate.

[0120] As an example, the process for removing the mask sidewall layer 116 in the PMOS device region 100A and the NMOS device region 100B includes a wet etching process.

[0121] refer to Figure 11 A gate structure 130 is formed across the stacked structure 121 on the top of the substrate of the PMOS device region 100A and the NMOS device region 100B. The gate structure 130 covers part of the top and part of the sidewall of the stacked structure 121.

[0122] In this embodiment, the gate structure 130 is a dummy gate structure, occupying space for the subsequent formation of the device gate structure. In this embodiment, the gate structure 130 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

[0123] In this embodiment, the step of forming the gate structure 130 includes: forming a gate material layer (not shown) on the stacked structure 121; forming a gate mask layer (not shown) on the gate material layer; using the gate mask layer as a mask, removing the gate material layer exposed by the gate mask layer, and the remaining gate material layer located on the channel stack 122 as the gate structure 130.

[0124] The gate mask layer is used as an etching mask when forming the gate structure 130, and the gate mask layer can also protect the top of the gate structure 130 in subsequent processes.

[0125] In this embodiment, the material of the gate mask layer is silicon nitride.

[0126] Continue to refer to Figure 11 Source and drain doped layers are formed in the stacked structure 121 on both sides of the gate structure 130 (not shown).

[0127] Source and drain doping layers are used to provide source and drain regions for semiconductor structures.

[0128] In this embodiment, the step of forming the source / drain doped layer includes: forming a groove (not shown) in the stacked structure 121 on both sides of the gate structure 130, with the groove exposing the stacked structure 121; forming an epitaxial layer (not shown) in the groove, and doping the epitaxial layer with ions, using the epitaxial layer doped with ions as the source / drain doped layer.

[0129] It should be noted that after the groove is formed but before the epitaxial layer is formed in the groove, the process further includes: laterally etching a portion of the sacrificial layer 1221 exposed on the sidewall of the groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure 130 to form an opening (not shown). The opening is surrounded by the adjacent channel layer 1222 and the remaining sacrificial layer 1221, or the opening is surrounded by the fin 180, the channel layer 1222 adjacent to the fin 180, and the remaining sacrificial layer 1221; and forming an inner wall layer (not shown) in the opening.

[0130] Specifically, after the source / drain doped layer is formed and the device gate structure is formed at the location of the sacrificial layer 1221, the inner wall layer is located between the source / drain doped layer and the device gate structure. The inner wall layer can isolate the source / drain doped layer and the device gate structure, which helps to increase the distance between the source / drain doped layer and the device gate structure, and thus helps to reduce the parasitic capacitance between the source / drain doped layer and the device gate structure.

[0131] In this embodiment, the process of forming an opening in the exposed portion of the sacrificial layer 1221 on the sidewall of the transversely etched groove includes a wet etching process.

[0132] Wet etching is an isotropic etching process, which enables the sacrificial layer 1221 to be etched in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 130. Wet etching is also easy to achieve a large etching selectivity, which helps to reduce the difficulty of etching the sacrificial layer 1221 and reduce the probability of damage to other film structures.

[0133] In this embodiment, the sacrificial layer 1221 is made of SiGe, and the channel layer 1222 is made of Si. The exposed sacrificial layer 1221 is wet-etched using HCl vapor. The etching rate of HCl vapor on SiGe is much higher than that on Si. Therefore, using HCl vapor to etch part of the sacrificial layer 1221 on the side of the trench can effectively reduce the probability of damage to the channel layer 1222.

[0134] Continue to refer to Figure 11 An interlayer dielectric layer 131 is formed on top of the source and drain doped layers, and the interlayer dielectric layer 131 covers the sidewalls of the gate structure 130.

[0135] Interlayer dielectric layer 131 is used to achieve electrical isolation between adjacent devices.

[0136] In this embodiment, the material of the interlayer dielectric layer 131 is silicon oxide.

[0137] In this embodiment, the step of forming the interlayer dielectric layer 131 includes: forming a dielectric material layer (not shown) on the substrate of the sidewall of the gate structure 130, the dielectric material layer also covering the top of the gate structure 130; removing the dielectric material layer above the top of the gate structure 130, and the remaining dielectric material layer serving as the interlayer dielectric layer 131.

[0138] refer to Figure 12 Remove the gate structure 130 and form a gate opening 140 in the interlayer dielectric layer 131.

[0139] Specifically, the gate opening 140 provides a process window for the subsequent formation of the sacrificial layer 1221 and also provides a spatial location for the subsequent formation of the device gate structure.

[0140] In this embodiment, the process for removing the gate structure 130 includes a dry etching process.

[0141] In this embodiment, before removing the gate structure 130, the method for forming the semiconductor structure further includes removing the gate mask layer.

[0142] The gate mask layer is removed to expose the top of the gate structure 130, in preparation for the removal of the gate structure 130.

[0143] refer to Figure 13 After forming the gate opening 140, the sacrificial layer 1221 is removed, and a through trench 142 communicating with the gate opening 140 is formed below the channel layer 1222.

[0144] Specifically, the through slot 142 provides space for the subsequent formation of the device gate structure.

[0145] In this embodiment, a wet etching process is used to remove the sacrificial layer 1221. Specifically, the channel layer 1222 is made of Si, and the sacrificial layer 1221 is made of SiGe. Therefore, the sacrificial layer 1221 exposed by the gate opening 140 is removed by HCl vapor. The etching rate of the sacrificial layer 1221 by the wet etching process is much greater than the etching rate of the channel layer 1222 and the fin 180.

[0146] The sacrificial layer 1221 is removed after the source and drain doped layers are formed. Therefore, after the sacrificial layer 1221 is removed, the two ends of the channel layer 1222 are connected to the source and drain doped layers along the extension direction of the fin 180 and are suspended in the gate opening 140, thereby providing a basis for the subsequent device gate structure to surround the channel layer 1222.

[0147] After removing the sacrificial layer 1221, the channel layers 1222 are spaced apart, and the remaining channel layers 1222 constitute the channel structure layer. The channel structure layer is located on the fin 180 and spaced apart from the fin 180.

[0148] refer to Figure 14 A device gate structure 150 is formed in the gate opening 140 and the through trench 142, and the device gate structure 150 surrounds the channel layer 1222.

[0149] The device gate structure 150 is used to control the opening and closing of the conductive channel when the device is working.

[0150] Specifically, the device gate structure 150 is a metal gate structure.

[0151] In this embodiment, the device gate structure 150 includes a gate dielectric layer (not shown) surrounding the channel layer 1222 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0152] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers the top, sidewalls, and bottom of the channel layer 1222, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0153] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0154] The gate electrode layer is used for subsequent electrical connection with external structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.

[0155] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes adjacent PMOS device regions and NMOS device regions; A channel structure layer is suspended on top of the substrate of the PMOS device region and the NMOS device region. The channel structure layer includes one or more channel layers spaced apart, and the width of the channel layer in the PMOS device region is greater than the width of the channel layer in the NMOS device region, with a width difference of 0.5 nanometers to 10 nanometers. A device gate structure is located on top of the substrate and spans the channel structure layer, the device gate structure surrounding the channel layer; along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, the sidewall of the device gate structure located directly below the channel layer is recessed relative to the sidewall of the channel layer; The inner wall layer is located between the sidewall of the device gate structure and the source / drain doped layer, directly below the channel layer; The source and drain doped layers are located in the channel structure layers on both sides of the gate structure of the device; An interlayer dielectric layer is located on top of the source / drain doped layers and covers the sidewalls of the device gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The device gate structure includes: a gate dielectric layer surrounding the channel layer, and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

3. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including adjacent PMOS device regions and NMOS device regions, and a stacked material layer is formed on top of the substrate of the PMOS device regions and NMOS device regions; A protruding mask sidewall layer is formed on top of the stacked structure material layer, and the width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region. Using the mask sidewall layer as a mask, the stacked structure material layer in the PMOS device region and NMOS device region is patterned to form a protruding stacked structure on the top of the substrate. The stacked structure includes one or more stacked channel stacks, each of which includes a sacrificial layer and a channel layer located on the sacrificial layer. Remove the mask sidewall layers from the PMOS and NMOS device regions; A gate structure is formed on top of the substrate of the PMOS device region and the NMOS device region, spanning the stacked structure, and the gate structure covers part of the top and part of the sidewalls of the stacked structure. Source and drain doped layers are formed in the stacked structures on both sides of the gate structure; The step of forming the source / drain doped layer includes: forming a groove in the stacked structure on both sides of the gate structure, with the groove exposing the stacked structure; Along a direction parallel to the substrate and perpendicular to the extension direction of the gate structure, a portion of the sacrificial layer exposed on the sidewall of the trench is etched laterally to form an opening. The opening is surrounded by the adjacent channel layer and the remaining sacrificial layer, or the opening is surrounded by the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer; an inner wall layer is formed in the opening. An epitaxial layer is formed in the groove, and ions are doped in the epitaxial layer. The ion-doped epitaxial layer is used as the source and drain doping layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the mask sidewall layer, the mask sidewall layer in the PMOS device region includes a first mask sidewall layer and a second mask sidewall layer located on both sides of the first mask sidewall layer, and the mask sidewall layer in the NMOS device region includes the first mask sidewall layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The thickness of the second mask sidewall layer is 1 nanometer to 10 nanometers.

6. The method for forming a semiconductor structure as described in claim 3 or 4, characterized in that, The steps of forming the mask sidewall layer include: forming a protruding first mask sidewall layer on top of the stacked structure material layer of the PMOS device region and the NMOS device region; forming a second mask sidewall material layer on top of the substrate, covering the top of the stacked structure material layer, as well as the top and sidewalls of the first mask sidewall layer; removing the second mask sidewall material layer of the NMOS device region; after removing the second mask sidewall material layer of the NMOS device region, removing the second mask sidewall material layer covering the top of the first mask sidewall layer and the top of the stacked structure material layer of the PMOS device region, using the remaining second mask sidewall material layer located on the sidewall of the first mask sidewall layer as the second mask sidewall layer, using the first mask sidewall layer and the second mask sidewall layer in the PMOS device region as the mask sidewall layer in the PMOS device region, and using the first mask sidewall layer in the NMOS device region as the mask sidewall layer in the NMOS device region.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the mask sidewall layer, the material of the mask sidewall layer includes one or more of silicon nitride, silicon carbide, silicon oxide, and silicon oxynitride.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for forming the second mask sidewall material layer includes atomic layer deposition.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The step of removing the second mask sidewall material layer of the NMOS device region includes: forming a mask layer covering the second mask sidewall material layer on top of the substrate of the PMOS device region, the mask layer exposing the second mask sidewall material layer of the NMOS device region; and removing the second mask sidewall material layer of the NMOS device region exposed by the mask layer by masking it.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the second mask sidewall material layer of the NMOS device region includes a dry etching process.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of removing the second mask sidewall material layer covering the top of the first mask sidewall layer and the top of the stacked structure material layer of the PMOS device region, the etching selectivity ratio between the second mask sidewall material layer and the first mask sidewall layer is greater than 100:

1.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of removing the second mask sidewall material layer of the NMOS device region, the etching selectivity ratio between the second mask sidewall material layer and the first mask sidewall layer is greater than 100:

1.

13. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the mask sidewall, the width of the mask sidewall layer in the PMOS device region is greater than the width of the mask sidewall in the NMOS device region by 1 nanometer to 10 nanometers.

14. The method for forming a semiconductor structure as described in claim 3, characterized in that, After forming a raised stacked structure on top of the substrate, the method for forming the semiconductor structure further includes: An interlayer dielectric layer is formed on top of the source / drain doped layers, and the interlayer dielectric layer covers the sidewalls of the gate structure. Remove the gate structure and form a gate opening in the interlayer dielectric layer; Remove the sacrificial layer exposed by the gate opening, and form a through trench below the channel layer that communicates with the gate opening; A device gate structure is formed in the gate opening and the through-hole, the device gate structure surrounding the channel layer.

Images