A method for improving the optoelectronic performance of AlGaInP red Micro LED chips

Abstract

The present application discloses a method for improving the optoelectronic performance of AlGaInP red Micro LED chips, comprising the following steps: S1, substrate pretreatment and buffer layer growth; S2, etching barrier layer growth; S3, insulating film layer preparation and patterning; S4, growth of n-type GaN / InGaN ohmic contact layer; S5, growth of epitaxial wafer structure: sequentially grow multiple functional layers on the ohmic contact layer; S6, chip process treatment: perform a series of chip process treatments on the epitaxial wafer; The high doping concentration and low contact resistivity of n-type GaN (InGaN) in the present application reduce the series resistance of the chip by 30% - 50% compared with the traditional solution, and the power consumption decreases synchronously; Avoiding light absorption by GaAs material and light shielding by the metal layer, combined with the microlens array, the light output power is increased by more than 25%, and the light extraction efficiency (LEE) is increased by 30% - 50%; The low resistance reduces the Joule heat, the working temperature is reduced by 10 - 15 °C, alleviating the thermal-induced brightness attenuation and extending the device life.

Description

Technical Field

[0001] The present invention relates to the technical field of Micro LED chip preparation, and particularly relates to a method for improving the optoelectronic performance of AlGaInP red Micro LED chips through optimizing a novel ohmic contact layer material and an epitaxial process. Background Art

[0002] In microdisplay applications such as augmented reality (AR), AlGaInP red Micro LED chips have strict requirements for ohmic contact layer materials and device structures due to high brightness and low power consumption requirements; in traditional technologies, n-type GaAs or n-type AlGaInP materials are generally used for the ohmic contact layer, but there are some problems: for AlGaInP materials, it is difficult to achieve n-type doping. When the subsequent film layer is interconnected between pixels with an ITO film layer, it is necessary to add metal film layers such as Au and Ge to improve the optoelectronic performance of the chip, but the overall contact resistance is still relatively high; at the same time, as an ohmic contact layer, n-type GaAs material has absorption for red light compared with AlGaInP material, which is not conducive to chip light emission. In addition, in order to further improve the contact characteristics between this film layer and ITO, it is also necessary to add metal film layers such as Au and Ge, and there is still a problem of light shielding, but the overall ohmic contact performance is better than that of n-type AlGaInP materials.

[0003] Compared with n-type ohmic contact layer materials such as GaAs (1.42 eV) and AlGaInP (1.9 - 2.3 eV), the bandgap of GaN material is about 3.4 eV, with extremely low absorption rate for red light, and it is easy to achieve n-type doping. The Hall test electron concentration is about 5.0×10 18 -2.0×10 19 cm -3 , which is better than the electron concentration of GaAs and AlGaInP materials (2.0×10 18 -3.0×10 18 cm -3 ). After the same ITO deposition, the ohmic contact performance has an advantage. Even when using metals such as Au and Ge, the specific contact resistivity after annealing is about 1×10 -5 -1×10 -3 , much higher than the specific contact resistivity between GaN and ITO (1×10 -5 -1×10 -7 , without a metal intermediate layer). In theory, the series resistance can be significantly reduced and light shielding can be avoided; however, the lattice mismatch between n-type GaN (InGaN) and AlGaInP materials is large, and direct growth will introduce a large number of defects, resulting in a decrease in light emission efficiency. Therefore, it is necessary to solve the interface matching problem through process innovation. Summary of the Invention

[0004] The object of the present invention is to provide a method for improving the optoelectronic performance of AlGaInP red Micro LED chips, which solves the lattice mismatch problem through the insulating film layer patterning technology, reduces the series resistance, reduces the light absorption of the material and the metal light shielding, and improves the optoelectronic performance of the chips.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A method for improving the optoelectronic performance of AlGaInP red Micro LED chips, comprising the following steps:

[0007] S1, Substrate pretreatment and buffer layer growth: Select an n-type doped GaAs substrate, clean it, and then use an MOCVD system to epitaxially grow an n-type GaAs buffer layer on the substrate, controlling the doping concentration, thickness, and growth temperature of the buffer layer within a specific range;

[0008] S2, Etch stop layer growth: At a specific temperature, epitaxially grow an n-type (Al x Ga 1-x ) y InP etch stop layer on the above buffer layer, and determine the value ranges of x and y and the thickness range of the etch stop layer;

[0009] S3, Insulating film layer preparation and patterning: Take out the substrate with the etch stop layer from the reaction chamber, clean and dry it, and then use a PECVD device to grow an insulating film layer on the etch stop layer; Through the processes of spin coating, exposure, development, and etching, form a patterned mask and multiple through holes on the insulating film layer;

[0010] S4, n-type GaN / InGaN ohmic contact layer growth: Remove the photoresist and clean the substrate, put it into the MOCVD reaction chamber, and epitaxially grow an n-type GaN or n-type InGaN ohmic contact layer at a certain temperature; After the growth is completed, use a specific etching or corrosion method to remove the insulating film layer and the excess GaN / InGaN film layer, so that the ohmic contact layer remains only in the through hole area;

[0011] S5, Epitaxial wafer structure growth: Epitaxially grow multiple functional layers on the ohmic contact layer in sequence, including an n-type AlInP confinement layer, an n-type superlattice structure, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure, a p-type graded layer, and a heavily doped layer, and precisely control the growth temperature, thickness, doping concentration, or doping source of each layer;

[0012] S6, Chip Process: Perform a series of chip processes on the epitaxial wafer, including depositing a P-ITO film layer on the p side and annealing, evaporating a bonding metal layer and bonding it with the Si-based CMOS driving IC; removing the GaAs substrate and the n-type GaAs buffer layer, and etching to open windows; wet etching to expose the ohmic contact layer and depositing a hard mask; lithography and etching to form a mesa structure and repair the sidewalls; depositing a sidewall passivation layer and achieving electrical insulation between pixels through IBE etching; depositing an N-ITO film layer and etching to open holes, achieving n-type interconnection and removing the N-ITO film layer in the non-display area, evaporating a metal layer to form a metal electrode; using a PECVD device to deposit or a film layer, and forming a microlens array through spin coating, exposure, development, hot plate reflow, and ICP etching to enhance the light collection effect of the chip.

[0013] In a preferred embodiment, in step S1, the doping concentration of the n-type GaAs buffer layer is 2.0×10 18 -3.0×10 18 cm -3 , the thickness is 100 - 300 nm, and the growth temperature is 620 - 700 °C.

[0014] In a preferred embodiment, in step S2, in the n-type (Al x Ga 1-x ) y InP etch stop layer, x is 0.1 - 0.2, y is 0.5, and its thickness is 100 - 300 nm.

[0015] In a preferred embodiment, in step S3, the insulating film layer grown by the PECVD device is or , its thickness is 10 - 40 nm; the aperture of the through hole is 1 - 50 μm, and the center spacing between adjacent through holes is 2 - 75 μm.

[0016] In a preferred embodiment, in step S4, an n-type GaN or n-type InGaN ohmic contact layer with a thickness of 10 - 40 nm is epitaxially grown at 700 - 950 °C; the doping source of the ohmic contact layer is silane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 .

[0017] In a preferred embodiment, in step S5, a multi-layer undoped (Al x Ga 1-x ) y InP graded layer is grown between the undoped spacer layer and the n-type superlattice structure, x gradually changes from 0.8 - 0.9 to 0.6 - 0.8, y = 0.5, and the thickness of each layer is 2.5 - 25 nm.

[0018] Preferably, in step S6, the annealing temperature of the P-ITO film layer is 350-600 °C, and the bonding metal layer includes one or more of Cr, Ti, Pt, Au, Sn, Al, Ag, Ni.

[0019] Preferably, in step S6, the etching process of the mesa structure is carried out using an ICP etching device, and the etching gas used includes and ; in the sidewall repair process, 、 、Ar, one or more of these gases are used.

[0020] Preferably, in step S6, the material of the sidewall passivation layer is 、 or ; the objects of IBE etching include the sidewall passivation layer, the P-ITO film layer, and the bonding metal layer.

[0021] Preferably, in step S6, the thickness of the N-ITO film layer for n-type interconnection is 200-400 nm; the evaporation of the metal layer is deposited by sputtering, electron beam evaporation, or RPD process, and the thickness of each layer of the metal electrode is 10-800 nm.

[0022] Due to the application of the above technical solutions, the beneficial effects of this application compared with the prior art are as follows:

[0023] A method for improving the optoelectronic performance of AlGaInP red micro-LED chips provided by this application, with a high doping concentration and low contact resistivity of n-type GaN (InGaN), reduces the series resistance of the chip by 30%-50% compared with the traditional solution, and the power consumption decreases synchronously; it avoids light absorption by GaAs materials and light shielding by the metal layer, combines with a microlens array, the light output power is increased by more than 25%, and the light extraction efficiency (LEE) is increased by 30%-50%; the low resistance reduces Joule heat, the working temperature is reduced by 10-15 °C, alleviates the thermal-induced brightness attenuation, and extends the device life. Description of the Drawings

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1Flow chart of a method for improving the optoelectronic performance of AlGaInP red Micro LED chips according to the present invention;

[0026] Figure 2 Schematic processing diagrams of steps S1 - S3 in the method of Example 1 of the present invention;

[0027] Figure 3 Schematic processing diagram of step S4 in the method of Example 1 of the present invention;

[0028] Figures 4 - 8 Schematic processing diagram of step S5 in the method of Example 1 of the present invention;

[0029] Figures 9 - 18 Schematic processing diagram of step S6 in the method of Example 1 of the present invention;

[0030] Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type (Al x Ga 1-x ) y InP etching stop layer; 4. or Insulating film layer; 5. Epitaxial wafer; 6. n-type GaN / InGaN ohmic contact layer; 7. n-type AlInP confinement layer; 8. n-type superlattice structure; 9. Undoped (Al x Ga 1-x ) y InP spacer layer; 10. Undoped (Al x Ga 1-x ) y InP graded layer; 11. InGaP / (Al x Ga 1-x ) y InP undoped quantum well structure; 12. p-type (Al x Ga 1-x ) y InP spacer layer; 13. p-type AlInP or (Al x Ga 1-x ) y InP confinement layer; 14. p-type superlattice structure; 15. p-type graded layer; 16. Heavily doped layer; 17. Si-based CMOS; 18. Bonding metal layer; 19. P-ITO film layer; 20. Hard mask; 21. Sidewall passivation layer; 22. N-ITO film layer; 23. Metal electrode; 24. Microlens array. Detailed implementation manners

[0031] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the protection scope of this application.

[0032] It should be noted that the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of this application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] In this application, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit that the indicated devices, elements or components must have a specific orientation, or be constructed and operated in a specific orientation.

[0034] Moreover, in addition to being able to represent an orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0035] In addition, the terms "install", "set", "provided with", "connect", "connected", "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0037] Embodiment 1

[0038] Please refer to Figures 1 - 18 , the present application provides a method for improving the optoelectronic performance of AlGaInP red Micro LED chips, including the following steps:

[0039] S1, Substrate pretreatment and buffer layer growth: Provide an n-type doped GaAs substrate 1 (wafer size 2 - 12 inches, thickness 350 - 650 μm, single-side polished / double-side polished). After cleaning the substrate with acetone, IPA, and deionized water, use an MOCVD system to epitaxially grow an n-type GaAs buffer layer 2 on the GaAs substrate 1. The doping source is disilane, and the doping concentration of the n-type GaAs buffer layer 2 is 2.0×10 18 -3.0×10 18 cm -3 , with a thickness of 100 - 300 nm and a growth temperature of 620 - 700 °C;

[0040] S2, Etch stop layer growth: At 700 - 780 °C, epitaxially grow an n-type (Al x Ga 1-x ) y InP etch stop layer 3 on the n-type GaAs buffer layer 2, where x is 0.1 - 0.2 and y is 0.5. The thickness of the etch stop layer is 100 - 300 nm; Utilize its high etch rate selectivity to provide an accurate etch boundary for the subsequent patterning process;

[0041] S3, Insulating film layer preparation and patterning: Take out the substrate with the etch stop layer grown from the reaction chamber, clean and dry it, and then use a PECVD device to grow an insulating film layer 4 with a thickness of 10 - 40 nm on the etch stop layer; or Form a patterned mask on the insulating film layer through photoresist coating, exposure, and development processes, and use ICP etching to form multiple through-holes on the insulating film layer, with a pore diameter of 1 - 50 μm and a center-to-center spacing of adjacent through-holes of 2 - 75 μm; This structure isolates the non-growth area and confines the growth of n-type GaN (InGaN) only within the through-holes, reducing defects caused by lattice mismatch;

[0042] S4, Growth of n-type GaN / InGaN ohmic contact layer 6: After removing the photoresist and cleaning, the substrate is placed in the MOCVD reaction chamber, and a 10 - 40 nm thick n-type GaN or n-type InGaN ohmic contact layer is epitaxially grown at 700 - 950 °C. The doping source is silane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 ; After growth, the insulating film layer and the excess GaN / InGaN film layer are removed by wet etching with BOE or dry etching with ICP, so that the ohmic contact layer remains only in the via region; Ensure that the top of the subsequent mesa structure is directly interconnected with the N-ITO film layer 22;

[0043] S5, Growth of subsequent epitaxial wafer 5 structure: Multiple functional layers are epitaxially grown in sequence on the ohmic contact layer, including:

[0044] n-type AlInP confinement layer 7: A 200 - 400 nm thick n-type AlInP confinement layer 7 is grown at 700 - 780 °C, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 , Conducting electrons and confining carriers;

[0045] n-type superlattice structure 8: Grow 5 - 10 periods of n-type (Al x1 Ga 1-x1 ) y1 InP / (Al x2 Ga 1-x2 ) y2 InP superlattice structure, where x1 is 0.1 - 0.2, y1 = 0.5, x2 is 0.8 - 0.9, y2 = 0.5, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 ; Adjust the energy band structure and optimize electron transport;

[0046] Undoped spacer layer: Grow a 40 - 80 nm thick undoped (Al x Ga 1-x ) y InP spacer layer 9, where x is 0.6 - 0.8 and y = 0.5. A multi-layer undoped (Al x Ga 1-x ) y InP graded layer 10 is grown between the undoped spacer layer and the n-type superlattice structure 8, with x gradually changing from 0.8 - 0.9 to 0.6 - 0.8 and y = 0.5, and the thickness of each layer is 2.5 - 25 nm; Relieve interface stress and reduce carrier scattering;

[0047] Quantum well structure: Grow an undoped InGaP / (Al x Ga 1-x ) y InP quantum well structure 11 at 710 - 790 °C for 1 - 5 cycles, where x is 0.7 - 0.8, y = 0.5, the thickness of InGaP is 2 - 4 nm, and the thickness of (Al x Ga 1-x ) y InP is 5 - 8 nm; realize red light emission (wavelength 620 - 660 nm) through quantum confinement effect;

[0048] p - type spacer layer: Grow a 40 - 80 nm p - type (Al x Ga 1-x ) y InP spacer layer 12 at 700 - 780 °C, where x is 0.8 - 0.9, y = 0.5, and the doping source is , with a doping concentration of 1.0×10 18 -3.0×10 18 cm -3 ;

[0049] p - type confinement layer: Grow a 10 - 20 nm p - type AlInP or (Al x Ga 1-x ) y InP confinement layer 13 at the same temperature, where x is 0.9 - 0.95, y = 0.5, and the doping source is , with a doping concentration of 1.0×10 18 -3.0×10 18 cm -3 ;

[0050] p - type superlattice structure 14: Grow 5 - 10 cycles of p - type (Al x1 Ga 1-x1 ) y1 InP / (Al x2 Ga 1-x2 ) y2 InP superlattice structure at the same temperature, where x1 is 0.1 - 0.2, y1 = 0.5, x2 is 0.8 - 0.9, y2 = 0.5, the thickness of each layer is 2.5 - 25 nm, and the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ;

[0051] p - type graded layer 15 and heavily doped layer 16: Grow 20 - 60 nm of p - type (Al x1 Ga 1-x1 ) y1InP graded layer (x1 is 0.8 - 0.9, y1 = 0.5), 10 - 20 nm p-type (Al x2 Ga 1-x2 ) y2 InP graded layer (x2 gradually changes from 0.8 - 0.9 to 0.2 - 0.3, y2 = 0.5), 10 - 20 nm p-type (Al x3 Ga 1-x3 ) y3 InP graded layer (x3 gradually changes from 0.2 - 0.3 to 0.01, y3 = 0.5), and the doping concentrations of all three layers are 1.0×10 18 -3.0×10 18 cm -3 ; At 720 - 800 °C, 20 - 60 nm of p-type GaP-1 and 80 - 120 nm of p-type GaP-2 are grown in sequence. The doping source is , and the doping concentration is 2.0×10 18 -4.0×10 18 cm -3 ; At 520 - 560 °C, 10 - 30 nm of p-type GaP-3 is grown. The doping source is C, and the doping concentration is 1.0×10 19 -3.0×10 19 cm -3 ; A hole transport channel is formed, and finally the p-side contact resistance is reduced through the heavily doped layer 16 of p-type GaP-3;

[0052] S6, Chip process treatment: A series of chip process treatments are performed on the epitaxial wafer 5, including the following treatments:

[0053] P-ITO film layer 19 deposition and bonding: On the p-side, a 1000 - 3000 Å P-ITO film layer 19 is deposited by electron beam evaporation, sputtering or RPD process, and annealed in or oxygen atmosphere; Subsequently, a bonding metal layer 18 is evaporated, with each layer of metal having a thickness of 10 - 500 Å, and the epitaxial wafer 5 is bonded to the Si-based CMOS17 drive IC at 260 - 300 °C and a pressure of 50 - 100 KN;

[0054] Substrate removal and etching window opening: Use and solutions to remove the GaAs substrate 1 and the n-type GaAs buffer layer 2. Through photoresist coating, exposure, development, and ICP / IBE etching, the alignment mark window and the pixel window are opened in sequence until the Si-based CMOS surface is exposed;

[0055] Wet etching and hard mask deposition: Through wet etching with HCl and solution, the n-type GaN / InGaN ohmic contact layer is exposed; Deposit 200 - 800 nm of Hard mask 20;

[0056] Mesa structure preparation: A mesa structure with a diameter of 1 - 50 μm and a pixel pitch of 2 - 75 μm is formed through photolithography and etching processes. The etching process is carried out using an ICP etching device, and the etching gases used include and ; An ALE device is used to repair the etched mesa sidewalls damaged; In the ALE device repair process, , Ar, one or more of the gases are used;

[0057] Sidewall passivation and insulation isolation: Deposit a 10 - 100 nm thick , or sidewall passivation layer 21 through an ALD device, and achieve electrical insulation between pixels through IBE etching; The objects of IBE etching include sidewall passivation layer 21, P - ITO film layer 19, and bonding metal layer 18;

[0058] n - type interconnection and electrode preparation: Deposit a 150 - 250 nm thick or insulating film layer, etch an opening to expose the n - type ohmic contact layer, deposit an N - ITO film layer 22 to achieve n - type interconnection, the thickness of the N - ITO film layer 22 is 200 - 400 nm, and remove the N - ITO film layer 22 in the non - display area; Evaporate the metal layer through a device, deposit it through sputtering, electron beam evaporation, or RPD process to form a metal electrode 23, and the thickness of each layer of the metal electrode 23 is 10 - 800 nm;

[0059] Micro - lens array 24 preparation process: Deposit a 1 - 3.5 μm thick or film layer using a PECVD device, and form a micro - lens array 24 through spin - coating, exposure, development, hot plate reflow, and ICP etching to enhance the light - collecting effect of the chip, and the light - collecting effect increases the light - emitting efficiency by 20% - 30%.

[0060] Example 2

[0061] Preparation of an epitaxial wafer based on a 4 - inch GaAs substrate, including the following steps:

[0062] S1, Substrate pretreatment and buffer layer growth: Select a 4 - inch n - type GaAs substrate (thickness 650 μm, double - polished surface), ultrasonically clean it with acetone, isopropyl alcohol (IPA), and deionized water for 10 minutes in sequence, and dry it with nitrogen.

[0063] In the MOCVD reaction chamber, using disilane as the doping source (flow rate 50 sccm), a 200-nm n-type GaAs buffer layer was grown at 680 °C, with a doping concentration of 2.8×10 18 cm -3 , and the growth rate was 1.5 μm / h.

[0064] S2, growth of the etch stop layer:

[0065] The temperature was raised to 750 °C, and trimethylaluminum (TMA), trimethylgallium (TMG), and phosphine ( ) were introduced to grow an n-type etch stop layer with a thickness of 200 nm and a doping concentration of 2.5×10 18 cm -3 (disilane flow rate 30 sccm).

[0066] S3, preparation and patterning of the insulating film layer:

[0067] The substrate was taken out, cleaned with acetone, and then in a PECVD device, using silane ( ) and nitrous oxide ( ) as raw materials, a 20-nm insulating film layer was deposited at a deposition temperature of 300 °C and a pressure of 100 Pa.

[0068] Photoresist (AZ5214E) was coated, with an exposure wavelength of 365 nm. After development, a circular mask with a pore diameter of 15 μm and a center spacing of 30 μm was formed. Using ICP etching (gas: / Ar = 5 / 10 sccm, power 100 W), vias were formed in the film layer, and the etching rate was 50 nm / min.

[0069] S4, growth of the n-type InGaN ohmic contact layer:

[0070] After removing the photoresist and cleaning, the substrate was placed in the MOCVD reaction chamber, and trimethylgallium (TMG), trimethylindium (TMI), and ammonia ( ) were introduced. Using silane (flow rate 80 sccm) as the doping source, a 25-nm n-type InGaN layer (In composition 10%) was grown at 850 °C, with a doping concentration of 1.8×10 19 cm -3 .

[0071] The film layer was removed by wet etching with a BOE solution (HF: = 1:6), and then by ICP dry etching (gas: / Remove the InGaN layer in the non-through-hole region (flow rate of 15 / 5 sccm), and retain the ohmic contact layer in the through-hole.

[0072] S5, subsequent growth of the epitaxial structure:

[0073] n-type AlInP confinement layer: grown at 750 °C for 300 nm, doping concentration 1.2×10 18 cm -3 (flow rate of disilane 20 sccm).

[0074] n-type superlattice structure: grown for 8 periods / , each layer with a thickness of 10 nm, doping concentration 1.5×10 18 cm -3 .

[0075] Undoped spacer layer and graded layer: grow a 60-nm spacer layer, and grow 3 graded layers (x from 0.85 → 0.75 → 0.7) below it, each layer with a thickness of 5 nm.

[0076] Quantum well structure: grow 3 periods of InGaP / quantum well at 750 °C, InGaP thickness 3 nm, barrier layer thickness 6 nm.

[0077] p-type layer stack: grow p-type spacer layer (60 nm, doping concentration 2.0×10 18 cm -3 ), p-type AlInP confinement layer (15 nm, doping concentration 2.5×10 18 cm -3 ), p-type superlattice (6 periods, each layer with a thickness of 15 nm), three graded layers (x from 0.9 → 0.3 → 0.05) and p-type GaP heavily doped layer (GaP - 3 layers with a thickness of 20 nm, doping concentration 2.0×10 19 cm -3 , doping source is carbonane).

[0078] Example 3

[0079] Micro LED chip preparation and performance testing:

[0080] S6, chip process treatment: perform the following treatments on the epitaxial wafer in sequence:

[0081] ITO film layer and bonding:

[0082] Deposit a 2000 Å ITO film layer (In:Sn = 9:1) on the p side by sputtering process, anneal it in an O2 atmosphere at 500 °C for 5 minutes, and the sheet resistance ≤ 10 Ω / □. (The sheet resistance, with the unit of ohm per square (Ω / □), refers to the resistance value of the material per unit thickness and per unit area.)

[0083] Evaporate bonding metal layers such as Cr / Au (Cr thickness 50 Å, Au thickness 200 Å, etc.), and thermocompression bond the epitaxial wafer and the Si-based CMOS driving IC at 280 °C and 80 KN pressure.

[0084] Substrate removal and etching window opening:

[0085] Etch the GaAs substrate with a solution of volume ratio 7:1 and at an etching rate of 5 - 7 μm / min until the n-type GaAs buffer layer is exposed.

[0086] Open the alignment mark window through ICP etching (gas: / = 10 / 15 sccm), and then remove the p-side ITO and bonding metal by IBE etching (Ar gas, power 200 W) to expose the Si-based CMOS mark.

[0087] Mesa structure preparation and passivation:

[0088] Wet-etch with a solution of HCl: = 2:1 to expose the n-type InGaN contact layer, and then deposit a 500 nm hard mask by PECVD.

[0089] Lithographically define the mesa pattern (diameter 30 μm, pixel pitch 50 μm), and form the mesa structure through ICP etching ( / = 15 / 10 sccm) at an etching rate of 200 nm / min; use the ALE technique (gas: / Ar = 8 / 12 sccm) to repair the sidewall damage and remove the 20 nm etching damage layer.

[0090] Deposit a 50 nm sidewall passivation layer by ALD, and then use IBE etching (gas: Ar / = 20 / 5 sccm) to achieve insulation between pixels, etching to the bonding metal layer.

[0091] n-type interconnection and microlens preparation:

[0092] Deposit a 200 nm The film layer is etched to open holes to expose the n-type InGaN ohmic contact layer. A 300-nm ITO film layer is deposited by the RPD process to achieve n-type interconnection, and the sheet resistance is ≤15 Ω / square (the sheet resistance, with the unit of ohm per square (Ω / square), refers to the resistance value of the material per unit thickness and per unit area).

[0093] Evaporate a Cr / Pt / Au metal layer (Cr 30 Å, Pt 500 Å, Au 7000 Å) to form a metal electrode.

[0094] Finally, deposit a 2-μm film layer by PECVD, and form a microlens array through photolithography, hot plate reflow (temperature 160 °C) and ICP etching ( / = 20 / 10 sccm), and the light concentration efficiency is increased by 25%.

[0095] Performance test:

[0096] Series resistance: At a current density of 20 mA / cm², the series resistance of the chip in this embodiment is measured to be 7.5 , which is 37.5% lower than that of the traditional n-type GaAs solution (12 ).

[0097] Luminous efficiency: At a wavelength of 630 nm, the light output power is 15 μW (current 10 μA), and the luminous efficiency reaches 30 lm / W, which is 36% higher than that of the traditional solution (22 lm / W).

[0098] Operating temperature: After continuous operation for 30 minutes, the chip junction temperature is 65 °C, which is 15 °C lower than that of the traditional solution (80 °C).

[0099] Comparative example: A traditional n-type GaAs ohmic contact layer chip;

[0100] 1. Key difference steps:

[0101] 1.1 In step S4, n-type GaAs is used as the ohmic contact layer (thickness 30 nm, doping concentration 2.5×10 18 cm -3 ), and the insulating film layer patterning process is not used and it is directly grown on the etching barrier layer.

[0102] 1.2 The microlens array is not prepared.

[0103] 2. Performance comparison:

[0104] 2.1 Series resistance: 12 (higher than 7.5 of Example 3 ).

[0105] 2.2 Luminous efficiency: 22 lm / W (lower than 30 lm / W in Example 3), mainly due to the absorption of red light by the GaAs material and the light shielding of the metal interconnection layer.

[0106] 2.3 Operating temperature: 80 °C (higher than 65 °C in Example 3), and the thermal effect results in a brightness attenuation rate of 15% (8% in Example 3).

[0107] The above embodiments strictly follow the technical solutions of this application. The lattice mismatch problem is solved by the n-type InGaN ohmic contact layer + patterned growth of the insulating film, and the light extraction efficiency is improved by combining with the microlens array, finally achieving a reduction in the series resistance of the chip, an increase in luminous efficiency, and an optimization of thermal stability. The data of the embodiments show that all performance indicators of the present invention are significantly better than the traditional solutions, verifying the feasibility and innovation of the technical solutions.

[0108] A method for improving the optoelectronic performance of an AlGaInP red Micro LED chip provided by this application, with a high doping concentration and low contact resistivity of n-type GaN (InGaN), reduces the series resistance of the chip by 30% - 50% compared to the traditional solution, and the power consumption decreases synchronously; it avoids the light absorption of the GaAs material and the light shielding of the metal layer, combines with the microlens array, the light output power increases by more than 25%, and the light extraction efficiency (LEE) increases by 30% - 50%; the low resistance reduces Joule heat, the operating temperature decreases by 10 - 15 °C, alleviates the brightness attenuation caused by heat, and extends the device life.

[0109] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for improving the optoelectronic performance of AlGaInP red Micro LED chips, characterized in that, It includes the following steps: S1, Substrate pretreatment and buffer layer growth: Select an n-type doped GaAs substrate. After cleaning it, use an MOCVD system to epitaxially grow an n-type GaAs buffer layer on the substrate, and control the doping concentration, thickness, and growth temperature of this buffer layer within a specific range; S2, Etch stop layer growth: At a specific temperature, an n-type (Al x Ga 1-x ) y InP etch stop layer is epitaxially grown on the above buffer layer to determine the value ranges of x and y and the thickness range of the etch stop layer; S3, Insulating film layer preparation and patterning: Take out the substrate with an etching stop layer from the reaction chamber. After cleaning and drying, use a PECVD device to grow an insulating film layer on the etching stop layer; Through processes such as spin coating, exposure, development, and etching, form a patterned mask and multiple through holes on the insulating film layer; S4, Growth of n-type GaN / InGaN ohmic contact layer: Remove the photoresist and clean the substrate, then put it into the MOCVD reaction chamber to epitaxially grow an n-type GaN or n-type InGaN ohmic contact layer at a certain temperature; After growth, use a specific etching or corrosion method to remove the insulating film layer and the excess GaN / InGaN film layer, so that the ohmic contact layer remains only in the through hole area; S5, Growth of epitaxial wafer structure: Epitaxially grow multiple functional layers in sequence on the ohmic contact layer, including an n-type AlInP confinement layer, an n-type superlattice structure, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure, a p-type graded layer, and a heavily doped layer, and precisely control the growth temperature, thickness, doping concentration, or doping source of each layer; S6, Chip process treatment: Perform a series of chip process treatments on the epitaxial wafer, including depositing a P-ITO film layer on the p side and annealing it, and bonding with a Si-based CMOS driving IC after evaporating a bonding metal layer; Remove the GaAs substrate and the n-type GaAs buffer layer, etch and open windows; Wet-etch to expose the ohmic contact layer and deposit a hard mask; Lithography and etching are performed to form a mesa structure and repair the sidewalls; Deposit a sidewall passivation layer and achieve electrical insulation between pixels through IBE etching; Deposit an N-ITO film layer, etch and open holes, achieve n-type interconnection and remove the N-ITO film layer in the non-display area, evaporate a metal layer to form a metal electrode; Use a PECVD device to deposit or a film layer, and form a microlens array through spin coating, exposure, development, hot plate reflow, and ICP etching to enhance the light collection effect of the chip.

2. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S1, the doping concentration of the n-type GaAs buffer layer is 2.0×10 18 -3.0×10 18 cm -3 , the thickness is 100 - 300 nm, and the growth temperature is 620 - 700 °C.

3. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S2, in the n-type (Al x Ga 1-x ) y InP etching stop layer, x is 0.1 - 0.2, y is 0.5, and its thickness is 100 - 300 nm.

4. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S3, the insulating film layer grown by the PECVD device is or , and its thickness is 10 - 40 nm; the aperture of the through hole is 1 - 50 μm, and the center-to-center spacing of adjacent through holes is 2 - 75 μm.

5. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S4, an n-type GaN or n-type InGaN ohmic contact layer with a thickness of 10 - 40 nm is epitaxially grown at 700 - 950 °C; the doping source of the ohmic contact layer is silane, and the doping concentration is 5.0×10 18 - 2.0×10 19 cm -3 .

6. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, characterized in that In step S5, a multi-layer non-doped (Al x Ga 1-x ) y InP graded layer is grown between the non-doped spacer layer and the n-type superlattice structure, where x gradually changes from 0.8 - 0.9 to 0.6 - 0.8, y = 0.5, and the thickness of each layer is 2.5 - 25 nm.

7. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S6, the annealing temperature of the P-ITO film layer is 350 - 600 °C, and the bonding metal layer includes one or more of Cr, Ti, Pt, Au, Sn, Al, Ag, Ni.

8. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, characterized in that, In step S6, the etching process of the mesa structure is carried out using an ICP etching device, and the etching gases used include and ; in the sidewall repair process, one or more of the gases , Ar, are used.

9. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S6, the sidewall passivation layer is made of , or ; The objects of IBE etching include the sidewall passivation layer, the P-ITO film layer, and the bonding metal layer.

10. The method for improving the optoelectronic performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S6, the thickness of the n-type interconnecting N-ITO film layer is 200 - 400 nm; The evaporation of the metal layer is deposited by sputtering, electron beam evaporation, or RPD process, and the thickness of each layer of the metal electrode is 10 - 800 nm.

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