Multi-valued transistor
By modifying the self-assembled single molecule layer at the PN junction interface and regulating the carrier transmission path, the stable, continuously adjustable intermediate state of multi-value transistors is achieved, and the problem of relying on special materials or processes in the prior art is solved, and it is universal and efficient.
Patent Information
- Application Number
- CN202510302429.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-06-10
AI Technical Summary
The implementation of existing multi-value logic transistors mostly relies on the material's own characteristics or special process processes, and lacks universal and efficient implementation methods.
By modifying the self-assembled single molecule layer at the interface of the P-type organic semiconductor layer and the N-type inorganic semiconductor layer in the PN junction region, the transmission path and accumulated number of carriers in the conductive channel are regulated, thereby achieving a stable, continuously adjustable intermediate state.
A multi-value transistor that does not depend on special material properties or process processes is realized, which is highly universal, and the off-state current can be controlled through the source and drain voltage to form a stable intermediate state.
Smart Images
Figure CN120129401A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of transistors, and in particular to a multi-value transistor. Background Art
[0002] Over the past few decades, the development of integrated circuits has been following Moore's Law, which states that when the price remains unchanged, the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 months, and the performance will also double. However, as the size of transistors approaches the physical limit, new technologies are urgently needed to maintain the development of Moore's Law.
[0003] Multi-valued logic transistors are a potential alternative technology. Traditional transistor circuits have two states: on and off. Translated into binary language, they are 0 and 1, expressing only two pieces of information. Multi-valued logic transistors, on the other hand, have at least one intermediate state between on and off, which means that multi-valued logic transistors can be realized, increasing the amount of information expressed by transistors and significantly reducing the number of transistors and interconnection lines per unit area, thereby achieving higher information density and lower power consumption.
[0004] At present, the realization of multi-valued logic transistors mostly depends on the material's own properties (such as negative differential resistance, negative differential transconductance, etc.) or requires special process technology (such as doping, superlattice, electronic filtering structure, etc.). How to rely on commonly used technical principles to realize multi-valued logic transistors is the key and difficult problem in the current development of multi-valued logic transistors. Summary of the invention
[0005] The invention provides a multi-value transistor, which adjusts the carrier distribution in the conductive channel by self-assembling single molecules, thereby realizing a stable and continuously adjustable intermediate state in the transistor.
[0006] In order to achieve the above application purpose, the technical solution adopted in this application is as follows:
[0007] The invention provides a multi-value transistor, which comprises a source, a drain, a gate and a PN junction region, wherein the PN junction region comprises from top to bottom a P-type organic semiconductor layer, a self-assembled monomolecular layer, an N-type inorganic semiconductor layer and a gate insulating layer.
[0008] By modifying a self-assembled monolayer at the interface of the P-type organic semiconductor layer and the N-type inorganic semiconductor layer in the PN junction region, the transmission path and accumulation number of carriers in the conductive channel of the transistor can be selectively regulated. Therefore, the off-state current of the transistor can be regulated by the source-drain voltage, thereby achieving a stable, continuously adjustable intermediate state in the transistor.
[0009] The present invention provides a novel multi-value transistor.
[0010] Furthermore, the insulating layer material is an oxide insulating material.
[0011] Furthermore, the N-type inorganic semiconductor is one or more of a metal oxide semiconductor and a two-dimensional material.
[0012] Furthermore, the self-assembled monolayer is an organic small molecule material with O=P-OH, O=C-OH, O=S-OH, O=Si-OH functional groups at one end, which can bond with metal oxides to form a self-assembled monolayer.
[0013] Furthermore, the P-type organic semiconductor is one or more of small molecule or polymer semiconductors.
[0014] The beneficial effects of the present invention are:
[0015] The present invention provides a novel multi-value transistor which is independent of special material properties or special process and has strong universality; a stable and continuously adjustable intermediate state can be realized in the transistor through source-drain voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a schematic diagram of the transistor structure provided in an embodiment of the present application.
[0017] Figure 2 It is a transfer characteristic curve diagram of the transistor provided in Example 1 of the present application.
[0018] Figure 3 This is a transfer characteristic curve diagram of the transistor provided in Example 2 of the present application.
[0019] Figure 4 This is a transfer characteristic curve diagram of the transistor provided in Example 3 of the present application.
[0020] Figure 5 This is a transfer characteristic curve diagram of the transistor provided in Example 4 of the present application.
[0021] Figure 6 This is a test of the transfer characteristic curves of the devices of Example 1 and Comparative Example 1. DETAILED DESCRIPTION
[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0023] In this application, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In this application, "at least one" refers to one or more, and "more than one" refers to two or more.
[0024] It should be noted that when an element is referred to as being "provided on" another element, it may be directly on the other element or indirectly on the other element. The terms "thickness", "upper", "lower", "vertical", "horizontal", "top", "bottom" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.
[0025] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.
[0026] An embodiment of the present invention provides a multi-value transistor, the structure of which is as follows Figure 1 As shown, it includes: a source, a drain, a gate and a PN junction region, and the PN junction region includes a P-type organic semiconductor layer, a self-assembled monolayer, an N-type inorganic semiconductor layer and a gate insulating layer from top to bottom, wherein the gate is on one side of the PN junction region and the source and drain are on the other side.
[0027] The N-type and P-type semiconductor layer materials of the PN junction region in the present invention can be semiconductor materials in the prior art, the P-type material is preferably one or more of organic small molecule semiconductors or organic polymer semiconductor materials, and the N-type material is one or more of metal oxides or two-dimensional materials. The transfer and output characteristic curves are important bases for judging semiconductor materials, and the injection and transmission of carriers in the conductive channel of the transistor can be regulated by the gate voltage or the source-drain voltage.
[0028] The material of the P-type organic semiconductor layer in the present invention is preferably an organic small molecule semiconductor, specifically at least one of 2,6-diphenylanthracene, pentacene, 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, with a thickness of 1-50 nm.
[0029] The material of the N-type inorganic semiconductor layer in the present invention is preferably a metal oxide semiconductor, specifically at least one or more of zinc oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, etc., with a thickness of 1-200 nm.
[0030] The self-assembled monolayer in the present invention is preferably an organic small molecule, specifically one or more of (4-(3,6-dimethyl-9H-carbazole-9-yl)butyl)phosphonic acid (Me-4PACz), (2-(9H-carbazole-9-yl)ethyl)phosphonic acid (2PACz), (4-(9H-carbazole-9-yl)butyl)phosphonic acid (4PACz), octadecyltrimethoxysilane (OTMS), and octadecyltrichlorosilane (OTS), with a thickness of about 1 nm.
[0031] The gate insulating layer material in the present invention is preferably an oxide insulating material, specifically at least one or more of silicon dioxide, zirconium oxide, aluminum oxide, hafnium oxide, etc., with a thickness of 10-500 nm.
[0032] The gate material in the present invention is preferably a highly conductive material, which can be silicon or common metal electrodes (gold, silver, copper, aluminum, etc.), or ITO, graphene, carbon nanotubes, poly(3,4-ethylenedioxythiophene): poly(styrene sulfonic acid) (PEDOT:PSS), etc., with a thickness of 10nm-10um.
[0033] The following describes it in conjunction with specific embodiments.
[0034] Example 1
[0035] In this embodiment, if Figure 1 As shown, a multi-value transistor includes, from bottom to top, a substrate, a gate, a gate insulating layer, an N-type inorganic semiconductor layer, a self-assembled monolayer, a P-type organic semiconductor layer, a source electrode and a drain electrode.
[0036] Gate: material is Si, thickness is 200um;
[0037] Gate insulation layer: material is SiO 2 , thickness is 300nm;
[0038] N-type inorganic semiconductor layer: material is InZnO, thickness is 30nm;
[0039] Self-assembled monolayer: the material is [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphoric acid, the thickness is 1nm;
[0040] P-type organic semiconductor layer: the material is 2,6-diphenylanthracene, the thickness is 50nm;
[0041] Source: material is Au, thickness is 100nm;
[0042] Drain: Material is Au, thickness is 100nm.
[0043] The transfer characteristic curve of the multi-value transistor in this embodiment is as follows: Figure 2 As shown, by adjusting the source-drain voltage, the off-state current of the device changes significantly, forming a stable and adjustable intermediate state.
[0044] Example 2
[0045] In this embodiment, a multi-value transistor includes, from bottom to top, a substrate, a gate, a gate insulating layer, an N-type inorganic semiconductor layer, a self-assembled monolayer, a P-type organic semiconductor layer, a source electrode, and a drain electrode.
[0046] Gate: material is Si, thickness is 200um;
[0047] Gate insulation layer: material is SiO 2 , thickness is 300nm;
[0048] N-type inorganic semiconductor layer: material is In 2 O 3 , thickness is 30nm;
[0049] Self-assembled monolayer: the material is [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphoric acid, the thickness is 1nm;
[0050] P-type organic semiconductor layer: the material is 2,6-diphenylanthracene, the thickness is 50nm;
[0051] Source: material is Au, thickness is 100nm;
[0052] Drain: Material is Au, thickness is 100nm.
[0053] The transfer characteristic curve of the multi-value transistor in this embodiment is as follows: Figure 3 As shown, by adjusting the source-drain voltage, the off-state current of the device changes significantly, forming a stable and adjustable intermediate state.
[0054] Embodiment 3:
[0055] In this embodiment, a multi-value transistor includes, from bottom to top, a substrate, a gate, a gate insulating layer, an N-type inorganic semiconductor layer, a self-assembled monolayer, a P-type organic semiconductor layer, a source electrode, and a drain electrode.
[0056] Gate: material is Si, thickness is 200um;
[0057] Gate insulation layer: material is SiO 2 , thickness is 300nm;
[0058] N-type inorganic semiconductor layer: material is In 2 O 3 , thickness is 30nm;
[0059] Self-assembled monolayer: the material is (2-(9H-carbazol-9-yl)ethyl)phosphonic acid, with a thickness of about 1 nm;
[0060] P-type organic semiconductor layer: the material is 2,6-diphenylanthracene, the thickness is 50nm;
[0061] Source: material is Au, thickness is 100nm;
[0062] Drain: Material is Au, thickness is 100nm.
[0063] The transfer characteristic curve of the multi-value transistor in this embodiment is as follows: Figure 4 As shown, by adjusting the source-drain voltage, the off-state current of the device changes significantly, forming a stable and adjustable intermediate state.
[0064] Example 4
[0065] In this embodiment, a multi-value transistor includes, from bottom to top, a substrate, a gate, a gate insulating layer, an N-type inorganic semiconductor layer, a self-assembled monolayer, a P-type organic semiconductor layer, a source electrode, and a drain electrode.
[0066] Gate: material is Si, thickness is 200um;
[0067] Gate insulation layer: material is SiO 2 , thickness is 300nm;
[0068] N-type inorganic semiconductor layer: material is In 2 O 3 , thickness is 30nm;
[0069] Self-assembled monolayer: the material is [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphoric acid, the thickness is 1nm;
[0070] P-type organic semiconductor layer: the material is 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, with a thickness of 50nm;
[0071] Source: material is Au, thickness is 100nm;
[0072] Drain: Material is Au, thickness is 100nm.
[0073] The transfer characteristic curve of the multi-value transistor in this embodiment is as follows: Figure 5 As shown, by adjusting the source-drain voltage, the off-state current of the device changes significantly, forming a stable and adjustable intermediate state.
[0074] Comparative Example 1
[0075] A PN junction transistor comprises, from bottom to top, a substrate, a gate, a PN junction region, a P-type organic semiconductor layer, a source electrode and a drain electrode.
[0076] Among them, the PN junction region is composed of a gate insulating layer, a gate N-type inorganic semiconductor and a P-type organic semiconductor from bottom to top, and there is no self-assembled monolayer;
[0077] The other layers are the same as those in Example 1.
[0078] Performance Testing
[0079] The transfer characteristic curves of the devices of Example 1 and Comparative Example 1 were tested, and the results are as follows: Figure 6 As shown, for devices without a self-assembled monolayer, the off-state current cannot be controlled and an intermediate state cannot be formed.
[0080] The above results prove that the multi-value transistor of the embodiment of the present application can control the off-state current of the transistor by adjusting the source-drain voltage, thereby realizing a stable, continuously adjustable intermediate state in the transistor.
[0081] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A multi-value transistor, characterized in that: By regulating the carrier distribution in the conductive channel through self-assembled single molecules, a stable and continuously adjustable intermediate state can be achieved in the transistor; The transistor comprises: a source electrode, a drain electrode, a gate electrode and a PN junction region, wherein the PN junction region comprises, from top to bottom, a P-type organic semiconductor layer, a self-assembled monomolecular layer, an N-type inorganic semiconductor layer and a gate insulating layer, and a gate electrode is on one side of the PN junction region and a source electrode and a drain electrode are on the other side.
2. A multi-value transistor according to claim 1, characterized in that: By modifying a self-assembled monolayer at the interface of the P-type organic semiconductor layer and the N-type inorganic semiconductor layer in the PN junction region, the transmission path and accumulation number of carriers in the conductive channel of the transistor can be selectively regulated, thereby enabling the off-state current of the transistor to be regulated by the source-drain voltage.
3. A multi-value transistor according to claim 1, characterized in that: The insulating layer material is an oxide insulating material.
4. A multi-value transistor according to claim 1, characterized in that: The N-type inorganic semiconductor is one or more of a metal oxide semiconductor and a two-dimensional material.
5. A multi-value transistor according to claim 4, characterized in that: The N-type inorganic semiconductor is at least one or more of zinc oxide, indium oxide, indium zinc oxide, and indium gallium zinc oxide, with a thickness of 1-200 nm.
6. A multi-value transistor according to claim 1 or 2, characterized in that: The self-assembled monolayer is an organic small molecule material with O=P-OH, O=C-OH, O=S-OH, O=Si-OH functional groups at one end, which can bond with metal oxides to form a self-assembled monolayer.
7. A multi-value transistor according to claim 6, characterized in that: The self-assembled monolayer is one or more of (4-(3,6-dimethyl-9H-carbazole-9-yl)butyl)phosphonic acid (Me-4PACz), (2-(9H-carbazole-9-yl)ethyl)phosphonic acid (2PACz), (4-(9H-carbazole-9-yl)butyl)phosphonic acid (4PACz), octadecyltrimethoxysilane (OTMS), and octadecyltrichlorosilane (OTS), and has a thickness of about 1 nm.
8. A multi-value transistor according to claim 1, characterized in that: The P-type organic semiconductor is one or more of a small molecule semiconductor or an organic polymer semiconductor.
9. A multi-value transistor according to claim 8, characterized in that: The P-type organic semiconductor is at least one of 2,6-diphenylanthracene, pentacene, 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, and has a thickness of 1-50 nm.
10. The multi-value transistor according to claim 1, characterized in that: The gate insulating layer material is an oxide insulating material, including at least one or more of silicon dioxide, zirconium oxide, aluminum oxide, and hafnium oxide, with a thickness of 10-500 nm.