Information processing apparatus and information processing method

Abstract

An information processing device (1) is provided with: an acquisition unit (11) that acquires a netlist of circuits; and a processing unit (12) that extracts a component name list and a wiring name list from the netlist, creates a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, creates a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and stores the component name list and the wiring name list. The component names corresponding to the wiring names in the updated wiring name list are extracted from the component names in the updated component name list, a combination list including the extracted component names is created, and the updated component name list and the combination list are output.

Description

Technical Field

[0001] The present disclosure relates to an information processing apparatus and an information processing method. Background Art

[0002] Circuit diagram data representing a circuit designed using CAD (Computer-Aided Design) is data including component information related to components and connection information related to wirings between components. For example, the following technique is described in Patent Document 1: Circuit diagram data of a circuit having a similar structure is retrieved from a database in which circuit diagram data is registered, using a circuit matrix that represents a circuit using a matrix.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-128383 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] A graph network representing a circuit using nodes and edges is created using list information extracted from a netlist of the circuit. The list information is information related to components and wirings included in the circuit, and has a component name list and a wiring name list. Component names of components included in the circuit are set in the component name list. Wiring names of wirings connecting components are set in the wiring name list.

[0008] The wirings in which wiring names are set in the wiring name list include ground wirings, input wirings, and output wirings in the circuit. On the other hand, only component names of circuit components having structural features are set in the component name list, and elements representing ground, input, and output that do not have structural features are not included. Therefore, the existing list information needs to define each type of ground, multiple inputs, and multiple outputs using wirings.

[0009] On the other hand, in the existing list information, in the case where a circuit has an inherent ground or inherent inputs and outputs, if no special mechanism is provided for each circuit, the ground or inputs and outputs cannot be distinguished as different circuit information. For example, in the input of a circuit component, power supply to the circuit component is included, and in addition, input of an external signal is included. Thus, the input of a circuit component is diverse, and when defined only using wiring names, the two are confused. Therefore, after converting a circuit into a graph network, it is difficult to separate the two only using the graph network.

[0010] In order to separate the above two, it is necessary to determine the number of components or the order of recording for the graph network, etc., and it can only be used when the number of input terminals is predetermined. If the above determination is not made and the graph network is created using list information with inappropriate definitions of grounding, input and output in circuit components, information degradation may occur in the graph network. When information degradation occurs, it may be impossible to restore the original circuit diagram from the graph network.

[0011] However, in the prior art described in Patent Document 1, when a circuit matrix is ​​created using list information with inappropriate definitions of ground, input, and output, it is foreseeable that information degradation will occur in the circuit matrix as described above. In this case, even if the circuit matrix is ​​used, circuit diagram data of similar circuits may not be accurately retrieved.

[0012] The present disclosure solves the above-mentioned problems, and an object of the present disclosure is to obtain an information processing device and an information processing method that can provide list information capable of suppressing information degradation caused by converting a circuit into a graph network.

[0013] Means for solving problems

[0014] The information processing device disclosed in the present invention comprises: an acquisition unit, which acquires a netlist of a circuit; and a processing unit, which extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names representing ground terminals, input terminals, and output terminals, creates an updated wiring name list by removing wiring names representing ground wiring, input wiring, and output wiring, extracts component names corresponding to wiring names in the updated wiring name list from component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and the combination list.

[0015] Effects of the Invention

[0016] According to the present disclosure, a component name list and a wiring name list are extracted from a netlist of a circuit, a component name list is updated by adding component names representing ground terminals, input terminals, and output terminals, a wiring name list is updated by removing wiring names representing ground wiring, input wiring, and output wiring, component names corresponding to wiring names in the updated wiring name list are extracted from component names in the updated component name list, a combination list containing the extracted component names is created, and an updated component name list and a combination list are output. Thus, the information processing device of the present disclosure outputs list information that defines ground, input, and output in a circuit as circuit components, and thus, list information that can suppress information degradation caused by converting a circuit into a graph network can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [Figure 1 ] is a block diagram showing a structural example of an information processing device according to embodiment 1.

[0018] [ Figure 2 ] is a schematic diagram showing example (1) of the circuit and graph network in implementation mode 1.

[0019] [ Figure 3 ] is a schematic diagram showing example (2) of the circuit and graph network in implementation mode 1.

[0020] [ Figure 4 ] Figure 4 A and Figure 4 B is a block diagram showing a hardware configuration that realizes the functions of the information processing device of Embodiment 1.

[0021] [ Figure 5 ] is a flowchart showing the information processing method of implementation mode 1.

[0022] [ Figure 6 ] is a circuit diagram showing example (1) of the circuit.

[0023] [ Figure 7 ] is a circuit diagram showing example (2) of the circuit.

[0024] [ Figure 8 ] is a circuit diagram showing example (3) of the circuit.

[0025] [ Figure 9 ] is a schematic diagram showing a graph network in which nodes are connected by edges.

[0026] [ Figure 10 ] is a schematic diagram showing a graph network in which nodes are connected via wiring nodes.

[0027] [ Figure 11 ] is a flowchart showing the data input processing (1) for the graph network in implementation mode 1.

[0028] [ Figure 12 ] is a flowchart showing the data input processing (2) for the graph network in implementation mode 1.

[0029] [ Figure 13 ] is a flowchart showing the data input processing (3) for the graph network in implementation mode 1.

[0030] [ Figure 14 ] is a graph showing example (1) of the calculation results of the inference accuracy of the information processing device based on implementation example 1.

[0031] [ Figure 15 ] is a graph showing example (2) of the calculation results of the inference accuracy of the information processing device based on implementation example 1.

[0032] [ Figure 16 ] is a block diagram showing a structural example of an information processing device according to embodiment 2.

[0033] [ Figure 17 ] is a flowchart showing the information processing method of implementation mode 2.

[0034] [ Figure 18 ] is a circuit diagram showing example (4) of the circuit.

[0035] [ Figure 19 ] is a circuit diagram showing example (5) of the circuit.

[0036] [ Figure 20 ] is a schematic diagram showing example (1) of a circuit and graph network in Implementation Example 2.

[0037] [ Figure 21 ] is a schematic diagram showing example (2) of the circuit and graph network in Implementation Example 2.

[0038] [ Figure 22 ] is a schematic diagram showing example (3) of the circuit and graph network in Implementation Example 2.

[0039] [ Figure 23 ] is a graph showing an example of calculation results of the inference accuracy of the information processing device based on embodiment 2. DETAILED DESCRIPTION

[0040] Implementation Method 1

[0041] Figure 1 1 is a block diagram showing a configuration example of the information processing device 1 according to the first embodiment. Figure 1 In the invention, the information processing device 1 obtains a netlist of the circuit and uses the obtained netlist to provide list information that can suppress information degradation in the graph network of the circuit. The graph network of the circuit is information that represents the circuit using nodes representing components and edges representing wiring. The graph network also includes information representing feature quantities of nodes and feature quantities of edges.

[0042] In the production of a circuit, a circuit diagram of the circuit is designed using a circuit design CAD, information representing the circuit diagram is handed over to a substrate design CAD, and a substrate circuit pattern is designed using the substrate design CAD. The information representing the circuit diagram handed over from the circuit design CAD to the substrate design CAD is a netlist of the circuit. For example, the information processing device 1 obtains a netlist from the circuit design CAD, and outputs the netlist containing list information produced using the obtained netlist to a computer equipped with the substrate design CAD. In the computer, the substrate design CAD is used to design a substrate circuit pattern related to the circuit diagram shown in the input netlist.

[0043] The circuit diagram shown in the netlist contains information representing passive components, active components, I / O components and wiring in the circuit. Passive components are, for example, coils, capacitors, resistors or diodes. Active components are, for example, power supplies, processors, memories or FPGAs (Field Programmable Gate Arrays). I / O components include, for example, substrate connectors, power connectors and communication connectors. Wiring is used to connect the above components.

[0044] The circuit diagram shows a circuit that operates when power is supplied from the outside or when a control signal such as Ethernet (registered trademark) is input or an analog signal obtained from a sensor is input, so the power source itself is not included in the circuit diagram. The power source is a battery or a commercial power source.

[0045] In addition, in the following, it is assumed that at least the ground wiring, the input wiring, and the output wiring are connected to one or more circuit components in the circuit diagram. In addition, the circuit diagram shown in the netlist does not necessarily have to be a circuit diagram for performing an operation, but may also be a circuit diagram in the middle of the design, or may also be a circuit diagram of only a circuit portion that realizes a part of the function of the overall circuit.

[0046] In the netlist, there are dozens of known representation methods such as TELESIS form, PADS form or SCICARDS form, but any form contains information representing the components contained in the circuit and the wiring connecting the components. Generally speaking, the circuit diagram contains ground wiring, input wiring and output wiring. However, in the circuit diagram that processes electromagnetic waves or heat that are input or output without wiring, sometimes there is no input wiring or output wiring. In addition, in the case where electromagnetic waves or heat are converted into electrical signals and electrical signals are converted into electromagnetic waves or heat, the circuit diagram contains input wiring that propagates the electrical signals converted from electromagnetic waves or heat, and contains output signals that propagate the electrical signals to be converted into electromagnetic waves or heat. Information related to such wiring is also contained in the netlist.

[0047] In addition, the netlist includes a component name list and a wiring name list. All component names in the netlist are set in the component name list. All wiring names in the netlist are set in the wiring name list. The wiring name list also sets wiring names representing ground wiring, input wiring, and output wiring in the circuit. However, the component name list does not set information representing ground, input, and output. Only circuit components with structural characteristics such as semiconductor elements (hereinafter simply referred to as semiconductors) or capacitors are set. Therefore, when there are multiple grounds, inputs, and outputs in the circuit, they cannot be distinguished from the component name list.

[0048] In this case, in the wiring name list, the ground wiring, input wiring, and output wiring need to be further classified and defined according to the types of ground, input, and output. For example, when a component has multiple grounds, inputs, and outputs, it is necessary to define multiple wirings classified according to the types of ground, input, and output between components connected to the component, and the wiring name list becomes complicated. When the circuit is converted into a graph network using the list information including the complicated wiring name list, the possibility of causing information degradation in the graph network becomes high.

[0049] In contrast, the information processing device 1 adds component names representing ground terminals, input terminals, and output terminals to the component name list, and removes wiring names representing ground wiring, input wiring, and output wiring from the wiring name list. Then, the information processing device 1 extracts component names corresponding to wiring names in the wiring name list from the component names in the component name list, creates a combination list containing the extracted component names, and outputs list information containing the component name list and the combination list. Thus, in the information processing device 1, even if there are multiple groundings, inputs, and outputs in the circuit, they can be defined as individual components. Therefore, the list information will not be complicated as in the case of defining multiple wirings, and list information that can suppress information degradation in the circuit diagram network can be provided.

[0050] like Figure 1 As shown, the information processing device 1 includes an acquisition unit 11 and a processing unit 12 .

[0051] The acquisition unit 11 executes a first process of acquiring a netlist of a circuit. For example, the information processing device 1 is connected to a computer equipped with a circuit design CAD, and the acquisition unit 11 acquires a netlist created using the circuit design CAD from the computer.

[0052] Alternatively, the acquisition unit 11 may acquire a circuit diagram model of a circuit operating in a circuit simulator, and convert a circuit diagram represented by the circuit diagram model into a netlist.

[0053] That is, the acquisition of the netlist by the acquisition unit 11 also includes converting the circuit diagram to acquire the netlist.

[0054] The processing unit 12 extracts the component name list and the wiring name list from the netlist, creates an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, creates an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and the combination list. In addition, the processing unit 12 outputs the updated component name list and the combination list in which the component names are replaced with the unique identification numbers common to each feature of the component.

[0055] Specifically, the processing unit 12 executes the second process to the sixth process.

[0056] The second process is a process of extracting a component name list and a wiring name list from the net list acquired by the acquisition unit 11 .

[0057] The third process is a process of adding component names indicating a ground terminal, an input terminal, and an output terminal to the component name list.

[0058] The fourth process is a process of removing wiring names indicating ground wiring, input wiring, and output wiring from the wiring name list.

[0059] The fifth step is a process of extracting component names corresponding to wiring names in the wiring name list implemented in the fourth step from the component names in the component name list implemented in the third step, and creating a combination list including the extracted component names.

[0060] The sixth process is the following processing: using the inherent identification number common to each feature of the component, the component names in the component name list implemented in the third process and the component names in the combination list obtained in the fifth process are replaced, and the list information containing the component name list and the combination list in which the component names are replaced by the identification number is output.

[0061] Figure 2 is a schematic diagram showing example (1) of a circuit and a graph network, Figure 2 The left figure shows an example of a circuit, and the upper and lower figures on the right show a network diagram of the circuit on the left. Figure 2 The circuit shown is a circuit having a power supply V, a semiconductor X, an inductor L, a capacitor C, and a resistor R. In this circuit, the power supply V, one terminal of the semiconductor X, the capacitor C, and the resistor R are connected to the ground GND.

[0062] The power source V itself is not included in the circuit diagram of the circuit that operates by the power supplied (input) from the power source V. Therefore, in the net list representing the circuit diagram, the input terminal for supplying power from the power source is not set as a circuit component. In addition, in the list of component names included in the net list, circuit components such as semiconductor X, inductor L, capacitor C, and resistor R having functional structures are set, but the power source input or ground GND having no functional structure is not set.

[0063] When using a component name list without setting power input and ground GND, the graph network on the lower right side is created. The graph network on the lower right side has nodes for semiconductor X, inductor L, capacitor C, and resistor R, but does not have a node for power input from power supply V and a node for ground GND. In the graph network on the lower right side, the power input from power supply V and ground GND are defined as wiring.

[0064] For example, in the circuit on the left, power is supplied (input) from the power supply V to one terminal of the semiconductor X. Therefore, in the graph network on the lower right side, the wiring of the thick line connected to the node of the semiconductor X is the input wiring related to the power input from the power supply V.

[0065] Furthermore, in the circuit on the left side, the semiconductor X, the capacitor C, and the resistor R are respectively connected to the ground GND.

[0066] For example, as indicated by the white line, the ground GND is defined as a ground wiring between the semiconductor X and the capacitor C, a ground wiring between the semiconductor X and the resistor R, and a ground wiring between the capacitor C and the resistor R. That is, when the power supply input and the ground GND are not set in the component name list, four types of wiring representing the power supply input from the power supply V and the ground GND are defined in the net list.

[0067] After converting the netlist of the circuit into a graph network, when the converted graph network is inversely converted into a netlist, if the original circuit can be determined using the inversely converted netlist, it is determined that the graph network has no information degradation.

[0068] Generally speaking, there is no reversibility between the conversion from a netlist to a graph network and the reverse conversion from a graph network to a netlist, and the reversely converted netlist may not become a netlist that can be calculated by a circuit simulator.

[0069] Therefore, it is assumed that the reverse conversion from the graph network to the netlist is not performed, and the graph network is input into the graph neural network, and the information degradation of the graph network is determined by learning the graph neural network for inferring the original circuit. In the determination of information degradation using the graph neural network, the process of reversely converting the graph network to the netlist is not performed, and therefore, the above-mentioned problem is not generated. However, there is a problem of deviation in the inference result in the graph neural network. In this case, the learning of the graph neural network with a common network structure is performed multiple times, and the deviation of the learning result based on the inference result of the graph neural network is confirmed, thereby suppressing the impact of the deviation in the inference result to a smaller level.

[0070] In this way, the determination of information degradation using a graph neural network is an excellent determination method that obtains stable results compared to the case of reverse conversion from a graph network to a netlist.

[0071] Here, a graph neural network is a machine learning model (AI) that infers a circuit corresponding to a graph network when it is input into the graph network.

[0072] If the graph neural network infers the original circuit with high accuracy, it is determined that little information degradation occurs when the netlist of the circuit is converted into a graph network.

[0073] In the case where a circuit has multiple grounds GND, inputs, and outputs, in the graph network obtained by converting the netlist of the circuit, the wiring representing the grounds GND, inputs, and outputs is classified and defined according to the types of the grounds GND, inputs, and outputs. These wirings are defined under complex conditions that include not only information representing the classified types but also the relationship with the connected components. Therefore, the graph neural network needs to learn including the complex conditions of each wiring, and the inference accuracy of the graph neural network inferring the original circuit is reduced.

[0074] In contrast, the information processing device 1 adds component names indicating ground terminals, input terminals, and output terminals to the component name list included in the netlist of the circuit on the left, and removes wiring names indicating ground wiring, input wiring, and output wiring from the wiring name list included in the netlist. Then, the information processing device 1 extracts component names corresponding to wiring names in the wiring name list from the component names in the component name list, creates a combination list including the extracted component names, and outputs the component name list and the combination list.

[0075] In the above component name list and the above combination list, the power input of the power supply V and the ground GND in the circuit on the left are set as components. Therefore, the netlist including the above component name list and the above combination list is converted into the graph network on the upper right side. In the graph network on the upper right side, in addition to the node of the semiconductor X, the node of the inductor L, the node of the capacitor C, and the node of the resistor R, the node of the power input from the power supply V and the node of the ground GND are also set.

[0076] The power input from the power supply V and the ground GND are defined as components, therefore, in the diagram network on the upper right side, the wiring related to the power input from the power supply V to the semiconductor X does not need to be classified as input wiring and is defined as a connection between nodes.

[0077] As for the ground GND, there is no need to classify the ground wiring, and it is defined as the connection between nodes. That is, in the graph network on the upper right side, all the wiring in the original circuit is defined by one type of wiring connecting the nodes.

[0078] Therefore, the various grounds GND, inputs, and outputs in the circuit are respectively divided into components. That is, the graph neural network can learn the grounds GND, inputs, and outputs in the circuit as components, and the accuracy of the graph neural network in inferring the original circuit is improved.

[0079] Figure 3 is a schematic diagram showing example (2) of a circuit and a graph network, Figure 3 The left figure shows an example of a circuit, and the upper and lower figures on the right show a network diagram of the circuit on the left. Figure 3 The circuit shown is a circuit having a power source V, a semiconductor X, an inductor L, a capacitor C, and a resistor R. When a component name list in which the ground GND in the circuit on the left is not set is used, the above circuit is converted into a network in the lower right diagram.

[0080] In the network of the figure on the lower right side, a power input node from a power supply V, a node of a semiconductor X, a node of an inductor L, a node of a capacitor C, and a node of a resistor R are set, but as shown by a white line, a ground GND is defined as a ground wiring set between the nodes. Generally speaking, among the components included in a circuit, there are many components connected to the ground GND, so a large number of ground wirings need to be defined for the ground GND depending on the circuit scale. In addition, the output node is the voltage at both ends of the resistor R.

[0081] This time, in Figure 3 In the circuit diagram shown, a power supply V serving as an input node and a resistor R serving as a load serving as an output node are recorded for simplicity of explanation. However, in a common circuit diagram in electrical design, the power supply V and the resistor R are not recorded and are shown as open ends.

[0082] In the graph network on the lower right side, six ground wirings are set for the ground GND, but in addition to the ground GND, five wirings for connecting nodes are set. That is, a total of 11 wirings need to be defined in the netlist.

[0083] In contrast, the information processing device 1 provides list information that sets the ground GND as a component. This list information can be converted into a graph network on the upper right side. In the graph network on the upper right side, Figure 3 As shown, in addition to the power supply input node from the power supply V, the node of the semiconductor X, the node of the inductor L, the node of the capacitor C, and the node of the resistor R, a node of the ground GND is also set.

[0084] In addition, semiconductors include not only single-function semiconductors such as transistors, diodes, MOS FETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), but also large-scale integrated circuits such as ICs or LSIs, such as CPUs, GPUs, memories or ASICs.

[0085] In the first embodiment, a large-scale integrated circuit whose internal circuit elements are unknown (black box) is defined as a node, so all semiconductors can be processed in the same way. In the case where the internal circuit elements are known, in the circuit that processes high frequency or signals in a frequency band other than the frequency of the semiconductor, due to the influence of parasitic capacitance, residual inductance or residual resistance, the result of the circuit calculation is inconsistent with the actual measurement, that is, there are many cases where it does not become an equivalent circuit. Therefore, even if the internal circuit elements can be determined, it is useless in most cases, and this embodiment that can be processed as a black box has a special effect.

[0086] However, when the circuit elements inside the integrated circuit are unknown, in most cases it is possible to grasp the attribute information of the integrated circuit itself, such as the CPU or memory. Therefore, it is preferred to input the attribute information of the integrated circuit as the attribute information of the semiconductor node.

[0087] In addition, the attribute information is information that is a combination of various information recorded in a specification sheet (also called an instruction manual), such as the manufacturer, type of component, model of component, product batch, number of terminals of the component, frequency of the input signal to the component, voltage of the input signal, current of the input signal, power of the input signal, frequency of the output signal from the component, voltage of the output signal, current of the output signal, power or size of the output signal.

[0088] By defining the ground GND as a component, in the graph network on the upper right side, 9 wirings connecting 9 nodes can be set. Therefore, only a total of 9 wirings need to be defined in the netlist, which can reduce the number of wirings that should be defined in the netlist compared to the case where the ground GND is not defined as a component. The reduction in the number of wirings can reduce the amount of calculation, and large-scale circuits can be processed even with computers with low computing performance or edge calculations.

[0089] Next, the hardware configuration for realizing the functions of the information processing device 1 will be described.

[0090] The information processing device 1 is, for example, a computer connected to an information network.

[0091] The computer may be a server or client that can be connected to the cloud via an information network, or may be an independent computer that is not connected to the information network. In addition, it may be a computer used in a closed network environment within a factory, which is called edge computing.

[0092] Furthermore, the information processing device 1 may be a smartphone, a tablet terminal, a PC (Personal Computer), or a microcomputer.

[0093] The information processing device 1 may also be a device that utilizes information processing services provided in the form of SaaS (Software as a Service). That is, a dedicated application for providing the information processing service in Embodiment 1 is executed by a server to which the information processing device 1 is connected via an information network, and the information processing device 1 can also receive the provision of information processing services on a Web browser without installing the dedicated application.

[0094] The functions of the acquisition unit 11 and the processing unit 12 of the information processing device 1 are realized by a processing circuit. That is, the information processing device 1 has a circuit for executing the following Figure 5 The processing circuit for the processing of steps ST1 to ST9 shown in the figure may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in a memory.

[0095] Figure 4 A is a block diagram showing a hardware structure that realizes the functions of the information processing device 1. Figure 4 In A, the input interface 100, the output interface 101 and the processing circuit 102 are connected to each other via bus wiring. Figure 4 B is a block diagram showing a hardware structure for executing software that realizes the functions of the information processing device 1. Figure 4In B, the input interface 100, the output interface 101, the processor 103 and the memory 104 are connected to each other via bus wiring. Figure 4 A and Figure 4 In B, the input interface 100 is, for example, an interface for relaying a net list acquired by the information processing device 1. The output interface 101 is an interface for relaying list information output from the information processing device 1 to an external device.

[0096] The processing circuit is Figure 4 In the case of the dedicated hardware processing circuit 102 shown in A, the processing circuit 102 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a component formed by a combination thereof.

[0097] The functions of the acquisition unit 11 and the processing unit 12 of the information processing device 1 may be realized by different processing circuits, or these functions may be realized by one processing circuit.

[0098] The processing circuit is Figure 4 In the case of the processor 103 shown in B, the functions of the acquisition unit 11 and the processing unit 12 of the information processing device 1 are implemented by software, firmware, or a combination of software and firmware. The software or firmware is described as a program and stored in the memory 104.

[0099] The processor 103 reads out and executes the program stored in the memory 104 , thereby realizing the functions of the acquisition unit 11 and the processing unit 12 included in the information processing device 1 .

[0100] For example, the information processing device 1 has a memory 104 for storing the information processing program which, when executed by the processor 103, results in execution. Figure 5 The programs for the processing of steps ST1 to ST9 shown in the figure. These programs cause the computer to execute the steps or methods of the processing performed by the acquisition unit 11 and the processing unit 12. The memory 104 may be a computer-readable storage medium storing a program for causing the computer to function as the acquisition unit 11 and the processing unit 12.

[0101] The memory 104 is, for example, a nonvolatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically-EPROM), a magnetic disk, a floppy disk, an optical disk, a high-density disk, a mini disk, a DVD, etc.

[0102] The functions of the acquisition unit 11 and the processing unit 12 of the information processing device 1 may be partially implemented by dedicated hardware, and partially implemented by software or firmware. For example, the function of the acquisition unit 11 may be implemented by the processing circuit 102 as dedicated hardware, and the function of the processing unit 12 may be implemented by the processor 103 reading and executing the program stored in the memory 104. In this way, the processing circuit can implement the above functions by hardware, software, firmware, or a combination thereof.

[0103] The program executed by the processor 103 may be a program received from a system (comport) such as the WWW (World Wide Web) that connects a plurality of hardware via either or both wired and wireless connections.

[0104] In addition, when the information processing device 1 performs learning of the graph neural network described later, the parameters obtained through learning, especially the weight matrix in the neural network, can also be sent and received in the above-mentioned system.

[0105] The information processing device 1 may also function as a learning device that performs machine learning.

[0106] Furthermore, the learning device may be a device that includes, in addition to the CPU, general-purpose hardware such as a GPU (Graphics Processing Unit) that is good at parallel computing. Furthermore, the information processing device 1 may be composed of a plurality of computers connected via a communication port.

[0107] In the following description, it is assumed that the information processing device 1 performs both learning and inference, but learning and inference may be performed by separate devices that operate independently of each other. In this case, one of these devices may be the information processing device 1, or both may be the information processing device 1.

[0108] Furthermore, the information processing device 1 may be a device that provides a plurality of virtual hardware environments within one piece of hardware, and that virtually processes each virtual hardware as an independent piece of hardware.

[0109] Next, the operation of the information processing device 1 according to the first embodiment will be described.

[0110] Figure 5 It is a flowchart showing the information processing method according to the first embodiment, and shows a series of operations performed by the information processing device 1 .

[0111] First, the acquisition unit 11 acquires a netlist (step ST1). For example, the acquisition unit 11 obtains Figure 4 The circuit diagram model is read out from the memory 104 shown in B, and the circuit diagram shown in the circuit diagram model is converted into a netlist. Regarding the notation form of the netlist, there is a form in which the wiring name is recorded after the component name. For example, there are forms such as Telesis, PADS, Allegro, Express PCB, Intergraph and Scicards.

[0112] In addition, there are also formats for notating netlists in which the wiring names are listed followed by the component names, such as Calay, Mentor, or Vectron.

[0113] Furthermore, there are also formats for notating netlists that simultaneously list component names and wiring names, such as ComputerVision, Algorex, or Multiwire.

[0114] In any notation, ground, input, and output are defined as wiring. The following netlist expresses the netlist of the circuit that operates the switching power supply in the form of telesis.

[0115] $PACKAGES

[0116] lt3489! LT3489; U1

[0117] ind! 2.2u; L1

[0118] schottky! 1N5818;D1

[0119] cap! 20u; C1

[0120] res! 28.7K; R1

[0121] res! 5.23K; R2

[0122] cap! .001u; C2

[0123] $NETS

[0124] N002; U1.1 U1.7

[0125] N003; U1.2 R1.2 R2.1

[0126] IN; U1.3 U1.6 L1.1

[0127] 0; U1.4 C1.2 R2.2 C2.2

[0128] N001; U1.5 L1.2 D1.1

[0129] N004;U1.8 C2.1

[0130] OUT; D1.2 C1.1 R1.1

[0131] $END

[0132] The processing unit 12 extracts a component name list from the netlist (step ST2-1), and extracts a wiring name list from the netlist (step ST2-2). For example, the processing unit 12 stores all component names included in the netlist in the component name list, and stores all wiring names included in the netlist in the wiring name list.

[0133] In addition, regarding the processing of step ST2-1 and the processing of step ST2-2, one of them may be executed first, or they may be executed simultaneously.

[0134] The component name list stores components with structural characteristics such as semiconductors and capacitors, and does not include ground terminals, input terminals, and output terminals. On the other hand, the wiring name list includes ground wiring, input wiring, and output wiring as part of the wiring.

[0135] The processing unit 12 adds the ground wiring, input wiring, and output wiring included in the netlist as ground terminals, input terminals, and output terminals to the component name list (step ST3-1). The processing unit 12 removes the ground wiring, input wiring, and output wiring from the wiring name list (step ST3-2). Thus, information indicating the ground terminal, input terminal, and output terminal is retained as component information in the component name list, thereby suppressing information degradation when converting a circuit into a graph network using list information including the component name list.

[0136] In addition, regarding the processing of step ST3-1 and the processing of step ST3-2, one of them can be executed first, or they can be executed simultaneously.

[0137] The line following "$PACKAGES" in the above netlist indicates component names, and the line following "$NETS" indicates wiring names. The component names "U1, L1, D1, C1, R1, R2, C2" extracted from the netlist are a component name list.

[0138] In addition, the wiring names "N002, N003, IN, 0, N001, N004, OUT" extracted from the netlist are a list of wiring names. The input wiring is defined as "IN" and the output wiring is defined as "OUT". Depending on the netlist, the input and output are sometimes not named, but no matter what kind of netlist it is, it contains wiring corresponding to the input and output of the circuit. "0" is a wiring name representing a ground wiring, for example, it must exist in a substrate on which a semiconductor is mounted.

[0139] In this case, N001, N002, N003, and N004 are wiring names mechanically assigned by CAD to wirings that are not intentionally assigned wiring names by the designer.

[0140] The processing unit 12 adds ground (GND), input (IN), and output (OUT) to the component name list. For example, the component name list to which ground (GND), input (IN), and output (OUT) are added is "U1, L1, D1, C1, R1, R2, C2, GND, IN, OUT". Ground (GND), input (IN), and output (OUT) are different from circuit components and do not have structural characteristics. Therefore, they are not set in the component name list. However, the processing unit 12 processes ground (GND), input (IN), and output (OUT) as circuit components.

[0141] In the netlist, ground (GND), input (IN), and output (OUT) do not need to be one, but can be multiple. For example, ground is sometimes divided into system ground and frame ground, and depending on the circuit, the two are sometimes connected using capacitors, resistors, or inductors. These grounds can also be defined as different grounds.

[0142] In a circuit, there are not only power supply terminals connected to a commercial power supply or a battery, but also various input terminals such as an input terminal for external signals.

[0143] In addition, in the circuit, for example, in addition to an output terminal for outputting a signal connected to a rotating electric machine such as a motor, there are a plurality of output terminals such as an output terminal for outputting a signal indicating the rotation speed of the rotating electric machine.

[0144] The processing unit 12 removes the ground wiring (0), input wiring (IN), and output wiring (OUT) from the wiring name list. The above wiring name list becomes "N002, N003, N001, N004". Thus, the ground, input, and output are defined as components rather than wiring, and as a result, it is possible to reduce information degradation when converting from a circuit to a graph network.

[0145] For example, when the same circuit is expressed using "PADS" which is another notation format of a netlist, as follows, in this case, a component name list and a wiring name list can be created in the same manner.

[0146] In addition, no matter what form the netlist is expressed in, a circuit does not exist without components and wirings, so a component name list and a wiring name list can be created without fail.

[0147] *PART*

[0148] U1 LT3489

[0149] L1 2.2u

[0150] D 1 1N5818

[0151] C 1 20u

[0152] R1 28.7K

[0153] R2 5.23K

[0154] C2 .001u

[0155] *NET*

[0156] *SIGNAL*N002

[0157] U1.1 U1.7

[0158] *SIGNAL*N003

[0159] U1.2 R1.2 R2.1

[0160] *SIGNAL*IN

[0161] U1.3 U1.6 L1.1

[0162] *SIGNAL*0

[0163] U1.4 C1.2 R2.2 C2.2

[0164] *SIGNAL*N001

[0165] U1.5 L1.2 D1.1

[0166] *SIGNAL*N004

[0167] U1.8 C2.1

[0168] *SIGNAL*OUT

[0169] D1.2 C1.1 R1.1

[0170] *END*

[0171] Next, the processing unit 12 extracts the component names corresponding to the wiring names in the wiring name list from the component names in the component name list, and creates a combination list including the extracted component names (step ST4). For example, the processing unit 12 extracts the component names in the component name list corresponding to the wiring names in the wiring name list in the order of the list from the netlist, and creates a combination list including the extracted component names. Here, the processing unit 12 includes the ground terminal, input terminal, and output terminal added to the component name list in the combination list.

[0172] Furthermore, the “component name corresponding to the wiring name” indicates the component name of the component connected to the wiring indicated by the wiring name.

[0173] By including the ground terminal in the combination list, the amount of information in the combination list can be reduced. Generally speaking, most components in a circuit are connected to the ground GND. For example, when N components are connected to the ground GND, the combination list includes N combinations of the ground GND and the components.

[0174] In addition, when the ground GND is not defined, it is necessary to create a number of combinations of the ground GND and components that is proportional to the square of N.

[0175] If the components are not connected by wiring, the circuit will not be established. Therefore, as long as the circuit functions normally, a combination list can be created.

[0176] Figure 6 This is a circuit diagram showing example (1) of the circuit. Figure 6 The netlist of the circuit shown is as follows.

[0177] #part

[0178] A

[0179] B

[0180] C

[0181] D

[0182] #wiring

[0183] (1); IN, A

[0184] (2); A, B

[0185] (3); B, C, D

[0186] (4); D,OUT

[0187] GND; A, B, C

[0188] The list of component names extracted from the above netlist becomes "A, B, C, D, IN, OUT, GND" by adding "IN", "OUT", and "GND".

[0189] The wiring name list becomes "(1),(2),(3),(4)" by removing "IN", "OUT", and "GND".

[0190] In a net list in which a wiring connected to a ground terminal is not defined, a wiring is provided between the ground and a component, and a name is given to the wiring.

[0191] That is, according to Figure 6 In the netlist of the circuit shown in the figure, for example, "G" is used to represent ground, and the component names are connected, and wiring names such as "GA", "GB", and "GC" are given. As a result, the wiring name list becomes "(1), (2), (3), (4), GA, GB, GC".

[0192] The list obtained by extracting the component names corresponding to the wiring names in the wiring name list "(1), (2), (3), (4), GA, GB, GC" from the component name list "A, B, C, D, IN, OUT, GND" in sequence from the netlist is the following combination list.

[0193] (1); IN, A

[0194] (2); A, B

[0195] (3); B, C, D

[0196] (4); D,OUT

[0197] GA; GND, A

[0198] GB; GND, B

[0199] GC; GND, C

[0200] Next, the processing unit 12 determines whether the number of component names corresponding to one wiring name among the component names in the combination list is three or more (step ST5). Here, when it is determined that the number of component names corresponding to one wiring name in the combination list is less than three (step ST5: No), the processing unit 12 replaces the component names in the combination list with identification numbers (step ST6).

[0201] On the other hand, when it is determined that there are more than three component names corresponding to one wiring name in the combination list (step ST5: Yes), the processing unit 12 decomposes it into a combination of two component names (step ST7). For example, when the component name held by a certain wiring name, that is, the component name corresponding to one wiring name, is [capacitor, coil, resistor], the processing unit 12 decomposes it into three combinations of [capacitor, coil], [coil, resistor], and [resistor, capacitor]. Similarly, when the component name is [capacitor, coil, resistor, semiconductor], the processing unit 12 decomposes it into six combinations of [capacitor, coil], [capacitor, resistor], [capacitor, semiconductor], [coil, resistor], [coil, semiconductor], and [resistor, semiconductor].

[0202] The processing unit 12 adds the combination decomposed into two component names each to the combination list, and removes the combination having three or more component names before decomposition from the combination list. However, this process is for preparing the adjacency matrix in the graph network, and as long as the adjacency matrix can be prepared directly from the combination list, decomposition is not necessary.

[0203] For example, in the above netlist, (3); B, C, D is equivalent to a combination of three or more component names, so the processing unit 12 decomposes it into (B, C), (C, D) and (D, B). As a result, Figure 6 The circuit diagram shown results in the following combination list.

[0204] (1); (IN, A)

[0205] (2); (A, B)

[0206] (3); (B, C), (C, D), (D, B)

[0207] (4); (D, OUT)

[0208] GA; (GND, A)

[0209] GB; (GND, B)

[0210] GC; (GND, C)

[0211] Figure 7 This is a circuit diagram showing example (2) of the circuit. Figure 7 The circuit diagram shown becomes the netlist described below.

[0212] #part

[0213] A

[0214] C

[0215] D

[0216] E

[0217] F

[0218] #wiring

[0219] ';IN,A

[0220] ';A,D

[0221] ';C,D,E

[0222] (4A); E, F

[0223] (5A); F,OUT

[0224] GND; A, C, E

[0225] The component name list included in the above-mentioned netlist is "A, C, D, E, F, GND, IN, OUT", and the wiring name list is "(1A), (2A), (3A), (4A), (5A), GA, GC, GE". The processing unit 12 extracts the component name corresponding to each wiring name in the wiring name list from the netlist, thereby producing the following combination list.

[0226] (1A); IN, A

[0227] (2A); A, D

[0228] (3A); C, D, E

[0229] (4A); E, F

[0230] (5A); F,OUT

[0231] GA; GND, A

[0232] GC; GND, B

[0233] GE; GND, E

[0234] Next, when each combination list has three or more component names, the processing unit 12 decomposes them. For example, the processing unit 12 decomposes the combination "(3A); C, D, E" into combinations of two component names each, thereby creating the following combination list.

[0235] (1A); (IN, A)

[0236] (2A); (A,D)

[0237] (3A); (C, D), (D, E), (E, C)

[0238] (4A); (E, F)

[0239] (5A); (F, OUT)

[0240] GA; (GND, A)

[0241] GC; (GND, B)

[0242] GE; (GND, E)

[0243] The above description has been given on the premise that component names other than the same component do not match. However, when the same component name is used in a circuit component having another function, the processing unit 12 changes the component name.

[0244] On the contrary, when other component names are used in the same circuit component, the component name is changed by the processing unit 12. When there are many component names and it is difficult to unify them, it is easy to unify them if the model numbers of each component manufacturer are used.

[0245] The processing unit 12 defines a unique identification number common to each type of component or each model of component indicated by each component name in the component name list (step ST8 ), and replaces each component number in the component name list with the identification number (step ST9 ).

[0246] The processing unit 12 replaces each component name included in the component name list and the combination list with an identification number, and outputs the component name list and the combination list obtained in this way as list information.

[0247] By using list information including a component name list and a combination list in which component names are replaced with identification numbers, circuit information can be expressed using numerical values, thereby reducing information degradation of the graph network as described above. Therefore, by using the graph network, the original circuit can be produced.

[0248] Furthermore, the identification number may be defined for each type of component that is a characteristic of the component.

[0249] The type of component can be expressed by information such as capacitor, coil, power IC or diode. The types of components are based on the classification method, but are generally less than 100. In this way, the types of components are relatively small. For example, the processing unit 12 uses a continuous number set for each type of component as an identification number to replace the component name.

[0250] Furthermore, the identification number may also be defined for each model of the component.

[0251] When the number of components used in a circuit is limited, the number of identification numbers for each component model is relatively small. In this case, by using the identification number defined by the component model, it is possible to prevent information degradation when converting from list information to a graph network.

[0252] In step ST8 , the processing unit 12 defines an identification number by the following method, and assigns the defined identification number to the component name.

[0253] As mentioned above, Figure 6 The list of parts names associated with the circuit shown is "A, B, C, D, IN, OUT, GND", as described above, with Figure 7 The list of component names associated with the circuit shown is "A, C, D, E, F, GND, IN, OUT".

[0254] The processing unit 12 combines these component name lists to create a component name list such as “A, A, B, C, C, D, D, E, F, GND, GND, IN, IN, OUT, OUT.” The component name list includes a plurality of identical component names.

[0255] The processing unit 12 removes duplication of component names, thereby creating a component name list such as “A, B, C, D, E, F, GND, IN, OUT”.

[0256] Next, the processing unit 12 assigns identification numbers so that each component in the component name list has a different identification number. When using natural numbers as identification numbers, the component name list in which the component name is replaced with the identification number is as follows. In addition, the identification number does not need to be a continuous number, and a character or symbol may also be used.

[0257] A→1

[0258] B→2

[0259] C→3

[0260] D→4

[0261] E→5

[0262] F→6

[0263] GND→7

[0264] IN→8

[0265] OUT→9

[0266] The identification number of the component name "GND" is "0", the identification number of the component name "IN" is "1", and the identification number of the component name "OUT" is "2", and the order can be arbitrarily reversed.

[0267] In addition, the identification number may also be a number corresponding to the circuit constant of the component, the model of the component, the manufacturer of the component, or the withstand voltage of the component. For example, the same identification number is assigned to components with the same function, such as a power supply, a memory, and a CPU.

[0268] For example, in a switching power supply, when the switching power supply is divided into an isolated power supply and a non-isolated power supply, the same identification number is assigned to the isolated power supply and the same identification number is assigned to the non-isolated power supply.

[0269] Furthermore, the same identification number may be assigned to actions such as voltage increase, voltage decrease, or voltage rise and fall.

[0270] Furthermore, an identification number may be assigned based on a circuit constant of a passive element.

[0271] For example, the same identification number may be assigned to capacitors with a capacitance of 1.0 μF, and the same identification number may be assigned to capacitors with a capacitance ranging from 1.0 μF to 3.3 μF.

[0272] Furthermore, the definition of the identification number may be changed according to the user's request.

[0273] Furthermore, an identification number may be assigned to each model number set by a component manufacturer for each component.

[0274] The method of defining the identification number may also be changed depending on the circuit to be processed.

[0275] For example, when replacing the component name with the identification number of each type of component (capacitor, coil, resistor, semiconductor, etc.), Figure 6 The list of component names related to the circuit shown becomes "1,2,3,4,7,8,9", and the combined list becomes "(8,1),(1,2),(2,3),(3,4),(4,2),(4,9),(7,1),(7,2),(7,3)".

[0276] In addition, Figure 7 The list of component names related to the circuit shown becomes "1,3,4,5,6,7,8,9", and the combined list becomes "(8,1),(1,4),(3,4),(4,5),(5,3),(5,6),(6,9),(7,1),(7,2),(7,5)".

[0277] The processing unit 12 repeatedly performs the above-mentioned series of processing, thereby preparing a list of component names and a list of combinations related to all circuit diagrams. The definition of the identification number is arbitrary, so by determining the identification number based on the characteristics of the component to be concerned, the method of using the circuit can be changed according to the purpose of use of the circuit. For example, in the problem of predicting the type of component, the model number is redundant information when used as an identification number. On the other hand, when the manufacturer of the component is used as the identification number, insufficient information may make it impossible to make a correct prediction. Therefore, it is necessary to select an identification number corresponding to the purpose of use. When the identification number is correctly selected, the amount of calculation when predicting the type of component is small, and the prediction accuracy can be improved.

[0278] Furthermore, a plurality of identification numbers may be assigned to one component name.

[0279] For example, identification numbers corresponding to the model number of the component, the type of the component, and the circuit constant of the component may be assigned. In this case, for example, Figure 7 The list of component names for the circuit shown becomes "(1,3,0),(3,3,7),(4,5,3),(5,2,0),(6,8,1),(7,1,0),(8,1,0),(9,1,0)".

[0280] Since the types of components "IN", "OUT", and "GND" as component names are all wiring, the identification number is defined as "1", the identification number "1" is given to semiconductors, the identification number "5" is given to other semiconductors, and the components indicated by the component names "IN", "OUT", and "GND" are input terminals, output terminals, and grounds, and have no circuit constants. In this case, for example, the identification number is defined as "0".

[0281] For example, circuit constants may be set for the semiconductor in consideration of the internal characteristics of the semiconductor, or different identification numbers may be given to the types of components indicated by "IN", "OUT", and "GND".

[0282] The method of assigning the identification number may be arbitrary as long as it is based on a rule common to all circuits.

[0283] The identification number only needs to be a real number and does not need to be a natural number.

[0284] It is also possible to directly input the circuit constant of a component as an identification number.

[0285] For example, the range of circuit constants used in general circuits is about 10 to the power of 20, ranging from a maximum of f (femto) to several 100 G (giga). Therefore, when circuit constants are used as identification numbers in their original form, larger numbers are dominant.

[0286] In addition, due to calculation errors, smaller values ​​are sometimes rounded off or changed to different values. In order to avoid these situations, a function that includes logarithms in the circuit constants can also be used. For example, the function is set to f(x) = log10(x) + 15. In this case, +15 is -log10 (f = 1 micro). Thus, f(x) can be converted to a real number greater than 0. In addition, in order to avoid the situation where 1f becomes 0 and it is impossible to determine which component is placed, it can also be set to log10(x) + 16, or to log10(x) + 15 + (a small amount greater than 0 and less than 1). In addition, in order to simplify the explanation, the case where the base of the logarithm is 10 is described, but it may not be 10.

[0287] There are many cases where a precision of 1 digit or less is sufficient for the component constant. In this case, the value may be rounded off as described below and the identification number may be defined by level.

[0288] 1f→1,10f→2,100f→3,1n→4,10n→5,100n→6,1u→7,10u→8,100u→9,1m→10,10m→11,100m→12,1→13,10→14,100→15,1k→16,10k→17,100k→18,1M→19,10M→20,100M→21,1G→22,10G→23,100G→24.

[0289] Through the above series of processing, the circuit diagram can be converted into a netlist, and the netlist can be converted into a component name list and a combination list. When the component name list and the combination list are used, a graph network in graph theory can be created.

[0290] Graph networks can be used to search for difficult, similar circuits in netlists.

[0291] For example, the processing unit 12 sequentially searches the adjacency matrix created using the combination list, thereby being able to search for loop paths such as semiconductors, capacitors, coils, grounds, and semiconductors. In particular, in a circuit using specific circuit components, the identification numbers of the components constituting the circuit are sequentially searched.

[0292] For example, the processing unit 12 performs a search process with reference to a database containing semiconductors serving as noise sources and terminal numbers of the semiconductors, extracts a current loop representing the semiconductor and ends the search process. In this search process, adjacent components are continuously searched from the circuit starting from the terminal corresponding to the terminal number under the condition that the same component does not pass more than twice.

[0293] Specifically, the following processing is performed continuously: the terminal of the semiconductor to be searched is used as the starting point of the search, one or more adjacent components are searched from the starting point, and one or more circuit components adjacent to the component are searched. However, components other than the semiconductor that is the starting point of the search are searched under the condition that they will not pass through more than two times. In this way, searches that are contrary to physical phenomena such as the current returning to the original state or the current stopping midway can be avoided.

[0294] The processing unit 12 ends the search process when the search ends at any terminal other than the terminal serving as the search start point in the semiconductor.

[0295] The path generated by this search process is referred to as the above-mentioned “current loop.” That is, the above-mentioned processing is equivalent to the processing of extracting the current loop path in Kirchhoff's current law (Kirchhoff's first law), which is Kirchhoff's law.

[0296] The terminal can be any terminal. For example, the ground terminal is the most common, but in the case of a differential line, any terminal of the differential signal is the starting point, and the opposite terminal is the end point.

[0297] This makes it possible to detect the extraction of a noise filter, etc., based on an algorithm, or to estimate the impedance of a propagation path through which a current may flow, and predict which current loop in the circuit the current is most likely to flow through, for example.

[0298] Thus, the processing unit 12 can extract the characteristics of the semiconductor as the search object and the characteristics of the current loop representing the semiconductor from one or more circuits including one or more semiconductors, and use the extracted semiconductor characteristics and current loop characteristics to search for semiconductors similar to the semiconductor as the search object.

[0299] In addition, the processing unit 12 can also determine whether there is a component representing a noise filter in the current loop. As an example, the case of detecting a path from the power input terminal of the semiconductor via the grounded capacitor (Y capacitor) and the ground to the ground terminal of the semiconductor is described. In this embodiment, the grounded capacitor and the ground are defined as nodes of the graph network. Therefore, by determining whether there is a path from the starting node (semiconductor) via two nodes to the same node as the starting point, the path can be detected. In order to perform this detection, all current loops passing through two nodes are extracted. As long as one node of the extracted current loop is a capacitor and the other node is a grounded current loop, a current loop with a noise filter can be extracted.

[0300] Furthermore, a database having model numbers of components used as noise countermeasures is prepared in advance in the information processing device 1. The processing unit 12 checks whether the extracted capacitor is included in the database, and can determine that a noise filter is included in the current loop if so.

[0301] Furthermore, in order to limit nodes that may become noise sources and reduce the amount of calculation, a database having models of circuit components that may become noise sources is prepared in advance in the information processing device 1. The processing unit 12 can reduce the search targets by setting only appropriate nodes as search starting points.

[0302] In the above description, an example of a grounded capacitor is shown, but even a T-type filter, a π-type filter, etc. can be extracted in the same manner.

[0303] In addition, the presence or absence of connection between arbitrary components can also be confirmed.

[0304] Furthermore, by using the attribute information of each node, it is possible to predict the frequency characteristics or time waveform of the impedance between components, the current amount, or the voltage drop.

[0305] The processing unit 12 creates a current loop for each terminal of the semiconductor and analyzes the circuit components through which the current loop passes, thereby being able to extract similar circuits.

[0306] Through the above-mentioned search processing, the processing unit 12 can search for a noise filter circuit or a similar circuit without depending on the number of components or wirings in the circuit, the number of grounding or input / output ports, etc. Thus, by searching for a path adjacent to a semiconductor, an input connector, or an output connector that is a noise source and is provided with a noise filter, it is possible to reduce search errors.

[0307] In addition, for semiconductors that become noise sources, the model of the component can be extracted from the netlist as text data. In addition, in circuit diagrams, inputs and outputs are mostly recorded using input symbols and output symbols, but sometimes they are recorded as input connectors and output connectors with connector models assigned. Therefore, the above-mentioned database in which semiconductors that become noise sources, noise countermeasure components, input connectors, or output connectors are registered is prepared, and only text data is extracted by referring to the database, thereby preventing omissions in the search.

[0308] Furthermore, in addition to searching for noise sources or noise filters, by making nodes and edges have resistance components or delay components, the processing unit 12 can also calculate the impedance between two components and estimate the path through which the most current flows or the path through which the pulse signal arrives earliest.

[0309] When the circuit has a plurality of components connected in parallel to one wiring, the number of combinations of components in the combination list increases in the previous processing. Figure 8 This is a circuit diagram showing example (3) of the circuit. Figure 8 The circuit shown is a circuit in which a wiring Line1 is connected between an input terminal IN and an output terminal OUT, and capacitors C1, C2, and a resistor R are connected in parallel to the wiring Line1. An information processing device 1 that processes grounding, input, and output as components is produced. The above circuit is converted into the following Figure 9 List information of the graph network shown.

[0310] Figure 9 This is a schematic diagram showing a graph network in which nodes are connected by edges. Figure 9 The graph network shown is represented by nodes Figure 8The components in the circuit shown are connected by edges. The information processing device 1 creates list information that treats grounding, input, and output as components. Therefore, the list information created by the information processing device 1 is converted into the following graph network, for example: semiconductor X, capacitor C1, capacitor C2, resistor R, and output terminal OUT are represented as nodes, and all these nodes are connected by edges. Figure 9 In order to simplify the description, the description of the node representing the input terminal IN and the node representing the ground is omitted.

[0311] In addition, this graph network has the characteristics that component names are nodes and nodes adjacent to any node are nodes with component names.

[0312] When the circuit has a plurality of components connected in parallel to one wiring, the combinations of components corresponding to each other in the combination list increase in proportion to approximately the square of the number of components connected in parallel to the wiring. Figure 9 In the example, three components (capacitor C1, capacitor C2, and resistor R) are connected in parallel to one wiring Line1, so there are 9 combinations of 3 squared. For example, in a large-scale circuit, there are circuits in which more than 10 bypass capacitors are connected in parallel to one wiring. In such a circuit, the number of combinations increases significantly. Therefore, the amount of calculation required to search the current loop increases exponentially, and the search time also increases.

[0313] In addition, Figure 9 In the graph network shown in FIG. 1 , when searching all current loops starting from a specific component name node, it is possible to search nodes comprehensively in a manner that satisfies the condition that a node that has been passed once will not be passed twice. However, when the component name nodes are adjacent, as described above, it is necessary to include a number of components that is approximately proportional to the square of the number of components connected in parallel to one wiring. For example, Figure 9 As shown, when the number of components connected in parallel is three, it is difficult to calculate a path that returns to the node with the same component name as the starting point via the nodes corresponding to the component names of the three components.

[0314] Therefore, the information processing device 1 may also create a combination list including wiring names and component names to suppress the increase in the number of combinations of component names related to a large-scale circuit in which a plurality of components are connected in parallel to one wiring as described above. For example, the processing unit 12 extracts a component name list and a wiring name list from a netlist of the circuit, creates an updated component name list by adding component names representing ground terminals, input terminals, and output terminals, creates an updated wiring name list by removing wiring names representing ground wiring, input wiring, and output wiring, extracts component names corresponding to wiring names in the updated wiring name list from component names in the updated component name list, creates a combination list including the extracted component names and wiring names corresponding to the extracted component names, and outputs the updated component name list and the combination list.

[0315] Figure 10 is a schematic diagram showing a graph network in which nodes are connected via wiring nodes. Figure 10 As shown, the processing unit 12 extracts the combination of the component name corresponding to the component connected by the wiring indicated by each wiring name in the wiring name list and the above wiring name as a combination list. The graph network converted from the list information uses nodes to represent the component name and the wiring name, and has a feature that the node adjacent to the node of any component name becomes the node of the wiring name. In this way, the number of combinations can be made proportional to the first power of the number of components.

[0316] exist Figure 10 In the graph network shown, when searching all current loops starting from a node with a specific component name, it is possible to search all nodes so as to satisfy the condition that a node that has been passed through once will not be passed through twice.

[0317] On the other hand, in this graph network, the component name node and the wiring name node are adjacent, and the search is performed to return to the starting point via four wiring name nodes and three component name nodes instead of the nodes that are three circuit components (capacitor C1, capacitor C2, and resistor R). However, the wiring connected to each node is proportional to one degree, so the amount of calculation required for the search does not increase exponentially.

[0318] As an example of an experiment, in the same computer environment, searching for a current loop in a large-scale circuit with more than 1,000 components took 10 minutes when the component name nodes were adjacent in the graph network. On the other hand, when the component name nodes and wiring name nodes were adjacent, the search was completed in less than 1 second. This example shows that a particularly large effect can be obtained in the current loop search.

[0319] However, compared with the case where the component name node and the wiring name node are adjacent, the case where the number of components connected in parallel to a wiring is adjacent is advantageous when the number of components connected in parallel is large, but since the wiring name nodes increase, it is disadvantageous when the number of components connected in parallel is small.

[0320] Therefore, it is preferable to distinguish and use the two methods according to the scale of the circuit or the number of components connected in parallel to one wiring. For example, if searching for a current loop of a circuit having about 100 components, it is often better to use a graph network in which the component name nodes are adjacent.

[0321] In addition, regardless of whether the wiring name node is included, in the above two methods, paths with the same loop path and opposite directions can be obtained. Therefore, in post-processing, only one path can be retained and the other path can be removed. However, in the case of a directed graph with a known current direction, only one path is extracted, so the above post-processing may not be performed.

[0322] The processing unit 12 may replace the elements corresponding to the passive circuit in the feature quantity matrix with the function value calculated by substituting the circuit constant of the component into the function including the logarithm.

[0323] In a component having a circuit constant, the element corresponding to the passive circuit in the feature quantity matrix is ​​changed using a function value obtained by applying a function including a logarithm to the circuit constant, thereby enabling conversion into a graph network including the circuit constant.

[0324] Components with circuit constants are resistors, capacitors, or coils, but they can also be small signal circuits such as operational amplifiers. Components other than resistors, capacitors, and coils can also be circuit components with circuit constants if they can be converted into components composed of resistors, capacitors, and coils under certain conditions.

[0325] In addition, a component having a physical size has parasitic components such as stray capacitance, residual inductance, or residual resistance. Therefore, the processing unit 12 decomposes a component having a parasitic component into components having only two or more resistors, capacitors, or coils. The decomposition can be achieved by predicting an equivalent circuit through impedance measurement and determining the circuit constants of the equivalent circuit. As a result, even a circuit with complex component characteristics can be expressed using a graph network.

[0326] The circuit constant of a component having only one characteristic is assigned to the component name in the component name list. In most cases except for special cases, the circuit constant has a width of 1p to 1G or more, so the circuit constant can be logarithmically applied. By applying the logarithm to the circuit constant, it is possible to prevent, for example, a 1pF capacitor from being buried due to calculation errors.

[0327] The processing unit 12 may perform both normalization and standardization or one of the normalization and standardization on the function value.

[0328] For example, the result obtained by performing logarithm calculation on the circuit constant is normalized.

[0329] When the graph network is input into the graph neural network, the activation function in the graph neural network reacts to a real number between 0 and 1.

[0330] The result obtained by applying logarithm to the circuit constant is normalized and bijected to a real number greater than 0 and less than 1, or greater than 0 and less than 1, thereby making it possible to correspond the result obtained by applying logarithm to the circuit constant to the activation function of the real number.

[0331] The result obtained by applying logarithm to the circuit constant may be normalized.

[0332] For example, in the distribution of the results obtained by applying the logarithm to the circuit constants of the capacitors used in the circuit, when there are many capacitors below 100μF, as long as there is such a capacitor of 100F, the distribution of the results obtained by applying the logarithm to the circuit constants will be biased, and the difference in the results obtained by applying the logarithm to the circuit constants of each capacitor is estimated to be smaller.

[0333] Therefore, by normalizing the result obtained by performing logarithm analysis on the circuit constant, it is possible to reduce the deviation of the distribution.

[0334] In addition, the range of the circuit constants varies for each type of circuit component, and therefore, normalization or standardization may be performed differently for each type of circuit component. For example, a 100F capacitor is placed in a larger category of capacitors, whereas a 100Ω resistor is placed in a smaller category of resistors, and thus the range becomes larger. Therefore, for example, in the case of capacitors, the distribution is adjusted in a manner centered on 1μF, and in the case of resistors, the distribution is adjusted in a manner centered on 100Ω, etc., to reduce rounding errors and improve the estimation accuracy of the results obtained by applying logarithms to the circuit constants.

[0335] In addition, the processing unit 12 may normalize the result obtained by applying logarithm to the circuit constant and then perform the normalization, or may normalize the result and then perform the normalization. By combining the normalization and the normalization in this way, both effects can be obtained.

[0336] Circuit components that do not have a circuit constant do not become information by assigning the same numerical value such as "0" or "1" as an identification number. Therefore, the feature quantity list generated from the additional information can be expressed in a matrix.

[0337] For example, if it is a capacitor or a coil, it can be classified using circuit constants, and since it is a two-terminal device, there is no information degradation when converting from a graph network to a circuit.

[0338] On the other hand, when a circuit includes two or more semiconductors and includes two or more semiconductors of the same model, information degradation occurs when converting from a graph network to a circuit. Therefore, additional information indicating that the components are different may be given to the component name list for the semiconductor.

[0339] For example, a real number greater than 0 and less than 1 is divided by the number of semiconductors, and a different real number is assigned to each semiconductor as additional information.

[0340] When two semiconductors of the same model number exist in one circuit, different real numbers such as 0.3 are assigned to one semiconductor and 0.6 are assigned to the other semiconductor.

[0341] Furthermore, if it is only known that a component in a circuit is a semiconductor and that the circuit is composed of 10 semiconductors, 0.1 to 1.0 may be allocated in 0.1 increments as additional information.

[0342] Furthermore, the additional information may be any information as long as the values ​​are different, and real numbers may be assigned in any order.

[0343] Furthermore, when the identification number is not used, the processing unit 12 may directly output the component name list and the combination list as the list information without replacing the component name with the identification number.

[0344] Modification 1

[0345] In the information processing device 1 of variant example 1, the processing unit 12 sets the component name list as nodes in the graph network, the wiring name list as edges in the graph network, and the combination list as an adjacency matrix in the graph network, and uses the graph network to learn the graph neural network.

[0346] When the dataset of learning data consists only of nodes and edges, the learning of graph neural networks becomes unsupervised learning.

[0347] On the other hand, when correct answer data is obtained through circuit simulation or experiment, the processing unit 12 uses the nodes, edges, and correct answer data as a data set of learning data to perform learning of the graph neural network.

[0348] Furthermore, the processing unit 12 performs learning of the graph neural network including edge attribute information (edge ​​attribute) such as edge frequency characteristics.

[0349] Furthermore, the processing unit 12 performs graph neural network learning using the characteristics of each circuit constant or each semiconductor component as node attribute information (node ​​attribute).

[0350] Figure 11 This is a flowchart showing an example (1) of data input processing for a graph network in Embodiment 1. When the number of circuits is n, n netlists equal to the number of circuits are created, and therefore, the processing unit 12 sets n netlists as processing objects (step ST1A). The processing unit 12 sets "1" as parameter i (step ST2A).

[0351] The processing unit 12 sets the value of parameter i to the function g[i]=[[node], [edge]] (step ST3A). The processing unit 12 extracts the component name list and the wiring name list from the i-th net list acquired by the acquisition unit 11.

[0352] The processing unit 12 reads the component name list extracted from the i-th netlist as the nodes of the graph network, and reads the wiring name list as the edges of the graph network (step ST4A). The processing unit 12 sets the nodes and edges related to the i-th netlist as a data set, associates it with the function g[i], and stores it in a storage area such as the memory 104 (step ST5A).

[0353] The processing unit 12 determines whether the parameter i is less than or equal to n (step ST6A). If the parameter i is less than or equal to n (step ST6A: Yes), the processing unit 12 adds "1" to the parameter i (step ST7A) and returns to the process of step ST4A.

[0354] On the other hand, when it is determined that the parameter i is greater than n (step ST6A: No), the processing unit 12 outputs data sets associated with g[1] to g[n], respectively (step ST8A).

[0355] The nodes become a matrix of (the number of components in each circuit + ground terminal + input terminal + output terminal) × (the number of feature quantities of the node). Figure 6 In the circuit shown, the nodes form a matrix of 7 × 1. In addition, although the input terminal and the output terminal have been described above as one circuit, it is sufficient to have one or more terminals, in which case the columns of the matrix become larger.

[0356] In addition, the number of feature quantities of the node can also be input as one hot. In this case, when the number of feature quantities of the node is set to M (for example, Figure 6As shown in the circuit, when the types of components include capacitors, coils, first semiconductors, and second semiconductors, when M=4), the nodes become a matrix of 7×M. The edges become a matrix of 2×(the number of edges). Here, "2" multiplied by (the number of edges) means any two components in the component name list, and the edges become a matrix indicating the connection between these two components by the number of edges.

[0357] In addition, when the direction of the current is known, it can also be a directed graph. In a directed graph, when the order in which the current flows through the components in the combination list is expressed as (1,2), by definition, it means the direction from 1 to 2 or from 2 to 1. There can also be bidirectional edges like an undirected graph. In this case, (2,1) can be further added to (1,2). When considering bidirectional edges, in the case of an undirected graph, the matrix is ​​2×(the number of edges), while in a directed graph, the maximum matrix is ​​4×(the number of edges).

[0358] exist Figure 6 In the case of the circuit shown, the combinations in the combination list are (8,1), (1,2), (2,3), (3,4), (4,2), (4,9), (7,1), (7,2), (7,3), so the nodes are a 2×9 matrix. The elements of this matrix are the identification numbers included in the component name list that become nodes. This means that the components included in a circuit do not form edges with the components included in other circuits.

[0359] In graph neural networks, each circuit can be processed sequentially, but when using dedicated hardware such as GPUs, it can be parallelized.

[0360] In particular, when the number of circuits is as large as several thousand or more, it is preferable to process them collectively rather than sequentially calculating each circuit in terms of calculation speed or calculation efficiency. Therefore, all or a combination of nodes and edges that can be stored in the memory at once are input collectively.

[0361] In this example, there is no correct answer data, so it becomes unsupervised learning.

[0362] Figure 12 This is a flowchart showing an example (2) of data input processing for a graph network in Embodiment 1. When the number of circuits is n, n netlists equal to the number of circuits are established, and therefore, the processing unit 12 sets n netlists as processing objects (step ST1B). The processing unit 12 sets "1" as parameter i (step ST2B).

[0363] Processing unit 12 sets the value of parameter i to function g[i]=[[node],[edge],[correct answer data]] (step ST3B). Processing unit 12 extracts the component name list and wiring name list from the i-th net list acquired by acquisition unit 11, and acquires the correct answer data obtained in advance.

[0364] The processing unit 12 reads the component name list extracted from the i-th netlist as the nodes of the graph network, and reads the wiring name list as the edges of the graph network, and then reads the correct answer data (step ST4B). The processing unit 12 sets the nodes, edges and correct answer data related to the i-th netlist as one data set, associates it with the function g[i] and stores it in a storage area such as the memory 104 (step ST5B).

[0365] The processing unit 12 determines whether the parameter i is less than or equal to n (step ST6B). If the parameter i is less than or equal to n (step ST6B: Yes), the processing unit 12 adds "1" to the parameter i (step ST7B) and returns to the process of step ST4B.

[0366] On the other hand, when it is determined that the parameter i is greater than n (step ST6B: No), the processing unit 12 outputs data sets associated with g[1] to g[n], respectively (step ST8B).

[0367] Figure 13 This is a flowchart showing an example (3) of data input processing for a graph network in Embodiment 1. When the number of circuits is n, n netlists equal to the number of circuits are established, and therefore, the processing unit 12 sets n netlists as processing objects (step ST1C). The processing unit 12 sets "1" as parameter i (step ST2C).

[0368] The processing unit 12 sets the value of parameter i to the function g[i]=[[node],[edge],[edge attribute],[correct answer data]] (step ST3C). The processing unit 12 extracts the component name list and wiring name list from the i-th netlist acquired by the acquisition unit 11, and acquires the edge attributes and correct answer data obtained in advance.

[0369] The processing unit 12 reads the component name list extracted from the i-th netlist as the nodes of the graph network, and reads the wiring name list as the edges of the graph network, and then reads the attributes and correct answer data of the edges (step ST4C). The processing unit 12 sets the nodes, edges, edge attributes and correct answer data related to the i-th netlist as one data set, associates it with the function g[i] and stores it in a storage area such as the memory 104 (step ST5C).

[0370] The processing unit 12 determines whether the parameter i is less than or equal to n (step ST6C). If the parameter i is less than or equal to n (step ST6C: Yes), the processing unit 12 adds "1" to the parameter i (step ST7C) and returns to the process of step ST4C.

[0371] On the other hand, when it is determined that the parameter i is greater than n (step ST6C: No), the processing unit 12 outputs data sets associated with g[1] to g[n], respectively (step ST8C).

[0372] The data set obtained as described above can be used for clustering, autoencoder, and self-supervised learning which is one of contrastive learning. Clustering can be used to classify the types of nodes or edges.

[0373] An autoencoder is a learning method of a graph neural network that aims to obtain output data that is the same as the input data after passing through the graph neural network. In an autoencoder, multiple circuits can be abstracted and maintained.

[0374] In addition, self-supervised learning is similar to clustering, but it is possible to classify each input data and classify similar circuits into any number of sets, for example.

[0375] These are just examples, and multiple techniques can be combined to predict whether there are edges between nodes or whether there are nodes.

[0376] In addition, regarding neural networks that process data of circuits set as graph networks, in addition to graph neural networks, many other neural networks are known, such as graph convolutional neural networks and graph attention networks.

[0377] For example, a neural network suitable for large-scale models, a neural network that is good at using a sparse adjacency matrix network made with edges, etc. can be used. Any neural network can be used according to the characteristics of the data or the characteristics of the correct solution data.

[0378] The processing unit 12 uses the types of circuit diagrams as correct answer data and supervisory data as learning data, and uses, for example, 3,362 types of sampled circuits processed by a circuit simulator to perform graph neural network learning.

[0379] Sampling circuits are circuits used to make semiconductors operate, and include nine types: switch circuits (89), reference circuits (59), ADC circuits (27), DAC circuits (29), comparator circuits (40), filter circuits (25), power supply circuits (2272), and operational amplifier circuits (665).

[0380] The processing unit 12 uses, as learning data, a data set obtained by combining a graph network and circuit classification data assigned to a plurality of circuits, and performs learning of a graph neural network for classifying circuits. The graph network not used in this learning is input to the graph neural network, thereby classifying the circuits.

[0381] For example, learning of a graph neural network for solving a classification problem of classifying a circuit into the above nine types is performed. Here, 2,300 randomly obtained data are used as learning data, and the remaining 897 data are used as test data not used in the learning. The graph neural network of the learning result performs random classification, and the distribution of the classification problems of the learning data and the test data is similar. In addition, in all the calculations of the graph neural network shown in the embodiment, the same data is used for the learning data and the test data.

[0382] In addition, under the above conditions, nodes of component constants or component models are not used, and each node is only an identification number for each type of component such as a semiconductor, a capacitor, or a coil.

[0383] This is because, in the circuit classification problem, it is expected to make a prediction based on the connection information between circuit components. When the component model is put into the data, the circuit can be classified according to the model. Therefore, this situation needs to be prevented.

[0384] Furthermore, regarding the edges, only the information connecting the respective identification numbers is input. At this time, an undirected graph in which the current direction is not considered is set, so the adjacency matrix becomes a symmetric matrix.

[0385] Figure 14 It is a graph showing an example (1) of the calculation result of the inference accuracy of the information processing apparatus 1 according to Embodiment 1. In Figure 11 it, the horizontal axis is the number of repetitions (iteration periods) when learning the graph neural network using the learning data and updating the parameters of the graph neural network. The vertical axis represents the inference accuracy of the learned graph neural network for the test data not used in the learning.

[0386] As Figure 11 shown, as the number of repetitions increases, the inference accuracy for the test data improves, and in 4,000 repetitions, the maximum inference accuracy becomes 96.26%.

[0387] In addition, Figure 14 the graph neural network used in the calculation of the inference result shown has a combination of 6 hidden layers and Relu (Rectified Linear Unit), and uses 2 fully connected layers to classify the feature amounts obtained through the graph neural network and Relu into any one of 9 types of outputs.

[0388] In addition, cross entropy is used in the loss function, and Adam (Adaptive Moment Estimation) is used in the optimization function. The batch size is 500, and the graph neural network is trained in such a way that the loss function approaches 0.

[0389] In this way, through the training of the graph neural network with only the types of components and the connection relationships of each component, the inference accuracy based on the trained graph neural network becomes about 90%.

[0390] In addition, for the circuit shown in the test data, 77% of people have no preconception that it is a power supply circuit. When classifying the circuit according to the graph network, the inference accuracy based on human judgment is about 50%.

[0391] From this result, it can be seen that the inference accuracy based on the present method is significantly improved compared with that of humans.

[0392] Figure 15 It is a graph showing an example (2) of the calculation result of the inference accuracy of the information processing apparatus 1 based on Embodiment 1, showing the result of training the graph neural network using, as learning data, the data obtained by assigning component constants to the passive components, which are the nodes used in the inference calculation. Passive components are, for example, resistors, capacitors, or coils. Since the passive components have a large dynamic range of values that can be taken, the logarithm to the base 10 is taken for the identification number corresponding to the type of passive component so as to be 0 or more and 1 or less, and it is input as a real number. Figure 14 For example, when the information of the nodes is (C1, 0.33 uF), (L2, 10 uH), and the identification number of C1 is 1 and the identification number of L2 is 2, the processing unit 12 converts it to (1, -6.48), (2, -5.00). After all the conversions are completed, the processing unit 12 performs normalization processing using the maximum value and the minimum value and inputs it as node information into the graph neural network. Since the information on the type of active component (semiconductor) (for power supply circuit or operational amplifier circuit, etc.) is the same as the correct answer data, it is not input, and the component information of the active component is 0.

[0393] However, the component information of the active circuit may not be 0, and appropriate information may be selected.

[0394]

[0395] In addition, regarding GND, IN, and OUT, they are also 0 in the same way as the active components. When the inference calculation is performed without changing other conditions compared with the calculation, it can be confirmed that, at the same number of iterations, the inference accuracy for the test data becomes 98.90%. Figure 14

[0396] ​​Through the learning of the graph neural network by the processing unit 12, for a circuit, the type of the circuit can be classified only based on the link information. In addition, a common identification number is assigned to the semiconductor elements. When the type of the semiconductor element is set as the identification number, it is consistent with the type of the circuit. Therefore, even without learning the link information, the inference accuracy becomes higher. Therefore, the information possessed by the semiconductor elements is discarded, and information other than the semiconductor elements is not included. The processing unit 12 updates the component names in the component name list and the combination list through the identification numbers assigned to the respective component names in this way.

[0397] Variant Example 2

[0398] The processing unit 12 can also use a data set formed by combining a graph network and the correct answer data of the characteristics of the circuit respectively assigned to multiple circuits as learning data, and simultaneously learn the generation network and the recognition network in the generative adversarial network. Input data representing characteristics similar to the correct answer data is input into the generation network, thereby generating a new graph network. By combining the generative adversarial network with the graph neural network, a circuit diagram can be generated according to circuit specifications such as the desired output signal waveform.

[0399] The processing unit 12 simultaneously learns the neural network on the generator side (Generator) in the generative adversarial network, that is, the generation network, and the neural network on the discriminator side (Discriminator), that is, the recognition network. Then, the processing unit 12 improves the performance of the generation side, and performs learning of the graph neural network in such a way that the difference between the circuit or the output of the circuit that is the supervised data and the output of the circuit on the generation side becomes smaller. Thereby, input data can be generated according to the correct answer data. That is, when the required design requirements are used as the correct answer data, the combination of nodes and edges that satisfies the correct answer data, that is, the input data, can be generated.

[0400] Furthermore, not only the output signal, but also multiple data such as heat generation or the cost of components can be used as the correct answer data to make the generative adversarial network learn.

[0401] In this case, a circuit that optimizes the signal waveform flowing through each edge, the heat generation at each node, the power at each node, or the cost of the entire circuit can be generated.

[0402] In addition, since the circuit can be designed in a short time, it is possible to re-evaluate the requirement specifications or the cost at the initial stage of the design.

[0403] In order to generate a specific waveform at a node that is a circuit component, nodes with unknown characteristics or types can also be given, the characteristics or types of the components are predicted, and the waveform is optimized.

[0404] The prediction of the characteristics of the components can be achieved by using the generative adversarial network to generate the node attributes in the graph neural network.

[0405] The prediction of the type of component can be achieved by a technique of classifying nodes in a graph neural network.

[0406] In addition, a part of the type of nodes of the correct answer data as learning data is set as a black box, and as self-supervised learning, the graph neural network is made to learn to predict the type of nodes. Thus, it is also possible to use the learned graph neural network to predict the type of nodes.

[0407] In addition, the information processing device 1 can also use the data for which the calculation related to the large-scale circuit diagram has been completed to perform learning of the graph neural network, and use the learned graph neural network to predict the voltage applied to the component or the frequency characteristics of the voltage.

[0408] This can be achieved by an existing technique of generating attribute information of nodes in a graph neural network using a generative adversarial network. However, since Kirchhoff's law, which is a physical constraint, cannot be violated, it can be achieved by a constrained generative adversarial network.

[0409] Alternatively, a part of the voltage or the frequency characteristics of the voltage of the correct answer data as learning data is set as a black box, and as self-supervised learning, the graph neural network is made to learn to predict the voltage or the frequency characteristics of the voltage. Thus, it is also possible to use the learned graph neural network to predict the voltage or the frequency characteristics of the voltage.

[0410] Furthermore, the information processing device 1 predicts the existing connections between nodes to generate a specific waveform for the edges that are the wirings within the circuit, whereby a circuit corresponding to the design purpose can be generated.

[0411] This corresponds to link prediction in the graph neural network. After making a graph network according to the present embodiment, the graph neural network can be used to perform prediction using an existing technique.

[0412] Alternatively, a part of the presence or absence of edges between nodes of the correct answer data as learning data is set as a black box, and as self-supervised learning, the graph neural network is made to learn to predict the presence or absence of edges between nodes. Thus, it is also possible to use the learned graph neural network to predict the presence or absence of edges between nodes in an unknown circuit (graph network).

[0413] For example, it is also possible to use a graph neural network that has been learned using the calculation result for a large-scale circuit diagram that is difficult to simulate to predict the current applied to the component and the frequency characteristics of the current.

[0414] Specifically, similar to the case of generating node attributes using a generative adversarial network as described above, the processing unit 12 gives a data set obtained by combining a graph network and correct answer data as learning data to the nodes. The correct answer data is a matrix having, as elements of node attributes, feature amounts obtained by assigning voltages or frequency characteristics of voltages to respective nodes in the graph network. Then, as a generative adversarial network for predicting voltages or frequency characteristics of voltages, a graph neural network can also be used to learn the relationship between the graph network generated from a circuit diagram and voltages or frequency characteristics of voltages, and the graph neural network is used to predict voltages or frequency characteristics of voltages in some or all of the nodes in the graph network that are not used in this learning.

[0415] The generative adversarial network includes a generator network and a discriminator network. The generator network predicts voltages or frequency characteristics of voltages by hiding the computation-completed results of learning data, and the discriminator network identifies the correctness of the generated prediction. In the generative adversarial network, the generator network and the discriminator network are learned simultaneously to reduce the difference between the identification result and the computation-completed results of learning data.

[0416] Alternatively, a part of the current and the frequency characteristics of the current in the correct answer data as learning data is set as a black box, and as self-supervised learning, the graph neural network is made to learn to predict the current and the frequency characteristics of the current. Thereby, it is also possible to use the learned graph neural network to predict the current and the frequency characteristics of the current in an unknown circuit (graph network).

[0417] In addition, the processing unit 12 can also use, as learning data, a data set obtained by combining a graph network and data including the types of components corresponding to the respective nodes in the graph network, and perform learning of a graph neural network for predicting the types of components, and use the graph neural network to predict the types of components of some or all of the nodes in the graph network that are not used in the learning. This is to create a graph network that is input data for creating a graph neural network from a circuit diagram and learning data having output data as the types of components corresponding to the nodes, and perform supervised learning using this learning data as supervised data. Thereby, it is possible to use the learned graph neural network to predict the types of components used in an arbitrary graph network.

[0418] Furthermore, the processing unit 12 can also use, as learning data, a data set obtained by combining a graph network and correct answer data, and perform learning of a graph neural network for predicting the current or the frequency characteristics of the current in an edge, and use the graph neural network to predict the current or the frequency characteristics of the current in some or all of the edges in the graph network that are not used in the learning. The correct answer data is a matrix having, as elements, feature amounts representing the current or the frequency characteristics of the current in the respective edges of the graph network.

[0419] A graph network that creates input data for a graph neural network based on a circuit and learning data in which output data is set to a current corresponding to an edge or a frequency characteristic of the current is used as supervised data for supervised learning. Thus, the learned graph neural network can be used to predict the current or the frequency characteristic of the current in an arbitrary graph network.

[0420] In addition, when there is sufficient learning data, similar to the case of generating node attributes using the adversarial generative network described above, the adversarial generative network or self-supervised learning can be used to predict the current or the frequency characteristic of the current in an arbitrary graph network. The prediction of the current or the frequency characteristic of the current in an arbitrary graph network can be achieved by methods such as supervised learning, adversarial generative network, or self-supervised learning.

[0421] Here, supervised learning is effective when the dataset has few label errors and the bias (deviation) and variance of the entire dataset are small. The adversarial generative network is effective when the dataset is large and an inverse problem solution is required, such as when optimizing the entire circuit. Self-supervised learning is effective when it is difficult to attach labels due to an increase in the amount of calculation, when there are many label errors, or when more abundant computing resources are available.

[0422] In addition, it is also possible to perform transfer learning or fine-tuning on the result of the graph neural network obtained by self-supervised learning, that is, the weight matrix obtained by learning, and perform supervised learning, etc. in problems with insufficient datasets, and they can also be used in combination. In this way, the information processing device 1 can also change the structure of the graph neural network, the learning method, the method of providing supervised data, etc. according to the given conditions or the obtained results.

[0423] Furthermore, the processing unit 12 can also use a dataset formed by combining a graph network and correct answer data as learning data to perform learning of a graph neural network for predicting the power or the frequency characteristic of the power in at least one of nodes and edges, and use the graph neural network to predict the power or the frequency characteristic of the power in at least one of a part or all of the nodes and edges of a graph network not used in the learning. The correct answer data is a matrix having, as elements, characteristic quantities representing the power or the frequency characteristic of the power in at least one of a part or all of the nodes and edges of the graph network.

[0424] In this case, supervised learning of a graph neural network with the graph network as the input and the power or the frequency characteristic of the power as the output is also performed. The power or the frequency characteristic of the power can be inferred from the unknown input of the learned graph neural network thus obtained.

[0425] In addition, the input is set as a graph network, the power or the frequency characteristics of the power are predicted according to the generation network, and the graph neural network is learned by using the recognition network to reduce the difference between the prediction result and the correct data. The power or the frequency characteristics of the power can be inferred from the unknown input of the learned graph neural network thus obtained.

[0426] Furthermore, a self-supervised learning of a graph neural network is performed in which the input is set as a graph network and the learning is performed in such a way as to hide a part of the power or the frequency characteristics of the power and predict the hidden value. The power or the frequency characteristics of the power can be inferred from the unknown input of the learned graph neural network thus obtained.

[0427] In the past, even for prediction calculations that require a long time, by using inference based on a graph neural network, it has been possible to predict the output in real time without using a circuit simulator. For example, after roughly inferring using a graph neural network, the prediction is interpolated by the calculation of a circuit simulator, whereby the number of times of using the circuit simulator that requires prediction calculation time and calculation cost can be reduced. Furthermore, the results calculated by using a circuit simulator or the measured results can also be reused as supervised data.

[0428] Modification Example 3

[0429] In Modification Example 3, the following situation is described: the wiring has a current direction, the component name list can have a voltage with a specific frequency or the frequency characteristics of the voltage, and furthermore, the combination list can have a current with a specific frequency or the frequency characteristics of the current.

[0430] In the current direction, according to Figure 6 the netlist of the circuit shown, the following combination list is obtained.

[0431] (1); (IN,A)

[0432] (2); (A,B)

[0433] (3); (B,C),(C,D),(D,B)

[0434] (4); (D,OUT)

[0435] G-A; (GND,A)

[0436] G-B; (GND,B)

[0437] G-C; (GND,C)

[0438] For example, in (IN,A), considering the writing order, when written as (IN,A), it can be defined as the current direction from the IN terminal to the A terminal.

[0439] When applying the component name list and the wiring name list to graph theory, the component name list is the node and the wiring name list is the edge. Without considering the current direction, the graph network becomes an undirected graph.

[0440] On the other hand, by defining the writing order, the graph network can be considered as a directed graph. In addition, in the case of a circuit including alternating current, the current direction cannot be correctly defined only by the circuit diagram.

[0441] In the case of a directed graph, the circuit is put into an operating state through circuit simulation or actual measurement, a pulsed signal that has no influence on the operation is superimposed, and at the same time, multiple points on the wiring to be measured are observed using a voltage probe or a current probe. Thus, the current direction can be grasped based on the arrival time difference. However, in circuit simulation, no time difference occurs on the wiring, so it is difficult to detect.

[0442] In this case, the processing unit 12 virtually configures a small inductor on the wiring at a level of the residual inductance of the wiring (about 1 nH / mm), and the current direction can be inferred based on the time difference of the voltage or current change at both ends of the inductor.

[0443] In addition, in communication, signals sometimes flow bidirectionally. In this case, in the combination list, not only (A, B) but also (B, A) is included, so that the signal can be processed as flowing bidirectionally.

[0444] In graph theory, the combination list can be defined as an adjacency matrix.

[0445] To form an adjacency matrix, a square matrix with the same number of rows and columns as the maximum value of the elements of the combination list is prepared, the rows and columns of the square matrix are made to correspond to the combination list, and for example, 1 is input to the corresponding part, and all non-corresponding parts are set to 0. Thus, the adjacency matrix can be generated.

[0446] For example, when (5, 3) is placed in the combination list, the 5th row and 3rd column are set to 1, and thus the adjacency matrix can be generated. Without considering the current flow in the circuit, this adjacency matrix becomes a symmetric matrix. Therefore, when the above (5, 3) exists in the combination list, 1 is input to both the 5th row and 3rd column and the 3rd row and 5th column.

[0447] On the other hand, when considering the current direction in the circuit, only one of the 5th row and 3rd column and the 3rd row and 5th column is made 1, and the other is set to 0. As a result, it becomes a symmetric matrix without considering the current direction, while it becomes an asymmetric matrix when considering the current direction.

[0448] In both the case of not considering the current direction and the case of considering the current direction, the adjacency matrix becomes an upper triangular matrix or a lower triangular matrix.

[0449] Specifically, in the following Embodiment 2, there is no self-loop, and thus, the adjacency matrix becomes an upper triangular matrix with a diagonal component of 0 or a lower triangular matrix with a diagonal component of 0.

[0450] However, as long as there is one two-way element in the circuit, such as an antenna or a communication signal, where both reception and transmission signals are carried out using one wiring, it does not become an upper triangular matrix or a lower triangular matrix, but an asymmetric matrix.

[0451] In addition, in the component name list, the voltage at a specific frequency in the circuit or the frequency characteristics of the voltage can be set in the same way as component constants.

[0452] When setting the frequency characteristics in the component name list, it is necessary to convert the frequency characteristics into discrete values and input the signal as the amplitude of discrete frequencies.

[0453] For example, when it is desired to incorporate the frequency characteristics from 1 MHz to 10 MHz, it is sufficient to set 10 elements attached to each component at 1 MHz intervals.

[0454] In this case, it is set as a matrix having the same number of rows as the number of components and the number of columns corresponding to the frequency scale (in the range of 1 MHz to 10 MHz, the 1 MHz scale has 10 columns).

[0455] However, the frequency band or scale needs to be an equal condition for all circuit diagrams and all components used in the processing.

[0456] In addition, a 1 MHz scale is shown in the range of 1 MHz to 10 MHz, but if it is shared among all components, the interval of the frequency scale can be logarithmic or arbitrary, and it can also be uneven.

[0457] Furthermore, the order of the frequencies can also be different, and they can be combined in such a way that the identification numbers and frequency characteristics defined by the component type or component model form different columns, and the component name list can be constructed as a single matrix.

[0458] Furthermore, the current at a specific frequency or the frequency characteristics of the current can be assigned to the combination list. In this case, it can be considered in the same way as the frequency characteristics of the voltage.

[0459] If the frequency band and frequency scale are the same for all circuit diagrams and all wirings, the combination list can be input as the following matrix: the vertical axis has the number of rows corresponding to the number of combinations in the combination list, and the horizontal axis has the number of columns corresponding to the number of frequency scales (in the range of 1 MHz to 10 MHz, the 1 MHz scale has 10 columns).

[0460] However, regarding the combination list, the combination itself has meaning, and it is not preferable to assign current information to the combination list in the same way as the component name list. Therefore, it is preferable to define these frequency characteristics as separate matrices and assign them to the combination list as attribute information of the wiring (edge attribute in graph theory).

[0461] The combination list has rows corresponding to the number of combinations, so it can also be used for directed graphs. Even when the frequency characteristics of the outgoing current and the incoming current are different, it can be processed as different matrices.

[0462] In addition, for the combination list, information other than current or the frequency characteristics of current, such as the length or thickness of the wiring, can be input as information in different columns into the above-mentioned separate matrix.

[0463] As described above, the information processing apparatus 1 according to Embodiment 1 includes: an acquisition unit 11 that acquires a netlist of a circuit; and a processing unit 12 that extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names representing a ground terminal, an input terminal, and an output terminal, creates an updated wiring name list by removing wiring names representing a ground wiring, an input wiring, and an output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and the combination list.

[0464] Thereby, the information processing apparatus 1 can provide list information that can suppress information degradation caused by converting a circuit into a graph network.

[0465] The information processing apparatus 1 according to Embodiment 1 includes: an acquisition unit 11 that acquires a netlist of a circuit; and a processing unit 12 that extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names representing a ground terminal, an input terminal, and an output terminal, creates an updated wiring name list by removing wiring names representing a ground wiring, an input wiring, and an output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names and their corresponding wiring names, and outputs the updated component name list and the combination list.

[0466] Thereby, the information processing apparatus 1 can provide list information that can suppress information degradation caused by converting a circuit into a graph network. Furthermore, since the information processing apparatus 1 can suppress an increase in the number of component combinations, it can reduce an increase in the amount of calculation and calculation time required for processing by a graph neural network using the list information including the combination list.

[0467] In the information processing apparatus 1 according to the first embodiment, the processing unit 12 outputs an updated component name list and a combination list in which the component names are replaced with the identification numbers inherent to each feature of the components. Thereby, the information processing apparatus 1 represents the list information numerically, thereby being able to reduce the amount of information and prevent information degradation that occurs when converting from the list information to a graph network. This is because when the definition that converts the features of the components into numerical values is used in reverse, the features of the components can be determined based on the numerical values, that is, the features of the components and the numerical values are bijective.

[0468] In the information processing apparatus 1 according to the first embodiment, the processing unit 12 defines the identification numbers inherent to each type of component. Thereby, the information processing apparatus 1 represents the list information numerically, thereby being able to reduce the amount of information and prevent information degradation that occurs when converting from the list information to a graph network. This is because when the definition that converts the types of components into numerical values is used in reverse, the types of components can be determined based on the numerical values, that is, the types of components and the numerical values are bijective.

[0469] In the information processing apparatus 1 according to the first embodiment, the processing unit 12 defines the identification numbers inherent to each model of component. Thereby, the information processing apparatus 1 represents the list information numerically, thereby being able to reduce the amount of information and prevent information degradation that occurs when converting from the list information to a graph network. This is because when the definition that converts the models of components into numerical values is used in reverse, the models of components can be determined based on the numerical values, that is, the types of components and the numerical values are bijective.

[0470] In the information processing apparatus 1 according to the first embodiment, the processing unit 12 replaces the component names in the component name list with the rows or columns of the feature quantity matrix obtained by performing one-hot expression on the features of the components. Thereby, the information processing apparatus 1 can perform matrix calculations on the features of the components for the component names in the component name list. This is because when the definition that converts the features of the components into one-hot expression is used in reverse, the features of the components can be determined based on the one-hot expression.

[0471] In the information processing apparatus 1 according to the first embodiment, when the circuit includes two or more semiconductors, the processing unit 12 changes the elements corresponding to the semiconductors in the feature quantity matrix to different values for each semiconductor. Thereby, the information processing apparatus 1 can prevent information degradation that occurs when converting from the list information to a graph network. This is because when the definition that converts the semiconductors into the elements corresponding to each semiconductor is used in reverse, the semiconductors can be determined based on the elements corresponding to the semiconductors.

[0472] In the information processing apparatus 1 of Embodiment 1, the processing unit 12 replaces the elements corresponding to the passive circuits in the feature quantity matrix with the function values calculated by substituting the circuit constants of the components into a function including a logarithm. Thus, the information processing apparatus 1 represents the list information numerically, thereby being able to reduce the amount of information and prevent information degradation that occurs when converting from the list information to a graph network. This is because the circuit constant is a real number greater than 0 and has a bijective relationship with the function including a logarithm. Therefore, the numerical value of the original circuit constant can be calculated based on the numerical value obtained after applying the function to the function including a logarithm.

[0473] In the information processing apparatus 1 of Embodiment 1, the processing unit 12 performs both or one of normalization and standardization on the function values. Thus, the information processing apparatus 1 represents the list information numerically, thereby being able to reduce the amount of information and prevent information degradation that occurs when converting from the list information to a graph network. This is because in normalization or standardization, the value before performing normalization or standardization and the value after performing normalization or standardization also have a bijective relationship. Therefore, conversion can be performed bidirectionally.

[0474] In the information processing apparatus 1 of Embodiment 1, when there are combinations of three or more component names corresponding to one wiring name in the combination list, the processing unit 12 decomposes each of them into two combinations. Thus, the information processing apparatus 1 can easily create the adjacency matrix of the graph network based on the combination list.

[0475] In the information processing apparatus 1 of Embodiment 1, when the combination list has three or more component names, the processing unit 12 decomposes each of them into lists having two component names.

[0476] Thus, the information processing apparatus 1 can prevent information degradation that occurs when converting from the list information to a graph network.

[0477] In the information processing apparatus 1 of Embodiment 1, the acquisition unit 11 acquires the netlists of two or more circuits respectively. The processing unit 12 extracts the component name lists from the respective netlists, combines the extracted component name lists into one component name list, and removes the duplicate component names from the combined one component name list. Thus, the information processing apparatus 1 can suppress an increase in the amount of information in the component name list.

[0478] In the information processing apparatus 1 of Embodiment 1, the component name list is a node in the graph network, the wiring name list is an edge in the graph network, and the combination list is an adjacency matrix in the graph network. Thus, the information processing apparatus 1 can use the list information as a graph network.

[0479] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 performs a search process by referring to a database including a semiconductor as a noise source and terminal numbers of the semiconductor, extracts a current loop of the semiconductor, and ends the search process. In this search process, starting from a terminal corresponding to the terminal number in the circuit, adjacent components are continuously searched under the condition that the same component is not passed through more than twice. Thus, the information processing apparatus 1 can search for a loop path such as a semiconductor, a capacitor, a coil, a ground, and a semiconductor.

[0480] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 determines whether there is a component representing a noise filter in the current loop. Thus, the information processing apparatus 1 can extract a noise filter provided in the current loop, which is a path through which current flows.

[0481] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 extracts the characteristics of a semiconductor to be searched and the characteristics of a current loop representing the semiconductor from one or more circuits including one or more semiconductors, and searches for a semiconductor similar to the semiconductor to be searched using the extracted characteristics of the semiconductor and the current loop. Thus, the information processing apparatus 1 can search for similar circuits.

[0482] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 extracts a combination list consistent with the direction of current flow, and generates an adjacency matrix of an asymmetric matrix based on the extracted combination list. Thus, for a circuit in which the direction of current flow is known, the information processing apparatus 1 can also suppress the occurrence of information degradation.

[0483] In the information processing apparatus 1 according to Embodiment 1, in the adjacency matrix, the processing unit 12 sets the amplitude of the current to a real number between components that are connected to each other, and sets the amplitude of the current to 0 between wirings that are not connected. Thus, for a circuit in which the direction of current flow is known, the information processing apparatus 1 can also suppress the occurrence of information degradation.

[0484] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 sets a combination of nodes and edges as input data of a graph neural network. Thus, the information processing apparatus 1 can perform learning of a graph neural network using a graph network.

[0485] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses a data set obtained by combining a graph network and circuit classification data respectively assigned to a plurality of circuits as learning data, performs learning of a graph neural network for classifying circuits, and inputs the graph network not used in this learning to the graph neural network to classify the circuits. Thus, the information processing apparatus 1 can classify circuits.

[0486] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses, as learning data, a data set obtained by combining a graph network and correct solution data of the characteristics of each of a plurality of circuits, and simultaneously performs learning of a generation network and a recognition network in a generative adversarial network. The processing unit 12 inputs data representing characteristics similar to the correct solution data into the generation network, thereby generating a new graph network.

[0487] Accordingly, the information processing apparatus 1 can automatically design a circuit corresponding to the new graph network.

[0488] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses, as learning data, a data set obtained by combining a graph network and correct solution data, and performs learning of a graph neural network for predicting a voltage applied to a node or a frequency characteristic of the voltage. The processing unit 12 uses the graph neural network to predict a voltage or a frequency characteristic of the voltage in some or all of the nodes in the graph network that was not used in the learning. The correct solution data is a matrix having, as elements, feature amounts obtained by applying a voltage or a frequency characteristic of the voltage to each node in the graph network. Accordingly, the information processing apparatus 1 can predict an output voltage or a frequency characteristic of the output voltage of an unknown circuit without performing circuit simulation.

[0489] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses, as learning data, a data set obtained by combining a graph network and data including types of components corresponding to the respective nodes in the graph network, and performs learning of a graph neural network for predicting types of components. The processing unit 12 uses the graph neural network to predict types of components in some or all of the nodes in the graph network that were not used in the learning. Accordingly, the information processing apparatus 1 can predict types of components.

[0490] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses, as learning data, a data set obtained by combining a graph network and correct solution data, and performs learning of a graph neural network for predicting a current in an edge or a frequency characteristic of the current. The processing unit 12 uses the graph neural network to predict a current or a frequency characteristic of the current in some or all of the edges in the graph network that was not used in the learning. The correct solution data is a matrix having, as elements, feature amounts representing a current or a frequency characteristic of the current in each edge of the graph network.

[0491] Accordingly, the information processing apparatus 1 can predict an output current or a frequency characteristic of the output current of an unknown circuit without performing circuit simulation.

[0492] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses, as learning data, a data set obtained by combining a graph network and correct answer data, and performs learning of a graph neural network for predicting power or the frequency characteristics of power in at least one of nodes and edges. Then, the processing unit 12 uses the graph neural network to predict power or the frequency characteristics of power in at least one of a part or all of the nodes and edges included in the graph network that was not used in the learning. Here, the correct answer data is a matrix having, as elements, feature amounts indicating power or the frequency characteristics of power in at least one of a part or all of the nodes and edges included in the graph network. Thus, the information processing apparatus 1 can predict the output power or the frequency characteristics of the output power of an unknown circuit without performing circuit simulation.

[0493] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses the graph network as learning data, and performs learning of a graph neural network for predicting whether there is an edge between nodes in the graph network. Then, the processing unit 12 uses the graph neural network to predict whether there is an edge between nodes in the graph network that was not used in the learning.

[0494] Thus, the information processing apparatus 1 can predict whether there is an edge between nodes in the graph network that was not used in the learning.

[0495] In the information processing apparatus 1 according to Embodiment 1, the processing unit 12 uses the graph network as learning data, and performs learning of a graph neural network for clustering circuits into a finite number according to their characteristics. Then, the processing unit 12 uses the graph neural network to cluster the graph network that was not used in the learning, thereby classifying the graph network into similar circuit groups. Thus, the information processing apparatus 1 can classify similar circuit groups.

[0496] In the information processing method according to Embodiment 1, the information processing apparatus 1 executes the following steps: obtaining a netlist of a circuit; extracting a component name list and a wiring name list from the netlist; creating an updated component name list by adding component names representing a ground terminal, an input terminal, and an output terminal; creating an updated wiring name list by removing wiring names representing a ground wiring, an input wiring, and an output wiring; and extracting, from the component names in the updated component name list, component names corresponding to the wiring names in the updated wiring name list, and creating a combination list including the extracted component names. Thus, list information capable of suppressing information degradation caused by converting a circuit into a graph network can be provided.

[0497] In the information processing method of Embodiment 1, the information processing apparatus 1 performs the following steps: obtaining a netlist of a circuit; extracting a component name list and a wiring name list from the netlist; creating an updated component name list by adding component names representing ground terminals, input terminals, and output terminals; creating an updated wiring name list by removing wiring names representing ground wirings, input wirings, and output wirings; extracting component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and creating a combination list including the extracted component names and the corresponding wiring names; and outputting the updated component name list and the combination list. Thereby, it is possible to provide list information that can suppress information degradation caused by converting a circuit into a graph network. Furthermore, it is possible to suppress an increase in the number of component combinations. Therefore, it is possible to reduce an increase in the amount of calculation and calculation time required for processing by a graph neural network using the list information including the combination list.

[0498] Embodiment 2

[0499] Figure 16 is a block diagram showing a structural example of the information processing apparatus 1A according to Embodiment 2. In Figure 16 this, the information processing apparatus 1A obtains a netlist of a circuit, and uses the obtained netlist to provide list information that can suppress information degradation when converting the circuit into a graph network. The graph network of the circuit is information representing the circuit using nodes representing components and edges representing wirings. The graph network also includes information representing the feature amounts of nodes and edges.

[0500] As Figure 16 shown, the information processing apparatus 1A includes an acquisition unit 11 and a processing unit 12A.

[0501] The acquisition unit 11 executes a first process of obtaining a netlist of a circuit. For example, the information processing apparatus 1 is connected to a computer equipped with circuit design CAD, and the acquisition unit 11 obtains a netlist created using the circuit design CAD from the computer.

[0502] In addition, the acquisition unit 11 may obtain a circuit diagram model of a circuit operating in a circuit simulator, and convert the circuit diagram shown in the circuit diagram model into a netlist.

[0503] That is, regarding the acquisition of the netlist by the acquisition unit 11, it also includes a case where a netlist is obtained by converting a circuit diagram.

[0504] The processing unit 12A uses the component name list updated by adding the component names representing the ground terminal, input terminal, and output terminal, and the wiring name list updated by removing the wiring names representing the ground wiring, input wiring, and output wiring. It regards the component connected to three or more wirings as a two-terminal component with the same number of wirings as the number of wirings, adds the component name representing the two-terminal component to the updated component name list, removes the component name representing the component before being regarded as a two-terminal component from the updated component name list. When one terminal of the two-terminal component is connected to three or more wirings respectively, the other terminals of the two-terminal components are connected by new wirings, adds the wiring name representing the new wiring to the updated wiring name list, extracts the component names corresponding to the wiring names in the updated wiring name list from the updated component name list, creates a combination list containing the extracted component names, and outputs the updated component name list and the combination list. In addition, the processing unit 12A may also output the updated component name list and the combination list in which the component names are replaced with identification numbers.

[0505] The information processing device 1A is, for example, a computer connected to an information network.

[0506] This computer may be a server or a client capable of connecting to the cloud or the like via an information network, or may be an independent computer not connected to the information network. In addition, it may also be a computer used in a closed network environment within a factory, which is called edge computing.

[0507] In addition, the information processing device 1A may also be a smart phone, a tablet terminal, a PC, or a microcomputer.

[0508] Figure 17 It is a flowchart showing the information processing method of Embodiment 2, showing a series of operations based on the information processing device 1A. The acquisition unit 11 acquires a netlist (step ST1D). The processing unit 12A extracts a component name list from the netlist (step ST2D-1), and extracts a wiring name list from the netlist (step ST2D-2).

[0509] For example, the processing unit 12A stores all the component names included in the netlist in the component name list, and stores all the wiring names included in the netlist in the wiring name list.

[0510] Regarding the processing of step ST2D-1 and the processing of step ST2D-2, either one can be executed first, or they can be executed simultaneously.

[0511] The processing unit 12A adds the ground wiring, input wiring, and output wiring included in the netlist as a ground terminal, an input terminal, and an output terminal to the component name list (step ST3D-1). The processing unit 12A removes the ground wiring, input wiring, and output wiring from the wiring name list (step ST3D-2). Thus, information indicating the ground terminal, input terminal, and output terminal is retained as component information in the component name list, and therefore, it is possible to suppress information degradation when converting a circuit into a graph network using list information including the component name list. In addition, regarding the processing of step ST3D-1 and the processing of step ST3D-2, either one of them may be executed first, or they may be executed simultaneously.

[0512] The processing unit 12A determines whether there is a component connected to three or more wirings using the component name list and the wiring name list (step ST4D). In the case where there is no component connected to three or more wirings (step ST4D: No), the process proceeds to the processing of step ST5D. In Figure 17 this, the processing of step ST5D, step ST6D, step ST7D, step ST12D, step ST13D, and step ST14D is the same as the steps ST4, ST5, ST6, ST7, ST8, and ST9 in Figure 5 and thus the description thereof is omitted.

[0513] In the case where there is a component connected to three or more wirings (step ST4D: Yes), the processing unit 12A regards the component connected to three or more wirings as two-terminal components having the same number as the number of wirings (step ST8D). Next, the processing unit 12A assigns a new component name to the two-terminal components (step ST9D). Then, the processing unit 12A respectively connects three or more wirings to one terminal of the two-terminal components, and adds new wirings to connect the other terminals of the two-terminal components to each other (step ST10D). The processing unit 12A adds the wiring names assigned to the new wirings to the wiring name list (step ST11D).

[0514] In this way, the processing unit 12A connects between the two-terminal components decomposed from one component, and assigns new wiring names to the wirings used in each connection. Moreover, since the number of the other terminals of each two-terminal component is the same as the number of three or more wirings, the above wirings are connected to each terminal. By such conversion, it is possible to prevent self-loops or multiple edges from occurring, and it is possible to prevent information degradation when converting from a circuit to a graph network and when converting from a graph network to a circuit.

[0515] For example, a self-loop is generated when wiring from a terminal of a semiconductor to a different terminal of the same semiconductor without passing through a circuit component. However, in order to define the operation of the semiconductor, such wiring may be required, and in such a case, such wiring is generated. In Embodiment 1, such conditions are discarded, resulting in information degradation. However, as in Embodiment 2, by dividing into 2-terminal components, it is possible to convert to a graph network while maintaining such information.

[0516] In addition, in order to ensure current capacity using a power supply or the like, when there are multiple input terminals, multiple edges are generated when performing bus wiring from one semiconductor to another semiconductor.

[0517] In this case, in Embodiment 1, such conditions are also discarded, resulting in information degradation. However, as in Embodiment 2, by dividing into 2-terminal components, it is possible to convert to a graph network while maintaining such information.

[0518] For the wiring name list updated in step ST11D, the component names held by each wiring name are extracted in the same manner as in Embodiment 1, and a combination list of the component names is extracted.

[0519] Similar to Embodiment 1, when one wiring name holds three or more component names, for one wiring, it is decomposed into combinations of two components each.

[0520] In addition, identification numbers are assigned to each component name using the updated component name list, and the identification numbers are used to replace the identification numbers corresponding to each component name in the combination list.

[0521] Furthermore, the component name list is replaced with identification numbers, and the component name list replaced with these identification numbers and the combination list replaced with identification numbers are output, and the process is completed.

[0522] Figure 18 It is a circuit diagram showing an example (4) of a circuit. Figure 19 It is a circuit diagram showing an example (5) of a circuit. In Figure 18 Among them, there are three wirings between the input terminal "IN" and component A, between component B and component A, and between GND and component A connected to component A. Component A is decomposed into three 2-terminal components, and names such as A1, A2, and A3 are given respectively. In order to connect one terminal of the decomposed component to the terminals of the other decomposed components, connections are made between A1 and A2, between A2 and A3, and between A3 and A1 respectively. Names such as A1 - A2, A1 - A3, and A2 - A3 are given respectively. In addition, a name G - A3 is also given between A3 and GND. Similarly, component B is also decomposed, and names are given to the decomposed components and the wirings between the components. Thus, the circuit becomesFigure 18 The structure shown

[0523] Regarding Figure 19 Similarly, among Figure 18 the components with three or more wirings are Component A and Component E. Therefore, each component is decomposed, and names are assigned to the wirings between the decomposed components. In addition, for simplicity of explanation, the circuit diagram is set as the processing object. However, even a netlist can be processed in the same way.

[0524] The netlist shown in Embodiment 1 is shown below. When Component A is searched for in the # wirings in the netlist, it can be seen that it is held by wirings such as (1), (2), and GND.

[0525] Therefore, it can be determined that three wirings are connected to Component A, and it can be decomposed into a two-terminal component.

[0526] # Component

[0527] A

[0528] B

[0529] C

[0530] D

[0531] # Wiring

[0532] (1); IN, A

[0533] (2); A, B

[0534] (3); B, C, D

[0535] (4); D, OUT

[0536] GND; A, B, C

[0537] By decomposing the components into two-terminal components as Figure 18 shown, the component name list becomes "A1, A2, A3, B1, B2, B3, C, D, GND, IN, OUT", and the wiring name list becomes "(1), (2), (3), (4), A1 - A2, A2 - A3, A1 - A3, B1 - B2, B2 - B3, B1 - B3, G - A3, G - B3, G - C".

[0538] Similar to Embodiment 1, the processing unit 12A adds "IN", "OUT", and "GND" to the component name list, and removes "IN", "OUT", and "GND" from the wiring name list.

[0539] Similarly, by as Figure 19Decompose the components into 2-terminal components as such, the component name list becomes "A1, A2, A3, C, D, E1, E2, E3, F, GND, IN, OUT", and the wiring name list becomes "(1A), (2A), (3A), (4A), (5A), A1 - A2, A2 - A3, A1 - A3, E1 - E2, E2 - E3, E1 - E3, G - A3, G - E3, G - C".

[0540] Regarding components with 3 or more terminals, through the combination list generated based on the updated wiring name list and the combination list of 2-terminal components, Figure 18 The combination list of the shown circuit is as follows. (1) - (4), G - C, G - A3, G - B3 are generated from the netlist, and A1 - A2, A1 - A3, A1 - A3, B1 - B2, B2 - B3, B1 - B3 are the combination lists generated from the updated wiring name list.

[0541] (1); IN, A1

[0542] (2); A2, B1

[0543] (3); B2, C, D

[0544] (4); D, OUT

[0545] A1 - A2; A1, A2

[0546] A2 - A3; A2, A3

[0547] A1 - A3; A1, A3

[0548] B1 - B2; B1, B2

[0549] B2 - B3; B2, B3

[0550] B1 - B3; B1, B3

[0551] G - A3; GND, A3

[0552] G - B3; GND, B3

[0553] G - C; GND, C

[0554] Similarly, regarding Figure 19 the shown circuit diagram, the following combination list can also be extracted.

[0555] (1A); IN, A1

[0556] (2A); A2, D

[0557] (3A); D, C, E1

[0558] (4A); E2, F

[0559] (5A); F, OUT

[0560] A1 - A2; A1, A2

[0561] A2 - A3; A2, A3

[0562] A1 - A3; A1, A3

[0563] E1 - E2; E1, E2

[0564] E2 - E3; E2, E3

[0565] E1 - E3; E1, E3

[0566] G - A3; GND, A3

[0567] G - E3; GND, E3

[0568] G - C; GND, C

[0569] After decomposing the circuit components with three or more terminals in this way, it is the same as in Embodiment 1.

[0570] With Figure 18 The list of component names related to the circuit shown is "A1, A2, A3, B1, B2, B3, C, D, GND, IN, OUT", and with Figure 19 The list of component names related to the circuit shown is "A1, A2, A3, C, D, E1, E2, E3, F, GND, IN, OUT". After combining these two and removing duplicates, it becomes "A1, A2, A3, B1, B2, B3, C, D, E1, E2, E3, F, GND, IN, OUT". When assigning different identification numbers to each component name, the combined list is as follows, for example.

[0571] A1 → 1

[0572] A2 → 2

[0573] A3 → 3

[0574] B1 → 4

[0575] B2 → 5

[0576] B3 → 6

[0577] C → 7

[0578] D → 8

[0579] E1 → 9

[0580] E2 → 10

[0581] E3 → 11

[0582] F → 12

[0583] GND → 13

[0584] IN → 14

[0585] OUT → 15

[0586] When using the identification numbers, the list of component names related to the circuit shown in Figure 18 becomes "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15", and the list of component names related to the circuit shown in Figure 19 becomes "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15".

[0587] In addition, in the combined list, the part with more than 3 component names is also decomposed into 2, and each component name is replaced with the identification number. Thus, the combined list related to the circuit shown in Figure 18 is as follows.

[0588] (1); (14, 1)

[0589] (2); (2, 4)

[0590] (3); (5, 7), (7, 8), (8, 5)

[0591] (4); (8, 15)

[0592] A1 - A2; (1, 2)

[0593] A2 - A3; (2, 3)

[0594] A1 - A3; (1, 3)

[0595] B1 - B2; (4, 5)

[0596] B2 - B3; (5, 6)

[0597] B1 - B3; (4, 6)

[0598] G - A3; (13, 3)

[0599] G - B3; (13, 3)

[0600] G - C; (13, 7)

[0601] In addition, the combined list related to the circuit shown in Figure 19 is as follows.

[0602] (1A); (15, 1)

[0603] (2A); (2, 8)

[0604] (3A); (8, 7)(8, 9), (7, 9)

[0605] (4A); (10, 12)

[0606] (5A); (12, 15)

[0607] A1 - A2; (1, 2)

[0608] A2 - A3; (2, 3)

[0609] A1 - A3; (1, 3)

[0610] E1 - E2; (9, 10)

[0611] E2 - E3; (10, 11)

[0612] E1 - E3; (9, 11)

[0613] G - A3; (13, 3)

[0614] G - E3; (13, 11)

[0615] G - C; (13, 7)

[0616] As the output result of the processing unit 12A, the list of component names related to the Figure 18 shown circuit becomes "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15", and the combination list becomes "(14, 1)(2, 4)(5, 7)(7, 8)(8, 5)(8, 15)(1, 2)(2, 3)(1, 3)(4, 5)(5, 6)(4, 6)(13, 3)(13, 3)(13, 7)". In addition, related to the Figure 19 shown circuit, the list of component names becomes "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15", and the combination list becomes "(15, 1)(2, 8)(8, 7)(8, 9), (7, 9)(10, 12)(12, 15)(1, 2)(2, 3)(1, 3)(9, 10)(10, 11)(9, 11)(13, 3)(13, 11)(13, 7)".

[0617] In components of a circuit, especially in semiconductors, sometimes wiring is used to short - circuit between different terminals of the same semiconductor, thereby controlling the operation. A circuit having such a structure has a self - loop where the wiring comes out from itself and returns to itself.

[0618] However, although it is possible to create a combination list based on a netlist related to a circuit with a self-loop, it is not possible to convert the combination list with a self-loop back into the original netlist. This is because information degradation occurs when converting from the netlist to the combination list. In contrast, by decomposing a component into three or more components as described above, it is possible to eliminate the wiring that forms a self-loop. Therefore, the information processing apparatus 1A according to the second embodiment can create a combination list related to a circuit without a self-loop using a netlist related to a circuit with a self-loop. As a result, it is possible to convert from the combination list to the netlist without causing information degradation.

[0619] For example, in a circuit connected to a power supply with a large current, the wiring connected to the same power supply may be connected to multiple terminals of a semiconductor to distribute the current.

[0620] In addition, there is a circuit having a semiconductor that connects a pull-up power supply or a control signal to multiple terminals.

[0621] Their connection relationships form multi-edges. Therefore, when multi-edges are included in the combination list, similar to a self-loop, the information of each edge is not retained, and it is not possible to return the combination list to the netlist. Therefore, it is considered that information degradation has occurred.

[0622] In contrast, in the information processing apparatus 1A according to the second embodiment, even for a circuit having multi-edges, it is possible to return the combination list to the original netlist. Therefore, it is possible to convert the netlist into a combination list and inversely convert the combination list into a netlist without causing information degradation.

[0623] Figure 20 It is a schematic diagram showing an example (1) of a circuit and a graph network in the second embodiment. Figure 20 The shown circuit has a switching power supply U1, and when a voltage is applied between the input terminal and the ground GND, a different voltage is output between the output terminal and the ground GND. The result of extracting a component list and a combination list from the netlist related to this circuit is called a graph. In Figure 20 the shown circuit, it is not possible to convert the graph into a circuit diagram. In particular, Figure 20 the information of the wiring shown in gray in the upper circuit diagram is missing. Therefore, it is considered that information degradation has occurred when converting the graph.

[0624] Figure 21 It is a schematic diagram showing an example (2) of a circuit and a graph network in the second embodiment. Figure 21 The shown graph is configured to set an input terminal, an output terminal, and a ground terminal in the component name list as in the first embodiment. It can be seen that it becomes a circuit diagram with a structure Figure 20 similar to.

[0625] However, it can be seen that Figure 21The line between "IN" and "U1" in the figure of the following figure becomes a multiple edge. Furthermore, among the lines from "U1" to "OUT", there are lines passing through L1 and lines not passing through L1, and the circuit diagram is different from the figure. In most cases where the figure is utilized, a slight degradation of information is tolerated. Therefore, the method of Embodiment 1 has an effect compared to the prior art. However, the circuit diagram cannot be completely reversibly converted from the figure.

[0626] Figure 22 It is a schematic diagram showing an example (3) of the circuit and the graph network in Embodiment 2. The processing unit 12A decomposes components with three or more terminals in the circuit into two-terminal components. Thus, as Figure 22 shown, this circuit has a structure in which two-terminal components are connected to each wiring. That is, it becomes a structure in which all two-terminal components in the circuit are connected, so the figure and the circuit diagram can be reversibly converted.

[0627] When decomposing components as described above, it has the advantage of being able to reversibly convert the figure and the circuit diagram. On the other hand, it is necessary to consider the wiring between the decomposed components. That is, the wiring between the decomposed components increases, and thus the required information or the amount of calculation increases. Therefore, it is not necessarily better than Embodiment 1. Therefore, it is preferable to select and use the information processing method of Embodiment 1 or the information processing method of Embodiment 2 according to the inference accuracy required by the graph neural network or the allowable amount of calculation.

[0628] In Embodiment 2, as long as no self-loop or multiple edge is generated, the processing unit 12A may also remove the decomposed node and the wiring connected to the node. For example, when it can be determined that the multiple edge or self-loop itself has no information, the node and the wiring connected to the node may also be removed. By removing in this way, not only can the processing be speeded up, but also since unnecessary information is not included, the inference accuracy of the graph neural network can be improved.

[0629] Figure 23 It is a graph showing an example of the calculation result of the inference accuracy of the information processing apparatus 1A based on Embodiment 2, showing the result in the case where components with three or more terminals are decomposed.

[0630] For comparison with the result shown in Figure 15 which has the highest inference accuracy, only the identification number of the component is assigned to the node, and only the connection information between the identification numbers is input to the edge. Similar to Figure 15 , the correct answer data is a classification problem of classifying nine circuits according to each type.

[0631] Using the same as the one obtained Figure 15The same graph neural network as the one for the results shown learns including circuit constants, and uses the learned graph neural network to perform the above classification inference. As a result, the inference accuracy becomes 95.32%, which is 3.58% lower than that of the results shown in Figure 15 . It is presumed that this is because the learning includes the relationships between the two-terminal components obtained by decomposition, and there is little learning data when determining these unknowns. Thus, the information processing method in Embodiment 2 is a method suitable for cases where a highly reversible conversion between a netlist and a graph is required. However, there are also cases where the information processing method in Embodiment 1 is more excellent.

[0632] On the other hand, in the case where information that becomes the correct solution is obtained in advance through circuit simulation or the like, in the learning of the graph neural network, the update can also be stopped without learning the weights of the edges that have been calculated. In this case, even if the process of decomposing components with three or more terminals into two-terminal components is implemented, the inference accuracy of the graph neural network can be improved.

[0633] Thus, it is preferable to distinguish between using the information processing method of Embodiment 1 and the information processing method of Embodiment 2 according to the available data or purpose.

[0634] In the above example, the correct solution data is set to the type of circuit. However, the output waveform obtained by a circuit simulator or the frequency characteristics of the output waveform, etc. can also be used as learning data. In this case, by making use of the circuit simulator, the supervised data required for learning can be produced.

[0635] In addition, not limited to the output waveform, as long as the correct solution data is changed by predicting the signal waveform of a specific wiring in the circuit, predicting the area of the eye diagram of the signal waveform, predicting the heat generation at a specific part of the circuit, predicting the cost of the components required to form the circuit, or predicting the frequency characteristics of the electromagnetic noise appearing at the input terminal, the graph neural network can be freely learned according to the purpose.

[0636] In addition, by combining with circuit simulation to produce and use edge attribute information data, the same calculations as above can also be performed in a directed graph including the directionality of current.

[0637] It is also possible to assign frequency characteristics of voltage to nodes or frequency characteristics of current to edges. However, as shown in Modification 3, when inputting frequency data column by column for the attribute information of nodes or edges of a graph neural network one frequency at a time, it becomes a large matrix, and learning requires a large amount of computing time and computational complexity. In this case, it is also possible to prepare a high-performance computer with a large memory for learning. However, for example, by performing learning to convert frequency characteristics into vector information through graph embedding, even for input data with a large matrix containing frequency characteristics in a large-scale circuit, its computational complexity can be reduced, and graph neural network learning can be performed without using a high-performance computer.

[0638] In addition, for a circuit having a plurality of components connected in parallel to one wiring, even with the information processing method of the above-described Embodiment 2, the number of combinations of components increases. That is, when a circuit has a plurality of components connected in parallel to one wiring, the combinations of corresponding components in the combination list increase approximately in proportion to the square of the number of components connected in parallel to the wiring. Therefore, the computational complexity required for searching for current loops increases exponentially, and the search time also increases.

[0639] Therefore, the information processing apparatus 1A can also create a combination list including the combination of wiring names and component names to suppress an increase in the number of combinations of component names related to a large-scale circuit in which a plurality of components are connected in parallel to one wiring. For example, similar to Embodiment 1, the processing unit 12A creates a component name list updated by adding component names representing ground terminals, input terminals, and output terminals, and creates a wiring name list updated by removing wiring names representing ground wiring, input wiring, and output wiring. Then, as described above, the processing unit 12A regards a component connected to three or more wirings as a two-terminal component having the same number as the number of wirings, adds the component name representing the two-terminal component to the updated component name list, and removes the component name representing the component before being regarded as a two-terminal component from the updated component name list. Furthermore, the processing unit 12A defines a connection relationship in which one terminal of the two-terminal component is connected to three or more wirings respectively and the other terminal of the two-terminal component is connected by a new wiring, and adds the wiring name representing the new wiring to the updated wiring name list. Then, the processing unit 12A extracts the component name corresponding to the wiring name in the updated wiring name list from the updated component name list, creates a combination list including the extracted component name and the corresponding wiring name, and outputs the updated component name list and the combination list. That is, the combination list includes the component name corresponding to the wiring name in the updated wiring name list and the corresponding wiring name. The graph network converted from the list information including this combination list uses nodes to represent component names and wiring names, as Figure 10As shown, a node adjacent to a node with any component name becomes a node with a wiring name. Thus, the number of combinations can be made proportional to the first power of the number of components.

[0640] As described above, in the information processing apparatus 1A of the second embodiment, the processing unit 12A uses the component name list updated by adding component names representing the ground terminal, the input terminal, and the output terminal, and the wiring name list updated by removing the wiring names representing the ground wiring, the input wiring, and the output wiring. The component connected to three or more wirings is regarded as a two-terminal component having the same number as the number of wirings. The component name representing the two-terminal component is added to the updated component name list, and the component name representing the component before being regarded as the two-terminal component is removed from the updated component name list. When three or more wirings are connected to one terminal of the two-terminal component, the other terminals of the two-terminal component are respectively connected by new wirings. The wiring name representing the new wiring is added to the updated wiring name list. The component name corresponding to the wiring name in the updated wiring name list is extracted from the updated component name list, a combination list including the extracted component names is created, and the updated component name list and the combination list are output.

[0641] Thus, the information processing apparatus 1A can provide list information capable of suppressing information degradation generated when converting a circuit into a graph network. In addition, by defining the two-terminal component, it is possible to prevent self-loops or multiple edges from occurring, and to suppress information degradation generated when converting from a circuit to a graph network and when converting from a graph network to a circuit.

[0642] In the information processing apparatus 1A according to Embodiment 2, the processing unit 12A creates an updated component name list in which the component names are updated by additionally indicating the ground terminal, input terminal, and output terminal, and an updated wiring name list in which the wiring names indicating the ground wiring, input wiring, and output wiring are removed. A component connected to three or more wirings is regarded as a two-terminal component having the same number of terminals as the number of wirings, the component name indicating the two-terminal component is added to the updated component name list, and the component name indicating the component before being regarded as the two-terminal component is removed from the updated component name list. A connection relationship is defined in which one terminal of the two-terminal component is respectively connected to three or more wirings and the other terminals of the two-terminal component are connected by new wirings. The wiring name indicating the new wiring is added to the updated wiring name list, the component names corresponding to the wiring names in the updated wiring name list are extracted from the updated component name list, a combination list including the extracted component names and the corresponding wiring names is created, and the updated component name list and the combination list are output. Thereby, the information processing apparatus 1A can provide list information capable of suppressing information degradation generated when converting a circuit into a graph network. Furthermore, the information processing apparatus 1A can suppress an increase in the number of combinations of components, and thus can reduce the amount of calculation and calculation time required for processing of a graph neural network using the list information including the combination list.

[0643] In the information processing apparatus 1A according to Embodiment 2, the processing unit 12A outputs the updated component name list and the combination list in which the component names are replaced with the identification numbers inherent to each feature of the components. Thereby, the information processing apparatus 1A represents the list information numerically, and thus can reduce the amount of information and can prevent information degradation generated when converting from the list information into a graph network.

[0644] In the information processing method according to Embodiment 2, the information processing apparatus 1A executes the following steps: regarding a component connected to three or more wirings as a two-terminal component having the same number of terminals as the number of wirings, and adding the component name indicating the two-terminal component to the updated component name list; removing the component name indicating the component before being regarded as the two-terminal component from the updated component name list; for one terminal of the two-terminal component being respectively connected to three or more wirings, respectively connecting the other terminals of the two-terminal component by new wirings, and adding the wiring name indicating the new wiring to the updated wiring name list; extracting the component names corresponding to the wiring names in the updated wiring name list from the updated component name list, and creating a combination list including the extracted component names; and outputting the updated component name list and the combination list. Thereby, by defining the two-terminal component, it is possible to prevent self-loops or multiple edges from occurring, and it is possible to prevent information degradation during conversion from a circuit to a graph network and from a graph network to a circuit.

[0645] In the information processing apparatus 1A according to the second embodiment, as long as there are no self-loops or multiple edges in the wiring connecting the two-terminal components, the processing unit 12A removes nodes from the two-terminal components. Thereby, the information processing apparatus 1A can provide list information capable of suppressing information degradation when creating a circuit graph information.

[0646] In the information processing method according to the second embodiment, the information processing apparatus 1A performs the following steps: creating an updated component name list by adding component names representing ground terminals, input terminals, and output terminals, and creating an updated wiring name list by removing wiring names representing ground wiring, input wiring, and output wiring; regarding components connected to three or more wirings as two-terminal components having the same number as the number of wirings; adding the component names representing the two-terminal components to the updated component name list; removing the component names representing the components before being regarded as two-terminal components from the updated component name list; for one terminal of each two-terminal component, connecting three or more wirings respectively, and connecting the other terminals of the two-terminal components with new wirings respectively, and adding the wiring names representing the new wirings to the updated wiring name list; extracting the component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and creating a combination list including the extracted component names; and outputting the updated component name list and the combination list.

[0647] Thereby, it is possible to provide list information capable of suppressing information degradation generated when converting a circuit into a graph network.

[0648] Furthermore, by defining two-terminal components, it is possible to prevent self-loops or multiple edges from occurring, and to suppress information degradation generated when converting from a circuit into a graph network and when converting from a graph network into a circuit.

[0649] In the information processing method according to the second embodiment, the information processing apparatus 1A performs the following steps: extracting the component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and creating a combination list including the extracted component names and the corresponding wiring names; and outputting the updated component name list and the combination list. Thereby, it is possible to provide list information capable of suppressing information degradation generated when converting a circuit into a graph network. Furthermore, it is possible to suppress an increase in the number of combinations of components, and thus, it is possible to reduce an increase in the amount of calculation and calculation time required for processing of a graph neural network using the list information including the combination list.

[0650] In addition, combinations of the respective embodiments or deformations of arbitrary structural elements of the respective embodiments or omissions of arbitrary structural elements of the respective embodiments can be performed.

[0651] Industrial Applicability

[0652] The information processing apparatus of the present disclosure can be used, for example, for the design of circuits using circuit design CAD and substrate design CAD.

[0653] Description of reference numerals

[0654] 1, 1A: Information processing apparatus; 11: Acquisition unit; 12, 12A: Processing unit; 100: Input interface; 101: Output interface; 102: Processing circuit; 103: Processor; 104: Memory.

Claims

1. An information processing device, characterized in that, the information processing device has: an acquisition unit that acquires a netlist of a circuit; and a processing unit that extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names representing ground terminals, input terminals, and output terminals, creates an updated wiring name list by removing wiring names representing ground wiring, input wiring, and output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list containing the extracted component names, and outputs the updated component name list and the combination list.

2. The information processing device according to claim 1, characterized in that, the processing unit regards a component connected to three or more wirings as two-terminal components having the same number as the number of wirings, adds the component names representing the two-terminal components to the updated component name list, removes the component names representing the components before being regarded as the two-terminal components from the updated component name list, connects the three or more wirings to one terminal of the two-terminal component respectively, connects the other terminals of the two-terminal components with new wirings, adds a wiring name representing the new wiring to the updated wiring name list, extracts component names corresponding to the wiring names in the updated wiring name list from the updated component name list, creates the combination list containing the extracted component names, and outputs the updated component name list and the combination list.

3. An information processing device, characterized in that, the information processing device has: an acquisition unit that acquires a netlist of a circuit; and a processing unit that extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names representing ground terminals, input terminals, and output terminals, creates an updated wiring name list by removing wiring names representing ground wiring, input wiring, and output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list containing the extracted component names and their corresponding wiring names, and outputs the updated component name list and the combination list.

4. The information processing device according to claim 3, characterized in that, the processing unit regards a component connected to three or more wirings as two-terminal components having the same number as the number of wirings, adds the component names representing the two-terminal components to the updated component name list, removes the component names representing the components before being regarded as the two-terminal components from the updated component name list, connects the three or more wirings to one terminal of the two-terminal component respectively, connects the other terminals of the two-terminal components with new wirings, adds a wiring name representing the new wiring to the updated wiring name list, Extract the component names corresponding to the wiring names in the updated wiring name list from the updated component name list. Create the combination list including the extracted component names and their corresponding wiring names, and output the updated component name list and the combination list.

5. The information processing apparatus according to any one of claims 1 to 4, characterized in that the processing unit outputs the updated component name list and the combination list in which the component names are replaced with unique identification numbers common to each feature of the components.

6. The information processing apparatus according to claim 5, characterized in that the processing unit defines the unique identification numbers common to each type of component.

7. The information processing apparatus according to claim 5, characterized in that the processing unit defines the unique identification numbers common to each model of component.

8. The information processing apparatus according to claim 5, characterized in that the processing unit replaces the component names in the updated component name list with the rows or columns of the feature quantity matrix obtained by one-hot expressing the features of the components.

9. The information processing apparatus according to claim 8, characterized in that when the circuit includes two or more semiconductor elements, the processing unit changes the elements corresponding to the semiconductor elements in the feature quantity matrix into different values respectively.

10. The information processing apparatus according to claim 8, characterized in that the processing unit replaces the elements corresponding to the passive circuits in the feature quantity matrix with the function values calculated by substituting the circuit constants of the components into a function including logarithm.

11. The information processing apparatus according to claim 10, characterized in that the processing unit performs both or one of normalization and standardization on the function values.

12. The information processing apparatus according to claim 5, characterized in that when there are combinations of three or more component names corresponding to one wiring name in the combination list, the processing unit decomposes them into combinations of two component names respectively.

13. The information processing apparatus according to any one of claims 1 to 5, characterized in that the acquisition unit acquires the netlists of two or more circuits respectively, the processing unit extracts the component name lists from each of the netlists, combines the extracted component name lists into one component name list, and removes the duplicate component names from the combined one component name list.

14. The information processing apparatus according to claim 2, characterized in that as long as there is no self-loop or multi-edge in the wiring connecting the two-terminal components, the processing unit removes the nodes from the two-terminal components.

15. The information processing apparatus according to any one of claims 1 to 5, characterized in that the component name list is the nodes in the graph network, the wiring name list is the edges in the graph network, the combination list is the adjacency matrix in the graph network.

16. The information processing apparatus according to claim 15, characterized in that The processing unit performs a search process by referring to a database including semiconductor elements as noise sources and terminal numbers of the semiconductor elements, extracts a current loop representing the semiconductor element, and ends the search process. In the search process, starting from the terminal corresponding to the terminal number in the circuit, adjacent components are continuously searched under the condition that the same component among the components serving as the nodes is not passed through more than twice.

17. The information processing apparatus according to claim 16, wherein, the processing unit determines whether a noise filter is present in the current loop.

18. The information processing apparatus according to claim 16, wherein, the processing unit extracts the characteristics of the semiconductor element to be searched and the characteristics of the current loop representing the semiconductor element from one or more of the circuits including one or more of the semiconductor elements, and searches for the semiconductor element similar to the semiconductor element to be searched using the extracted characteristics of the semiconductor element and the characteristics of the current loop.

19. The information processing apparatus according to claim 16, wherein, the processing unit extracts the combination list consistent with the direction of current flow, and generates an adjacency matrix of an asymmetric matrix based on the extracted combination list.

20. The information processing apparatus according to claim 19, wherein, in the adjacency matrix, the processing unit sets the amplitude of the current to a real number between the connected components, and sets the amplitude of the current to 0 between the unconnected wirings.

21. The information processing apparatus according to claim 15, wherein, the processing unit uses the combination of nodes and edges as input data for a graph neural network.

22. The information processing apparatus according to claim 21, wherein, the processing unit uses a data set obtained by combining the graph network and circuit classification data respectively assigned to a plurality of the circuits as learning data, performs learning of the graph neural network for classifying the circuits, and inputs the graph network not used in the learning into the graph neural network to classify the circuits.

23. The information processing apparatus according to claim 21, wherein, the processing unit uses a data set obtained by combining the graph network and correct solution data of the characteristics of the respective circuits respectively assigned to a plurality of the circuits as learning data, simultaneously performs learning of a generation network and an identification network in an adversarial generation network, and inputs data representing characteristics similar to the correct solution data into the generation network to generate a new graph network.

24. The information processing apparatus according to claim 21, wherein, The processing unit uses a data set formed by combining the graph network and the correct solution data as learning data to perform learning of the graph neural network for predicting the voltage or frequency characteristics of the voltage assigned to the nodes, and uses this graph neural network to predict the voltage or frequency characteristics of the voltage in a part or all of the nodes in the graph network that is not used in this learning. The correct solution data is a matrix having, as elements, feature amounts obtained by assigning the voltage or frequency characteristics of the voltage to each node in the graph network.

25. The information processing apparatus according to claim 21, wherein, the processing unit uses a data set formed by combining the graph network and data including the types of components corresponding to the respective nodes in the graph network as learning data to perform learning of the graph neural network for predicting the types of components, and uses this graph neural network to predict the types of components of a part or all of the nodes in the graph network that are not used in the learning.

26. The information processing apparatus according to claim 21, wherein, the processing unit uses a data set formed by combining the graph network and the correct solution data as learning data to perform learning of the graph neural network for predicting the current or frequency characteristics of the current in the edges, and uses this graph neural network to predict the current or frequency characteristics of the current in a part or all of the edges in the graph network that are not used in the learning. The correct solution data is a matrix having, as elements, feature amounts indicating the current or frequency characteristics of the current in the respective edges of the graph network.

27. The information processing apparatus according to claim 21, wherein, the processing unit uses a data set formed by combining the graph network and the correct solution data as learning data to perform learning of the graph neural network for predicting the power or frequency characteristics of the power in at least one of the nodes and the edges, and uses this graph neural network to predict the power or frequency characteristics of the power in at least one of a part or all of the nodes and edges included in the graph network that are not used in the learning. The correct solution data is a matrix having, as elements, feature amounts indicating the power or frequency characteristics of the power in at least one of a part or all of the nodes and edges included in the graph network.

28. The information processing apparatus according to claim 21, wherein, the processing unit uses the graph network as learning data to perform learning of the graph neural network for predicting the presence or absence of edges between nodes in the graph network, and uses this graph neural network to predict the presence or absence of edges between nodes in the graph network that are not used in the learning.

29. The information processing apparatus according to claim 21, wherein, the processing unit uses the graph network as learning data to perform learning of the graph neural network for clustering the circuit into a finite number according to its characteristics, and uses this graph neural network to cluster the graph network that is not used in the learning, thereby classifying it into similar circuit groups.

30. An information processing method, wherein, an information processing apparatus executes the following steps: obtain a netlist of a circuit; extract a component name list and a wiring name list from the netlist; Create an updated component name list with component names for additional ground terminals, input terminals, and output terminals added; Create an updated wiring name list with wiring names for ground wiring, input wiring, and output wiring removed; Extract component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and create a combination list containing the extracted component names; and Output the updated component name list and the combination list.

31. The information processing method according to claim 30, wherein, the information processing device performs the following steps: Regard a component connected to 3 or more wirings as 2-terminal components with the same number as the number of wirings, and append the component names representing the 2-terminal components to the updated component name list; Remove the component names representing the components before being regarded as the 2-terminal components from the updated component name list; Connect one terminal of the 2-terminal component to each of the 3 or more wirings respectively, and connect the other terminals of the 2-terminal components to each other using new wirings, and append the wiring names representing the new wirings to the updated wiring name list; Extract component names corresponding to the wiring names in the updated wiring name list from the updated component name list, and create the combination list containing the extracted component names; and Output the updated component name list and the combination list.

32. An information processing method, wherein, the information processing device performs the following steps: Obtain the netlist of the circuit; Extract the component name list and the wiring name list from the netlist; Create an updated component name list with component names for additional ground terminals, input terminals, and output terminals added; Create an updated wiring name list with wiring names for ground wiring, input wiring, and output wiring removed; Extract component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and create a combination list containing the extracted component names and their corresponding wiring names; and Output the updated component name list and the combination list.

33. The information processing method according to claim 32, wherein, the information processing device performs the following steps: Regard a component connected to 3 or more wirings as 2-terminal components with the same number as the number of wirings, and append the component names representing the 2-terminal components to the updated component name list; Remove the component names representing the components before being regarded as the 2-terminal components from the updated component name list; Connect one terminal of the 2-terminal component to each of the 3 or more wirings respectively, and connect the other terminals of the 2-terminal components to each other using new wirings, and append the wiring names representing the new wirings to the updated wiring name list; Extract the component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and create the combination list including the extracted component names and their corresponding wiring names; and Output the updated component name list and the combination list.

34. The information processing method according to any one of claims 30 to 33,[[]]END]] characterized in that the information processing apparatus performs the following steps: Output the updated component name list and the combination list in which the component names are replaced with the inherent identification numbers common to each feature of the components.

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