Semiconductor device with variable polarization direction

Abstract

A semiconductor device includes a plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface of the barrier layer and the channel layer, where a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and where the priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer. The polarization direction of the barrier layer may be changed by applying an electric field on the barrier layer. The semiconductor device further includes a first source terminal and a second source terminal, where one of the first source terminal and the second source terminal is ohmic to electrons and the other is ohmic to holes. The semiconductor device also includes first and second drain terminals, a gate terminal, and a set terminal in ohmic contact with the channel layer.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having a variable polarization direction. Background Art

[0002] Modern semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), high electron mobility transistors (HEMTs), and insulated gate bipolar transistors (IGBTs) are typically fabricated using silicon (Si) semiconductor materials. However, the limited critical electric field and relatively high resistance of silicon make currently available commercial power devices, circuits, and systems bulky, further limiting the operating frequency. Thus, such commercial devices are not suitable for different types of applications, such as high-power electronics applications.

[0003] III-N semiconductor devices have many advantages over silicon-based devices. For example, III-N semiconductor devices can carry large currents, provide very low on-resistance, and operate at high voltages with fast switching times. III-N semiconductor devices are made of group-III nitride materials. Group-III nitride materials have a unique combination of physical properties useful in modern microelectronics and optoelectronics. These properties include wide bandgap, high saturation drift velocity, high breakdown voltage, high thermal conductivity, and remarkable chemical and thermal stability. Due to the above properties, group-III nitride materials are used to fabricate many electronic and optoelectronic devices.

[0004] However, despite these advantages of group-III nitride materials, there are still many technical challenges to be addressed. For example, it is difficult to control defects due to the lack of a natural substrate. Incorporating a high concentration of indium into In x Ga 1-x N alloys remains challenging due to phase separation and lattice mismatch between gallium nitride (GaN) and indium nitride (InN).

[0005] Therefore, there is still a need to explore the properties of group-III nitride materials and improve the performance / function of III-N semiconductor devices. Summary of the Invention

[0006] Some embodiments aim to provide a single-channel-layer-based III-N semiconductor device that can act as a p-channel field-effect transistor (also referred to as a p-FET) and an n-channel field-effect transistor (also referred to as an n-FET). Additionally or alternatively, some embodiments aim to provide a semiconductor device that acts as both a p-FET and an n-FET and occupies less circuit area. Additionally or alternatively, some embodiments aim to provide a semiconductor device with a high switching speed.

[0007] Some embodiments provide a semiconductor device that includes an epitaxial layer that includes a barrier layer and a channel layer. The semiconductor device also includes a plurality of terminals, e.g., a first source terminal, a second source terminal, a gate terminal, a first drain terminal, a second drain terminal, and a set terminal. In an embodiment, the first source terminal is ohmic to electrons and the second source terminal is ohmic to holes. The first drain terminal is ohmic to electrons and the second drain terminal is ohmic to holes. In some alternative embodiments, the first source terminal is ohmic to holes and the second source terminal is ohmic to electrons; and the first drain terminal is ohmic to holes and the second drain terminal is ohmic to electrons. The first drain terminal and the second drain terminal are interconnected by an interconnect to form a single output terminal. The gate terminal is disposed on the barrier layer. The set terminal is in ohmic contact with the channel layer.

[0008] Some embodiments are based on the recognition that in order for a semiconductor device to operate as a p-FET, the channel layer should include holes as majority charge carriers, and in order for a semiconductor device to operate as an n-FET, the channel layer should include electrons as majority charge carriers. For this purpose, whether the semiconductor device acts as a p-FET or an n-FET depends on the majority charge carriers in the channel layer.

[0009] Some embodiments are based on the recognition that the priority of the charge carriers in the channel layer (i.e., the majority charge carriers, holes or electrons) depends on the polarization direction of the barrier layer. According to an embodiment, the barrier layer is a group III nitride compound layer, e.g., a scandium-doped aluminum nitride (ScAlN) layer. The ScAlN material has ferroelectric properties. Ferroelectricity is a property of materials that have a spontaneous polarization that can be reversed by applying an external electric field. All ferroelectrics are pyroelectric, with the additional property that their natural electric polarization is reversible. For this purpose, the polarization direction of the barrier layer as an ScAlN layer can be changed by applying an electric field on the barrier layer.

[0010] Since the majority charge carriers in the channel layer depend on the polarization direction of the barrier layer, and the polarization direction of the barrier layer can be changed by applying an electric field on the barrier layer, an electric field can be applied on the barrier layer to switch the polarization direction of the barrier layer so that the semiconductor device can be used as both an n-FET and a p-FET.

[0011] For example, a first voltage can be applied between the gate terminal and the set terminal to form a two-dimensional electron gas (2-DEG) at the interface between the barrier layer and the channel layer. When a 2-DEG exists at the interface between the barrier layer and the channel layer, the semiconductor device acts as an n-FET. Similarly, a second voltage can be applied between the gate terminal and the set terminal to form a two-dimensional hole gas (2-DHG) at the interface between the barrier layer and the channel layer. When a 2-DHG exists at the interface between the barrier layer and the channel layer, the semiconductor device acts as a p-FET. The second voltage is different from the first voltage. For example, the first voltage applied between the gate terminal and the set terminal can correspond to a positive bias voltage, and the second voltage applied between the gate terminal and the set terminal can correspond to a negative bias voltage. In this way, the semiconductor device can act as both an n-FET and a p-FET.

[0012] In an embodiment, the channel layer is a gallium nitride (GaN) layer. Specifically, the channel layer corresponds to an unintentionally doped GaN layer. GaN is a binary III / V direct bandgap semiconductor and is a hard material with a wurtzite crystal structure. In an embodiment, the epitaxial layer (i.e., the barrier layer and the channel layer) is grown on the substrate by a deposition method. Examples of the substrate include a sapphire substrate, a GaN substrate, a silicon substrate, and a silicon carbide (SiC) substrate. The deposition method can include, for example, molecular beam epitaxy (MBE). MBE is an epitaxial process by which the growth of materials is carried out under ultra-high vacuum (UHV) conditions on a heated crystal substrate through the interaction of adsorbed substances provided by atomic or molecular beams. MBE provides several capabilities that are beneficial for the growth of high-purity epitaxial thin film metals. For example, the UHV conditions result in the highest achievable purity of the grown film.

[0013] In some embodiments, the materials of the first source terminal and the first drain terminal are different from the materials of the second source terminal and the second drain terminal. In other words, the first source terminal and the first drain terminal are made of a material different from the material used to fabricate the second source terminal and the second drain terminal. For example, the first source terminal and the first drain terminal are Ti-based n-type ohmic contacts, and the second source terminal and the second drain terminal are Ni-based p-type ohmic contacts. In another example, the first source terminal and the first drain terminal are gold (Au)-based n-type ohmic contacts, and the second source terminal and the second drain terminal are Au-based p-type ohmic contacts.

[0014] Alternatively, in some embodiments, instead of two source terminals and two drain terminals, the semiconductor device can include only one source terminal and one drain terminal, which makes the design of the semiconductor device simpler and more cost-effective.

[0015] Accordingly, one embodiment discloses a semiconductor device that includes a plurality of epitaxial layers, the plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, wherein a priority of charge carriers in the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is changed by applying an electric field to the barrier layer. The semiconductor device further includes: a first source terminal and a second source terminal, wherein one of the first source terminal and the second source terminal is ohmic to electrons and the other is ohmic to holes; a first drain terminal and a second drain terminal, wherein one of the first drain terminal and the second drain terminal is ohmic to electrons and the other is ohmic to holes; a gate terminal disposed on the barrier layer; and a set terminal that makes an ohmic contact with the channel layer.

[0016] Accordingly, another embodiment discloses a semiconductor device that includes a plurality of epitaxial layers, the plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, wherein a priority of charge carriers in the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is changed by applying an electric field to the barrier layer. The semiconductor device further includes: a source terminal; a drain terminal; a gate terminal disposed on the barrier layer; and a set terminal that makes an ohmic contact with the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1

[0018] Figure 1 A schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure is shown.

[0019] Figure 2A

[0020] Figure 2A A charge balance diagram of the semiconductor device in accordance with some embodiments of the present disclosure when the semiconductor device acts as an n-channel field effect transistor (n-FET) is shown.

[0021] Figure 2B

[0022] Figure 2B A charge balance diagram of the semiconductor device in accordance with some embodiments of the present disclosure when the semiconductor device acts as a p-channel field effect transistor (p-FET) is shown.

[0023] Figure 3

[0024] Figure 3 ​​​​​​​​A schematic diagram of a semiconductor device including a source terminal and a drain terminal according to some embodiments of the present disclosure is shown.

[0025] Figure 4

[0026] Figure 4 A schematic diagram is shown that illustrates the biaxial strain of Sc x Al (1-x) N, Ga x Al (1-x) N, and In x Al (1-x) N barriers pseudomorphically grown on relaxed indium nitride (InN), gallium nitride (GaN), and aluminum nitride (AlN) buffer layers.

[0027] Figure 5

[0028] Figure 5 A graph showing the piezoelectric coefficient versus the scandium (Sc) atomic content according to an embodiment of the present disclosure is shown.

[0029] Figure 6

[0030] Figure 6 A graph showing the piezoelectric coefficient versus the Sc atomic content according to an embodiment of the present disclosure is shown.

[0031] Figure 7

[0032] Figure 7 A graph showing the piezoelectric polarization versus the alloy composition x according to some embodiments of the present disclosure is shown.

[0033] Figure 8

[0034] Figure 8 A graph showing the predicted spontaneous polarization versus the metal atom content x for a metal-polar wurtzite crystal structure random Me x Al (1-x) N alloy according to some embodiments of the present disclosure is shown.

[0035] Figure 9

[0036] Figure 9 A graph showing the polarization-induced surface charge and total polarization versus the alloy composition x for barriers of different materials according to some embodiments of the present disclosure is shown.

[0037] Figure 10 ​​​​​​​​​​​​​​

[0038] Figure 10 Shows a graph of the relative permittivity with respect to alloy composition x according to some embodiments of the present disclosure.

[0039] Figure 11

[0040] Figure 11 Shows a graph of the bandgap with respect to alloy composition x according to some embodiments of the present disclosure.

[0041] Figure 12

[0042] Figure 12 Shows a graph of the polarization-induced electron layer charge with respect to alloy composition x according to some embodiments of the present disclosure.

[0043] The presently disclosed embodiments will be further explained with reference to the accompanying drawings. The drawings shown are not necessarily to scale, but generally focus on illustrating the principles of the presently disclosed embodiments. Detailed Embodiments

[0044] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, devices and methods are shown only in block diagram form in order not to obscure the present disclosure.

[0045] As used in this specification and the claims, the terms "such as", "for example", and "including", and the verbs "comprising", "having", "including", and their other verb forms, when used in conjunction with a list of one or more components or other items, are each to be construed as open-ended, meaning that the list should not be considered as excluding other, additional components or items. The term "based on" means at least in part based on. Further, it should be understood that the language and terminology used herein are for the purpose of description and should not be regarded as limiting. Any headings used in this specification are for convenience only and have no legal or limiting effect.

[0046] Figure 1 ​​​​Schematic diagram of a semiconductor device 100 in accordance with some embodiments of the present disclosure is shown. The semiconductor device 100 includes an epitaxial layer that includes a barrier layer 101 and a channel layer 103 such that a two-dimensional carrier density is formed at an interface 119 between the barrier layer 101 and the channel layer 103. Further, the semiconductor device 100 includes a buffer layer 105 and a substrate 107. The semiconductor device 100 includes a plurality of terminals, for example, a first source terminal 109a, a second source terminal 109b, a gate terminal 111, a first drain terminal 113a, a second drain terminal 113b, and a set terminal 115. The semiconductor device 100 further includes an insulating layer (not shown in the figure) between the gate terminal 111 and the barrier layer 101.

[0047] In some embodiments, one of the first source terminal 109a and the second source terminal 109b is ohmic to electrons and the other is ohmic to holes. Further, one of the first drain terminal 113a and the second drain terminal 113b is ohmic to electrons and the other is ohmic to holes. For example, in an embodiment, the first source terminal 109a is ohmic to electrons and the second source terminal 109b is ohmic to holes; and the first drain terminal 113a is ohmic to electrons and the second drain terminal 113b is ohmic to holes. The first drain terminal 113a and the second drain terminal 113b are interconnected by an interconnect 117 to form a single output terminal. The gate terminal 111 is disposed on the barrier layer 101. The set terminal 115 is in ohmic contact with the channel layer 103.

[0048] Some embodiments are based on the recognition that in order for the semiconductor device 100 to operate as a p-channel field effect transistor (also referred to as a p-FET), the channel layer 103 should include holes as majority charge carriers, and in order for the semiconductor device 100 to operate as an n-channel field effect transistor (also referred to as an n-FET), the channel layer 103 should include electrons as majority charge carriers. For this purpose, whether the semiconductor device 100 acts as a p-FET or an n-FET depends on the majority charge carriers in the channel layer 103.

[0049] Some embodiments are based on the recognition that the priority of charge carriers in the channel layer 103 (i.e., majority charge carriers, holes or electrons) depends on the polarization direction of the barrier layer 101. According to an embodiment, the barrier layer 101 is a group III nitride compound layer, such as a scandium-doped aluminum nitride (ScAlN) layer. The barrier layer 101 may also be referred to as a "barrier". The ScAlN material has ferroelectric properties. Ferroelectricity is a property of materials having a spontaneous polarization that can be reversed by applying an external electric field. All ferroelectrics are pyroelectric, with the additional property that their natural electric polarization is reversible. For this reason, the polarization direction of the barrier layer 101 as an ScAlN layer can be changed by applying an electric field on the barrier layer 101.

[0050] Since the majority charge carriers in the channel layer 103 depend on the polarization direction of the barrier layer 101, and the polarization direction of the barrier layer 101 can be changed by applying an electric field on the barrier layer 101, an electric field can be applied on the barrier layer 101 to switch the polarization direction of the barrier layer 101, so that the semiconductor device 100 can be used as both an n-FET and a p-FET.

[0051] For example, a first voltage can be applied between the gate terminal 111 and the set terminal 115 to form a two-dimensional electron gas (2-DEG) at the interface 119 between the barrier layer 101 and the channel layer 103. When a 2-DEG exists at the interface 119 between the barrier layer 101 and the channel layer 103, the semiconductor device 100 acts as an n-FET. Similarly, a second voltage can be applied between the gate terminal 111 and the set terminal 115 to form a two-dimensional hole gas (2-DHG) at the interface 119 between the barrier layer 101 and the channel layer 103. When a 2-DHG exists at the interface 119 between the barrier layer 101 and the channel layer 103, the semiconductor device 100 acts as a p-FET. The second voltage is different from the first voltage. For example, the first voltage applied between the gate terminal 111 and the set terminal 115 can correspond to a positive bias voltage, and the second voltage applied between the gate terminal 111 and the set terminal 115 can correspond to a negative bias voltage.

[0052] Figure 2A A charge balance diagram 200 when the semiconductor device 100 acts as an n-FET according to some embodiments of the present disclosure is shown. The charge balance diagram 200 is a graph of the c-axis (metal pole) 201 versus the charge density 203. It can be observed from the charge balance diagram 200 that at the interface 205 (representing the interface 119) between the barrier layer 101 and the channel layer 103, the charge density 207 of the barrier layer 101 is positive, and the charge density 209 of the channel layer 103 is negative. Therefore, a 2-DEG 211 exists at the interface 205 between the barrier layer 101 and the channel layer 103, and the semiconductor device 100 acts as an n-FET.

[0053] Figure 2B FIG. 213 shows a charge balance diagram when the semiconductor device 100 acts as a p-FET according to some embodiments of the present disclosure. It can be observed from the charge balance diagram 213 that at the interface 205 between the barrier layer 101 and the channel layer 103, the charge density 215 of the barrier layer 101 is negative, and the charge density 217 of the channel layer 103 is negative. Therefore, 2-DHG 219 exists at the interface 205 between the barrier layer 101 and the channel layer 103, and the semiconductor device 100 acts as a p-FET.

[0054] In this way, the semiconductor device 100 can act as both an n-FET and a p-FET.

[0055] In an embodiment, the channel layer 103 of the semiconductor device 100 is a gallium nitride (GaN) layer. Specifically, the channel layer 103 corresponds to an unintentionally doped GaN layer. GaN is a binary III / V direct bandgap semiconductor and is a hard material with a wurtzite crystal structure. In an embodiment, the epitaxial layers (i.e., the barrier layer 101 and the channel layer 103) are grown on the substrate 107 by a deposition method. Examples of the substrate 107 include a sapphire substrate, a GaN substrate, a silicon substrate, and a silicon carbide (SiC) substrate. The deposition method may include, for example, molecular beam epitaxy (MBE). MBE is an epitaxial process by which the growth of materials is carried out on a heated crystal substrate under ultra-high vacuum (UHV) conditions through the interaction of adsorbed substances provided by atomic or molecular beams. MBE provides several capabilities that are beneficial for the growth of high-purity epitaxial thin-film metals. For example, UHV conditions result in the highest achievable purity of the grown film. Further, the gate terminal 111 is made of a metal such as titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), tungsten (W), or platinum (Pt).

[0056] In some embodiments, the materials of the first source terminal 109a and the first drain terminal 113a are different from the materials of the second source terminal 109b and the second drain terminal 113b. In other words, the first source terminal 109a and the first drain terminal 113a are made of a material different from the material used to fabricate the second source terminal 109b and the second drain terminal 113b. For example, the first source terminal 109a and the first drain terminal 113a are Ti-based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Ni-based p-type ohmic contacts. In another example, the first source terminal 109a and the first drain terminal 113a are gold (Au)-based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Au-based p-type ohmic contacts.

[0057] Alternatively, in some embodiments, instead of two source terminals and two drain terminals (asFigure 1 As shown, the semiconductor device 100 can include only one source terminal and one drain terminal, which makes the design of the semiconductor device 100 simpler and more cost-effective. This is described below in Figure 3 This type of semiconductor device is described.

[0058] Figure 3 FIG. shows a schematic diagram of a semiconductor device 300 according to some embodiments of the present disclosure. The semiconductor device 300 includes a barrier layer 101, a channel layer 103, a buffer layer 105, and a substrate 107. Further, the semiconductor device 100 includes a plurality of terminals, for example, a source terminal 301, a drain terminal 303, a gate terminal 111, and a set terminal 115. The source terminal 301 and the drain terminal 303 are disposed on the channel layer 103. The source terminal 301 and the drain terminal 303 have the same material. For example, the source terminal 301 and the drain terminal 303 are Ni-based p-type ohmic contacts. Since the barrier layer 101 of the semiconductor device 300 (and the semiconductor device 100) is made of a group III nitride material, the semiconductor device 300 (and the semiconductor device 100 as well) can be referred to as a group III nitride semiconductor device.

[0059] Due to the ferroelectric properties of ScAlN (i.e., the barrier layer 101), the semiconductor device 100 (or the semiconductor device 300) can act as both an n-FET and a p-FET. Therefore, it is necessary to model different material-based parameters of ScAlN, such as lattice parameters, strain parameters, piezoelectric polarization, spontaneous polarization, etc. Different material-based parameters of ScAlN are described below.

[0060] Lattice parameter and strain calculation:

[0061] Lattice parameters a MeAlN (x) and C MCAlN (x) (where Me = scandium (Sc), gallium (Ga), indium (In)) of wurtzite crystals according to Vegard's law:

[0062] a GaAlN (x) = 3.1095 + 0.0891x,

[0063] a InAlN (x) = 3.1095 + 0.4753x,

[0064] c GaAlN (x) = 4.9939 + 0.2323x,

[0065] c InAlN (x) = 4.9939 + 0.8063x,

[0066] To describe the non-linearity of the predicted and experimentally observed structural properties, a quadratic equation for the shape bending parameter is chosen:

[0067] Y ScAlN (x) = Y ScN x + Y AlN (1 - x) + bx(1 - x), where b = 4Y ScAlN (x = 0.5) - 2(Y ScN + Y AlN )

[0068] The theoretical methods and experimental measurements of wurtzite Sc x Al (1-x) N are limited to Sc concentrations 0 ≤ x ≤ 0.5 because a phase transition to the cubic structure is expected to occur at approximately x = 0.45 ± 0.05.

[0069] Furthermore, the non-linear correlation of the lattice constants can be described by the following equations:

[0070] a ScAlN (x) = 3.741x + 3.110(1 - x) - 0.242x(1 - x),

[0071] c ScAlN (x) = 4.245x + 4.994(1 - x) + 1.114x(1 - x)

[0072] For pseudomorphic heterostructures, the biaxial strain generated is isotropic in the plane of the barrier (ε 1 = ε 2 ), and makes the stress σ 1 = σ 2 , while the stress σ 3 along the

[0001] axis must be zero. The biaxial strain of the barrier is determined by the following equation

[0073] where Me = Sc, Ga, In

[0074] Figure 4 Figure 400 is shown, which illustrates the biaxial strain of pseudomorphically grown Sc x Al (1-x) N, Ga x Al (1-x) N, and In x Al (1-x) N barriers on relaxed indium nitride (InN), GaN, and aluminum nitride (AlN) buffer layers, according to some embodiments of the present disclosure. The gray shaded region 401 represents the range of biaxial strain relevant to processing robust electronic devices based on pseudomorphic MeAlN / buffer heterostructures. Furthermore, fromFigure 4 It can be observed that

[0075] Me x Al (1-x) N / InN,0≤x≤1:

[0076] Me x Al (1-x) N / AlN,0≤x≤1:

[0077] Ga x Al (1-x) N / GaN,0≤x≤1:

[0078] In x Al (1-x) N / GaN, 0≤x≤0.18:

[0079] 0.18≤x≤l:

[0080] Sc x Al (1-x) N / GaN,0≤x≤0.2: and

[0081] 0.2≤x≤0.5:

[0082] for If the wurtzite crystal is metallically polar, the barrier is under biaxial tensile strain and the vector of the piezoelectric polarization points from the heterostructure surface to its interface. The barrier is under biaxial compressive strain, and the piezoelectric polarization vector points toward the heterostructure surface. If the polarity of the wurtzite crystal is toward the N-face instead of the Me-face, the sign and orientation of the piezoelectric (and spontaneous) polarization vectors are reversed.

[0083] Piezoelectric Polarization:

[0084] According to an embodiment, for a C 6v For materials of the crystallographic point group hexagonal, the piezoelectric polarization as a function of strain is given by:

[0085] Among them, k=1,2,3,l=1,…,6.

[0086] The non-zero component of the piezoelectric polarization oriented along the

[0001] axis in the basal plane caused by the biaxial strain is

[0087] P PE,3 =ε 1 e 31+ε 2 e 32 +ε 3 e 33 , where ε1 = ε2,

[0088] = 2ε 1 e 31 +ε 3 e 33 , where where C 13 and C 33 are the elastic constants of a crystal with a wurtzite structure.

[0089] where

[0090] Some embodiments are based on the recognition that although the piezoelectric polarization along the c-axis linearly depends on the relative change in the lattice constant a barrier , but P PE(biaxial),3 is always negative for the barrier under biaxial tensile strain and is always positive for the crystal under biaxial compressive strain .

[0091] Density functional theory (DFT) simulations produce values of lattice parameters called elastic coefficients (given in GPa) to observe the non-linear behavior of the lattice parameters of Sc x Al (1-x) N and the linear behavior of the lattice parameters of Ga x Al (1-x) N and In x Al (1-x) N, which is described in the following equation:

[0092]

[0093] DFT simulations also produce values of tensor components called piezoelectric coefficients (given in C / m 2 ) to observe the non-linear behavior of the lattice parameters of Sc x Al (1-x) N and the linear behavior of the lattice parameters of Ga x Al (1-x) N and In x Al (1-x) N, which is described in the following equation:

[0094]

[0095] Figure 5 Shows the piezoelectric coefficient according to an embodiment of the present disclosure Graph 500 of piezoelectric coefficient with respect to Sc atomic content. Line 501 represents the piezoelectric coefficient of Sc x Al (1-x) N alloy with respect to Sc atomic content (0 ≤ x ≤ 0.5) Lines 503 and 505 respectively represent the piezoelectric coefficients of Ga x Al (1-x) N and In x Al (1-x) N over the entire possible composition range (0 ≤ x ≤ 1)

[0096] Figure 6 shows the piezoelectric coefficient according to an embodiment of the present disclosure Graph 600 of piezoelectric coefficient with respect to Sc atomic content. Line 601 represents the piezoelectric coefficient of Sc x Al (1-x) N alloy with respect to Sc atomic content (0 ≤ x ≤ 0.5) Lines 603 and 605 respectively represent Ga x Al (1-x) N and In x Al (1-x) N over the entire possible composition range (0 ≤ x ≤ 1)

[0097] From Figure 5 and Figure 6 it can be observed that if the number of Al atoms in AlN replaced by Sc atoms increases, the piezoelectric coefficient and values increase in a non - linear manner. Further, due to the opposite signs of the piezoelectric coefficients and if x increases, the value of the piezoelectric polarization for Sc x Al (1-x) N increases.

[0098] For the same biaxial strain ε1 and alloy composition x, the value of the piezoelectric polarization of Sc x Al (1-x) N is larger than that of In x Al (1-x) N and Ga x Al (1-x) N.

[0099] Figure 7 shows the piezoelectric polarization according to some embodiments of the present disclosure Graph 700 of piezoelectric polarization with respect to alloy composition x. Stars 701 and 703 respectively represent lattice - matched In without piezoelectric polarization x Al(1-x) N / GaN [x = (0.18 ± 0.01)] and Sc x Al (1-x) Alloy composition of the N / GaN [x = (0.20 ± 0.01)] heterostructure.

[0100] For heterostructures with barriers under moderate strain, in a self - consistent Schrödinger - Poisson solver based on, for example, effective mass or tight - binding theory, depending on the implementation of the polarization - induced effect, the following equations can be used as inputs for the reasons of surface and interface bound - layer charges.

[0101]

[0102] From Figure 7 It can be observed that if the number of Al atoms replaced by another metal atom (Me = Sc, Ga, In) increases, the piezoelectric polarization increases, regardless of the binary buffer layer selected. For heterostructures grown on an AlN buffer layer, the piezoelectric polarization of the barrier is always positive (oriented along the

[0001] axis), reaching maximum values of 0.028 C / m, 0.057 C / m, and 0.089 C / m for GaN / ALN, In 0.20 Al 0.80 N / AlN and Sc 0.21 Al 0.79 N / AlN heterostructures, respectively. For x > 0.18 and x > 0.20, the piezoelectric barrier polarization of In 2 、0.057 C / m 2 and 0.089 C / m 2 Al x Al 1-x N / GaN and Sc x Al 1-x N / GaN heterostructures is also positive, reaching 0.053 C / m and 0.153 C / m for x = 0.39 and x = 0.38, respectively. For 0 ≤ x < 0.18 and 0 ≤ x < 0.20, the barriers of In 2 and 0.153 C / m 2 Al x Al 1-x N / GaN and Sc x Al 1-x N / GaN heterostructures, as well as Ga x Al 1-x N / GaN heterostructures show negative piezoelectric polarization, with the highest value for AlN / GaN being - 0.058 C / m 2 .

[0103] The piezoelectric polarization within the barrier of the pseudomorphic MeAlN / buffer heterostructure dependent on the alloy composition is determined by using nonlinear and linear equations of biaxial strain, elastic coefficients, and piezoelectric coefficients to examine Sc x Al (l-x) N and Ga x Al (l-x) N and In x Al (1-x) compared to the piezoelectric polarization of AlN.

[0104] Spontaneous and total polarization:

[0105] Figure 8 FIG. 800 shows the predicted spontaneous polarization as a function of the metal atom content x for random Me x Al (l-x) N (Me = Ga, In, or Sc) alloys having a wurtzite crystal structure according to some embodiments of the present disclosure. with respect to the metal atom content x.

[0106] The non-linear spontaneous polarization of the random alloy can be approximated by the following equation (in C / m 2 ),

[0107]

[0108] For the metal-polar GaAlN, InAlN, and ScAlN barriers, and for the buffer layer, the spontaneous polarization is oriented along the

[0001] direction. If an Al atom is replaced by a Ga or In atom, the value of the spontaneous polarization decreases, while if Al is replaced by a Sc atom, the value of the spontaneous polarization increases significantly.

[0109] Figure 9 FIG. 900 shows the polarization-induced surface charge and total polarization of the barriers for different materials as a function of the alloy composition x according to some embodiments of the present disclosure. Stars 901 and 903 represent the polarization-induced surface charge and the total polarization of the barriers in lattice-matched In x Al 1-x N / GaN [x = (0.18 ± 0.01)] and Sc x Al 1-x N / GaN [x = (0.20 ± 0.01)] heterostructures, respectively.

[0110] The total polarization is the sum of the piezoelectric polarization and the spontaneous polarization:

[0111]

[0112] It can be observed from Figure 9 that as the number of Al atoms replaced by Ga-, In-, or Sc-atoms increases, the value of the total polarization decreases. For Ga x Al 1-xN / GaN and Sc x Al 1-x N / GaN heterostructures and In with 0 ≤ x < 0.11 x Al 1-x barriers of N / GaN heterostructures, observed a high total polarization value above 0.10 C / m 2 of. Sc x Al 1-x barriers of N / GaN heterostructures show the highest value of total polarization in the range of 0 ≤ x < 0.31. The polarization-induced surface layer charge of the metal-polar barrier layer can be determined by the total polarization divided by the electronic charge (e = 1.602 × 10 -19 C). For the lattice-matched Sc 0.20 Al 0.80 N / GaN heterostructures, where the piezoelectric polarization of the barrier disappears, the total polarization is as high as 0.128 C / m 2 .

[0113] Furthermore, it is observed from Figure 9 that the polarization-induced surface layer charge of the pseudomorphic heterostructure is always negative. For Ga x Al 1-x N / GaN and Sc x Al 1-x N / GaN heterostructures and In x Al 1-x barriers of N / GaN heterostructures with 0 ≤ x < 0.11, a negative polarization-induced surface layer charge lower than -6.2 × 10 13 cm -2 is observed. For the lattice-matched Sc 0.20 Al 0.80 N / GaN and In 0.18 Al 0.82 N / GaN heterostructures, the barrier surface layer charges of -7.99 × 10 13 cm -2 and -4.17 × 10 13 cm -2 are determined respectively. These surface layer charges are equal to about 8 and 4 elementary electronic charges per 100 surface atoms. The positive bound layer charges at the bottom of the relaxed InN, GaN, and AlN buffer crystals are induced only by the gradient in the spontaneous polarization and are calculated to be 2.62 × 10 13 , 2.12 × 10 13 and 5.56 × 10 13 cm -2 .

[0114] Layer charge density and polarization-induced 2-DEG:

[0115] A higher barrier bandgap compared to the buffer layer is an additional criterion for selecting a suitable heterostructure for fabricating a high electron mobility transistor (HEMT).

[0116]

[0117] The penetration of the conduction band edge below the Fermi level is determined by an iterative method

[0118]

[0119] where the ground subband energy level of the 2-DEG is given as

[0120]

[0121] where h = 4.1357×10 -15 eV is Planck's constant, and is the effective mass of the electrons in the buffer layer (m* GaN = 0.222me, m* InN = 0.055me). ε0 is the permittivity of vacuum, is the relative dielectric constant, and is the layer electron concentration.

[0122] Figure 10 Shows a graph of the dielectric constant relative to 1000 of the alloy composition x according to some embodiments of the present disclosure. In graph 1000, circles 1001, squares 1003, and diamonds 1005 represent Sc x Al 1-x N's measured dielectric constant The line 1007 represents the calculated dielectric constant of Sc x Al 1-x N Lines 1009 and 1011 represent the dielectric constants of Ga x Al (1-x) N and In x Al (1-x) N

[0123] To describe the physical properties of the barrier related to the alloy composition within the x interval, the following interpolation is used:

[0124] Dielectric constant:

[0125]

[0126] For If the crystal is metal-polar, the barrier is under biaxial tensile strain, and the vector of the piezoelectric polarization points from the heterostructure surface to its interface. For the barrier is under biaxial compressive strain, and the piezoelectric polarization vector points to the heterostructure surface. If the polarity of the wurtzite crystal is the N-face instead of the Me-face, the sign and orientation of the piezoelectric (and spontaneous) polarization vector are reversed.

[0127] Figure 11 Figure 1100 shows the bandgap versus the alloy composition x according to some embodiments of the present disclosure. In Figure 1100, the black circles 1101, circles 1103, and diamonds 1105 represent the measured values of the bandgap of Sc x Al 1-x N. The line 1107 represents the calculated bandgap of Sc Al x N. The lines 1109 and 1111 represent the bandgaps of Ga 1-x Al N and In x Al (1-x) N and In x Al (1-x) N, respectively.

[0128] The bandgap formula is given as follows:

[0129]

[0130] For 0 ≤ x ≤ 1.0

[0131]

[0132] For 0 ≤ x ≤ 1.0

[0133]

[0134] For 0 ≤ x ≤ 0.5

[0135] Figure 12 Figure 1200 shows the polarization-induced electron layer charge versus the alloy composition x according to some embodiments of the present disclosure. The line 1201 represents the polarization-induced electron layer charge of the pseudomorphic metal-polar Ni / Sc x A1 1-x N / GaN. The lines 1203, 1205, and 1207 represent the polarization-induced electron layer charges of Ni / In x Al 1-x N / GaN, Ni / Ga x Al 1-x N / GaN, and Ni / In x Al 1-xPolarization-induced electron sheet charge in the N / InN heterostructure. The bolded portions 1209, 1211, 1213, and 1215 of lines 1201 - 1207 represent the polarization-induced electron sheet charge relative to the alloy composition that can be achieved considering the limitations set by depletion caused by maximum strain, critical barrier thickness, and Schottky contact. The stars 1217 and 1219 represent lattice-matched In x Al 1- x N / GaN [x = (0.18 ± 0.01)] and Sc x Al 1-x Polarization-induced electron sheet charge in the N / GaN [x = (0.20 ± 0.01)] heterostructure.

[0136] The polarization-induced electron sheet charge that can be achieved within a specific range of barrier alloy composition can be approximated by: (in units of 10 13 cm -2 given)

[0137]

[0138] To demonstrate the effect of Schottky contact on the electron sheet charge of the Ni / Me x Al 1-x N / buffer heterostructure, for different MeAlN barriers and alloy compositions x, in the range 0 < d MeAlN < 50 nm, it is calculated by:

[0139]

[0140] For barrier thicknesses greater than the space charge region, the electron sheet charge increases with increasing d MeAlN and is independent of the alloy composition of the MeAlN barrier. Such an increasing trend is caused by a reduction in depletion from the Ni gate contact if the distance between the Schottky contact and the electron accumulation position increases.

[0141] The semiconductor device 100 (or semiconductor device 300) can be used as a logic inverter. For example, when the semiconductor device 100 acts as a p-FET, for an input of '0' (low), the semiconductor device 100 outputs '1' (high). When the semiconductor device 100 acts as an n-FET, for an input of '1', the semiconductor device outputs '0'. Since the semiconductor device 100 can be used as both an n-FET and a p-FET, the area of the inverter circuit using the semiconductor device 100 is reduced, which in turn reduces the capacitance. Therefore, the switching speed increases. Further, such an inverter based on the semiconductor device 100 can be applied to the design of logic gates and other more complex digital circuits.

[0142] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Instead, the following description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. It is contemplated that various changes may be made to the functionality and arrangement of the elements without departing from the spirit and scope of the disclosed subject matter as set forth in the appended claims.

[0143] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, those of ordinary skill in the art will understand that the embodiments may be practiced without these specific details. For example, systems, processes, and other elements in the disclosed subject matter may be shown as components in block diagrams in order to avoid obscuring the embodiments with unnecessary details. In other instances, well-known processes, structures, and techniques may be shown without unnecessary details in order to avoid obscuring the embodiments. Further, like reference numerals and names in the various figures indicate like elements.

[0144] In addition, the various embodiments may be described as a process depicted as a job diagram, flowchart, data flow diagram, structure diagram, or block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of the operations may be rearranged. When the operations of a process are completed, the process may be terminated, but the process may have additional steps not discussed or included in the figures. Further, not all operations in any specifically described process may appear in all embodiments. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, the termination of the function may correspond to the function returning to the calling function or the main function.

[0145] Embodiments of the present disclosure may be implemented as a method, and examples of the method have been provided. The actions performed as part of the method may be ordered in any suitable manner. Accordingly, embodiments may be constructed in which the actions are performed in an order different from that shown, which may include performing some actions simultaneously, even when shown as sequential actions in the illustrative embodiments.

[0146] Although the present disclosure has been described with reference to certain preferred embodiments, it should be understood that various other adaptations and modifications may be made within the spirit and scope of the present disclosure. Accordingly, the aspects of the appended claims cover all such variations and modifications that fall within the true spirit and scope of the present disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: a plurality of epitaxial layers, the plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, wherein a priority of charge carriers in the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is changed by applying an electric field on the barrier layer; a first source terminal and a second source terminal, wherein one of the first source terminal and the second source terminal is ohmic to electrons and the other of the first source terminal and the second source terminal is ohmic to holes; a first drain terminal and a second drain terminal, wherein one of the first drain terminal and the second drain terminal is ohmic to electrons and the other of the first drain terminal and the second drain terminal is ohmic to holes; a gate terminal disposed on the barrier layer; and a set terminal in ohmic contact with the channel layer.

2. The semiconductor device according to claim 1, wherein, the barrier layer includes a scandium-doped aluminum nitride ScAlN layer.

3. The semiconductor device according to claim 1, wherein, the channel layer includes a gallium nitride GaN layer.

4. The semiconductor device according to claim 1, wherein, materials of the first source terminal and the first drain terminal are different from materials of the second source terminal and the second drain terminal.

5. The semiconductor device according to claim 1, wherein, the first source terminal and the first drain terminal are titanium Ti-based n-type ohmic contacts.

6. The semiconductor device according to claim 1, wherein, the second source terminal and the second drain terminal are nickel Ni-based p-type ohmic contacts.

7. The semiconductor device according to claim 1, wherein, the gate terminal is made of one of the following: titanium Ti, aluminum Al, nickel Ni, molybdenum Mo, tungsten W, or platinum Pt.

8. The semiconductor device according to claim 1, the semiconductor device further includes an insulating layer between the gate terminal and the barrier layer.

10. The semiconductor device according to claim 1, wherein, the epitaxial layers are grown on a substrate by molecular beam epitaxy MBE, and wherein the substrate is one of a sapphire substrate, a GaN substrate, a silicon substrate, or a silicon carbide SiC substrate.

11. A semiconductor device, the semiconductor device comprising: a plurality of epitaxial layers, the plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, wherein a priority of charge carriers in the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is changed by applying an electric field on the barrier layer; a source terminal disposed on the channel layer; a drain terminal disposed on the channel layer; ​ ​ ​ A gate terminal, the gate terminal being disposed on the barrier layer; and A set terminal, the set terminal being in ohmic contact with the channel layer.

12. The semiconductor device according to claim 11, wherein, the source terminal and the drain terminal have the same material.

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