Semiconductor device with dummy pad and method thereof

Abstract

In certain aspects, a semiconductor device includes a device layer, a dummy pad, a dielectric structure between the device layer and the dummy pad and extending in a vertical direction, and an interconnect structure between the device layer and the dielectric structure and extending in the vertical direction. The dielectric structure, the interconnect structure, and the dummy pad are overlapping.

Description

BACKGROUND OF THE INVENTION

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of manufacturing the same.

[0002] Electrostatic discharge (ESD) is a sudden release of electrostatic electricity. ESD may occur when a charged object contacts an electronic device. For example, if not protected during the manufacturing and packaging of semiconductor devices, ESD may damage the semiconductor devices. One way to prevent damage caused by ESD is to use an ESD protection circuit (also known as an ESD circuit), which transfers the ESD current by providing a low-impedance path. SUMMARY OF THE INVENTION

[0003] In one aspect, a semiconductor device includes a device layer, a dummy pad, a dielectric structure located between the device layer and the dummy pad and extending in a vertical direction, and an interconnect structure located between the device layer and the dielectric structure and extending in a vertical direction. The dielectric structure, the interconnect structure, and the dummy pad are overlapping.

[0004] In some embodiments, the semiconductor device further includes a semiconductor layer located between the dummy pad and the interconnect structure. In some embodiments, the dielectric structure includes an isolation structure in the semiconductor layer.

[0005] In some embodiments, a lateral dimension of the isolation structure is greater than a lateral dimension of the dummy pad.

[0006] In some embodiments, the semiconductor device further includes a first via contact that contacts the interconnect structure and is separated from the dummy pad by the isolation structure.

[0007] In some embodiments, the first via contact includes tungsten.

[0008] In some embodiments, the semiconductor device further includes a second via contact that contacts the dummy pad and extends in a vertical direction. In some embodiments, the dielectric structure includes a dielectric layer located between the second via contact and the interconnect structure.

[0009] In some embodiments, the second via contact is separated from the interconnect structure by the dielectric layer.

[0010] In some embodiments, the second via contact includes tungsten.

[0011] In some embodiments, the semiconductor device further includes a bonding interface located between the dummy pad and the device layer. In some embodiments, the interconnect structure includes a bonding contact at the bonding interface.

[0012] In some embodiments, the interconnect structure further includes a device contact located between the bonding interface and the device layer and connecting the bonding interface and the device layer.

[0013] In some embodiments, the semiconductor device further includes a pad, another second via contact in contact with the pad, another first via contact in contact with the another second via contact, and another interconnect structure in contact with the another first via contact and the device layer.

[0014] In some embodiments, the pad and the dummy pad are coplanar, and the interconnect structure and the another interconnect structure are coplanar.

[0015] In another aspect, a semiconductor device includes: a device layer including an electrostatic discharge (ESD) circuit and a functional circuit; a dummy pad disconnected from the functional circuit; and an interconnect structure located between the device layer and the dummy pad. The dummy pad is connected to the ESD circuit at least through the interconnect structure.

[0016] In some embodiments, the semiconductor device further includes a first via contact located between the dummy pad and the interconnect structure and connected to the interconnect structure.

[0017] In some embodiments, the semiconductor device further includes a semiconductor layer located between the dummy pad and the first via contact, a spacer in the semiconductor layer, and a second via contact in contact with the dummy pad and the first via contact and extending through the spacer.

[0018] In some embodiments, the first via contact and the second via contact include tungsten.

[0019] In some embodiments, the dummy pad is connected to the ESD circuit at least through the interconnect structure and the first and second via contacts.

[0020] In some embodiments, the semiconductor device further includes a bonding interface located between the dummy pad and the device layer. In some embodiments, the interconnect structure includes a bonding contact located at the bonding interface.

[0021] In some embodiments, the interconnect structure further includes a device contact located between the bonding interface and the device layer and connecting the bonding interface and the device layer.

[0022] In yet another aspect, a method for forming a semiconductor device is provided. A device layer including a functional circuit is formed. An interconnect structure is formed on the device layer and disconnected from the functional circuit. A first via contact is formed on the interconnect structure and connected to the interconnect structure. An isolation structure is formed on the first via contact. A dummy pad is formed on the isolation structure and disconnected from the first via contact through the isolation structure.

[0023] In some embodiments, another interconnect structure is formed on the device layer and connected to the functional circuit, another first via contact is formed on the another interconnect structure and connected to the another interconnect structure, a second via contact is formed on the another first via contact and in contact with the another first via contact, and extends through the isolation structure, and a pad is formed on the second via contact and in contact with the second via contact.

[0024] In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, thereby exposing the first via contact and the another first via contact, and a dielectric layer is deposited to fill the trench.

[0025] In some embodiments, to form the second via contact, a portion of the isolation structure is removed to form a hole, thereby exposing the another first via contact but not exposing the first via contact, and a metal layer is deposited to fill the hole.

[0026] In some embodiments, the metal layer includes tungsten. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings are incorporated herein and constitute a part of the specification. The drawings illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those of ordinary skill in the relevant art to make and use the present disclosure.

[0028] Figure 1 A plan view of a semiconductor device having via contacts below dummy pads according to some aspects of the present disclosure is shown.

[0029] Figure 2 A plan view of a semiconductor device having no via contacts below dummy pads according to some aspects of the present disclosure is shown.

[0030] Figure 3A A cross-sectional side view of a semiconductor device having dummy pads according to some aspects of the present disclosure is shown.

[0031] Figure 3B A cross-sectional side view of a three-dimensional (3D) memory device having dummy pads and pads according to some aspects of the present disclosure is shown.

[0032] Figure 4 A cross-sectional side view of another semiconductor device having dummy pads according to some aspects of the present disclosure is shown.

[0033] Figure 5 A cross-sectional side view of yet another semiconductor device having dummy pads according to some aspects of the present disclosure is shown.

[0034] Figure 6A and Figure 6BShows a circuit diagram of an ESD circuit according to some aspects of the present disclosure.

[0035] Figures 7A-7E Shows a manufacturing process for forming a semiconductor device having dummy pads according to some aspects of the present disclosure.

[0036] Figures 8A-8E Shows a manufacturing process for forming another semiconductor device having dummy pads according to some aspects of the present disclosure.

[0037] Figure 9 Is a flowchart of a method for forming a semiconductor device having dummy pads according to some aspects of the present disclosure.

[0038] Aspects of the present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0039] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure can also be used in a variety of other applications. The functional and structural features described in the present disclosure can be combined, adjusted, and modified with each other in ways not specifically depicted in the drawings such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0040] Generally, terms can be understood at least in part based on their use in context. For example, at least in part depending on the context, the term "one or more" as used herein can be used to describe any feature, structure, or property in a singular sense or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, at least in part depending on the context, terms such as "a" or "the" can also be understood to convey a singular usage or convey a plural usage. Additionally, again at least in part depending on the context, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors and can instead allow for the existence of additional factors that are not necessarily explicitly described.

[0041] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest sense such that "on" not only means directly "on" something, but also includes the meaning of being "on" something with intermediate features or layers therebetween, and "above" or "over" not only means the meaning of being "above" or "over" something, but can also include the meaning of being "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0042] In addition, for ease of description, in this document, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used to describe the relationship of one element or feature with respect to another (or multiple) element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0043] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0044] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below. The layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0045] In a semiconductor device, a dummy pad, like a normal pad (referred to as a "pad" herein), can be used for wire bonding during semiconductor device packaging. However, different from a normal pad, the dummy pad is electrically disconnected from the functional circuit of the semiconductor device (e.g., having transistors or memory cells), and thus is not conducive to the operation of the functional circuit.

[0046] Although the dummy pad is designed to be electrically disconnected from the corresponding functional circuit below, during semiconductor device packaging, for example, when the distance between the functional circuit and the interconnect structure located below and in contact with the dummy pad is not far enough and / or the functional circuit is not protected against ESD, the ESD from the dummy pad may still damage the functional circuit.

[0047] To address one or more of the foregoing problems, the present disclosure introduces various solutions to prevent ESD-induced damage caused by dummy pads to semiconductor devices. According to one aspect of the present disclosure, at least one via contact in an interconnect structure located below and overlapping with a dummy pad is removed, for example, replaced with a dielectric structure, so that ESD from the dummy pad cannot propagate to the functional circuit. In some embodiments, the lateral dimension of an isolation structure (e.g., buried shallow trench isolation (BSTI)) in the dielectric structure is larger than the lateral dimension of the dummy pad, thereby further reducing the risk of burning due to defects between the dummy pad and the semiconductor layer below the dummy pad. According to another aspect of the present disclosure, the dummy pad is electrically connected to an ESD circuit at least through the interconnect structure, so that ESD from the dummy pad can be mitigated by the ESD circuit.

[0048] Figure 1 A plan view of a semiconductor device 100 having a via contact located below a dummy pad 104 is shown in accordance with some aspects of the present disclosure. The semiconductor device 100 may include logic devices such as microcontrollers, microprocessors, application processors, etc., memory devices such as dynamic random access memories (DRAMs), NAND or NOR flash memories, static random access memories (SRAMs), etc., or analog devices such as operational amplifiers, timers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. The semiconductor device 100 may include lead bonding pads for electrically connecting the semiconductor device 100 to external devices. For example, the lead bonding pads may be connected to a circuit board or a package substrate (e.g., a redistribution layer) or an interposer by soldering and attaching gold or aluminum leads. Thus, the lead bonding pads may serve as bonding sites on the semiconductor device 100. The semiconductor device 100 may also include a functional circuit (e.g., as part of its device layer) configured to perform the functions of the semiconductor device, such as transistors for logic devices, memory cells for memory devices, or resistors, capacitors, and inductors for analog devices.

[0049] In some embodiments, depending on whether the lead bonding pad is electrically connected to any functional circuit, i.e., whether the lead bonding pad also facilitates the operation of the corresponding functional circuit (e.g., sending an electrical signal to / receiving an electrical signal from the functional device), the lead bonding pad includes a normal pad (also referred to as a pad) 102 and a dummy pad 104. For example, each pad 102 may be electrically connected to a corresponding functional circuit to facilitate the operation of the functional circuit, while each dummy pad 104 may not be electrically connected to any functional circuit and thus does not facilitate the operation of any functional circuit. As Figure 1As shown, in some embodiments, the pad 102 or dummy pad 104 contacts one or more underlying via contacts that form part of an interconnect structure overlapping the pad 102 / dummy pad 104. It should be understood that the interconnect structure overlapping the pad 102 can connect the pad 102 to a corresponding functional circuit, while the interconnect structure overlapping the dummy pad 104 may not connect the dummy pad 104 to any functional circuit. In some embodiments described in detail below, the interconnect structure overlapping the dummy pad 104 can connect the dummy pad 104 to an ESD circuit to mitigate the risk of ESD damage from the dummy pad 104 to the functional circuit near the interconnect structure overlapping the dummy pad 104.

[0050] Figure 2 A plan view of a semiconductor device 200 without via contacts located under the dummy pad 104 is shown in accordance with some aspects of the present disclosure. The semiconductor device 200 is similar to the semiconductor device 100, except that at least one of the via contacts under the dummy pad 104 is removed (e.g., replaced by a dielectric structure). As a result, in some embodiments described in detail below, ESD from the dummy pad 104 can be isolated by the dielectric structure before reaching any functional circuit through the interconnect structure overlapping the dummy pad 104.

[0051] Figure 3A A cross-sectional side view of a semiconductor device 300 having a dummy pad 330 is shown in accordance with some aspects of the present disclosure. The semiconductor device 300 can be an example of the semiconductor device 200. As Figure 3A shown, in some embodiments, the semiconductor device 300 is a bonded chip including a first structure 302 and a second structure 304 stacked on top of each other in different planes in a vertical direction (e.g., the z-direction). In some embodiments, the first structure 302 and the second structure 304 are bonded at a bonding interface 306 therebetween.

[0052] As Figure 3A shown, the first structure 302 can include a substrate 308, which can include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 308 includes single-crystalline silicon, which is the part of the wafer on which the first structure 302 is fabricated, either having its native thickness or being thinned. In some embodiments, the first substrate 302 includes, for example, polysilicon, which is a semiconductor layer that replaces the part of the wafer on which the first structure 302 is fabricated. Note that in Figure 1 、 Figure 2 and Figure 3AIt includes the x, y, and z axes to further illustrate the spatial relationships of the components in semiconductor devices 100, 200, and 300. The substrate 308 of semiconductor device 300 includes two lateral surfaces that extend laterally in the x-y plane: a top surface on the front face of the wafer on which the device layer 310 can be formed, and a bottom surface on the back face of the wafer opposite the front face. The z axis is perpendicular to the x axis and the y axis. As used herein, when the substrate 308 is in the lowest plane of semiconductor device 300 in the z direction (the vertical direction perpendicular to the x-y plane), whether a component (e.g., a layer or a device) of semiconductor device 300 is "on", "above", "below", or "beneath" another component (e.g., a layer or a device) in the z direction is determined relative to the substrate 308 of semiconductor device 300. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0053] As Figure 3A shown, the first structure may include a device layer 310 on a substrate 308. In some embodiments, the device layer 310 includes functional circuitry 312. In some embodiments, semiconductor device 300 is a NAND flash device, where memory cells are formed as an array of NAND memory strings, and the functional circuitry 312 is a peripheral circuit (also referred to as a control and sensing circuit) that facilitates the operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuitry. For example, the peripheral circuit may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output circuits, charge pumps, voltage sources or generators, current or voltage references, any part of the above functional circuitry (e.g., sub-circuits), or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The functional circuitry 312 may use complementary metal-oxide-semiconductor (CMOS) technology, e.g., which may be implemented with a logic process in any suitable technology node.

[0054] In some embodiments, the first structure 302 further includes an interconnect layer 311 above the device layer 310 to transmit electrical signals to and from the device layer 310. As Figure 3AAs shown, the interconnect layer 311 can be vertically located between the bonding interface 306 and the device layer 310 (including the functional circuits 312). The interconnect layer 311 can include a plurality of interconnects (also referred to herein as "contacts"), including horizontal lines and via contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as mid-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 311 can also include one or more interlayer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which the horizontal lines and via contacts can be formed. That is, the interconnect layer 311 can include the horizontal lines and via contacts in a plurality of ILD layers. Although Figure 3A not shown in the figure, it should be understood that the functional circuits 312 in the device layer 310 can be electrically connected to any other suitable functional circuits through the interconnects in the interconnect layer 311. The interconnects in the interconnect layer 311 can include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer 311 can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 311 include, for example, device contacts 316 in the metal 3 - metal 5 (M3 - M5) layers. The device contacts 316 can include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0055] As Figure 3A shown, the first structure 302 can also include a bonding layer 313 located at and above the bonding interface 306 and in contact with the interconnect layer 311. The bonding layer 313 can include a plurality of bonding contacts 318 and a dielectric that electrically isolates the bonding contacts 318. The bonding contacts 318 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining regions of the bonding layer 313 can be formed of a dielectric, which includes but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 318 and the surrounding dielectric in the bonding layer 313 can be used for hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and can simultaneously achieve metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO 2 -to-SiO 2 ) bonding.

[0056] As Figure 3AAs shown, the second structure 304 may include a bonding layer 315 at the bonding interface 306, e.g., on the opposite side of the bonding interface 306 relative to the bonding layer 313 in the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically isolates the bonding contacts 320. The bonding contacts 320 may include a conductive material, such as Cu. The remaining region of the bonding layer 315 may be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric in the bonding layer 315 may be used for hybrid bonding. In some embodiments, the bonding interface 306 is the location where the bonding layers 313 and 315 meet and bond. In fact, the bonding interface 306 may be a layer having a certain thickness, which includes the top surface of the bonding layer 313 of the first structure 302 and the bottom surface of the bonding layer 315 of the second structure 304.

[0057] As Figure 3A shown, the second structure 304 may further include an interconnect layer 323 located above the bonding layer 315 to transmit electrical signals. The interconnect layer 323 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Although Figure 3A not shown in, in some examples, the interconnects in the interconnect layer 323 further include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 323 may further include one or more ILD layers in which horizontal lines and via contacts may be formed. The interconnects in the interconnect layer 323 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer 323 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 323 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, e.g., voids) among conductive metal materials.

[0058] As Figure 3A shown, the second structure 304 may further include a semiconductor layer 326 located above the interconnect layer 323. The semiconductor layer 326 may include a semiconductor material. In some embodiments, the semiconductor layer 326 is a thinned silicon substrate having single-crystalline silicon. In some embodiments, the semiconductor layer 326 is a deposited polysilicon layer that replaces at least part of the silicon substrate having single-crystalline silicon. It should be understood that in some examples, trench isolation and doping regions (not shown) may also be formed in the semiconductor layer 326. It should also be understood that in some examples, the semiconductor layer 326 may include a plurality of semiconductor layers in the vertical direction, and dielectric layers are formed therebetween.

[0059] As Figure 3AAs shown, the second structure 304 may further include a pad lead-out layer 327 located above the semiconductor layer 326. The pad lead-out layer 327 may include dummy pads 330, one or more ILD layers 332 (e.g., silicon oxide layer and silicon nitride layer), and a protective layer 334 (e.g., polyimide layer) located at the top surface of the semiconductor device 300. The pad lead-out layer 327 and the interconnect layer 323 may be formed on opposite sides of the semiconductor layer 326. In some embodiments, openings 336 are formed through the protective layer 334 and the ILD layers 332 in the pad lead-out layer 327 to expose the dummy pads 330, thereby allowing wire bonding to be performed on the top surface of the dummy pads 330.

[0060] Consistent with the scope of the present disclosure, the semiconductor device 300 may include a dielectric structure located between the device layer 310 and the dummy pads 330 in a vertical direction (e.g., Figure 3A the z direction in). The dielectric structure may extend in a lateral direction (e.g., Figure 3A the y direction in) and a vertical direction (e.g., Figure 3A the z direction in). In some embodiments as shown in Figure 3A , the dielectric structure includes an isolation structure 328 in the semiconductor layer 326, such as BSTI. For example, the isolation structure 328 may include silicon oxide. The semiconductor device 300 may further include an interconnect structure 314 located between the device layer 310 and the dielectric structure (e.g., Figure 3A the isolation structure 328 in) in a vertical direction (e.g., Figure 3A the z direction in). The interconnect structure 314 may extend in a vertical direction (e.g., Figure 3A the z direction in). The semiconductor layer 326 may be disposed between the dummy pads 330 and the interconnect structure 314 in a vertical direction. As shown in Figure 3A , according to some embodiments, the isolation structure 328, the interconnect structure 314, and the dummy pads 330 are overlapped, which are considered corresponding structures in the present disclosure. In other words, for each dummy pad 330, the semiconductor device 300 may include a corresponding overlapping isolation structure 328 and interconnect structure 314.

[0061] As shown in Figure 3A , the interconnect structure 314 may include bonding contacts 320 and 318 in the bonding layers 315 and 313, and device contacts 316 in the interconnect layer 311 of the first structure 302. According to some embodiments, the device contacts 316 are disposed between the bonding interface 306 and the device layer 310, and the bonding interface 306 is disposed between the dummy pads 330 and the device layer 310 in a vertical direction. It should be understood that in some embodiments, the interconnect structure 314 may further include interconnects 322 in the interconnect layer 323 of the second structure 304.

[0062] As shown Figure 3A in FIG. 3, the second structure 304 of the semiconductor device 300 may further include via contacts 324 extending in a vertical direction in the interconnect layer 323. The via contacts 324 may include W. In some embodiments, the via contacts 324 contact the interconnect structure 314 but are separated from the dummy pad 330 by an isolation structure 328. Thus, even if the device contacts 316 of the interconnect structure 314 are not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 through the interconnect structure 314 and the via contacts 324, the isolation structure 328 between the dummy pad 330 and the via contacts 324 can still prevent ESD from propagating from the dummy pad 330 to the via contacts 324. In some embodiments, the thickness of the isolation structure 328 (e.g., in the vertical direction) is between 500 nm and 1000 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded by any of these values as the lower end, or within any range defined by any two of these values).

[0063] In some embodiments, the lateral dimension of the isolation structure 328 (e.g., in the Figure 3A y direction) is greater than the lateral dimension of the dummy pad 330 (e.g., in the Figure 3A y direction). As a result, even if a defect may be formed in the semiconductor layer 326, the risk of burnout between the dummy pad 330 and the semiconductor layer 326 can be reduced due to the enlarged size of the isolation structure 328 (e.g., BSTI). In some embodiments, the distance d between the edge of the dummy pad 330 and the edge of the isolation structure 328 in the lateral direction (e.g., the Figure 3A y direction in FIG. 3) is greater than 1 μm, e.g., between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range bounded by any of these values as the lower end, or within any range defined by any two of these values).

[0064] Figure 3B FIG. 4 shows a cross-sectional side view of a 3D memory device 301 having a dummy pad 330 and a pad 346 according to some aspects of the present disclosure. The 3D memory device 301 may be Figure 3A an example of the semiconductor device 300 in FIG. 3, such as a NAND flash memory device. For ease of description, the same components already described above with respect to Figure 3A FIG. 3 will not be repeated.

[0065] As shown Figure 3BAs shown, the 3D memory device 301 may further include a pad 346, a via contact 344 located below the pad 346 and in contact with the pad 346, a via contact 342 located below the via contact 344 and in contact with the via contact 344, and an interconnect structure 340 located below the via contact 342 and in contact with the via contact 342. According to some embodiments, the pad 346, the via contacts 344 and 342, and the interconnect structure 340 are overlapping. As will be described in detail below with respect to the manufacturing process, the pad 346 and the dummy pad 330 may be formed by the same process and are coplanar. Similarly, the interconnect structure 314 and the interconnect structure 340 may be formed by the same process and are coplanar, and the via contact 324 and the via contact 342 may be formed by the same process and are coplanar. According to some embodiments, the via contact 344 extends through the isolation structure 328 (e.g., BSTI) and connects the pad 346 and the via contact 342. Thus, unlike the dummy pad 330 and the interconnect structure 314 that are electrically isolated by the isolation structure 328, the pad 346 may be electrically connected to the interconnect structure 340 through the via contacts 344 and 342. Similar to the via contact 324, the via contacts 344 and 342 may include W.

[0066] As Figure 3B shown, the device layer 310 may further include a functional circuit 338 electrically connected to the interconnect structure 340, which is different from the functional circuit 312 that is electrically isolated from the interconnect structure 314. As a result, the pad 346 may be electrically connected to the functional circuit 338 in the device layer 310 through the via contacts 344 and 342 and the interconnect structure 340, thereby facilitating the operation of the functional circuit 338. Although not shown, it should be understood that the device layer 310 may further include an ESD circuit electrically connected to the functional circuit 338 and the interconnect structure 340 to avoid ESD damage from the pad 346.

[0067] In some embodiments, the 3D memory device 301 further includes a memory cell array, such as an array of NAND memory strings 350 located above the bonding interface 306 in the second structure 304. In some embodiments, the NAND memory strings 350 are disposed in the vertical direction between the semiconductor layer 326 and the bonding interface 306. In some embodiments, the semiconductor layer 326 is disposed above the memory stack 348 and in contact with the source of the NAND memory strings 350. In some embodiments, each NAND memory string 350 is a "charge trapping" type NAND memory string including any suitable channel structure. It should be understood that the NAND memory strings 350 are not limited to the "charge trapping" type NAND memory strings and may be "floating gate" type NAND memory strings in other examples.

[0068] According to some embodiments, each NAND memory string 350 extends vertically through a plurality of pairs, each pair including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked structure, such as the memory stack 348. The memory stack 348, as well as the via contacts 324 and 342, can be coplanar. Thus, the via contacts 324 and 342 can also be referred to as "array contacts" because they are coplanar with the memory cell array in the memory stack 348. According to some embodiments, the interleaved conductive and dielectric layers in the memory stack 348 alternate in the vertical direction. Each conductive layer can include a gate electrode (gate line) surrounded by a bonding layer and a gate dielectric layer. The bonding layer can include a conductive material, such as titanium nitride (TiN), which can improve the adhesion between the gate electrode and the gate dielectric layer. The gate electrodes of the conductive layers can extend laterally as word lines and terminate at one or more stepped structures of the memory stack 348.

[0069] According to some embodiments, compared to the pad 346 that is electrically connected to the corresponding interconnect structure 340 through two via contacts 344 and 342, the dummy pad 330 is separated from the via contact 324 by the isolation structure 328. In other words, according to some embodiments, one of the two via contacts that overlap the dummy pad 330 (i.e., the one coplanar with the via contact 344) is replaced by the isolation structure 328 to ensure electrical insulation between the dummy pad 330 and the interconnect structure 314, thereby avoiding ESD damage to the functional circuit 312 even when the distance between the interconnect structure 314 and the functional circuit 312 is too close to have protection from the ESD circuit for the functional circuit 312.

[0070] To separate the dummy pad 330 from the interconnect structure 314, either or both of the two via contacts that overlap the dummy pad 330 can be replaced by a dielectric structure. Instead of Figure 3A and Figure 3B removing the via contact that contacts the dummy pad 330 as shown, in another example, the other via contact (e.g., 324) that contacts the interconnect structure 314 can be removed to achieve the same result. Figure 4 A cross-sectional side view of another semiconductor device 400 having a dummy pad 330 in accordance with some aspects of the present disclosure is shown. The semiconductor device 400 can be another example of the semiconductor device 200. For ease of description, the same components that have been described above with respect to Figure 3A will not be repeated.

[0071] Consistent with the scope of the present disclosure, the semiconductor device 400 can include a dielectric structure located between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., Figure 4 the z direction). The dielectric structure can be in the lateral direction (e.g.,Figure 4 in the y - direction) and the vertical direction (e.g., Figure 4 in the z - direction). In some embodiments, as Figure 4 shown, the dielectric structure includes a dielectric layer 401 in the interconnect layer 323. For example, the dielectric layer 401 may include silicon oxide. The semiconductor device 400 may also include an interconnect structure 314 in the vertical direction (e.g., Figure 4 in the z - direction) between the device layer 310 and the dielectric structure (e.g., Figure 4 the dielectric layer 401). The interconnect structure 314 may extend in the vertical direction (e.g., Figure 4 in the z - direction). As Figure 4 shown, according to some embodiments, the dielectric layer 401, the interconnect structure 314, and the dummy pad 330 are overlapped, which are considered corresponding structures in the present disclosure. In other words, for each dummy pad 330, the semiconductor device 400 may include a corresponding overlapping dielectric layer 401 and interconnect structure 314.

[0072] Unlike Figure 3A the semiconductor device 300, the semiconductor device 400 may also include a via contact 402 located under and in contact with the dummy pad 330. In some embodiments, the via contact 402 extends in the vertical direction (e.g., Figure 4 in the z - direction) through the isolation structure 328. The via contact 402 may include W. Since the via contact 402 also extends through the semiconductor layer 326, in some examples it may be referred to as a "through - silicon via (TSV)". Unlike Figure 3AIn contrast to the semiconductor device 300 including the via contact 324 located above and in contact with the interconnect structure 314, however, according to some embodiments, the semiconductor device 400 does not include the via contact 324, but includes a dielectric layer 401 between the via contact 402 and the interconnect structure 314. That is, the via contact 402 can be separated from the interconnect structure 314 by the dielectric layer 401. Therefore, even if the device contact 316 of the interconnect structure 314 is not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 through the interconnect structure 314, the dielectric layer 401 located between the interconnect structure 314 and the via contact 402 can still prevent ESD from propagating from the dummy pad 330 to the interconnect structure 314. In some embodiments, the thickness of the isolation structure 328 (e.g., in the vertical direction) is between 1000 nm and 2000 nm (e.g., 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, any range defined by any of these values as the lower end, or within any range defined by any two of these values).

[0073] In some embodiments, the lateral dimension of the isolation structure 328 (e.g., in Figure 4 the y direction) is greater than the lateral dimension of the dummy pad 330 (e.g., in Figure 4 the y direction). As a result, even if a defect may be formed in the semiconductor layer 326, due to the enlarged size of the isolation structure 328 (e.g., BSTI), the risk of burnout between the dummy pad 330 and the semiconductor layer 326 can be reduced. In some embodiments, the distance d between the edge of the dummy pad 330 and the edge of the isolation structure 328 in the lateral direction (e.g., Figure 4 the y direction in ) is greater than 1 μm, for example, between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range defined by any of these values as the lower end, or within any range defined by any two of these values).

[0074] It should be understood that although not shown, in some examples, the via contacts 324 and 402 overlapping the dummy pad 330 can be removed, for example, replaced by the isolation structure 328 and the dielectric layer 401, so that the dummy pad 330 can be separated from the interconnect structure 314 by the isolation structure 328 and the dielectric layer 401 to prevent the dummy pad 330 from causing ESD damage to the functional circuit 312.

[0075] Figure 5A cross-sectional side view of yet another semiconductor device 500 having a dummy pad 330 in accordance with some aspects of the present disclosure is shown. The semiconductor device 500 may be an example of the semiconductor device 100. As Figure 5 shown, according to some embodiments, the semiconductor device 500 is a bonded chip including a first structure 302 and a second structure 304, and the first structure 302 and the second structure 304 are stacked on top of each other in different planes in a vertical direction (e.g., the z-direction). According to some embodiments, the first structure 302 and the second structure 304 are bonded at a bonding interface 306 therebetween.

[0076] As Figure 5 shown, the first structure 302 may include a substrate 308, and the substrate 308 may include silicon (e.g., single-crystalline silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, the substrate 308 includes single-crystalline silicon, which is the portion of the wafer on which the first structure 302 is fabricated, either having its native thickness or being thinned. In some embodiments, the first substrate 302 includes, for example, polysilicon, which is a semiconductor layer that replaces the portion of the wafer on which the first structure 302 is fabricated.

[0077] As Figure 5 shown, the first structure may include a device layer 310 located on the substrate 308. In some embodiments, the device layer 310 includes a functional circuit 312 and an ESD circuit 502. In some embodiments, the semiconductor device 500 is a NAND flash memory device, where memory cells are formed as an array of NAND memory strings, and the functional circuit 312 is a peripheral circuit (also referred to as control and sensing circuitry) that facilitates the operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuits. For example, the peripheral circuit may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the above functional circuits (e.g., sub-circuits), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The functional circuit 312 may use CMOS technology, e.g., which may be implemented with a logic process in any suitable technology node.

[0078] The ESD circuit 502 may use ESD suppression components to reduce the ESD voltage below a specific limit. These components may be connected in parallel to vulnerable lines. When an ESD strike occurs, the ESD diode may break down and create a low-impedance path that can limit the peak voltage and current by diverting the current to ground. In one example, as Figure 6AAs shown, the ESD circuit 502 may include a resistor R, a capacitor C, and a transistor Q. The resistor R and the capacitor C may form a resistor-capacitor circuit (RC circuit), and the transistor Q may be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal A, the output terminal of the resistor-capacitor circuit may be at a logic high level, which may cause the transistor Q to conduct and conduct the ESD through the transistor Q. In another example, as Figure 6B shown, the ESD circuit 502 may include a resistor R, a capacitor C, transistors Qa, Qb, and Qc. The resistor R and the capacitor C may form an RC circuit, the transistors Qa and Qb may form an inverter, and the transistor Qc may be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal A, the output terminal of the resistor-capacitor circuit may be at a logic low level, the output terminal of the inverter may be at a logic high level, the transistor Qc may conduct, and the ESD may be conducted through the transistor Qc.

[0079] As Figure 5 shown, in some embodiments, the first structure 302 further includes an interconnect layer 311 above the device layer 310 to transmit electrical signals to and from the device layer 310. The interconnect layer 311 may be vertically located between the bonding interface 306 and the device layer 310 (including the functional circuit 312 and the ESD circuit 502). The interconnect layer 311 may include a plurality of interconnects and one or more ILD layers. That is, the interconnect layer 311 may include horizontal lines and via contacts in the plurality of ILD layers. Although Figure 5 not shown, it should be understood that the functional circuit 312 in the device layer 310 may be electrically connected to any other suitable functional circuit through the interconnects in the interconnect layer 311. The interconnects in the interconnect layer 311 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer 311 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 311 include, for example, device contacts 316 in the metal 3-metal 5 (M3-M5) layer. The device contacts 316 may include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0080] As Figure 5As shown, the first structure 302 may further include a bonding layer 313 located at the bonding interface 306, above and in contact with the interconnect layer 311. The bonding layer 313 may include a plurality of bonding contacts 318 and a dielectric that electrically isolates the bonding contacts 318. The bonding contacts 318 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining regions of the bonding layer 313 may be formed of a dielectric including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 318 and the surrounding dielectric in the bonding layer 313 may be used for hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and can achieve both metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO 2 -to-SiO 2 ) bonding.

[0081] As Figure 5 shown, the second structure 304 may include a bonding layer 315 at the bonding interface 306, e.g., on the opposite side of the bonding interface 306 relative to the bonding layer 313 in the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically isolates the bonding contacts 320. The bonding contacts 320 may include a conductive material, such as Cu. The remaining regions of the bonding layer 315 may be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric in the bonding layer 315 may be used for hybrid bonding. In some embodiments, the bonding interface 306 is the location where the bonding layers 313 and 315 meet and bond. In fact, the bonding interface 306 may be a layer having a certain thickness, which includes the top surface of the bonding layer 313 of the first structure 302 and the bottom surface of the bonding layer 315 of the second structure 304.

[0082] As Figure 5 shown, the second structure 304 may further include an interconnect layer 323 located above the bonding layer 315 to transmit electrical signals. The interconnect layer 323 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Although Figure 5Not shown in the figure, in some examples, the interconnections in the interconnect layer 323 also include local interconnections, such as bit line contacts and word line contacts. The interconnect layer 323 may further include one or more ILD layers in which horizontal lines and via contacts may be formed. The interconnections in the interconnect layer 323 may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer 323 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnections in the interconnect layer 323 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, e.g., voids) among conductive metal materials.

[0083] As Figure 5 shown, the second structure 304 may further include a semiconductor layer 326 located above the interconnect layer 323. The semiconductor layer 326 may include semiconductor materials. In some embodiments, the semiconductor layer 326 is a thinned silicon substrate having single-crystalline silicon. In some embodiments, the semiconductor layer 326 is a deposited polysilicon layer that replaces at least part of the silicon substrate having single-crystalline silicon. It should be understood that in some examples, trench isolation and doping regions (not shown) may also be formed in the semiconductor layer 326. It should also be understood that in some examples, the semiconductor layer 326 may include multiple semiconductor layers in the vertical direction, and dielectric layers are formed therebetween.

[0084] As Figure 5 shown, the second structure 304 may further include a pad lead-out layer 327 located above the semiconductor layer 326. The pad lead-out layer 327 may include dummy pads 330, one or more ILD layers 332 (e.g., silicon oxide layer and silicon nitride layer), and a protective layer 334 (e.g., polyimide layer) located at the top surface of the semiconductor device 500. The pad lead-out layer 327 and the interconnect layer 323 may be formed on opposite sides of the semiconductor layer 326. In some embodiments, openings 336 are formed through the protective layer 334 and the ILD layers 332 in the pad lead-out layer 327 to expose the dummy pads 330, thereby allowing wire bonding to be performed on the top surface of the dummy pads 330.

[0085] Consistent with the scope of the present disclosure, the semiconductor device 500 may include an interconnect structure 314 located between the device layer 310 and the dummy pads 330 in the vertical direction (e.g., Figure 5 the z direction in the figure), such that the dummy pads 330 are connected to the ESD circuit 502 in the device layer 310 at least through the interconnect structure 314. On the other hand, according to some embodiments, the dummy pads 330 are disconnected from the functional circuit 312 in the device layer 310. The interconnect structure 314 may be in the vertical direction (e.g., Figure 5extends in the z - direction). The semiconductor layer 326 can be disposed vertically between the dummy pad 330 and the interconnect structure 314. As Figure 5 shown, according to some embodiments, the interconnect structure 314 and the dummy pad 330 overlap, which are considered corresponding structures in the present disclosure. In other words, for each dummy pad 330, the semiconductor device 500 can include a corresponding overlapping interconnect structure 314.

[0086] As Figure 5 shown, the interconnect structure 314 can include bond contacts 320 and 318 in bond layers 315 and 313, and device contacts 316 in the interconnect layer 311 of the first structure 302. According to some embodiments, the device contacts 316 are disposed between the bond interface 306 and the device layer 310, and the bond interface 306 is disposed vertically between the dummy pad 330 and the device layer 310. It should be understood that in some embodiments, the interconnect structure 314 may further include interconnects 322 in the interconnect layer 323 of the second structure 304.

[0087] As Figure 5 shown, the second structure 304 of the semiconductor device 500 may further include via contacts 324 extending in the vertical direction in the interconnect layer 323. The via contacts 324 may include W. In some embodiments, the via contacts 324 contact the interconnect structure 314. That is, the via contacts 324 can be disposed between the dummy pad 330 and the interconnect structure 314 and connected to the interconnect structure 314. The second structure 304 of the semiconductor device 500 may further include spacers 504 in the semiconductor layer 326 and via contacts 402 extending vertically through the spacers 504. The spacers 504 may include dielectric materials, such as silicon oxide or silicon nitride. In some embodiments, the via contacts 402 contact the dummy pad 330 and the via contacts 324 at opposite ends. That is to say, the via contacts 402 can electrically connect the dummy pad 330 and the via contacts 324. The via contacts 402 may also include W. As a result, the dummy pad 330 can be electrically connected to the ESD circuit 502 in the device layer 310 at least through the interconnect structure 314 and the via contacts 324 and 402. Therefore, ESD from the dummy pad 330 can be propagated to the ESD circuit 502 and mitigated by the ESD circuit 502 to prevent damage to the functional circuit 312.

[0088] Figures 7A-7E illustrates a manufacturing process for forming a semiconductor device with a dummy pad according to some aspects of the present disclosure. Figures 8A-8E illustrates a manufacturing process for forming another semiconductor device with a dummy pad according to some aspects of the present disclosure. Figure 9FIG. 900 is a flow chart of a method for forming a semiconductor device having dummy pads in accordance with some embodiments of the present disclosure. Figures 7A-7E and Figures 8A-8E and Figure 9 Examples of semiconductor devices depicted in Figure 3A and Figure 3B and Figure 4 include semiconductor devices 300, 301, and 400 depicted in Figures 7A-7E and Figures 8A-8E and Figure 9 . It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously, or in an order different from the Figure 9 order shown.

[0089] Referring to Figure 9 , method 900 begins at operation 902, where a device layer including functional circuitry is formed. As Figure 7A and Figure 8A shown, a device layer 710 including functional circuitry 712 and 738 is formed on a silicon substrate 708 having single-crystalline silicon. The functional circuitry 712 and 738 may be formed by a variety of processes, including but not limited to lithography, dry / wet etching, thin-film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 708 by ion implantation and / or thermal diffusion, which are used as, for example, wells and source / drain regions of transistors in the functional circuitry 712 and 738. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 708 by wet / dry etching and thin-film deposition.

[0090] Method 900 proceeds to operation 904, as Figure 9 shown, where an interconnect structure is formed on the device layer and disconnected from the functional circuitry. In some embodiments, another interconnect structure is formed on the device layer and connected to the functional circuitry. The interconnect structure and the other interconnect structure may be formed by the same process.

[0091] As Figure 7A and Figure 8AAs shown, an interconnect layer 711 is formed over a device layer 710. The interconnect layer 711 may include interconnects of MEOL and / or BEOL in multiple ILD layers, such as device contacts 716, for making electrical connections to functional circuit 738 instead of functional circuit 712. That is, the device contacts 716 may be connected to the functional circuit 738 but are disconnected from the functional circuit 712. In some embodiments, the interconnect layer 711 includes multiple ILD layers formed in multiple processes and the interconnects therein. For example, the interconnects in the interconnect layer 711 may include conductive materials deposited by one or more thin film deposition processes, which include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing processes for forming the interconnects may also include lithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers may include dielectric materials deposited by one or more thin film deposition processes, which include but are not limited to CVD, PVD, ALD, or any combination thereof. Figure 7A and Figure 7B The ILD layers and interconnects shown in and may be collectively referred to as the interconnect layer 711. In some embodiments, the interconnects (such as device contacts 716) in the interconnect layer 711 include Cu, which has a relatively low resistivity among conductive metal materials.

[0092] As Figure 7A and Figure 8A As shown, a bonding layer 713 is formed over the interconnect layer 711. The bonding layer 713 may include multiple bonding contacts 718 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 711 by one or more thin film deposition processes, which include but are not limited to CVD, PVD, ALD, or any combination thereof. Then, the bonding contacts 718 that pass through the dielectric layer and contact the interconnects in the interconnect layer 711 may be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., lithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor. For example, the adhesion layer may improve the adhesion of the conductor to avoid defects, the barrier layer may prevent metal ions (e.g., Cu ions) from diffusing from the conductor into other structures and causing contamination, and the seed layer may facilitate the deposition of the conductor (e.g., Cu) in the contact holes to improve the deposition quality and speed.

[0093] As Figure 7A and Figure 8AAs shown, a stacked structure such as a memory stack 748 including interleaved conductive layers and dielectric layers is formed on a silicon substrate 726. To form the memory stack 748, in some embodiments, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 726. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The interleaved sacrificial layers and dielectric layers can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The memory stack 748 can then be formed by a gate replacement process, e.g., the gate replacement process is a wet / dry etch of the sacrificial layer selective to the dielectric layer and filling the resulting recess with a conductive layer, thereby replacing the sacrificial layer with the conductive layer. In some embodiments, each conductive layer includes a metal layer, e.g., a W layer. It should be understood that in some examples, the memory stack 748 can be formed by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some embodiments, a pad oxide layer including silicon oxide (e.g., local oxidation of silicon (LOCOS) thermally grown on silicon) is formed between the memory stack 748 and the silicon substrate 726.

[0094] As Figure 7A and Figure 8A shown, a NAND memory string 750 is formed, each NAND memory string vertically extending through the memory stack 748. In some embodiments, the manufacturing process for forming the NAND memory string 750 includes forming a channel hole through the memory stack 748 (or dielectric stack) and into the silicon substrate 726 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), and subsequently filling the channel hole with multiple layers (e.g., memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers) using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. It should be understood that the details of manufacturing the NAND memory string 750 can vary depending on the type of channel structure of the NAND memory string 750, and thus are not elaborated in detail for the sake of simplicity.

[0095] As Figure 7A and Figure 8AAs shown, a bonding layer 715 is formed over the memory stack 748. The bonding layer 715 may include a plurality of bonding contacts 720 surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the memory stack 748 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. The bonding contacts 720 through the dielectric layer may then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., lithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0096] As Figure 7A and Figure 8A shown, the silicon substrate 726 and the components formed thereon (e.g., the memory stack 748 and the NAND memory strings 750 formed therethrough) are flipped upside down. The face-down bonding layer 715 is bonded to the face-up bonding layer 713, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 706. That is, the silicon substrate 708 and the components formed thereon may be bonded to the silicon substrate 726 and the components formed thereon in a face-to-face manner such that the bonding contacts 718 in the bonding layer 713 contact the bonding contacts 720 in the bonding layer 715 at the bonding interface 706. In some embodiments, a processing process such as plasma processing, wet processing, and / or heat processing may be applied to the bonding surfaces before bonding. In some embodiments, the silicon substrate 726 is thinned after bonding to form a thinned silicon substrate, which is also referred to herein as the semiconductor layer 726.

[0097] As a result of the bonding, such as hybrid bonding, the bonding contacts 718 and 720 on opposite sides of the bonding interface 706 may be mixed with each other. After bonding, the bonding contacts 718 in the bonding layer 713 and the bonding contacts 720 in the bonding layer 715 are aligned and in contact with each other such that two interconnect structures 714 and 740 may be formed. The interconnect structure 714 or 740 may include the bonding contacts 718 and 720 spanning the bonding interface 706 and the device contacts 716. As Figure 7A and Figure 8A shown, the interconnect structure 714 is formed on the device layer 710 and is disconnected from the functional circuit 712, while the interconnect structure 740 is formed on the device layer 710 and is connected to the functional circuit 738.

[0098] Method 900 proceeds to operation 906, as Figure 9As shown, a first via contact is formed on the interconnect structure and connected to the interconnect structure. In some embodiments, another first via contact is formed on another interconnect structure and connected to that another interconnect structure. The first via contact and the another first via contact can be formed by the same process.

[0099] As Figure 7A shown, before bonding, via contacts 724 and 742 are formed, for example, by the same process as that for forming word line contacts through the memory stack 748. Then, via contacts 724 and 742 through the dielectric layer can be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., lithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor. After bonding, via contact 724 can become connected to and formed on interconnect structure 714, as Figure 7A shown. Similarly, via contact 742 can become connected to and formed on interconnect structure 740.

[0100] Method 900 proceeds to operation 908, as Figure 9 shown, where an isolation structure is formed on the first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, thereby exposing the first via contact and the another first via contact, and a dielectric layer is deposited to fill the trench.

[0101] As Figure 7A shown, trench 727 is formed by removing a portion of semiconductor layer 726 to expose one end of via contacts 724 and 742. Trench 727 can be formed by etching semiconductor layer 726, for example, using dry etching and / or wet etching to remove the portion of semiconductor layer 726 covering via contacts 724 and 742 until via contacts 724 and 742 are exposed.

[0102] As Figure 7B shown, trench 727 is filled with a dielectric layer ( Figure 7A shown). For example, a dielectric layer such as silicon oxide can be deposited to fill trench 727 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, isolation structure 728 can be formed on via contacts 724 and 742 as part of the deposited dielectric layer, as Figure 7B shown.

[0103] In some embodiments, a second via contact is formed on and in contact with another first via contact and extends through the isolation structure. To form the second via contact, in some embodiments, a portion of the isolation structure is removed to form a hole, thereby exposing another first via contact but not exposing the first via contact, and a metal layer is deposited to fill the hole. The metal layer may include W.

[0104] As Figure 7C shown, a hole 746 is formed by removing a portion of the isolation structure 728 to expose one end of the via contact 742 without exposing the via contact 724. The isolation structure 728 may be etched, such as by using dry etching and / or wet etching, to selectively remove the portion of the isolation structure 728 covering the via contact 742 without removing the via contact 724 until the via contact 742 is exposed to form the hole 746. A photolithography process may be first used to pattern an etch mask to expose only the portion of the isolation structure 728 covering the via contact 742 but not the via contact 724. The etch mask may then protect the portion of the isolation structure 728 covering the via contact 724 during the etching process. It should be understood that in some examples, another hole 747 may also be formed by the same process of forming the hole 746, for example, to expose components in the memory stack 748, such as a slit structure or the source extreme of the NAND memory string 750.

[0105] As Figure 7D shown, the hole 746 ( Figure 7C as shown therein) is filled with a metal layer such as W. For example, a metal layer such as W may be deposited to fill the hole 746 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, a via contact 744 may be formed through the isolation structure 728 to land on and in contact with the via contact 742, as Figure 7D shown. In contrast, as Figure 7D shown, a via contact in contact with the via contact 724 may not be formed on the via contact 724. It should be understood that in some examples, another via contact 749 in contact with a component (such as a slit structure or the source extreme of the NAND memory string 750) in the memory stack 748, for example, may also be formed by the same process of forming the via contact 744.

[0106] Method 900 proceeds to operation 910, as Figure 9 shown, where a dummy pad is formed on the isolation structure and is disconnected from the first via contact through the isolation structure. In some embodiments, a pad is formed on and in contact with the second via contact. The dummy pad and the pad may be formed by the same process.

[0107] As Figure 7DAs shown, a pad layer 729 such as aluminum is deposited on the via contact 744. For example, a metal layer such as aluminum can be deposited on the via contacts 744 and 749 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof.

[0108] As Figure 7E shown, the pad layer 729 ( Figure 7D shown) is patterned to form dummy pads 730 and pads 745. The pad 745 can be formed on and in contact with the via contact 744, and is thus electrically connected to the functional circuit 738 in the device layer 710 through the via contacts 744 and 742 and the interconnect structure 740. In contrast, the dummy pad 730 can be formed on the isolation structure 728 and is disconnected from the via contact 724 through the isolation structure 728. Thus, the dummy pad 730 can be electrically disconnected from the interconnect structure 714. To form the dummy pads 730 and pads 745, a patterning process (e.g., photolithography and dry / wet etching of the pad layer 729) can be performed on the pad layer 729. A dielectric layer 732 (e.g., including silicon nitride) and a protective layer 734 (e.g., including polyimide) can then be formed on the dummy pads 730 and pads 745, followed by a patterning process to form openings 736 and 746 through the dielectric layer 732 and the protective layer 734 to expose the dummy pad 730 and the pad 745, respectively.

[0109] It should be understood that in some examples, different from the operation 906 of forming a first via contact on the interconnect structure and connecting it to the interconnect structure, a dielectric layer is formed on the interconnect structure.

[0110] As Figure 8A shown, a dielectric layer 801 is formed on the interconnect structure 714. That is, according to some embodiments, the via contact 742 is only formed on the interconnect structure 740 and connected to the interconnect structure 740, but not connected to the interconnect structure 714.

[0111] In some embodiments, an isolation structure is formed on another first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench to expose another first via contact, and a dielectric layer is deposited to fill the trench.

[0112] As Figure 8A shown, a trench 727 is formed by removing a portion of the semiconductor layer 726 to expose one end of the via contact 742. The semiconductor layer 726 can be etched, for example, using dry etching and / or wet etching to remove the portion of the semiconductor layer 726 covering the via contact 742 until the via contact 742 is exposed to form the trench 727.

[0113] As Figure 8BAs shown, the trench 727 is filled with a dielectric layer ( Figure 8A as shown in). For example, a dielectric layer such as silicon oxide can be deposited to fill the trench 727 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, an isolation structure 728 can be formed on the via contact 742 as part of the deposited dielectric layer, as Figure 8B shown.

[0114] In some embodiments, a second via contact is formed extending through the isolation structure. In some embodiments, another second via contact is formed on and connected to another first via contact and extends through the isolation structure. To form the second via contact and the another second via contact, in some embodiments, a portion of the isolation structure is removed to form a hole through the isolation structure, and a metal layer is deposited to fill the hole. The metal layer can include W.

[0115] As Figure 8C shown, holes 746 and 802 are formed by removing portions of the isolation structure 728. Hole 746 can expose one end of the via contact 742, and hole 802 can be aligned with the interconnect structure 714. Holes 746 and 802 can be formed by etching the isolation structure 728, for example, using dry etching and / or wet etching, to selectively remove the portion of the isolation structure 728 covering the via contact 742 and the portion of the isolation structure 728 aligned with the interconnect structure 714 until the via contact 742 is exposed. A photolithography process can be first used to pattern an etch mask to expose the portion of the isolation structure 728 covering the via contact 742 and the portion of the isolation structure 728 aligned with the interconnect structure 714. It should be understood that in some examples, another hole 747 can also be formed by the same process of forming holes 746 and 802, for example, to expose components in the memory stack 748, such as a gap structure or the source extreme of the NAND memory string 750.

[0116] As Figure 8D shown, holes 746 and 802 are filled with a metal layer such as W ( Figure 8C as shown in). For example, a metal layer such as W can be deposited to fill holes 746 and 802 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, a via contact 744 can be formed through the isolation structure 728 to land on and contact the via contact 742, as Figure 8D shown. Another via contact 804 can be formed through the isolation structure 728 to land on the dielectric layer 801 and overlap with the interconnect structure 714, as Figure 8DAs shown. It should be understood that in some examples, for instance, another via contact 749 that contacts a component (such as a source extreme of a slit structure or a NAND memory string 750) in the memory stack 748 can also be formed by the same process that forms the via contacts 744 and 804.

[0117] In some embodiments, dummy pads are formed on and in contact with the second via contacts. In some embodiments, pads are formed on and in contact with another second via contact. The dummy pads and the pads can be formed by the same process.

[0118] As Figure 8D shown, a pad layer 729 such as aluminum is deposited on the via contacts 744 and 804. For example, a metal layer such as aluminum can be deposited on the via contacts 744, 804, and 749 by one or more thin - film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof.

[0119] As Figure 8E shown, the pad layer 729 ( Figure 8D as shown) is patterned to form the dummy pad 730 and the pad 745. The pad 745 can be formed on and in contact with the via contact 744, and thus is electrically connected to the functional circuit 738 in the device layer 710 through the via contacts 744 and 742 and the interconnect structure 740. The dummy pad 730 can be formed on and in contact with the via contact 804. However, the dummy pad 730 and the via contact 804 can be disconnected from the interconnect structure 714 through the dielectric layer 801. Thus, the dummy pad 730 can be electrically disconnected from the interconnect structure 714. To form the dummy pad 730 and the pad 745, a patterning process (such as lithography and dry / wet etching of the pad layer 729) can be performed on the pad layer 729. Subsequently, a dielectric layer 732 (such as including silicon nitride) and a protective layer 734 (such as including polyimide) can be formed on the dummy pad 730 and the pad 745, and then openings 736 and 746 are formed through the dielectric layer 732 and the protective layer 734 by a patterning process to expose the dummy pad 730 and the pad 745 respectively.

[0120] The above description of the specific embodiments can be easily modified and / or adapted for various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments.

[0121] The breadth and scope of the present disclosure should not be limited by any of the above - mentioned exemplary embodiments, but should be defined only by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: a device layer; a dummy pad; a dielectric structure located between the device layer and the dummy pad and extending in a vertical direction; and an interconnect structure located between the device layer and the dielectric structure and extending in the vertical direction, wherein the dielectric structure, the interconnect structure, and the dummy pad are overlapping.

2. The semiconductor device according to claim 1, further comprising: a semiconductor layer located between the dummy pad and the interconnect structure, wherein the dielectric structure includes an isolation structure located in the semiconductor layer.

3. The semiconductor device according to claim 2, wherein a lateral dimension of the isolation structure is greater than a lateral dimension of the dummy pad.

4. The semiconductor device according to claim 2 or 3, further comprising a first via contact that contacts the interconnect structure and is separated from the dummy pad by the isolation structure.

5. The semiconductor device according to claim 4, wherein the first via contact includes tungsten.

6. The semiconductor device according to claim 1, further comprising: a second via contact that contacts the dummy pad and extends in the vertical direction, wherein the dielectric structure includes a dielectric layer located between the second via contact and the interconnect structure.

7. The semiconductor device according to claim 6, wherein the second via contact is separated from the interconnect structure by the dielectric layer.

8. The semiconductor device according to claim 6 or 7, wherein the second via contact includes tungsten.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a bonding interface located between the dummy pad and the device layer, wherein the interconnect structure includes a bonding contact located at the bonding interface.

10. The semiconductor device according to claim 9, wherein the interconnect structure further includes a device contact located between the bonding interface and the device layer.

11. The semiconductor device according to any one of claims 1 - 10, further comprising: a pad; another second via contact that contacts the pad; another first via contact that contacts the another second via contact; and another interconnect structure that contacts the another first via contact and the device layer.

12. The semiconductor device according to claim 11, wherein: the pad is coplanar with the dummy pad; and the interconnect structure is coplanar with the another interconnect structure.

13. A semiconductor device, comprising: a device layer including an electrostatic discharge (ESD) circuit and a functional circuit; a dummy pad disconnected from the functional circuit; and an interconnect structure located between the device layer and the dummy pad, wherein the dummy pad is connected to the ESD circuit at least through the interconnect structure.

14. The semiconductor device according to claim 13, further comprising a first via contact located between the dummy pad and the interconnect structure and connected to the interconnect structure.

15. The semiconductor device according to claim 14, further comprising: a semiconductor layer located between the dummy pad and the first via contact; a spacer located in the semiconductor layer; and a second via contact that contacts the dummy pad and the first via contact and extends through the spacer.

16. The semiconductor device according to claim 15, wherein, the first via contact and the second via contact comprise tungsten.

17. The semiconductor device according to claim 15 or 16, wherein, the dummy pad is connected to the ESD circuit at least through the interconnect structure and the first via contact and the second via contact.

18. The semiconductor device according to any one of claims 16-17, further comprising a bonding interface located between the dummy pad and the device layer, wherein, the interconnect structure comprises a bonding contact located at the bonding interface.

19. The semiconductor device according to claim 18, wherein, the interconnect structure further comprises a device contact located between the bonding interface and the device layer.

20. A method for forming a semiconductor device, comprising: forming a device layer including a functional circuit; forming an interconnect structure on the device layer, and the interconnect structure is disconnected from the functional circuit; forming a first via contact on the interconnect structure, and the first via contact is connected to the interconnect structure; forming an isolation structure on the first via contact; and forming a dummy pad on the isolation structure, and the dummy pad is disconnected from the first via contact through the isolation structure.

21. The method according to claim 20, further comprising: forming another interconnect structure on the device layer, and the another interconnect structure is connected to the functional circuit; forming another first via contact on the another interconnect structure, and the another first via contact is connected to the another interconnect structure; forming a second via contact on the another first via contact, and the second via contact contacts the another first via contact and extends through the isolation structure; and forming a pad on the second via contact, and the pad contacts the second via contact.

22. The method according to claim 21, wherein, forming the isolation structure comprises: removing a portion of the semiconductor layer to form a trench to expose the first via contact and the another first via contact; and depositing a dielectric layer to fill the trench.

23. The method according to claim 21, wherein, forming the second via contact comprises: removing a portion of the isolation structure to form a hole to expose the another first via contact but not expose the first via contact; and depositing a metal layer to fill the hole.

24. The method according to claim 23, wherein, the metal layer comprises tungsten.

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