System-level chip cache method and system using adaptive prediction technology

Abstract

The present invention provides a system-on-chip cache method and system using adaptive prediction technology. It relates to the field of electronic information technology. In particular, the main memory is responsible for reading a series of continuous instructions and storing them in a buffer. The buffer is used to temporarily store these instructions, which may include a pre-jump instruction sequence and a post-jump instruction sequence, and are managed through labels. When the decoding unit determines to execute a jump instruction, it sends jump execution information to the buffer, and the buffer then reads the target instruction after the jump to the decoding unit based on the information. This embodiment manages the jump of instructions by using label indications, avoiding the need to clear the buffer or wait for the main memory to reload instructions when executing a jump instruction, thereby significantly reducing waiting time, improving system efficiency, reducing resource waste, and improving resource utilization.

Description

Technical Field

[0001] The present invention belongs to the field of electronic information technology, and in particular relates to a system-level chip cache method and system using an adaptive prediction technology. Background Art

[0002] With the continuous advancement of integrated circuits and industrial intelligence, the design scale of embedded SOCs is expanding, and performance requirements are increasing. This poses greater challenges to the overall performance and execution efficiency of instruction processing. For DSPs in particular, a commonly adopted solution to improve performance is to add a first-level cache after the Flash to compensate for the speed difference between the high-speed CPU and the slow Flash, thereby improving the overall efficiency of system instruction execution to a certain extent. However, this technology has a significant drawback when processing jump instructions: it flushes the cache and re-fetches the instruction from the Flash address after the jump, resulting in a long wait time and significantly reducing the overall efficiency of the system. This problem is particularly prominent due to the high proportion of jump instructions in programs. To further address this issue, existing technologies add a first buffer and a second buffer between the main memory and the decoding unit. By using the second buffer to pre-cache the instructions to be executed after the jump, the system does not need to wait for the instructions to be written to the buffer, effectively improving overall efficiency. However, due to the generally high cost of buffers, this solution actually only uses one of the two buffers to compensate for the speed difference between the high-speed CPU and the slow-speed Flash, while the other buffer is in standby mode most of the time, resulting in a certain amount of resource waste. Summary of the Invention

[0003] The present invention aims to address at least one of the technical problems existing in the prior art. To this end, the present invention proposes a system-on-chip cache method and system using adaptive prediction technology. This approach aims to improve overall efficiency while also enhancing resource utilization.

[0004] In a first aspect, an embodiment of the present invention provides a system-on-chip caching method using adaptive prediction technology, comprising the following steps:

[0005] According to a preset rule, a plurality of consecutive first instructions to be executed are read from a main memory and cached in a buffer, wherein the buffer further includes a first tag indication, wherein the first tag indication is used to indicate the number of remaining unexecuted instructions in the first instructions to be executed;

[0006] Based on the first tag indication, a first target to-be-executed instruction among the first to-be-executed instructions is read from the buffer to a decoding unit, wherein the decoding unit determines an instruction type of the first target to-be-executed instruction, where the instruction type includes a jump type and a non-jump type;

[0007] When it is determined that the instruction type of the first target to-be-executed instruction is a jump type, a jump prediction message is sent to the adaptive prediction module; the adaptive prediction module performs prediction based on the jump prediction message and sends the prediction result to the address selection module;

[0008] The address selection module reads a plurality of consecutive second instructions to be executed from the main memory based on the prediction result and caches them in a buffer, wherein the second instructions to be executed are instructions to be executed after a jump, and the buffer further includes a second tag indication, wherein the second tag indication is used to indicate the number of remaining unexecuted instructions in the second instructions to be executed;

[0009] When the decoding unit determines to execute the first target to-be-executed instruction, it sends a jump execution message to the buffer; after receiving the jump execution message, the buffer reads the second target to-be-executed instruction in the second to-be-executed instruction to the decoder based on the second tag indication.

[0010] In a second aspect, a system-on-chip cache system using adaptive prediction technology is provided, comprising: a main memory, a buffer, a decoding unit, an adaptive prediction module, and an address selection module;

[0011] The main memory is configured to read a plurality of consecutive first instructions to be executed according to a preset rule and cache the plurality of consecutive first instructions to be executed in a buffer, wherein the buffer further includes a first tag indication, wherein the first tag indication is configured to indicate the number of remaining unexecuted instructions in the first instructions to be executed;

[0012] The buffer is configured to read a first target to-be-executed instruction from the first to-be-executed instructions to a decoding unit based on the first tag indication;

[0013] The decoding unit is configured to determine an instruction type of the first target instruction to be executed, where the instruction type includes a jump type and a non-jump type; and when it is determined that the instruction type of the first target instruction to be executed is a jump type, send a jump prediction message to the adaptive prediction module;

[0014] The adaptive prediction module is used to make predictions based on the jump prediction message and send the prediction results to the address selection module;

[0015] The address selection module is configured to instruct the main memory to read a plurality of consecutive second instructions to be executed and cache them in a buffer based on the prediction result, wherein the second instructions to be executed are instructions to be executed after a jump, and the buffer further includes a second tag indication, wherein the second tag indication is used to indicate the number of remaining unexecuted instructions in the second instructions to be executed;

[0016] The decoding unit is further configured to, when determining to execute the first target instruction to be executed, send a jump execution message to the buffer;

[0017] The buffer is further configured to read a second target to-be-executed instruction in the second to-be-executed instructions to a decoder based on the second tag instruction after receiving the jump execution message.

[0018] The system-on-chip cache method and system using adaptive prediction technology according to the embodiments of the present invention have at least the following technical effects: there is no need to clear the instructions to be executed that have been cached in the buffer, and no more buffers are required. Jumps are achieved through label indications, and there is no need for the CPU to wait for the main memory to rewrite the instructions to be executed after the jump into the buffer. Compared with traditional caching methods, the waiting time when executing jump instructions is greatly reduced, the overall efficiency of the system is effectively improved, and at the same time, resource redundancy is reduced and resource utilization is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic diagram of the structure of a system-on-chip cache system using adaptive prediction technology provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of another system-on-chip cache system structure using adaptive prediction technology provided in an embodiment of the present application;

[0022] Figure 3 A flowchart of a system-on-chip caching method using adaptive prediction technology is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] In order to better describe the system-level chip cache method and system using adaptive prediction technology in an embodiment of the present invention, an embodiment of the present application provides an architecture platform for executing the system-level chip cache method using adaptive prediction technology, such as Figure 1As shown in 2, the system-on-chip cache system using adaptive prediction technology includes: a main memory, a buffer, a decoding unit, an adaptive prediction module and an address selection module;

[0025] Among them, Main Memory refers to the component in the computer used to store data and programs. It can be directly accessed by the CPU and is used to temporarily store running programs and data.

[0026] Buffer: A storage device used to temporarily store data to coordinate data transmission between devices of different speeds or processing capabilities.

[0027] Decoding Unit: usually refers to the instruction decoder, which is responsible for parsing the instructions received by the CPU and converting them into control signals that the computer can understand.

[0028] Adaptive Prediction Module: Used to predict system behavior or outcomes, and self-adjusts based on historical data and patterns to improve prediction accuracy.

[0029] Address Selection Module: Responsible for selecting an address for reading or writing data from multiple possible addresses.

[0030] In an embodiment of the present application, the main memory is used to read multiple consecutive first instructions to be executed according to a preset rule and cache them in a buffer.

[0031] The preset rule is a pre-set instruction reading order or logic condition, which is used to determine the calling priority and address sequence of the instructions to be executed in the main memory.

[0032] The continuous instructions are physically or logically adjacent storage states of the first instruction to be executed in the main memory, ensuring that the instruction stream is read without gaps.

[0033] The buffer is used to store a plurality of consecutive first instructions to be executed, and the buffer further includes a first tag indication. The first tag indication is used to indicate the number of remaining unexecuted instructions in the first instructions to be executed. The buffer is used to read a first target instruction to be executed in the first instructions to be executed to a decoding unit based on the first tag indication;

[0034] The decoding unit is used to determine the instruction type of the first target instruction to be executed, which includes a jump type and a non-jump type. When it is determined that the instruction type of the first target instruction to be executed is a jump type, the decoding unit sends a jump prediction message to the adaptive prediction module.

[0035] Among them, jump type instructions use the opcode to determine whether to change the program counter (PC) to implement branches, loops, or function calls; non-jump type instruction opcodes do not modify the PC and execute data processing, storage, and other operations sequentially.

[0036] The adaptive prediction module is used to make predictions based on the jump prediction message and send the prediction results to the address selection module.

[0037] The address selection module is used to instruct the main memory to read a plurality of consecutive second instructions to be executed and cache them in the buffer based on the prediction result, wherein the second instructions to be executed are instructions to be executed after a jump.

[0038] The address selection template parses the original address text and prediction message packets to extract instruction storage address features (segment address / offset / cache line identifier). Based on the jump prediction results, a candidate address set is generated to establish an instruction prefetch queue: main memory → L2 cache → L1 instruction cache. Verification is performed hierarchically based on the physical memory structure: NUMA node → memory channel → bank group → row address. Cache line alignment optimization (64-byte boundary detection) is implemented. Conflict resolution can also be performed, such as initiating a page table walk or triggering a page fault interrupt, and cache replacement strategies (LRU / Pseudo-LRU) are implemented.

[0039] The buffer further includes a second tag indication, where the second tag indication is used to indicate the number of remaining unexecuted instructions in the second to-be-executed instructions;

[0040] The decoding unit is further configured to send a jump execution message to the buffer when determining to execute the first target instruction to be executed;

[0041] The buffer is further configured to read a second target to-be-executed instruction in the second to-be-executed instructions to a decoder based on a second tag indication after receiving the jump execution message.

[0042] Through the embodiments of the present application, there is no need to clear the instructions to be executed that have been cached in the buffer, nor is there a need for more buffers. Jumps are achieved through label indications, and there is no need for the CPU to wait for the main memory to rewrite the instructions to be executed after the jump into the buffer. Compared with traditional caching methods, the waiting time for executing jump instructions is greatly reduced, the overall efficiency of the system is effectively improved, and at the same time, resource redundancy is reduced and resource utilization is improved.

[0043] In an embodiment of the present application, the main memory is responsible for reading a series of consecutive instructions and storing them in a buffer. The buffer is used to temporarily store these instructions and contains a tag indicator that indicates the number of unexecuted instructions. When the decoder receives these instructions, it identifies the instruction type and determines whether it is a jump instruction. If it is a jump instruction, the decoder sends jump prediction information to the adaptive prediction module, which makes a jump decision based on the prediction information and passes the result to the address selection module. Based on the prediction result, the address selection module instructs the main memory to read the instruction sequence after the jump and store it in the buffer. The buffer also contains another tag indicator that indicates the number of unexecuted instructions in the instruction sequence after the jump. When the decoder determines to execute the jump instruction, it sends jump execution information to the buffer, which then reads the target instruction after the jump and returns it to the decoder. This embodiment uses tag indicators to manage instruction jumps, eliminating the need to clear the buffer or wait for the main memory to reload instructions when executing a jump instruction. This significantly reduces latency, improves system efficiency, reduces resource waste, and improves resource utilization.

[0044] In the embodiment of the present application, the label indication may include multiple implementation methods. As an example, Figure 2 As shown, the buffer includes multiple tags, each tag corresponds to a storage area, and each area is used to store the first to-be-executed instruction or the second to-be-executed instruction read at the same time;

[0045] Each tag includes: quantity identifier, activation status identifier and jump identifier.

[0046] The label of the first state of the jump identifier corresponds to the first instruction to be executed, and the label of the second state of the jump identifier corresponds to the second instruction to be executed.

[0047] The quantity identifier is used to record the number of unexecuted instructions in the corresponding area. When the number of unexecuted instructions corresponding to the tag is 0, the tag is used to record that the corresponding area can be overwritten.

[0048] The activation status flag is used to indicate whether the to-be-executed instructions stored in the corresponding area can be read.

[0049] The first tag indicates that the tag corresponding to the jump flag being in the first state is in the active state, and the tag corresponding to the jump flag being in the second state is in the inactive state.

[0050] The second tag indicates that the tag corresponding to the jump flag being in the first state is in an inactive state, and the tag corresponding to the jump flag being in the second state is in an active state.

[0051] For example, when the decoding unit recognizes a jump instruction, the jump flag in the buffer switches from the first state (corresponding to the first instruction to be executed) to the second state (corresponding to the second instruction to be executed), and the quantity flag of the second instruction to be executed is greater than zero; at the same time, the activation state flag of the original first instruction to be executed changes from valid to invalid, but its quantity flag is retained for subsequent overwrite judgment.

[0052] After the main memory loads the second pending instruction sequence based on the jump prediction result from the address selection module, the buffer marks the switch between the old and new instruction streams by changing the jump flag state, while the count flag continuously tracks the number of unexecuted instructions. When the decode unit confirms the jump execution, the activation state flag is synchronously updated, allowing the second pending instruction sequence to be read while retaining the unused portion of the first instruction stream for exception fallback.

[0053] As another example, Figure 1 As shown, the buffer may include multiple tags, each tag is used to record a to-be-executed instruction; the first tag is used to record the first unexecuted to-be-executed instruction among the first to-be-executed instructions; the second tag is used to record the first unexecuted to-be-executed instruction among the second to-be-executed instructions; the third tag is used to record whether the first to-be-executed instruction or the second to-be-executed instruction currently being executed is executed;

[0054] Wherein, the first tag indicates execution of the first instruction to be executed corresponding to the third tag instruction;

[0055] The second tag indicates that the second instruction to be executed is executed corresponding to the third tag instruction.

[0056] After determining to execute the first instruction to be executed or the second instruction to be executed according to the third tag, a specific instruction to be executed is determined according to the first tag or the second tag.

[0057] For example, the number of unexecuted instructions in the storage area corresponding to a certain label in the buffer is reset to zero, and its activation status is marked as invalid (not the currently executing instruction stream); at the same time, the buffer detects that the main memory needs to load a new instruction sequence and there is no free storage area. When the third label indicates the switch to the second instruction stream to be executed, the label corresponding to the original first instruction stream continues to monitor the quantity identifier. If all the instructions in the area have been executed and have not been reactivated, it is marked as an overwriteable state. When the buffer is full and new instructions need to be written, the area corresponding to the overwriteable label is preferentially selected for replacement, and the jump identifier and quantity identifier are updated at the same time to ensure that the continuity of the instructions is not interrupted.

[0058] Furthermore, this embodiment provides a dynamic management mechanism for tag indications. During the execution of instructions, the tag indication is dynamically updated based on the execution status of the instructions. For example, when all instructions in a region are executed, the quantity indicator is updated accordingly, indicating that the number of unexecuted instructions in that region has decreased.

[0059] At the same time, the activation status flag will also change according to the execution of the instruction. Once the instruction is executed, the corresponding storage area will be marked as overwritten. At this time, the quantity flag will be displayed as 0, and the activation status flag will be updated to inactive, indicating that the instructions in the area are no longer needed.

[0060] During instruction execution, if a jump is required, a jump flag plays a key role. Based on the program's logical requirements, it instructs the processor to jump to the storage area pointed to by the corresponding label to retrieve the next instruction to be executed.

[0061] In order to ensure the correctness and efficiency of instruction execution, this embodiment also introduces a tag indication verification mechanism. Before each instruction jump or execution, the system will check the tag indication to ensure that it correctly reflects the status of the storage area.

[0062] In addition, this embodiment also takes into account exception handling. During the execution of instructions, if an abnormal situation occurs, the system will quickly locate the problem according to the label indication and take corresponding recovery measures to ensure the stable operation of the system.

[0063] In some embodiments, the decoding unit includes a pre-decoder and a multi-stage decoder connected in sequence;

[0064] Among them, the pre-decoder is used to confirm the instruction type of the first target instruction to be executed read; if the first target instruction to be executed is confirmed to be a jump type instruction, a jump prediction message is generated; the multi-level decoder is used to confirm the first jump requirement state of the first target instruction to be executed, the first jump requirement state includes a first jump state and a first non-jump state; if the first jump requirement state is confirmed to be the first jump state, a jump execution message is generated.

[0065] As an example, this solution employs a dual verification mechanism involving a primary instruction decoder and a secondary privilege decoder. The primary decoder first parses the instruction format, verifying the validity of the opcode and whether the target address is within the permitted range of the instruction set architecture. The secondary decoder then checks the access rights of the target address, comparing the current privilege level with the access rights flags of the memory region where the target address resides. Only when both decoders output verification pass signals does the control unit generate a jump execution message and update the program counter.

[0066] In some embodiments, the adaptive prediction module is specifically configured to:

[0067] The jump probability is predicted based on historical data and jump prediction messages to obtain the predicted probability;

[0068] Predict the number of instructions based on historical data and predicted probability to obtain the predicted number;

[0069] A second instruction to be executed is determined based on the predicted number and the jump address in the jump prediction message.

[0070] In some embodiments, the predicted probability can be determined based on the following formula :

[0071] ;

[0072] in, , including the feature vectors of historical jump frequency, jump distance, and instruction type;

[0073] are model parameters, estimated through training data, j Used to distinguish different jump instructions, n represents the number of eigenvectors.

[0074] As an example, the model parameters β Training and optimization can be performed through the following scheme.

[0075] Collect relevant data of historical jump instructions, including the address of the jump instruction, the jump target address, the jump frequency, the jump distance, etc.

[0076] Collect instruction type information, such as branch instructions, jump instructions, call instructions, etc.

[0077] Collect the execution context information of instructions, such as the execution order of instructions, the dependencies of instructions, etc.

[0078] The collected data is cleaned to remove outliers and noise.

[0079] Normalize the data to convert data of different scales into the same scale range.

[0080] The data is divided into training set, validation set and test set for model training and evaluation.

[0081] Select features related to jump prediction, such as historical jump frequency, jump distance, instruction type, instruction execution context, etc.

[0082] Use feature selection techniques (such as principal component analysis PCA, Lasso regression, etc.) to reduce the dimension and select features to extract the features with the most predictive ability.

[0083] The logistic regression model is selected as the basic model to predict the execution probability of jump instructions.

[0084] The output of the logistic regression model is a probability value, which indicates the probability of the jump instruction being executed.

[0085] Use the training set data to train the logistic regression model and optimize the model parameters β .

[0086] The optimization goal is to maximize the likelihood function, that is, to maximize the predicted probability of the training data.

[0087] Use gradient descent or other optimization algorithms (such as Newton method, quasi-Newton method, etc.) to optimize parameters.

[0088] The loss function of the logistic regression model is the cross entropy loss function:

[0089] ;

[0090] in, N is the number of training samples, y i is the actual jump label (1 means jump, 0 means no jump), p i is the predicted jump probability.

[0091] Gradient descent method is used for parameter optimization.

[0092] Use the validation set data to evaluate the trained model and calculate the model's prediction accuracy, recall rate, F1 score and other indicators.

[0093] Adjust model parameters and feature selection based on the evaluation results to optimize model performance.

[0094] In practical applications, the model is regularly updated with new data to adapt to system changes and new jump patterns.

[0095] Use online learning technology to update model parameters in real time to improve model adaptability and prediction accuracy.

[0096] As an example, the forecast quantity can be determined based on the following formula :

[0097] ;

[0098] in, is the minimum instruction length of the cache;

[0099] The maximum instruction length of the cache.

[0100] As another example, the forecast quantity is determined based on the following formula :

[0101] ;

[0102] in, is the minimum instruction length of the cache;

[0103] is the maximum instruction length of the cache;

[0104] δ is the adjustment coefficient, used to adjust the eigenvector X The value of dynamically adjusts the instruction length;

[0105] α 1 ，α 2 ，⋯，α n is the eigenvector X The weight coefficient of

[0106] i is used to distinguish different eigenvectors, n represents the number of eigenvectors.

[0107] The embodiment of the present application dynamically manages multiple instruction streams in the buffer through label indications. There is no need to clear the buffer or wait for main memory to be reloaded when jumping. The atomic switching mechanism of the jump identifier and the activation status identifier (such as the state flipping of the first label indication and the second label indication) is utilized to achieve nanosecond-level instruction stream switching.

[0108] The use of label multiplexing technology (resetting the quantity identifier to zero triggers storage area overwriting) enables a single buffer to support the residence of multiple instruction streams, reducing storage unit occupancy by 33% compared to the traditional double-buffer solution; through an adaptive prediction model (jump probability calculation based on logistic regression and instruction quantity prediction formula), the amount of preloaded instructions is accurately controlled, reducing redundant data transfer by 18%.

[0109] Illegal jumps are blocked through a dual-label verification mechanism (pre-decoder verifies instruction format + secondary decoder detects memory permissions); the exception fallback protection design (retains the unexhausted part of the original instruction stream) shortens the error prediction recovery delay to 5 clock cycles and increases the fault recovery success rate to 99.7%.

[0110] It does not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that, with the evolution of SOC technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0111] Reference below Figures 1 to 2 A system-on-chip cache method using adaptive prediction technology according to an embodiment of the first aspect of the present invention is described.

[0112] like Figure 3As shown, the embodiment of the present application also provides a flow chart of a system-on-chip cache method using adaptive prediction technology, which specifically includes the following steps:

[0113] S310, reading a plurality of consecutive first instructions to be executed from a main memory according to a preset rule and caching them in a buffer, wherein the buffer further includes a first tag indicator, the first tag indicator being used to indicate the number of remaining unexecuted instructions in the first instructions to be executed;

[0114] S320, based on the first tag indication, reading a first target to-be-executed instruction in the first to-be-executed instructions from the buffer to a decoding unit, the decoding unit determining an instruction type of the first target to-be-executed instruction, where the instruction type includes a jump type and a non-jump type;

[0115] S330, when it is determined that the instruction type of the first target to-be-executed instruction is a jump type, sending a jump prediction message to the adaptive prediction module; the adaptive prediction module performs prediction based on the jump prediction message and sends the prediction result to the address selection module;

[0116] S340: The address selection module reads a plurality of consecutive second instructions to be executed from the main memory based on the prediction result and caches them in a buffer, where the second instructions to be executed are instructions to be executed after a jump, and the buffer further includes a second tag indicator, where the second tag indicator is used to indicate the number of remaining unexecuted instructions in the second instructions to be executed;

[0117] S350, when the decoding unit determines to execute the first target to-be-executed instruction, it sends a jump execution message to the buffer; after receiving the jump execution message, the buffer reads the second target to-be-executed instruction in the second to-be-executed instruction based on the second tag indication to the decoder.

[0118] In an embodiment of the present application, the main memory is responsible for reading a series of consecutive instructions and storing them in a buffer. The buffer is used to temporarily store these instructions and contains a tag indicator that indicates the number of unexecuted instructions. When the decoder receives these instructions, it identifies the instruction type and determines whether it is a jump instruction. If it is a jump instruction, the decoder sends jump prediction information to the adaptive prediction module, which makes a jump decision based on the prediction information and passes the result to the address selection module. Based on the prediction result, the address selection module instructs the main memory to read the instruction sequence after the jump and store it in the buffer. The buffer also contains another tag indicator that indicates the number of unexecuted instructions in the instruction sequence after the jump. When the decoder determines to execute the jump instruction, it sends jump execution information to the buffer, which then reads the target instruction after the jump and returns it to the decoder. This embodiment uses tag indicators to manage instruction jumps, eliminating the need to clear the buffer or wait for the main memory to reload instructions when executing a jump instruction. This significantly reduces latency, improves system efficiency, reduces resource waste, and improves resource utilization.

[0119] In some embodiments, the buffer includes a plurality of tags, each tag corresponds to a storage area, each area is used to store the first to-be-executed instruction or the second to-be-executed instruction read at the same time, and each tag includes: a quantity identifier, an activation state identifier, and a jump identifier;

[0120] The label of the first state of the jump identifier corresponds to the first instruction to be executed, and the label of the second state of the jump identifier corresponds to the second instruction to be executed;

[0121] The quantity identifier is used to record the number of unexecuted instructions in the corresponding area. When the number of unexecuted instructions corresponding to the tag is 0, the tag is used to record that the corresponding area can be overwritten;

[0122] The activation status flag is used to indicate whether the pending instructions stored in the corresponding area can be read;

[0123] The first tag indicates that the tag corresponding to the jump flag of the first state is in the active state, and the tag corresponding to the jump flag of the second state is in the inactive state;

[0124] The second tag indicates that the tag corresponding to the jump flag being in the first state is in an inactive state, and the tag corresponding to the jump flag being in the second state is in an active state.

[0125] In some embodiments, the buffer includes a plurality of tags, each tag being used to record a to-be-executed instruction;

[0126] The first tag is used to record the first unexecuted instruction to be executed in the first instructions to be executed;

[0127] The second tag is used to record the first unexecuted pending instruction in the second pending instructions;

[0128] The third tag is used to record whether the currently executed first instruction to be executed is the second instruction to be executed;

[0129] Wherein, the first tag indicates execution of the first instruction to be executed corresponding to the third tag instruction;

[0130] The second tag indicates execution of the second to-be-executed instruction corresponding to the third tag.

[0131] In some embodiments, the decoding unit includes a pre-decoder, a first-stage decoder, and a second-stage decoder connected in sequence;

[0132] The pre-decoder confirms the instruction type of the first target instruction to be executed;

[0133] If the first target to-be-executed instruction is confirmed to be a jump instruction, a jump prediction message is generated;

[0134] confirming, by a first-level decoder, a first jump requirement state of a first target instruction to be executed, the first jump requirement state including a first jump state and a first non-jump state;

[0135] If the first jump requirement state is confirmed as the first jump state, a jump execution message is generated.

[0136] In some embodiments, the adaptive prediction module performs prediction based on the jump prediction message, including:

[0137] The jump probability is predicted based on historical data and jump prediction messages to obtain the predicted probability;

[0138] Predict the number of instructions based on historical data and predicted probability to obtain the predicted number;

[0139] A second instruction to be executed is determined based on the predicted number and the jump address in the jump prediction message.

[0140] Among them, the predicted probability and predicted quantity can be combined with the above Figure 1 and Figure 2 The introduction of the implemented solution shown will not be repeated here.

[0141] The architecture platform described in the embodiment of the present application is intended to more clearly illustrate the technical solutions of the embodiment of the present application. In all the examples shown and described herein, any specific values ​​should be interpreted as merely exemplary rather than limiting. Therefore, other examples of the exemplary embodiment may have different values.

[0142] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0143] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0144] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system-on-chip cache method using adaptive prediction technology, characterized in that: The following steps are involved: According to a preset rule, a plurality of consecutive first instructions to be executed are read from a main memory and cached in a buffer, wherein the buffer further includes a first tag indication, wherein the first tag indication is used to indicate the number of remaining unexecuted instructions in the first instructions to be executed; Based on the first tag indication, a first target to-be-executed instruction among the first to-be-executed instructions is read from the buffer to a decoding unit, wherein the decoding unit determines an instruction type of the first target to-be-executed instruction, where the instruction type includes a jump type and a non-jump type; When it is determined that the instruction type of the first target to-be-executed instruction is a jump type, sending a jump prediction message to the adaptive prediction module; The adaptive prediction module makes predictions based on the jump prediction message and sends the prediction results to the address selection module; The address selection module reads a plurality of consecutive second instructions to be executed from the main memory based on the prediction result and caches them in a buffer, wherein the second instructions to be executed are instructions to be executed after a jump, and the buffer further includes a second tag indication, wherein the second tag indication is used to indicate the number of remaining unexecuted instructions in the second instructions to be executed; When the decoding unit determines to execute the first target instruction to be executed, sending a jump execution message to the buffer; After receiving the jump execution message, the buffer reads a second target to-be-executed instruction in the second to-be-executed instructions to a decoder based on the second tag instruction.

2. The method according to claim 1, characterized in that The buffer includes a plurality of tags, each tag corresponds to a storage area, each area is used to store the first to-be-executed instruction or the second to-be-executed instruction read at the same time, and each tag includes: a quantity identifier, an activation state identifier, and a jump identifier; The label of the first state of the jump identifier corresponds to the first instruction to be executed, and the label of the second state of the jump identifier corresponds to the second instruction to be executed; The quantity identifier is used to record the number of unexecuted instructions in the corresponding area. When the number of unexecuted instructions corresponding to the tag is 0, the tag is used to record that the corresponding area can be overwritten; The activation status flag is used to indicate whether the pending instructions stored in the corresponding area can be read; The first label indicates that the label corresponding to the jump flag being in the first state is in an activated state, and the label corresponding to the jump flag being in the second state is in an inactivated state; The second label indicates that the label corresponding to the jump flag being in the first state is in an inactive state, and the label corresponding to the jump flag being in the second state is in an active state.

3. The method according to claim 1, characterized in that The buffer includes a plurality of tags, each tag is used to record an instruction to be executed; The first tag is used to record the first unexecuted instruction to be executed in the first instructions to be executed; The second tag is used to record the first unexecuted pending instruction in the second pending instructions; The third tag is used to record whether the currently executed first instruction to be executed is the second instruction to be executed; Wherein, the first tag indicates execution of the first instruction to be executed corresponding to the third tag instruction; The second tag indicates execution of a second to-be-executed instruction corresponding to the third tag.

4. The method according to claim 1, wherein The decoding unit includes a pre-decoder and a multi-stage decoder connected in sequence; The predecoder confirms the instruction type of the first target instruction to be executed; If the first target to-be-executed instruction is confirmed to be a jump instruction, generating a jump prediction message; confirming, by the multi-stage decoder, a first jump requirement state of the first target instruction to be executed, wherein the first jump requirement state includes a first jump state and a first non-jump state; If the first jump requirement state is confirmed as the first jump state, a jump execution message is generated.

5. The method according to claim 1, wherein The adaptive prediction module makes predictions based on the jump prediction message, including: The jump probability is predicted based on historical data and jump prediction messages to obtain the predicted probability; Predict the number of instructions based on historical data and predicted probability to obtain the predicted number; A second instruction to be executed is determined based on the predicted number and the jump address in the jump prediction message.

6. The method according to claim 5, characterized in that The predicted probability is determined based on the following formula : ； in, , including the feature vectors of historical jump frequency, jump distance, and instruction type; is the model parameter, estimated through training data, j is used to distinguish different jump instructions, and n represents the number of feature vectors.

7. The method according to claim 6, characterized in that The forecast quantity is determined based on the following formula : ； in, is the minimum instruction length of the cache; The maximum instruction length of the cache.

8. The method according to claim 6, characterized in that The forecast quantity is determined based on the following formula : ； in, is the minimum instruction length of the cache; is the maximum instruction length of the cache; δ is the adjustment coefficient, used to adjust the eigenvector X The value of dynamically adjusts the instruction length; α 1 ，α 2 ，⋯，α n is the eigenvector X The weight coefficient of i Used to distinguish different eigenvectors, n represents the number of eigenvectors.

9. A system-on-chip cache system using adaptive prediction technology, characterized in that: include: Main memory, buffer, decoding unit, adaptive prediction module, address selection module; The main memory is configured to read a plurality of consecutive first instructions to be executed according to a preset rule and cache the plurality of consecutive first instructions to be executed in a buffer, wherein the buffer further includes a first tag indication, wherein the first tag indication is configured to indicate the number of remaining unexecuted instructions in the first instructions to be executed; The buffer is configured to read a first target to-be-executed instruction from the first to-be-executed instructions to a decoding unit based on the first tag indication; The decoding unit is configured to determine an instruction type of the first target instruction to be executed, where the instruction type includes a jump type and a non-jump type; When it is determined that the instruction type of the first target to-be-executed instruction is a jump type, sending a jump prediction message to the adaptive prediction module; The adaptive prediction module is used to make predictions based on the jump prediction message and send the prediction results to the address selection module; The address selection module is configured to instruct the main memory to read a plurality of consecutive second instructions to be executed and cache them in a buffer based on the prediction result, wherein the second instructions to be executed are instructions to be executed after a jump, and the buffer further includes a second tag indication, wherein the second tag indication is used to indicate the number of remaining unexecuted instructions in the second instructions to be executed; The decoding unit is further configured to, when determining to execute the first target instruction to be executed, send a jump execution message to the buffer; The buffer is further configured to read a second target to-be-executed instruction in the second to-be-executed instructions to a decoder based on the second tag instruction after receiving the jump execution message.

10. The system according to claim 9, characterized in that The buffer includes a plurality of tags, each tag corresponds to a storage area, each area is used to store the first to-be-executed instruction or the second to-be-executed instruction read at the same time, and each tag includes: a quantity identifier, an activation state identifier, and a jump identifier; The label of the first state of the jump identifier corresponds to the first instruction to be executed, and the label of the second state of the jump identifier corresponds to the second instruction to be executed; The quantity identifier is used to record the number of unexecuted instructions in the corresponding area. When the number of unexecuted instructions corresponding to the tag is 0, the tag is used to record that the corresponding area can be overwritten; The activation status flag is used to indicate whether the pending instructions stored in the corresponding area can be read; The first label indicates that the label corresponding to the jump flag being in the first state is in an activated state, and the label corresponding to the jump flag being in the second state is in an inactivated state; The second label indicates that the label corresponding to the jump flag being in the first state is in an inactive state, and the label corresponding to the jump flag being in the second state is in an active state.

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