Data risk processing method and device, electronic equipment and medium
By introducing a register status tracking module into the processor, the problem of writing after writing data in the prior art eliminates the problem of large hardware overhead, and low power consumption and small area data risk detection and elimination are achieved.
Patent Information
- Application Number
- CN202510146522.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-10
- Publication Date
- 2025-06-13
AI Technical Summary
In the prior art, when detecting and eliminating the risk of writing data after writing, there are problems such as large hardware overhead, high area occupation, high power consumption and large delay.
By introducing a register status tracking module into the processor, the data adventure type is determined based on the register number of the instruction to be transmitted, and when writing the data adventure after writing, the register status of the instruction to be transmitted and the entry encoding of the reorder buffer are modified, thereby realizing the detection and elimination of the data adventure.
It realizes detection and elimination of data risk through less hardware overhead in edge computing scenarios, reducing power consumption and area consumption, while avoiding the need for register renaming.
Smart Images
Figure CN120144345A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technologies, and in particular, to a method for processing data hazards, a device for processing data hazards, a computer-readable storage medium, and an electronic device. Background Art
[0002] The detection and elimination of data hazards is one of the keys for a processor to correctly implement functions and improve performance. The write-after-write data hazard does not have a data dependency, but a dependency relationship is generated because the architectural register to be written by the latter instruction has the same name as the register to be operated on by the former instruction.
[0003] In the related art, the detection of data hazards is completed through a reservation station or a similar structure, which has problems of large hardware overhead and the need to save multiple copies of data. The elimination of the write-after-write data hazard can be solved by register renaming, but register renaming requires maintaining an additional physical register file and a renaming table, which has problems of large area, high power consumption, and large latency. Summary of the Invention
[0004] The present application aims to at least solve one of the technical problems in the related art to some extent. To this end, the first object of the present application is to propose a method for processing data hazards, the method including: responding to an instruction to be issued; determining a data hazard type according to the instruction to be issued; in the case where the data hazard type is a write-after-write data hazard, modifying the register state of the instruction to be issued and the entry encoding of the reorder buffer, and issuing the instruction to be issued. The present application uses a register state tracking module to determine the data hazard type according to the register number of the instruction to be issued, and reuses the data saved in the ROB, enabling a processor in an edge computing scenario to detect data hazards and save and use data with less hardware overhead; and when the data hazard type is a write-after-write data hazard, while modifying the register state of the instruction to be issued and the entry encoding of the reorder buffer, issuing the instruction to be issued, so that a processor in an edge computing scenario does not need to perform register renaming, and eliminates the write-after-write hazard with a small hardware cost, which is more suitable for the low power consumption and small area requirements of edge computing, and can also be applied to small-scale embedded processors.
[0005] The second object of the present application is to propose a device for processing data hazards.
[0006] The third object of the present application is to propose a computer-readable storage medium.
[0007] The fourth object of the present application is to propose an electronic device.
[0008] To achieve the above object, an embodiment of the first aspect of the present application provides a method for processing data hazards, the method including: responding to an instruction to be issued; determining the type of data hazard according to the instruction to be issued; in the case where the data hazard type is a write-after-write data hazard, modifying the register state of the instruction to be issued and the entry encoding of the reorder buffer, and issuing the instruction to be issued.
[0009] According to an embodiment of the present application, modifying the register state of the instruction to be issued and the entry encoding of the reorder buffer includes: modifying the register state of the instruction to be issued to an unfinished state, and modifying the entry encoding of the reorder buffer to the entry encoding corresponding to the instruction to be issued.
[0010] According to an embodiment of the present application, the above method further includes: in the case where the hazard type is a read-after-write data hazard, determining the data source of the instruction to be issued according to the position of the data of the instruction to be issued.
[0011] According to an embodiment of the present application, determining the data source of the instruction to be issued according to the position of the data of the instruction to be issued includes: obtaining the register state of the instruction to be issued; in the case where the register state of the instruction to be issued is that the data is in the register, determining that the data source of the instruction to be issued is the register of the instruction to be issued; in the case where the register state of the instruction to be issued is in the reorder buffer, determining that the data source of the instruction to be issued is the reorder buffer.
[0012] According to an embodiment of the present application, determining the data source of the instruction to be issued according to the position of the data of the instruction to be issued includes: in the case where the register state of the instruction to be issued is unfinished, obtaining the broadcast content of the data bypass; in the case where the broadcast content of the data bypass has been completed, determining that the data source of the instruction to be issued is the broadcast content of the data bypass.
[0013] According to an embodiment of the present application, after determining the data source of the instruction to be issued, the above method further includes: determining the read-after-write data hazard result according to the matching result between the entry encoding of the instruction to be issued and the entry encoding in the broadcast content of the data bypass.
[0014] According to an embodiment of the present application, the above method further includes: in the case where the matching result is consistent, determining that the read-after-write data hazard does not hold; in the case where the matching result is inconsistent, determining that the read-after-write data hazard holds, and blocking the issuance of the instruction to be issued.
[0015] To achieve the above object, an embodiment of the second aspect of the present application provides a data hazard processing apparatus, which includes: a response module for responding to an instruction to be issued; a determination module for determining the type of data hazard according to the instruction to be issued; and a status tracking module for, when the type of data hazard is a write-after-write data hazard, modifying the register status of the instruction to be issued and the entry encoding of the reorder buffer, and issuing the instruction to be issued.
[0016] To achieve the above object, an embodiment of the third aspect of the present application provides a computer-readable storage medium, on which a data hazard processing program is stored. When the data hazard processing program is executed by a processor, the foregoing data hazard processing method is implemented.
[0017] To achieve the above object, an embodiment of the fourth aspect of the present application provides an electronic device, including a memory, a processor, and a data hazard processing program stored on the memory and executable on the processor. When the processor executes the data hazard processing program, the foregoing data hazard processing method is implemented.
[0018] According to the data hazard processing method, apparatus, electronic device, and medium of the embodiments of the present application, an instruction to be issued is responded to; the type of data hazard is determined according to the instruction to be issued; when the type of data hazard is a write-after-write data hazard, the register status of the instruction to be issued and the entry encoding of the reorder buffer are modified, and the instruction to be issued is issued. The present application uses a register status tracking module to determine the type of data hazard according to the register number of the instruction to be issued, and reuses the data stored in the ROB, enabling the processor in the edge computing scenario to detect data hazards and save and use data with less hardware overhead; and when the type of data hazard is a write-after-write data hazard, while modifying the register status of the instruction to be issued and the entry encoding of the reorder buffer, the instruction to be issued is issued, enabling the processor in the edge computing scenario to eliminate write-after-write hazards without register renaming, achieving the elimination of write-after-write hazards with a small hardware cost, being more suitable for the low power consumption and small area requirements of edge computing, and can also be applied to small-scale embedded processors. Description of the Drawings
[0019] Figure 1 Schematic diagram of the ROB structure according to some embodiments of the present application;
[0020] Figure 2 Schematic diagram of the structure of an entry for storing instruction information in the ROB according to some embodiments of the present application;
[0021] Figure 3 Flowchart of the data hazard processing method according to some embodiments of the present application;
[0022] Figure 4Schematic diagram of write-after-write data hazard according to some embodiments of the present application;
[0023] Figure 5 Schematic diagram of register state transition for issuing instructions according to some embodiments of the present application;
[0024] Figure 6 Block diagram of a data hazard processing device according to some embodiments of the present application;
[0025] Figure 7 Block diagram of an electronic device according to some embodiments of the present application. Detailed implementation manners
[0026] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as a limitation of the present application.
[0027] The data hazard processing method, device, electronic device, and medium of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0028] In some embodiments, the CPU (central processor unit), as a core component of a computer, arranges the behavior of the entire computer through the execution of computer instructions. Its design generally adopts technologies such as pipelining, out-of-order scheduling, and instruction prediction to accelerate the execution of the instruction stream. In the implementation of modern CPU microarchitectures, the following cycles are generally required to complete the execution of an instruction: fetch (fetch instruction), decode (decode), registers rename (register renaming), schedule (scheduling), execute (execution), retire (write-back); specific hardware structures are required for each cycle to implement the functions. Compared with traditional in-order processors, out-of-order processors can achieve faster execution speed and better performance by scheduling the execution order of instructions and no longer executing completely in the original order of program instructions. However, when facing exceptions in instruction execution, it is difficult for out-of-order processors to locate the exact position of the exception instruction in the original program, resulting in difficulties in restoring the processor state after cleaning up the exception. To achieve precise exceptions under out-of-order execution, out-of-order processors introduce ROB (Re-order buffer, reorder buffer).
[0029] The ROB is a basic module of the CPU microarchitecture. Its function is to maintain the in-order submission of out-of-order execution instruction streams and accurately locate and recover exceptions. The ROB is generally set according to the FIFO (First In First Out) rule. Each instruction will write information into the ROB when entering the scheduling stage. The information written includes the instruction's PC (program counter), relevant information for writing to the register file, the state of the instruction in the pipeline, etc. After the instruction is completed, the calculation result is also stored in the ROB. The ROB is responsible for retiring (retiring) the completed instructions per cycle, that is, checking whether the instructions at the head of the FIFO structure have been completed this cycle. If completed, the results of the corresponding instructions are written back to the register file. If an exception occurs during the execution stage of an instruction, in addition to clearing the pipeline being executed, the processor will also locate the instruction in the ROB, clear all instructions after that instruction, and feedback the PC of that instruction to the control unit for debugging and re-execution later. This is the basic mechanism for out-of-order processors to achieve accurate exceptions. Data hazards refer to situations where there are data dependencies between program instructions that may lead to incorrect final storage results, including three types of hazards: RAW (Read after Write), WAW (Write after Write), and WAR (Write after Read). Assume that among two instructions with data dependencies, the instruction with a later execution order is named Instruction 2, and the earlier one is named Instruction 1. RAW means that Instruction 2 needs to read the operation result of Instruction 1, WAW means that Instruction 2 and Instruction 1 write to the same register, and WAR means that Instruction 2 needs to write to the register read by Instruction 1. Due to out-of-order execution, the relative order of the two instructions may be reversed, resulting in some incorrect results.
[0030] The detection and elimination of data hazards are one of the keys to the correct implementation of the processor's functions and performance improvement. RAW hazards are true data hazards that cannot be eliminated. Only by accelerating the calculation of instructions and the data bypass function can the dependent data be made available earlier. There is no data dependency in WAW and WAR hazards. Instead, the dependency relationship is caused because the structural register to be written by the later instruction has the same name as the register to be operated on by the earlier instruction. In an out-of-order processor, the detection of data hazards is completed through reservation stations or similar structures, and the elimination of WAW and WAR hazards can be solved by register renaming. However, register renaming requires maintaining an additional physical register file and renaming table, which consumes a lot in terms of area, power consumption, and latency.
[0031] The basic ROB structure can perform information preservation after instruction issuance, monitoring at the completion of instructions, and instruction write-back. The basic ROB structure is as Figure 1As shown in the figure. The smallest unit in the ROB is an entry. Each instruction is allocated an entry when it enters the ROB, and the information is cleared and released after write-back, waiting for a new instruction to be written again. Each entry in the ROB gets a specific index (number) according to its physical position, and is indexed according to its index without matching by content.
[0032] Each entry contains two parts: status and content. In the embodiments of the present application, the status information saved in each entry and the instruction information are as Figure 2 shown. The status information includes vld (valid) signal and compl (complete) signal. When an entry is allocated to a new instruction, the vld signal is set from 0 to 1, indicating that the entry is occupied, and the information related to the instruction is written, including Rd_en&Index (result register write enable signal and number), CSR_wen&Index (CSR register write enable signal and number), and the PC corresponding to the instruction. When the instruction is completed, its entry_index will be passed into the ROB by the execution unit together with information such as the result, and the compl signal of the corresponding entry is set from 0 to 1, indicating that the instruction is completed, and the data is written into Rd_data (data written back to the result register), CSR_data (data written back to the CSR register), Br_en&PC (branch instruction jump enable signal and target PC), LSU_exp (whether an exception occurs in the access instruction and the exception type) according to the instruction type. When the instruction is written back, all information is cleared.
[0033] In the embodiments of the present application, outside the basic ROB, a register status tracking module is added to the ROB. The register status tracking module is 64 structural registers (including 32 general-purpose registers and 32 floating-point registers), which are used to save and track the register status of the instructions to be issued and the entry encoding of the reorder buffer. The table structure for saving information in the register status tracking module can be analogous to the structure of the ROB. Each register corresponds to an item in a specific position, and the number of each item is equal to the number of the register. In addition, the register status tracking module will also judge data hazards according to the register numbers of the instructions to be issued passed in from the scheduling unit. It should be noted that the present application is applied to a sequential processor in an edge computing scenario. Therefore, compared with an out-of-order processor, the WAR hazard will not cause incorrect execution results, because instructions with a later order can only be issued after the instructions with an earlier order are issued, so its write cannot affect the data read by the previous instructions.
[0034] Based on this, the present application uses a register status tracking module to determine the data hazard type according to the register number of the instruction to be issued, and reuses the data stored in the ROB, enabling the processor in the edge computing scenario to detect data hazards and save and use data with less hardware overhead; and when the data hazard type is a write-after-write data hazard, modify the register status of the instruction to be issued and the entry encoding of the reorder buffer, and issue the instruction to be issued, so that the processor in the edge computing scenario does not need to perform register renaming, and eliminates the write-after-write hazard with a small hardware cost, which is more suitable for the low power consumption and small area requirements of edge computing, and can also be applied to small-scale embedded processors.
[0035] Figure 3 FIG. is a flowchart of a method for processing data hazards according to some embodiments of the present application. Referring to Figure 1 , the method for processing data hazards in the embodiments of the present application may include the following steps:
[0036] S110, in response to an instruction to be issued.
[0037] S120, determine the data hazard type according to the instruction to be issued.
[0038] Specifically, the register status tracking module determines the data hazard type by analyzing the operand register information of the instruction to be issued (such as the register number of the instruction to be issued), for example, determines that the data hazard type is a write-after-write data hazard.
[0039] Exemplarily, assume that the instruction sequence includes the previous instruction (instruction 1) and the instruction to be issued (instruction 2) of the instruction to be issued, and instructions 1 and 2 are as follows:
[0040] Instruction 1: ADD R1, R2, R3: Store the sum of R2 and R3 in R1
[0041] Instruction 2: ADD R1, R4, R5: Store the sum of R4 and R5 in R1
[0042] Referring to Figure 4 , due to the existence of a multi-cycle execution unit, a write-after-write data hazard may cause that after both instructions (such as instruction 1 and instruction 2) targeting the same register are issued, instruction 2 completes the instruction first through a single-cycle execution unit and writes it into the ROB, and instruction 1 completes it later through a multi-cycle execution unit. Finally, the result of instruction 1 in the ROB is used as the latest data and transmitted to the execution unit through data bypass, resulting in an incorrect execution result. Therefore, the data hazard type can be determined as a write-after-write data hazard according to the instruction to be issued.
[0043] S130. When the data hazard type is a write-after-write data hazard, modify the register status of the instruction to be issued and the entry encoding of the reorder buffer, and issue the instruction to be issued.
[0044] Specifically, when the data hazard type is a write-after-write data hazard, subsequent instructions cannot determine whether the data read is the result data of Instruction 1 or Instruction 2. Therefore, before the instruction to be issued (e.g., Instruction 2) is issued, modify the register status of the instruction to be issued and the entry encoding of the reorder buffer, and issue the instruction to be issued, so that subsequent instructions can determine that the data they read is the result data of Instruction 2, thereby avoiding the occurrence of write-after-write data hazards to a certain extent.
[0045] In some embodiments, modifying the register status of the instruction to be issued and the entry encoding of the reorder buffer includes: modifying the register status of the instruction to be issued to the unfinished state, and modifying the entry encoding of the reorder buffer to the entry encoding corresponding to the instruction to be issued.
[0046] Specifically, the register status of the instruction to be issued includes the unfinished state and the completed state. Specifically, when the instruction to be issued has not completed the calculation, the register status of the instruction to be issued is the unfinished state; after the instruction to be issued has completed the calculation, the register status of the instruction to be issued is the completed state.
[0047] After determining that the data hazard type is a write-after-write data hazard according to the instruction to be issued, regardless of the state of the register status of the instruction to be issued, modify the register status of the instruction to be issued to the unfinished state, and modify the entry encoding of the reorder buffer to the entry encoding corresponding to the instruction to be issued, so as to determine that the currently executed instruction is the instruction to be issued, and further enable subsequent instructions to determine that the data they read is the result data of the instruction to be issued, thereby avoiding the occurrence of write-after-write data hazards to a certain extent.
[0048] In some embodiments, the above method further includes: when the hazard type is a write-after-read data hazard, determine the data source of the instruction to be issued according to the position of the data of the instruction to be issued.
[0049] Specifically, assume that the instruction sequence includes Instruction 3, Instruction 4, and Instruction 5, where the instruction to be issued is Instruction 5, as follows:
[0050] Instruction 3: ADD R6,R7,R8: Store the sum of R7 and R8 in R6
[0051] Instruction 4: ADD R6,R9,R10: Store the sum of R9 and R10 in R6
[0052] Instruction 5: ADD R11,R6,R12: Store the sum of R6 and R12 in R11
[0053] Among them, the result data of Instruction 3 and the result data of Instruction 4 will both be stored in R6. Assume that Instruction 5 needs to read the data stored in R6 by Instruction 4, but Instruction 5 cannot determine the order in which the result data of Instruction 3 and the result data of Instruction 4 are stored in R6, resulting in Instruction 5 possibly reading the data stored in R6 by Instruction 3. Thus, according to the instruction to be issued, the data hazard type can be determined as a read-after-write data hazard.
[0054] In the case of a read-after-write data hazard, based on the position of the data of the instruction to be issued, determine the data source of the instruction to be issued. For example, determine that the data source of the instruction to be issued is the register of the instruction to be issued, the reorder buffer, or the broadcast content of the data bypass, so as to determine the result of the read-after-write data hazard according to the data source of the instruction to be issued, that is, determine whether the read-after-write data hazard is established.
[0055] In some embodiments, based on the position of the data of the instruction to be issued, determine the data source of the instruction to be issued, including: obtaining the register status of the instruction to be issued; when the register status of the instruction to be issued is that the data is in the register, determine that the data source of the instruction to be issued is the register of the instruction to be issued; when the register status of the instruction to be issued is in the reorder buffer, determine that the data source of the instruction to be issued is the reorder buffer.
[0056] Specifically, referring to Figure 5 , the register status of the issued instruction includes a completed status, where the completed status specifically includes an available status and a to-be-written-back status. After the operand register information of the instruction to be issued is passed in from the issuing unit, the register status of the instruction to be issued can be obtained by looking up a table, and at the same time, listen to the broadcast of the data bypass transmitted back from the execution unit. The broadcast content of the data bypass includes the execution result data of the instruction to be issued, the register code to which the execution result is to be stored, and the entry code of the reorder buffer corresponding to the instruction to be issued.
[0057] After the instruction to be issued completes the calculation, write the broadcast content of the data bypass back to the reorder buffer. At this time, the register status of the instruction to be issued is changed to the data being in the reorder buffer (to-be-written-back status); when appropriate, the reorder buffer writes the content in the reorder buffer back to the register, and at this time, the register status of the instruction to be issued is changed to the data being in the register (available status).
[0058] That is, the data source of the instruction to be issued can be determined according to the register state of the instruction to be issued. For example, if the register state of the instruction to be issued is that the data is in the register (usable state), it is determined that the data source of the instruction to be issued is the register of the instruction to be issued; if the register state of the instruction to be issued is in the reorder buffer (to be written back state), it is determined that the data source of the instruction to be issued is the reorder buffer.
[0059] In some embodiments, according to the location where the data of the instruction to be issued is located, the data source of the instruction to be issued is determined, including: when the register state of the instruction to be issued is unfinished, obtaining the broadcast content of the data bypass; when the broadcast content of the data bypass is completed, determining that the data source of the instruction to be issued is the broadcast content of the data bypass.
[0060] Specifically, referring to Figure 5 , the register state of the instruction to be issued also includes an unfinished state. For example, when the instruction to be issued has not completed the calculation, the register state of the instruction to be issued is in an unfinished state. When the instruction to be issued has completed the calculation but has not had time to transfer the broadcast content of the data bypass back to the reorder buffer, the register state of the instruction to be issued is also in an unfinished state. Therefore, when the register state of the instruction to be issued is unfinished, it is necessary to obtain the broadcast content of the data bypass, and when the broadcast content of the data bypass is completed, determine that the data source of the instruction to be issued is the broadcast content of the data bypass.
[0061] In some embodiments, after determining the data source of the instruction to be issued, the above method further includes: determining the write-after-read data hazard result according to the matching result between the entry code of the instruction to be issued and the entry code in the broadcast content of the data bypass.
[0062] Specifically, if the data source of the instruction to be issued is the register of the instruction to be issued or the reorder buffer, it means that the data source of the instruction to be issued is accurate, and it is determined that the write-after-read data hazard does not hold; if the data source of the instruction to be issued is the broadcast content of the data bypass, it is necessary to further determine the write-after-read data hazard result according to the matching result between the entry code of the instruction to be issued and the entry code in the broadcast content of the data bypass, for example, determining that the write-after-read data hazard holds or determining that the write-after-read data hazard does not hold.
[0063] Exemplarily, if the matching result between the entry code of the instruction to be issued and the entry code in the broadcast content of the data bypass is consistent, it is determined that the write-after-read data hazard does not hold; if the matching result between the entry code of the instruction to be issued and the entry code in the broadcast content of the data bypass is inconsistent, it is determined that the write-after-read data hazard holds.
[0064] In some embodiments, the above method further includes: when the matching result is consistent, determining that the read-after-write data hazard does not hold; when the matching result is inconsistent, determining that the read-after-write data hazard holds, and blocking the issue of the instruction to be issued.
[0065] Exemplarily, assume that the instruction sequence includes Instruction 3, Instruction 4, and Instruction 5, where the instruction to be issued is Instruction 5, specifically as follows:
[0066] Instruction 3: ADD R6, R7, R8: Store the sum of R7 and R8 into R6
[0067] Instruction 4: ADD R6, R9, R10: Store the sum of R9 and R10 into R6
[0068] Instruction 5: ADD R11, R6, R12: Store the sum of R6 and R12 into R11
[0069] Assume that Instruction 5 needs to read the result data stored in R6 by Instruction 4. If the result data of Instruction 3 is in the broadcast content of data bypass, obtain the entry code of Instruction 3, match the entry code of Instruction 5 with the entry code of Instruction 3, and if the obtained matching result is inconsistent, determine that the read-after-write data hazard holds. At this time, it is necessary to block the issue of Instruction 5; if the result data of Instruction 4 is in the broadcast content of data bypass, obtain the entry code of Instruction 4, match the entry code of Instruction 5 with the entry code of Instruction 4, and if the obtained matching result is consistent, determine that the read-after-write data hazard does not hold.
[0070] In summary, based on the edge computing requirements, this application designs the ROB structure of the sequential processor. Considering the design area, absolute power consumption, and energy consumption ratio, by adding limited hardware overhead, the data hazard detection and elimination function is added. There is no need to adopt structures such as reservation stations and register renaming, which is more suitable for the low power consumption and small area requirements of edge computing, and can also be applied to small-scale embedded processors; this application also adds a register status tracking module to the ROB and designs a streamlined table structure to implement this module. At the same time, by reusing the data in the ROB, it avoids the multiple storage of data in the physical register file of the ROB, reservation stations, and register renaming, reducing the hardware overhead required for data storage; in addition, the combination of the write-after-write hazard elimination function and fast data bypass takes into account the timing requirements of the design and improves the performance of the design.
[0071] Corresponding to the above embodiments, this application also proposes a data hazard processing device.
[0072] Referring to Figure 6 , the data hazard processing device 600 includes: a response module 610, a determination module 620, and a status tracking module 640.
[0073] Among them, the response module 610 is used to respond to the instruction to be issued. The determination module 620 is used to determine the data hazard type according to the instruction to be issued. The status tracking module 630 is used to modify the register status of the instruction to be issued and the entry encoding of the reorder buffer, and issue the instruction to be issued when the data hazard type is a write-after-write data hazard.
[0074] According to an embodiment of the present application, the status tracking module 630 is specifically used to modify the register status of the instruction to be issued to an unfinished state, and modify the entry encoding of the reorder buffer to the entry encoding corresponding to the instruction to be issued.
[0075] According to an embodiment of the present application, in the case where the hazard type is a read-after-write data hazard, the data source of the instruction to be issued is determined according to the position of the data of the instruction to be issued.
[0076] According to an embodiment of the present application, obtain the register status of the instruction to be issued; when the register status of the instruction to be issued is that the data is in the register, determine that the data source of the instruction to be issued is the register of the instruction to be issued; when the register status of the instruction to be issued is in the reorder buffer, determine that the data source of the instruction to be issued is the reorder buffer.
[0077] According to an embodiment of the present application, when the register status of the instruction to be issued is unfinished, obtain the broadcast content of the data bypass; when the broadcast content of the data bypass is completed, determine that the data source of the instruction to be issued is the broadcast content of the data bypass.
[0078] According to an embodiment of the present application, after determining the data source of the instruction to be issued, determine the read-after-write data hazard result according to the matching result between the entry encoding of the instruction to be issued and the entry encoding in the broadcast content of the data bypass.
[0079] According to an embodiment of the present application, when the matching result is consistent, determine that the read-after-write data hazard does not hold; when the matching result is inconsistent, determine that the read-after-write data hazard holds and block the issue of the instruction to be issued.
[0080] It should be noted that the above explanations of the embodiments and beneficial effects of the data hazard processing method also apply to the data hazard processing device of the embodiments of the present application. To avoid redundancy, no detailed expansion is made here.
[0081] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.
[0082] The computer-readable storage medium of the present application stores a program for processing data hazards thereon. When the program for processing data hazards is executed by a processor, the aforementioned method for processing data hazards is implemented.
[0083] It should be noted that the above explanations of the embodiments and beneficial effects of the method for processing data hazards are also applicable to the computer-readable storage medium of the embodiments of the present application. To avoid redundancy, no detailed elaboration will be made here.
[0084] Corresponding to the above embodiments, the present application also proposes an electronic device.
[0085] See Figure 7 As shown, the electronic device 700 of the present application includes a memory 710, a processor 720, and a program for processing data hazards stored on the memory 710 and executable on the processor 720. When the processor executes the program for processing data hazards, the aforementioned method for processing data hazards is implemented.
[0086] It should be noted that the above explanations of the embodiments and beneficial effects of the method for processing data hazards are also applicable to the electronic device of the embodiments of the present application. To avoid redundancy, no detailed elaboration will be made here.
[0087] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion (electronic device) having one or more wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.
[0088] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
[0089] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0091] In the present application, unless otherwise clearly specified and defined, terms such as "install", "connect", "couple", "fix", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.
Claims
1. A method for processing data hazards, characterized in that: The method comprises: responding to a pending transmission instruction; Determining a data hazard type according to the instruction to be transmitted; In the case where the data hazard type is a write-after-write data hazard, the register state of the instruction to be issued and the entry code of the reorder buffer are modified, and the instruction to be issued is issued.
2. The method for processing data hazards according to claim 1, characterized in that: The modifying of the register state of the to-be-issued instruction and the entry code of the reorder buffer comprises: The register state of the instruction to be issued is modified to an uncompleted state, and the entry code of the reorder buffer is modified to the entry code corresponding to the instruction to be issued.
3. The method for processing data hazards according to claim 1, characterized in that: The method further comprises: In the case where the hazard type is a read-after-write data hazard, the data source of the instruction to be issued is determined according to the location of the data of the instruction to be issued.
4. The method for processing data hazards according to claim 3, characterized in that: Determining the data source of the instruction to be transmitted according to the location of the data of the instruction to be transmitted includes: Acquire the register status of the instruction to be issued; When the register state of the instruction to be issued is that the data is in the register, determining that the data source of the instruction to be issued is the register of the instruction to be issued; When the register status of the to-be-issued instruction is in the reorder buffer, it is determined that the data source of the to-be-issued instruction is the reorder buffer.
5. The method for processing data hazards according to claim 4, characterized in that: Determining the data source of the instruction to be transmitted according to the location of the data of the instruction to be transmitted includes: When the register status of the instruction to be issued is incomplete, obtaining broadcast content of data bypass; In a case where the broadcast content of the data bypass has been completed, it is determined that the data source of the instruction to be transmitted is the broadcast content of the data bypass.
6. The method for processing data hazards according to claim 5, characterized in that: After determining the data source of the instruction to be transmitted, the method further includes: The read-after-write data hazard result is determined according to a matching result between the entry code of the instruction to be issued and the entry code in the broadcast content of the data bypass.
7. The method for processing data hazards according to claim 6, characterized in that: The method further comprises: When the matching result is consistent, determining that the read-after-write data hazard does not hold; When the matching result is inconsistent, it is determined that the read-after-write data hazard holds, and the issuance of the to-be-issued instruction is blocked.
8. A data risk processing device, characterized in that: The device comprises: A response module, used for responding to the instruction to be transmitted; A determination module, used to determine a data hazard type according to the instruction to be transmitted; The state tracking module is used to modify the register state of the instruction to be issued and the entry code of the reorder buffer when the data hazard type is a write-after-write data hazard, and to issue the instruction to be issued.
9. A computer-readable storage medium, characterized in that: A data hazard processing program is stored thereon, and when the data hazard processing program is executed by a processor, the data hazard processing method according to any one of claims 1-7 is implemented.
10. An electronic device, characterized in that: The invention comprises a memory, a processor and a data hazard processing program which is stored in the memory and can be run on the processor. When the processor executes the data hazard processing program, the data hazard processing method according to any one of claims 1 to 7 is implemented.