Predictive acknowledgement for cache subsystems

Abstract

The invention relates to predictive acknowledgement for cache subsystems. A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information into cache lines arranged in multiple ways. Request circuitry generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction as to which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line with a cache tag corresponding to one of the predicted paths. In response to determining that the prediction is correct, an acknowledgement indication indicating the correct prediction is stored. For a subsequent request for the particular cache line, the cache is configured to, based on the acknowledgement indication, abandon verification of a prediction of one of the ways included in the particular cache line.

Description

[0001] This application is a divisional application of the patent application for "Predictive Confirmation of Cache Subsystems" with the application number 202280054983.X and the filing date of July 20, 2022. Technical Field

[0002] This disclosure relates to computer systems and, more particularly, to cache subsystems. Background Art

[0003] Description of Related Art

[0004] Computer systems employ various types of memory in a memory hierarchy. This hierarchy can extend from architectural registers in a processor (e.g., to store operands of instructions to be executed) to mass storage such as on a hard disk drive or solid state disk. Many computer systems also include multiple levels of cache memory.

[0005] Cache memory is a type of memory that is below registers in the memory hierarchy but above system memory, such as random access memory (RAM), in that hierarchy. Caches can store information based on the principle of locality, including temporal locality (e.g., information that has been recently accessed is likely to be accessed again within a given time) and spatial locality (e.g., information that has been recently accessed is likely to be stored near other information that will be accessed). The access speed of information stored in a cache based on these principles can be faster than if it were stored only in system RAM or mass storage. Thus, caches can improve the overall performance of a computer system by reducing the access time of at least some of the information (e.g., data or instructions) that the processor is to use. Summary of the Invention

[0006] A device for predictive confirmation in a cache subsystem is disclosed. In one embodiment, the cache subsystem includes a cache configured to store information into cache lines arranged in multiple ways. A request circuit is configured to generate a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction as to which way of the multiple ways of the cache includes the particular cache line. A comparison circuit is configured to verify the prediction by comparing a particular address tag associated with the particular cache line and a cache tag corresponding to one of the predicted multiple ways. The prediction circuit is further configured to store a confirmation indication indicating that the prediction is correct in response to the comparison circuit determining that the prediction is correct, and wherein for subsequent access requests to the particular cache line, the cache is configured to forego verifying the prediction as to which way of the multiple ways the particular cache line is included based on the confirmation indication indicating that the prediction is correct.

[0007] In one embodiment, verifying the prediction includes reading a middle address tag from an address tag memory. The address tag is provided to a comparator together with the cache tag. After determining that the address tag and the cache tag match, it is confirmed that the prediction is correct, and the prediction circuit gives the same indication, causing a confirmation bit to be set. The confirmation bit is stored in a confirmation bit memory. For subsequent requests for a cache line with a correct prediction, the confirmation bit memory is queried. Since it is determined that the confirmation bit is set, the cache subsystem abandons reading the cache tag from the cache and the comparison operation. Thus, abandoning the tag read and comparison operations can save non-negligible power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which are briefly described now.

[0009] Figure 1 is a block diagram of an embodiment of a cache subsystem.

[0010] Figure 2 is a block diagram of an embodiment of a cache subsystem having an instruction cache.

[0011] Figure 3 is a block diagram of an embodiment of a cache subsystem having a data cache.

[0012] Figure 4 is a block diagram of an embodiment of a confirmation bit memory.

[0013] Figure 5 is a flowchart showing an embodiment of a method for operating a cache subsystem.

[0014] Figure 6 is a flowchart showing an embodiment of a method for operating a cache subsystem.

[0015] Figure 7 is a block diagram of an embodiment of an exemplary system. DETAILED DESCRIPTION

[0016] The present disclosure is directed to an apparatus and method for validating way prediction in a cache subsystem. Way prediction is used in a cache to reduce power consumption. Instead of looking for a block / page of a requested cache line in all ways, a prediction can be made as to which particular way the cache line is stored in. If the prediction is correct, less power will be consumed compared to looking in all ways.

[0017] When making a prediction, an address tag array may be read to obtain an address tag corresponding to the requested cache line. A cache tag corresponding to the predicted way may also be read from the cache. The address tag is then compared with the cache tag corresponding to the predicted way. If the tags match, the way storing the requested cache line has been correctly predicted. However, even when the prediction is correct, the reading of the cache tag and the subsequent comparison operation may consume a large amount of power, even though only a single way rather than all ways of the cache is looked up. In addition, predictions may be made for each subsequent access to the cache line, thus repeating the work of the original correct prediction.

[0018] This disclosure is based on the view that once the prediction for a cache line is correct, the prediction will continue to be correct for subsequent accesses to that cache line, unless the state of the cache line changes. Possible changes include eviction of the cache line, invalidation of the cache line, context switching, or prediction of a different virtual page. However, if the cache line remains validly stored in the predicted way, the prediction may also remain valid.

[0019] Based on the view discussed above, when a particular cache line is correctly predicted to be stored in a particular way, an acknowledgement bit may be added for the particular cache line. When a prediction is made for a particular cache line and it is verified that the particular cache line is stored in that particular way, the acknowledgement bit is set and remains set until the state changes, such as one of the examples provided in the previous paragraph. For subsequent access requests to the particular cache line, the acknowledgement bit is read, and the cache subsystem may forego reading the cache tag and thus forego the comparison operation. This can save more power compared to the case where the cache line is correctly predicted for multiple different accesses. In addition, a performance gain can be achieved by eliminating the steps required to re-confirm the prediction and thus not repeating the work of the original prediction. The use of the acknowledgement bit may be particularly useful in some cases, such as in a program loop that repeatedly accesses a particular cache line.

[0020] It should be noted that although prediction verification as discussed herein may include tag reading and comparison operations, this disclosure is not intended to be limited in this manner. Instead, this disclosure is intended to cover any suitable mechanism for verifying whether a cache line is stored in the predicted way of the cache.

[0021] This disclosure will now be discussed in more detail. First, the cache subsystem and the operations of the cache subsystem regarding predicted ways, confirming the prediction, and operations after the confirmation are discussed. Then, examples of cache subsystems utilizing the acknowledgement bit mechanism, including instruction cache subsystems and data cache subsystems, are discussed. Subsequently, an embodiment of a memory for storing the acknowledgement bits is described. Then, a flowchart showing a method for operating a cache subsystem with tag acknowledgement bits is described. The description ends with a discussion of an example system.

[0022] Cache Subsystem with Prediction Confirmation:

[0023] Figure 1 FIG. 4 is a block diagram of an embodiment of a cache subsystem in which the way of a requested cache line is predicted and, if the prediction is correct, a confirmation bit is set. Note that Figure 1 only a part of the cache subsystem is shown, and the cache subsystem may include other circuits, such as those to be referred to below Figure 2 and Figure 3 discussed circuits.

[0024] In the illustrated embodiment, cache subsystem 100 includes a prediction circuit 102, a cache 104, and a comparison circuit 120. Cache 104 in the illustrated embodiment includes N ways and is an N-way set associative cache. Embodiments where cache 104 is fully associative can also be considered.

[0025] Cache subsystem 100 is configured to receive a cache access request from a requester 110. The requester 110 can be one of a variety of different types of functional circuit units that can request access to the cache. In one embodiment, cache 104 is an instruction cache configured to store instructions executed by a processor. Thus, in this embodiment, the requester 110 can be an instruction fetch unit that initiates a cache request to fetch instructions. In another embodiment, cache 104 is a data cache, and the requester 110 can be a processor core or a part thereof that initiates a request for data used during instruction execution. Generally, cache 104 can be an instruction cache or a data cache, and the requester 110 can be any type of functional circuit that submits an access request to the corresponding cache type.

[0026] The prediction circuit 102 in the illustrated embodiment is configured to predict the way in which a particular cache line is stored. More specifically, the prediction circuit 102 generates a prediction in response to an incoming access request for the predicted cache line. After receiving an indication of the requested cache line, the prediction circuit 102 generates the prediction and provides the prediction to the comparison circuit 120. In the illustrated embodiment, the address tag associated with the requested cache line is accessed by the prediction circuit 102 and provided as part of the prediction process.

[0027] The comparison circuit 120 may also receive a cache tag provided by the receive cache 104 in response to a request to verify a prediction. The cache tag provided by the cache 104 may correspond to the predicted cache way. After obtaining the cache tag and the address tag (from the prediction circuit 102), the comparison circuit 120 performs a comparison operation. If the address tag matches the cache tag, the prediction is considered correct. Otherwise, the prediction is considered incorrect, and if the requested cache line exists in the cache, other ways are searched to find the requested cache line. If the requested cache line is not stored in the cache, the cache line may be accessed from the system memory.

[0028] In response to correctly predicting that the requested cache line is stored in a particular way, the prediction circuit 102 is configured to generate and store an acknowledgement indication. As described below, the acknowledgement indication or acknowledgement bit may be stored in a dedicated memory. For subsequent predictions of the particular cache line, the setting of the acknowledgement bit indicates that a previous prediction regarding the particular way storing the cache line was correct. Thus, in response to observing that the acknowledgement bit is in the set state, if the cache line associated with the correct prediction is requested again, the cache subsystem 100 may forego certain operations.

[0029] If the cache subsystem 100 determines that the acknowledgement bit has been set in the illustrated embodiment, the cache tag is not read from the cache 104. Additionally, the comparison circuit 120 does not perform a comparison operation because no cache tag is provided. Thus, for subsequent requests for a cache line that has been correctly predicted to be stored in a particular way, the cache tag read and comparison operations are cancelled. More generally, when the corresponding acknowledgement bit indicates that the way storing the requested cache line was correctly predicted in a previous access, verification is not performed. Cancelling the verification operation can significantly save power and improve performance.

[0030] When the acknowledgement bit is set in response to a correct prediction, the acknowledgement bit may remain in the set state as long as the prediction itself remains valid. The acknowledgement bit may be reset in response to various events that affect the cache line associated with the correct prediction. For example, if the cache line becomes invalid, the acknowledgement bit is reset. Similarly, if the cache line is evicted from the cache, the acknowledgement bit is reset. A context switch may also cause the acknowledgement bit to be reset because the cache may be flushed. However, as long as the cache line associated with the correct prediction remains stored in the predicted cache line and remains valid, the acknowledgement bit may remain in the set state.

[0031] Instruction and data cache subsystem:

[0032] Figure 2FIG. 0 is a block diagram of an implementation of a cache subsystem that implements an instruction cache. In the illustrated implementation, cache subsystem 200 includes an N-way set associative cache, namely instruction cache 204. In this particular implementation, the number of ways in each set is 2, and way 0 and way 1 form set 0. Although not explicitly shown, for this implementation, set 1 will include way 1 and way 2, and so on. Other implementations with different arrangements can also be considered. Instruction cache 204 also includes cache controller 209, which performs various cache control functions. These functions include, but are not limited to, storing cache lines, evicting cache lines, writing cache lines to instruction cache 204, invalidating cache lines, and reading and providing the requested cache line to the requester.

[0033] Instruction cache 204 in the illustrated implementation is configured to store instructions executed by the processor. Thus, the requester in this particular implementation is instruction fetch unit 210, which requests access to instructions that will be executed as part of a program or thread of instructions. The instruction fetch request is provided by instruction fetch circuit 210 to prediction circuit 202 and cache controller 209.

[0034] When an instruction fetch request is issued for a cache line, the request is received by prediction circuit 202 and cache controller 209. Prediction circuit 202 in the illustrated implementation can respond to the request by generating a prediction as to which particular way in instruction cache 204 the requested cache line is stored. After generating the prediction, prediction circuit 202 can access address tag memory 206 to obtain the address tag corresponding to the requested cache line. The address tag can then be provided to comparison circuit 209 for use in a validation operation. The predicted way can also be provided to cache controller 209, which can use this information to determine whether the requested cache line is the subject of a previously correctly predicted cache line that is still valid.

[0035] Address tag memory 206 in the illustrated implementation can store virtual addresses, although implementations where physical addresses are stored in the address tag memory can also be considered. The following implementation can also be considered: address tag memory 206 stores virtual addresses, while the corresponding physical addresses are accessed from a translation lookaside buffer (TLB) and used as the basis for comparison circuit 208 to perform the comparison. For the purposes of this disclosure, address tag memory 206 can be considered to store virtual addresses, physical addresses, and / or can also be considered to include multiple memories, where virtual addresses are stored in one memory circuit and the corresponding physical addresses are stored in another memory circuit (e.g., the TLB mentioned above). Regardless of whether the provided address tag is virtual or physical, comparison circuit 208 in the illustrated implementation performs a comparison to determine whether the way prediction of the requested cache line is correct.

[0036] In the illustrated embodiment, cache controller 209 may initially respond to a request for a cache line by querying the acknowledgment bit memory 212. In the illustrated embodiment, the acknowledgment bit memory 212 is configured with acknowledgment bits corresponding to the cache indices and the corresponding ways in which various cache lines may be stored. Using the relevant information of the predicted way and the relevant information of the requested cache line, cache controller 209 may query the acknowledgment bit memory to determine whether an acknowledgment bit has been set in that particular way for the requested cache line.

[0037] If the acknowledgment bit is not set (e.g., the acknowledgment bit is reset), indicating that the previous correct prediction for the requested cache line is currently invalid, cache controller 209 may respond by providing an instruction cache tag to comparison circuit 209 that corresponds to the predicted way. In response, comparison circuit 208 compares the address tag received from the address tag memory and the instruction tag received from instruction cache 204. If the tags match ("hit"), comparison circuit 208 provides an indication of the tag match to prediction circuit 202. In response to receiving the hit indication, prediction circuit 202 provides an indication to acknowledgment bit memory 212 to indicate the correctly predicted way and corresponding index. Subsequently, an acknowledgment bit is set in acknowledgment bit memory 212 for the predicted way and index. Additionally, an indication that the prediction is correct is provided to cache controller 209, and cache controller may respond by accessing the requested cache line and providing the requested cache line to instruction fetch circuit 210.

[0038] Note that embodiments may also be considered where the functions of prediction circuit 202 and comparison circuit 208 are combined into a single unit. The comparison circuit implemented in such embodiments may be the source indicating a correct prediction. In Figure 2 the embodiment specifically shown in, it may also be considered that comparison circuit 208 provides the indication of the correct prediction to acknowledgment bit memory 212.

[0039] If the prediction is incorrect (if the address tag and the instruction tag do not match), prediction circuit 202 (or comparison circuit 208) may provide an indication of the incorrect prediction to cache controller 209. In response to the incorrect prediction, cache controller 209 may look in other ways in cache 204 to determine whether the requested cache line is stored in another way. If the requested cache line is not stored in any way of instruction cache 204, a lookup in the main system memory may be performed by the memory controller. If the requested cache line is stored in a way different from the predicted way, the requested cache line is provided to instruction fetch circuit 210.

[0040] If there is a subsequent access request for a previously correctly predicted object (specific cache line), the verification process is not performed in the illustrated embodiment. Specifically, the cache controller 209 may, in response to a request for a specific cache line, query the confirmation bit memory 212 again. When receiving an indication from the confirmation bit memory that the confirmation bit for the predicted way for the specific cache line is set, the cache controller 209 in the illustrated embodiment issues a "forbid verification" signal, which is received by the comparison circuit 208. When the comparison circuit 208 receives this signal, the signal indicates that the cache controller 209 will no longer read the instruction tag for comparison and thus will not perform a comparison operation on this specific request. By abandoning the reading and comparison operations of the instruction tag, significant power consumption savings can be achieved. Canceling the tag reading and comparison operations can also improve performance. Since the confirmation bit is set, the cache controller 209 also responds by providing the specific cache line from the corresponding way of the instruction cache 204 to the instruction fetch circuit 210, without waiting for the delay caused by determining that the prediction has been verified.

[0041] The cache controller 209 in the illustrated embodiment is configured to reset the confirmation bits stored in the confirmation bit memory 212 in response to certain conditions. For example, if it is determined that the cache line that was the object of a previously correct prediction becomes invalid at a subsequent time, the cache controller 209 may reset the corresponding confirmation bit. Evicting the cache line that was previously correctly predicted and stored in a specific way may also reset the corresponding confirmation bit. Other conditions for resetting the confirmation bits include the corresponding virtual address to physical address translation failure, context switch when the cache is flushed (thus resetting all confirmation bits), and so on.

[0042] Figure 3 is a block diagram of an embodiment of a cache subsystem that implements a data cache. In the illustrated embodiment, the cache subsystem 300 is similar to Figure 2 the illustrated cache subsystem 200, with the main difference being that the cache 304 is a data cache including a cache controller 309. The requester 310 in the illustrated embodiment may be, for example, one of one or more processor cores that utilize the data cache 304. More generally, the requester 310 may be any type of functional circuit capable of accessing and utilizing the data cache. The functions of the prediction circuit 302, the comparison circuit 308, the address tag memory 306, the cache controller 309, and the confirmation bit memory 312 may be the same as Figure 2The corresponding parts shown are substantially similar. Additionally, as with the cache subsystem 200 discussed above, these circuit units can vary from one embodiment to another. In short, the cache subsystem 300 and its components in the illustrated embodiment are configured to make and verify a prediction for a particular way of a requested cache line storing data, set an acknowledgement bit in response to a correct prediction, and forego a verification process including tag read and comparison operations when the acknowledgement bit indicates that a previous prediction for the requested cache line was correct.

[0043] Example of an acknowledgement bit memory:

[0044] Figure 4 is a block diagram of one embodiment of an acknowledgement bit memory for storing acknowledgement bits corresponding to correct predictions in accordance with the present disclosure. In the illustrated embodiment, the acknowledgement bit memory 412 is arranged to store a plurality of acknowledgement bits 411. In the illustrated embodiment, when an acknowledgement bit is set (e.g., has a logical value of 1), it indicates that the way storing the requested cache line has been correctly predicted previously and that the prediction is still valid. The prediction can remain valid as long as the corresponding cache line remains stored in the cache effectively. As described above, if the corresponding cache line has become invalid, evicted, etc., and the corresponding way and index have not been correctly predicted, the acknowledgement bit can be placed in a reset state (e.g., logical value 0). After the cache is refilled after a context switch, the acknowledgement bits can remain in the reset state until the cache lines stored in the cache are correctly predicted.

[0045] In the illustrated embodiment, the acknowledgement bit memory 412 is arranged in a way-index fashion, where the index is associated with various address tags. Thus, if a cache line associated with an address tag corresponding to a correctly predicted index A is stored in, for example, way 2, then the acknowledgement bit 411 at the intersection of the index A row and the way 2 column can be set. For subsequent requests for that particular cache line, the reading of the acknowledgement bit by the cache controller can cause the verification of the prediction process (e.g., the cache tag read and comparison operations as described above) to be skipped.

[0046] Method for operating a cache subsystem:

[0047] Figure 5 is a flowchart of one embodiment of a method for operating a cache subsystem. As disclosed herein, method 500 can be executed by any of the various hardware embodiments described above. Hardware embodiments not discussed herein but otherwise capable of executing method 500 are also considered to fall within the scope of the present disclosure.

[0048] Method 500 includes: storing a cache line into a way of a cache (block 505). The method also includes: using a request circuit to generate a request to access a specific cache line in the cache (block 510), and subsequently using a prediction circuit to generate a prediction as to which way of the way of the cache includes the specific cache line (block 515). After generating the prediction, the method continues by using a comparison circuit to verify the prediction, where the verification includes comparing a specific address tag associated with the specific cache line and a cache tag corresponding to one of the predicted ways of the cache (block 520). The method also includes: in response to the comparison indicating that the prediction is correct, using the prediction circuit to store an acknowledgement bit (block 525), and for subsequent access requests for the specific cache line, based on the acknowledgement bit indicating that the prediction is correct, foregoing verification of subsequent predictions as to the specific cache line being included in one of the ways of the cache (block 530).

[0049] In various embodiments, foregoing verification of subsequent requests includes: foregoing reading the cache tag from the cache; and foregoing comparing the specific address tag and the cache tag. By foregoing these two operations, power savings and performance improvements can be achieved.

[0050] Various embodiments of method 500 include: storing a plurality of address tags including the specific address tag into a tag memory, where some of the plurality of address tags correspond to entries stored in the cache. For such embodiments, based on the specific address tag matching the cache tag, it is determined that the prediction is correct. After confirming that the prediction is correct, the method includes storing the acknowledgement bit into an acknowledgement bit memory. For a request to access a cache line, embodiments of the method include: in response to a subsequent prediction of the specific cache line, querying the acknowledgement bit memory to determine whether a previous prediction was correct.

[0051] Sometimes a correctly predicted cache line can be evicted from the cache. Accordingly, embodiments of method 500 include: in response to evicting a cache line corresponding to the specific acknowledgement bit from the cache, resetting the specific acknowledgement bit stored in the acknowledgement bit memory. Other conditions can also cause the acknowledgement bit to be reset. For example, embodiments of method 500 can include: in response to an address translation failure associated with a cache line corresponding to the specific acknowledgement bit, resetting the specific acknowledgement bit stored in the acknowledgement bit memory.

[0052] Figure 6 is a flowchart of another embodiment of a method for operating a cache subsystem. Similar to method 500 described above, method 600 can be performed by some of the various hardware embodiments and components described with reference to Figures 1 to 4 described various hardware embodiments and components. Embodiments of cache subsystems that can perform method 600 but are not disclosed herein may also be considered to fall within the scope of the present disclosure.

[0053] Method 600 includes: a cache subsystem receiving a request for a cache line (block 605). Subsequently, the method includes: reading a validation bit memory and a tag memory for the requested cache line (block 610). In various embodiments, the tag memory includes an address tag, and thus the address tag corresponding to the requested cache line can be retrieved from the tag memory. At the same time, the validation bit memory can be read to determine whether a previous prediction regarding a particular way storing the requested cache line was correct. If it is determined that the corresponding validation bit is set (block 615, yes), indicating that the previous prediction regarding the particular way storing the requested cache line was correct, then the method continues by skipping the cache tag read and compare operations and retrieving the requested cache line from the cache (block 620). Subsequently, method 600 returns to block 605 and waits for the next cache line request.

[0054] If the validation bit is not set (block 615, no), then the cache tag corresponding to the predicted way is read (block 625). Then a compare operation is performed to compare the cache tag and the address tag corresponding to the requested cache line (block 630). If the address tag matches the cache tag (block 635, yes), then the prediction is correct, and the method continues by setting and storing the validation bit and accessing the cache line from the predicted way (block 640). Subsequently, method 600 returns to block 605 to wait for the next cache request.

[0055] On the other hand, if the address tag and the cache tag do not match (block 635, no), then the requested cache line is searched for in other ways of the cache (block 645), and if the requested line exists in the cache, the requested line is provided. Subsequently, method 600 returns to block 605.

[0056] Exemplary system:

[0057] Next turning to Figure 7 , a block diagram of one embodiment of a system 700 is shown, which system can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 700 includes at least one instance of a system-on-chip (SoC) 706, which can include various types of processing units (such as a central processing unit (CPU), a graphics processing unit (GPU), or others), a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 706 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 706 is coupled to an external memory 702, peripherals 704, and a power supply 708.

[0058] A power supply 708 is also provided that supplies a power supply voltage to the SoC 706 and one or more power supply voltages to the memory 702 and / or the peripherals 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, there are more than one instance of the SoC 706 (and also more than one external memory 702).

[0059] The memory 702 is any type of memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, etc., and / or low-power versions of SDRAM such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module such as a single in-line memory module (SIMM), dual in-line memory module (DIMM), etc. Alternatively, these devices are mounted with the SoC or integrated circuit in a chip stack configuration, a package stack configuration, or a multi-chip module configuration.

[0060] The SoC 706 in the illustrated embodiment may include various levels of cache memory, some of which may be shared among various components while others may be dedicated caches. Such cache memory may be implemented as part of a corresponding cache memory subsystem. At least some of the cache subsystems in the cache subsystem on the SoC 706 may operate according to the various hardware and method embodiments discussed above with reference to Figures 1 to 6 the various hardware and method embodiments discussed above. Thus, at least some of the cache subsystems in the various cache subsystems on the SoC 706 may be arranged to predict the way to store the requested cache line and are also configured to generate and store an indication when the prediction is correct. For subsequent access requests to the currently valid cache line, such cache subsystems may use the indication to confirm that the cache line is stored in the predicted way and thus cancel the verification operation (e.g., the tag read and comparison operations discussed above, although other mechanisms for verification may also be considered). Canceling the verification operation may reduce power consumption and may also improve the performance of the cache subsystem.

[0061] Depending on the type of system 700, the peripheral device 704 includes any desired circuitry. For example, in one embodiment, the peripheral device 704 includes devices for various types of wireless communication such as Wi-Fi, Bluetooth, cellular, Global Positioning System, etc. In some embodiments, the peripheral device 704 also includes additional storage, including RAM storage, solid state storage, or disk storage. The peripheral device 704 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, a speaker, etc.

[0062] As shown, the system 700 is shown to have applications in a wide range of fields. For example, the system 700 can be used as part of a chip, circuitry, components, etc. of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box coupled to the television). A smartwatch and a health monitoring device 760 are also shown. In some embodiments, the smartwatch 760 can include various general computing-related functions. For example, the smartwatch 760 can provide access to email, cellular service, the user's calendar, etc. In various embodiments, the health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device can monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and so on.

[0063] The system 700 can also be used as part of a cloud-based service 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Further, the system 700 can be used in one or more devices in the home other than the previously mentioned ones. For example, household appliances can monitor and detect notable situations. For example, various devices in the home (e.g., a refrigerator, a cooling system, etc.) can monitor the status of the device and provide an alert to the homeowner (or, for example, a repair agency) in the event of a specific event being detected. Alternatively, a thermostat can monitor the temperature in the home and can automate the adjustment of the heating / cooling system based on the homeowner's historical response to various situations. Figure 7Also illustrated is the application of system 700 to various modes of transportation. For example, system 700 can be used in the control and / or entertainment systems of airplanes, trains, buses, rental cars, private cars, watercraft from personal boats to cruise ships, small motorcycles (for rental or private use), etc. In various cases, system 700 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Any number of other such implementations are possible and contemplated. Note that Figure 7 The devices and applications shown are only exemplary and are not intended to be limiting. Other devices are possible and contemplated.

[0064] This disclosure includes references to "embodiments" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or instances of the disclosed concepts. References to "an embodiment", "one embodiment", "a particular embodiment", etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure.

[0065] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why a particular implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or diminishes one or more of the disclosed advantages. Additionally, suboptimal design execution of a particular implementation (e.g., a particular implementation technology or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technology, the realization of the advantages can still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring in a particular instance, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside the scope of this disclosure, any potential advantages described herein should not be construed as claim limitations that must be met to prove infringement. Instead, the identification of such potential advantages is intended to illustrate one or more types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (e.g., stating that a particular advantage "may occur") is not intended to convey doubt as to whether such advantages can actually be achieved, but rather to recognize the technical reality that the realization of such advantages typically depends on additional factors.

[0066] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even if only a single example is described for a particular feature. The disclosed embodiments of the present invention are intended to be exemplary rather than restrictive, without any contrary statement in this disclosure. Therefore, this application is intended to allow claims that cover the disclosed embodiments, as well as such alternative forms, modifications, and equivalent forms, which will be obvious to those skilled in the art who are aware of the effective effects of this disclosure.

[0067] For example, the features in this application can be combined in any suitable manner. Thus, new claims can be made for any such combination of features during the prosecution of this patent application (or a patent application claiming priority therefrom). Specifically, with reference to the appended claims, the features of dependent claims can be combined with the features of other dependent claims, including claims that depend on other independent claims, where appropriate. Similarly, the features from corresponding independent claims can be combined, where appropriate.

[0068] Therefore, although the appended dependent claims can be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent claims that is consistent with this disclosure is contemplated, and such combinations can be claimed in this patent application or another patent application. In short, the combinations are not limited to those specifically listed in the appended claims.

[0069] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0070] ***

[0071] Since this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how to interpret the claims drafted based on this disclosure.

[0072] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "A plurality of" items means a collection of two or more items.

[0073] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0074] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0075] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," thus covering 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0076] The expressions "w, x, y, or z, or any combination thereof" or "at least one of w, x, y, and z" are intended to cover all possibilities involving a single element, up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0077] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. In addition, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0078] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, a decision may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0079] The phrases "responsive to" and "responsive" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect can be responsive solely to these factors, or can be responsive to the specified factors as well as other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. This phrase does not exclude the possibility that the performance of A may also be responsive to some other factor, such as C. This phrase also does not exclude the possibility that the performance of A may be performed in response to B and C in combination. This phrase is also intended to cover embodiments where A is performed responsive solely to B. As used herein, the phrase "responsive" is synonymous with the phrase "responsive at least in part to". Similarly, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to".

[0080] ***

[0081] Within the present disclosure, different entities (which may variously be referred to as "units", "circuits", other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression - [entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform certain tasks even if the structure is not currently being operated. Thus, an entity described or represented as "configured to" perform certain tasks refers to a physical thing for implementing that task, such as a device, a circuit, a system having a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0082] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations even if not specifically stated.

[0083] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA can be "configurable to" perform that function. After appropriate programming, the FPGA can then be considered "configured to" perform a particular function.

[0084] For purposes of U.S. patent applications based on this disclosure, reciting in a claim that a structure "is configured to" perform one or more tasks is specifically intended not to invoke 35 U.S.C. § 112(f) for that claim element. If an applicant wishes to invoke 35 U.S.C. § 112(f) during the prosecution of a U.S. patent application based on this disclosure, it will use the "means for [performing a function]" structure to phrase the claim element.

[0085] In this disclosure, different "circuits" may be described. These circuits or "circuits" constitute hardware, which includes various types of circuit elements such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. The circuits may be custom designed or taken from a standard library. In various embodiments, the circuits may optionally include digital components, analog components, or a combination of both. Certain types of circuits may generally be referred to as "units" (e.g., decoding unit, arithmetic logic unit (ALU), functional unit, memory management unit (MMU), etc.). Such units also refer to circuits or circuit systems.

[0086] Accordingly, the disclosed circuits / units / components and other elements shown in the figures and described herein include hardware elements such as those described in the previous paragraphs. In many cases, the internal arrangement of the hardware elements in a particular circuit may be specified by describing the function of the circuit. For example, a particular "decoding unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units", which means that the decoding unit "is configured to" perform that function. For those skilled in the art of computers, this functional specification is sufficient to imply a set of possible structures for the circuit.

[0087] In various embodiments, as described in the previous paragraphs, circuits, cells, and other elements may be defined by the functions or operations they are configured to perform. The arrangement relative to each other and such circuits / cells / components, and the way they interact, form the microarchitecture definition of the hardware, which is ultimately fabricated in an integrated circuit or programmed into an FPGA to form the physical implementation of the microarchitecture definition. Thus, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, a person skilled in the art having a microarchitecture definition provided according to the present disclosure can, without undue experimentation and using the application of an ordinary skilled person, implement the structure by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a way that can appear functional. However, to those skilled in the art, the HDL description is a way to transform the structure of a circuit, cell, or component into the next level of implementation details. Such HDL descriptions can take the form of behavioral code (which is typically non-synthesizable), register transfer language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description can be sequentially synthesized for a cell library designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof can also be custom designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as the interconnects between the transistors and circuit elements. Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements can be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent lower-level implementation of those circuits typically results in a situation where the circuit or logic designer never specifies a particular set of structures for the lower-level implementation beyond the description of what the circuit is configured to do, because the process is performed at different stages of the circuit implementation process.

[0088] The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a large number of equivalent structures of that circuit. As noted, these low-level circuit implementations can vary according to changes in manufacturing technology, the foundry selected for manufacturing the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of generating these different implementations through different design tools or methods can be arbitrary.

[0089] In addition, for a given implementation, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the sheer volume of this information makes it impractical to provide a complete narrative of the low-level structures for implementing a single implementation, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of a circuit using functional shorthand commonly used in the industry.

[0090] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The present disclosure is intended that the following claims be construed to cover all such variations and modifications.

Claims

1. An apparatus, comprising: a tag array circuit configured to store tags corresponding to cache lines arranged in multiple ways in a cache storage circuit; a prediction circuit configured to generate a prediction of a specific way in the multiple ways including a specific cache line associated with the request in response to an access request to the tag array circuit; and a comparison circuit configured to verify the prediction based on a comparison between a first tag associated with the specific cache line and a second tag associated with the specific way in the multiple ways; wherein the prediction circuit is further configured to store an acknowledgment bit indicating that the prediction is correct in response to a comparison indicating that the first tag matches the second tag; and wherein, based on the acknowledgment bit, the comparison circuit is configured to indicate that the first tag matches the second tag for a subsequent access request to the specific cache line without reading the tag array circuit and without performing a comparison.

2. The apparatus according to claim 1, wherein the first tag is an address tag and the second tag is a cache tag.

3. The apparatus according to claim 2, wherein the comparison circuit is configured to verify that the prediction is correct in response to determining that the address tag matches the cache tag.

4. The apparatus according to claim 1, further comprising an acknowledgment bit memory configured to store a plurality of acknowledgment bits, wherein one of the plurality of acknowledgment bits, when set, indicates that the prediction made by the prediction circuit is correct.

5. The apparatus according to claim 4, further comprising a cache controller configured to query the acknowledgment bit memory in response to a subsequent prediction that the specific cache line is stored in the specific way in the multiple ways.

6. The apparatus according to claim 5, wherein the cache controller is configured to generate a signal that prohibits the comparison circuit from verifying the subsequent prediction in response to determining that the acknowledgment bit among the plurality of acknowledgment bits is set.

7. The apparatus according to claim 5, wherein the cache controller is configured to provide the specific cache line from the cache storage circuit in response to determining that the acknowledgment bit among the plurality of acknowledgment bits is set.

8. The apparatus according to claim 5, wherein the cache controller is configured to reset the acknowledgment bit among the plurality of acknowledgment bits in response to evicting the specific cache line from the way in the multiple ways.

9. The apparatus according to claim 5, wherein the cache controller is configured to reset the acknowledgment bit among the plurality of acknowledgment bits in response to an address translation failure associated with the specific cache line.

10. The apparatus according to claim 1, wherein the cache storage circuit is an instruction cache, and the apparatus further comprises an instruction fetch unit configured to fetch instructions from the cache storage circuit.

11. A method, comprising: storing, in a tag array circuit, tags corresponding to cache lines arranged in multiple ways in a cache storage circuit; using a prediction circuit, in response to an access request to the tag array circuit, predicting a specific way in the multiple ways that stores a specific cache line; Verify whether the prediction is correct using a comparison circuit, where the verification includes the comparison circuit performing a comparison to determine whether the tag associated with the specific cache line matches the tag associated with the specific way in the multiplexer; In response to determining that the prediction is correct, the prediction circuit stores an acknowledgment bit indicating that the prediction is correct in the acknowledgment bit memory; And For subsequent access requests to the specific cache line, indicate a match without reading the tag array circuit and without performing a comparison.

12. The method according to claim 11, further comprising the cache controller clearing the acknowledgment bit from the acknowledgment bit memory in response to the specific cache line being evicted from the cache storage circuit.

13. The method according to claim 11, further comprising the cache controller clearing the acknowledgment bit from the acknowledgment bit memory in response to an address translation failure associated with the specific cache line.

14. The method according to claim 11, wherein the tag associated with the specific cache line is an address tag stored in an address tag memory, and wherein the tag associated with the specific way in the multiplexer is a cache tag, and wherein the method further Comprises: In response to the request, providing the address tag from the address tag memory to the comparison circuit; And In response to the request, providing the cache tag from the cache storage circuit to the comparison circuit.

15. The method according to claim 11, further comprising the prediction circuit providing an indication that the prediction is correct to a cache controller associated with the cache storage circuit.

16. The method according to claim 11, wherein the method further comprises providing the requested instruction stored in the specific cache line from the cache storage circuit to an instruction fetch circuit.

17. A system, Comprising: A cache subsystem, where the cache subsystem includes: A tag array circuit configured to store tags corresponding to cache lines of a cache storage circuit arranged in a multiplexer; A prediction circuit configured to generate a prediction for a specific way in the multiplexer including a specific cache line associated with the request in response to an access request to the tag array circuit; and A comparison circuit configured to verify whether the prediction is correct by comparing an address tag associated with the specific cache line and a cache tag associated with the specific way in the multiplexer, To verify whether the prediction is correct; Wherein the prediction circuit is configured to cause an acknowledgment bit to be stored in an acknowledgment bit memory in response to the comparison circuit indicating that the prediction is correct; and Wherein, based on the acknowledgment bit, the comparison circuit is configured to indicate a match between the address tag and the cache tag for subsequent access requests to the specific cache line without reading the tag array circuit and without performing a comparison.

18. The system according to claim 17, wherein the comparison circuit is configured to verify that the prediction is correct in response to determining that the address tag matches the cache tag.

19. The system according to claim 17, wherein the cache storage circuit is an instruction cache, and the system further includes an instruction fetch unit configured to request an instruction from the instruction cache.

20. The system according to claim 17, wherein the cache subsystem further includes a cache controller configured to clear the acknowledgement bit from the acknowledgement bit memory in response to at least one of the following: evicting the specific cache line from the cache storage circuit; or an address translation associated with the specific cache line failing.

21. An apparatus, comprising: a prediction circuit configured to generate a prediction that a specific cache line associated with a cache access request is included in a specific way of a plurality of ways in a cache memory in response to the cache access request; a comparison circuit configured to determine whether the prediction is correct, wherein, to determine whether the prediction is correct, the comparison circuit is configured to compare a first tag associated with the specific cache line and a second tag associated with the specific way of the plurality of ways; and an acknowledgement bit memory, wherein the prediction circuit is configured to set an acknowledgement bit in the acknowledgement bit memory in response to the comparison circuit determining that the prediction is correct; wherein, for a subsequent cache access request to the specific cache line, the comparison circuit is configured to forego performing the comparison of the first tag and the second tag in response to determining that the acknowledgement bit in the acknowledgement bit memory is set.

22. The apparatus according to claim 21, further comprising a tag array circuit configured to store address tags corresponding to the plurality of ways of the cache memory, wherein, when foregoing performing the comparison, the comparison circuit is configured to forego accessing the tag array circuit to obtain the second tag.

23. The apparatus according to claim 21, wherein, when foregoing performing the comparison, the comparison circuit is configured to forego accessing the cache memory to obtain the first tag.

24. The apparatus according to claim 21, wherein the comparison circuit is configured to determine that the prediction is correct if the first tag matches the second tag.

25. The apparatus according to claim 21, wherein the acknowledgement bit memory is configured to store a plurality of acknowledgement bits corresponding to correct predictions generated by the prediction circuit.

26. The apparatus according to claim 21, further comprising a cache controller coupled to the cache memory and the prediction circuit, wherein the cache controller is configured to determine whether the acknowledgement bit is set in response to the subsequent cache access request that the specific cache line is stored in the specific way of the plurality of ways.

27. The apparatus according to claim 26, wherein the cache controller is configured to reset the acknowledgement bit in response to evicting the specific cache line from the cache memory.

28. The apparatus according to claim 26, wherein the cache controller is configured to reset the acknowledgement bit in response to determining that an address translation associated with the specific cache line is invalid.

29. The apparatus according to claim 26, wherein the cache controller is configured to provide the specific cache line to a requester in response to determining that the acknowledgement bit is set.

30. The apparatus according to claim 26, wherein the cache controller is configured to generate a signal that causes the comparison circuit to forego the comparison in response to determining that the acknowledgement bit is set.

31. A method, comprising: Using a prediction circuit, in response to a cache access request, generate a prediction for a specific way among multiple ways in a cache memory including a specific cache line associated with the cache access request; Using a comparison circuit, determine whether the prediction is correct, wherein the determination includes comparing a first tag associated with the specific cache line and a second tag associated with the specific way among the multiple ways; In response to determining that the prediction is correct, set an acknowledgment bit in an acknowledgment bit memory; And In response to determining that the acknowledgment bit in the acknowledgment bit memory is set, for a subsequent cache access request for the specific cache line, forgo determining whether the prediction is correct.

32. The method according to claim 31, wherein forgoing determining whether the prediction is correct includes: Forgoing reading the first tag from the cache memory, where the first tag is a cache tag associated with the way among the multiple ways; And Forgoing reading the second tag from a tag array circuit, where the second tag is an address tag associated with the specific cache line.

33. The method according to claim 31, wherein forgoing determining whether the prediction is correct includes using a cache controller to determine whether the acknowledgment bit is set in response to a subsequent cache access request for which the specific cache line is stored in a specific way among the multiple ways.

34. The method according to claim 31, further including determining that the prediction is correct in response to the first tag matching the second tag.

35. The method according to claim 31, further including using a cache controller to reset the acknowledgment bit in response to the specific cache line being evicted from the cache memory.

36. The method according to claim 31, further including using a cache controller to reset the acknowledgment bit in response to determining that an address translation associated with the specific cache line is invalid.

37. The method according to claim 31, further including using a cache controller to provide the specific cache line to a requester that initiated the cache access request.

38. A system, comprising: A request circuit configured to initiate a cache access request; And A cache subsystem, wherein the cache subsystem includes: A cache controller configured to receive a cache access request; A prediction circuit configured to, in response to a cache access request, generate a prediction for a specific way among multiple ways in a cache memory including a specific cache line associated with the cache access request; A comparison circuit configured to determine whether the prediction is correct, wherein, to determine whether the prediction is correct, the comparison circuit is configured to compare a first tag associated with the specific cache line and a second tag associated with the specific way among the multiple ways; and An acknowledgment bit memory, wherein the prediction circuit is configured to set an acknowledgment bit in the acknowledgment bit memory in response to the comparison circuit determining that the prediction is correct; wherein the cache controller is configured to, for a subsequent cache access request for the specific cache line, prohibit the comparison circuit from determining whether the prediction is correct in response to determining that the acknowledgment bit in the acknowledgment bit memory is set.

39. The system according to claim 38, to prohibit the comparison circuit from determining whether the prediction is correct for a subsequent cache access request for the specific cache line, the cache controller is configured to: Cause the comparison circuit to forgo reading the first tag from the cache memory, where the first tag is a cache tag associated with the path among the multiple paths; and Cause the comparison circuit to forgo reading the second tag from the tag array circuit, where the second tag is an address tag associated with the specific cache line.

40. The system according to claim 38, wherein the comparison circuit is configured to determine that the prediction is correct in response to determining that the first tag matches the second tag.

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