Incremental glitch analysis for efficient glitch power optimization

Abstract

The invention relates to incremental glitch analysis for efficient glitch power optimization. A system and method for designing an integrated circuit using incremental glitch analysis for efficient glitch power optimization includes determining a glitch factor for a combinatorial logic (CL) gate of a circuit based on a time-of-arrival range at first and second inputs of the CL gate of the circuit and an internal delay of the CL gate, a glitch factor for the CL gate is updated after the modification to the circuit design affecting the CL gate, and a determination is made as to whether to preserve the modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.

Description

Technical Field

[0001] The present disclosure generally relates to electronic design automation (EDA) systems. In particular, the present disclosure relates to incremental glitch analysis for efficient glitch power optimization. Background Art

[0002] A glitch is a spurious pulse that occurs at the output of a combinational logic gate before the output stabilizes to its final value or state. Glitches can occur due to differences in the arrival times of the inputs of a combinational logic gate. Glitches can occur due to reconvergence in a logic cone, where a signal arriving at one branch arrives or transitions earlier than the signal in another branch. If the width of a glitch pulse is less than the inherent delay of a combinational logic gate, the glitch pulse can be absorbed by the combinational logic gate. Wider glitch pulses can propagate and accumulate, resulting in glitch hotspots, where the glitch pulses are more similar to functional transitions. Glitches may not have an adverse effect on the functionality of a circuit, but can consume significant power. For example, in a data path-centric circuit, glitches can account for a portion of the total power consumption (e.g., 30% or more of the total power consumption). As transistor sizes shrink, glitches are increasingly becoming a major source of power consumption. Summary of the Invention

[0003] Disclosed herein are a system and method for designing an integrated circuit with incremental glitch analysis for efficient glitch power optimization. One example is a non-transitory computer-readable medium that includes stored instructions that, when executed by a processor, cause the processor to determine a glitch induction window (GIW) for a combinational logic (CL) gate of a circuit design based on arrival time ranges of a first input and a second input of the CL gate after a modification to the circuit design that affects the CL gate, and determine whether to retain the modification to the circuit design based on the first GIW.

[0004] Another example is a method that includes determining a glitch factor for a CL gate of a circuit design based on arrival time ranges at a first input and a second input of the CL gate and an internal delay of the CL gate, performing an incremental modification to the circuit design, where a first incremental modification affects the CL gate, updating the glitch factor for the CL gate after the incremental modification, and determining whether to retain the incremental modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.

[0005] Another example is a system that includes a memory storing instructions and a processor coupled to the memory and executing the instructions, which when executed, cause the processor to determine a glitch factor for a CL gate of a circuit based on a range of arrival times at a first input and a second input of the CL gate and an internal delay of the CL gate, update the glitch factor for the CL gate after a modification to the circuit design that affects the CL gate, and determine whether to retain the modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0007] Figure 1 is a block diagram of a computing platform according to an embodiment.

[0008] Figure 2 is a logic diagram of a circuit design according to an embodiment.

[0009] Figure 3A is a logic diagram of a combinational logic (CL) gate network according to an embodiment.

[0010] Figure 3B illustrates a timing diagram of a CL gate according to an embodiment for Figure 3A

[0011] Figure 3C illustrates another timing diagram of a CL gate according to an embodiment for Figure 3A

[0012] Figure 4A is a diagram of a glitch induction window (GIW) of a CL gate according to an embodiment for Figure 3A

[0013] Figure 4B is a diagram of another GIW of a CL gate according to an embodiment for Figure 3A

[0014] Figure 4C is a diagram of another GIW of a CL gate according to an embodiment for Figure 3A

[0015] Figure 5A illustrates a timing diagram corresponding to points of a GIW according to an embodiment for Figure 4A

[0016] Figure 5B illustrates according to an embodiment Figure 5AA subset of the timing diagram.

[0017] Figure 6 Illustrates another CL gate network according to an embodiment.

[0018] Figure 7 Illustrates an incremental glitch analysis method according to an embodiment.

[0019] Figure 8 Illustrates another incremental glitch analysis method according to an embodiment.

[0020] Figure 9 Depicts a flowchart of various processes used during the design and manufacture of an integrated circuit according to some embodiments of the present disclosure.

[0021] Figure 10 Depicts a diagram of an example simulation system according to some embodiments of the present disclosure.

[0022] Figure 11 Depicts a diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0023] Aspects of the present disclosure relate to incremental glitch analysis for efficient glitch power optimization.

[0024] A circuit design (e.g., a gate-level netlist) can be optimized (i.e., modified / changed) for desired characteristics such as performance (e.g., timing / frequency), power consumption (e.g., leakage or dynamic power), and / or area (e.g., physical area and / or lines of code) (collectively referred to as PPA). Optimization can include rerouting tracks (i.e., signal, power, and / or clock tracks), resizing transistors, inserting delay elements, and / or other changes. Optimization can include balancing competing desired characteristics.

[0025] Power consumption optimization can be for the power consumption of functional components and interconnects. Since glitch activity accounts for a large portion of the total power consumption in an integrated circuit, it is also useful to consider glitch activity / glitch power consumption when optimizing a circuit design.

[0026] Glitch activity in circuit design is a secondary effect of arrival propagation (i.e., the time at which a data signal transition arrives at the input of a logic gate). When modifying a circuit design, the modification can cause a change in arrival propagation, which can cause a change in glitch activity (i.e., increase or decrease). Changes in arrival propagation can occur due to modifications within the fan-in cone of a logic gate and / or from modifications in side paths from a logic gate. Changes in arrival propagation can occur in the modified fan-out cone. Tracking such dynamic changes in glitch activity is challenging because it can be difficult to determine the source of the change in glitch activity and / or it can be difficult to determine where the change in glitch activity can propagate within the fan-out cone of the source. Additionally, due to one or more of various reasons, a signal can arrive at the input of a logic gate later than expected (i.e., late arrival), which further complicates the analysis of glitch activity in a circuit design.

[0027] Glitch activity can be detected by simulating, emulating, and / or prototyping (collectively referred to as simulation) the operation of a circuit design. However, simulation of a circuit design is computationally expensive and time-consuming. Depending on the size / complexity of the circuit design and the simulation length, a single simulation cycle can take hours to complete and needs to be repeated as the circuit design changes. Thus, simulation-based glitch analysis during optimization is too expensive.

[0028] The incremental glitch analysis techniques disclosed herein include a system and method for modeling glitch activity (e.g., glitch-induced window (GIW)) and quantifying glitch activity (e.g., glitch factor (GF)) and tracking changes in glitch activity based on incremental modifications to a circuit design. The GIW models data signal interactions at the input of a combinational logic (CL) gate. The GIW is based on the maximum (late arrival) and minimum (glitch arrival) times at which a data signal can arrive at the input of a CL gate. The GF quantifies the glitch activity modeled by the GIW. Incremental optimization can cause a change in the GF of a CL gate. A change in the GF indicates whether the optimization is causing an increase or decrease in glitch activity at the CL gate.

[0029] The incremental glitch analysis system and method disclosed herein track incremental modifications to a circuit design (e.g., a netlist) and corresponding changes in the operating parameters of the circuit design (e.g., timing parameters such as slope, capacitance, delay, arrival). Based on the changes in the operating parameters, the CL gates affected by the modification are scheduled for incremental glitch analysis.

[0030] The incremental glitch analysis system and method disclosed herein are relatively fast and efficient and can be performed throughout the electronic design automation (EDA) optimization process. Incremental glitch analysis can be integrated as part of the EDA optimization process, such as performance (e.g., timing) optimization and / or power optimization. Such integration can help to allow the EDA optimization process to consider the glitch impact (e.g., as an optimization criterion) during optimization. Incremental glitch analysis can be performed as part of the inner loop of the EDA optimization process, where incremental glitch analysis can be performed multiple times (e.g., millions of times) on the incremental modification process of the circuit design. Incremental glitch analysis can help to ensure that timing-based optimization and / or power-based optimization do not have an adverse impact on glitch activity. For example, the timing optimization engine can use the incremental glitch analysis results as one of the multiple cost consideration factors.

[0031] The technical advantages of the present disclosure include, but are not limited to, reducing computing resources. By way of example and not limitation, analyzing the glitch activity of circuit components that may be affected by a modification to the circuit design, and doing so incrementally (i.e., after each of multiple modifications), uses far fewer computing resources (e.g., requires less memory resources to store the results of the incremental analysis) than analyzing the glitch activity of the entire circuit design after each modification. Analyzing glitch activity based on the known delay range of circuit components also uses fewer computing resources than analyzing glitch activity based on the simulation operations of the circuit design. The time saved makes it feasible to analyze glitch activity during EDA.

[0032] Figure 1 is a block diagram of a computing platform 100 according to an embodiment. The computing platform 100 may include, but is not limited to, a processor and memory encoded by one or more computer programs and / or other circuitry. The computing platform 100 may represent multiple computing platforms, which may be centralized or distributed.

[0033] The computing platform 100 includes a set of electronic design automation (EDA) tools 102 that analyze and optimize a circuit design 104. The computing platform 100 also includes a storage device 103.

[0034] In Figure 1In this, the EDA tool 102 includes an analysis tool 108 that analyzes the circuit design 104. The analysis tool 108 can determine or calculate the PPA parameters 110 of the circuit design 104 or a subset thereof. The PPA parameters 110 can include (by way of example but not limitation) performance (e.g., timing / frequency) parameters 110-1, power parameters 110-2, area parameters 110-3, which can be collectively referred to as the PPA parameters 110. The analysis tool 108 also determines glitch toggles 140, which will be further described below. The analysis tool 108 can represent multiple analysis tools, which can include but are not limited to a timing analysis tool, a power analysis tool, an area analysis tool, a switching activity detection tool, and / or other analysis tools.

[0035] The EDA tool 102 also includes an optimizer tool 116 that optimizes the circuit design 104 based on an optimization criterion 118. The optimization criterion 118 can include criteria related to performance, power, area (PPA), switching / glitch activity, and / or other factors. The optimizer tool 116 can optimize the circuit design 104 to improve the performance parameters 110-1, power parameters 110-2, area parameters 110-3, glitch toggles 140, and / or other parameters. The optimizer tool 116 can represent multiple optimization tools, which can include but are not limited to a timing optimizer tool, a power optimizer tool, a glitch power optimizer tool, and / or other optimizer tools.

[0036] The optimizer tool can be integrated with the corresponding analysis tool. The integrated tool can be used to combine one or more of various types of power consumption / loss (e.g., leakage, dynamic, glitch) with power analysis (e.g., measuring the power-related impact of circuit design modifications). Alternatively or additionally, the integrated tool can be used to combine delay-based optimization (e.g., optimization for improving the performance of the circuit design) with timing analysis (e.g., measuring the timing-related impact of circuit design modifications).

[0037] The EDA tool 102 also includes a glitch metric tool 120 that calculates a glitch metric 122. The glitch metric tool 120 and the glitch metric 122 will be further described below.

[0038] The circuit design 104 can include a netlist 106 that contains a description of the circuit elements and the connectivity of the circuit design 104. The netlist 106 can include a list of the electronic components of the circuit design 104 and a list of the nodes to which the electronic components are connected.

[0039] The circuit design 104 may include a sequential circuit. A sequential circuit is a circuit that includes sequential logic gates interleaved with a network of combinational logic (CL) gates (referred to herein as a CL network). A sequential logic gate is a logic gate whose output is at least partially based on a previous state of the inputs to the logic gate. Example sequential logic gates include flip-flops, latches, registers, and random access memories (RAMs). A sequential logic gate stores input data and asserts an output based on a clock. Correct operation of a sequential logic gate requires that the input data remain stable for a certain amount of time (setup time) before a clock event and for a certain amount of time (hold time) after the clock event. A CL gate is a logic gate whose output is a function of the current state of the inputs to the logic gate. CL gates typically lack memory and internal state. Example CL gates include AND gates, OR gates, XOR gates, and / or inverter logic gates.

[0040] Figure 2 is a logic diagram of a circuit design according to an embodiment. In Figure 2 example, the circuit design 200 includes sequential logic gates 202 and 204, illustrated here as flip-flops (FFs). The circuit design 104 also includes CL networks 206, 208, 210, and 212.

[0041] Figure 3A is a logic diagram of the CL network 208 according to an embodiment. In Figure 3A example, the CL network 208 includes a CL inverter gate 306, a CL NAND gate 308, and a CL XOR gate 310. The CL XOR gate 310 includes a plurality of data inputs (illustrated here as inputs 316 and 318) and an output 314. Glitches may occur at the output 314 when the data inputs 316 and 318 transition inconsistently, such as described below with reference to Figure 3B and Figure 3C described.

[0042] Figure 3B Illustrates a timing diagram 340 of the CL XOR gate 310 according to an embodiment. In Figure 3B In, at time 342, the data inputs 316 and 318 of the CL XOR gate 310 switch or change state simultaneously, from a logic state 0 to a logic state 1. In other words, there is no difference or little difference in the arrival times of the data inputs 316 and 318. In this example, the output 314 of the CL XOR gate 310 remains in the logic state 0 before time 342 and after time 342 (i.e., there are no glitches).

[0043] Figure 3C Illustrates a timing diagram 350 of the CL XOR gate 310 according to an embodiment. InFigure 3C In this case, shortly after the time 352 when the state of data input 316 changes, the data input 318 of the CL XOR gate 310 switches state or changes state, from the logical state 0 to the logical state 1. In other words, there is a difference 354 in the arrival times of data input 316 and data input 318. The difference 354 in arrival times causes a glitch 356. The duration of the glitch 356 corresponds to the difference 354 in arrival times.

[0044] The arrival times of input data inputs 316 and 318 can be different from each other for various reasons, including differences in delays that cause data inputs 316 and 318. In Figure 3A the example, the arrival time of data input 316 depends in part on the delay 338 before the CL inverter gate 306, the internal delay 344 of the CL inverter gate 306 (e.g., gate or switch delay), and the interconnect delay 322 of the interconnect between the output of the CL inverter gate 310 and data input 316. The arrival time of data input 318 depends in part on the delay 346 before the input 336 of the CL NAND gate 308, the interconnect delay 326 between the output of the CL inverter gate 310 and the input 334 of the CL NAND gate 308, the internal delays 328 and 329 of the CL NAND gate 308, and the interconnect delay 330 between the output of the CL NAND gate 308 and data input 318. The internal delays 360 and 362 of the CL XOR gate will be further discussed below.

[0045] Interconnect delays and internal delays can depend on variable factors that can include but are not limited to process corners, driver strength, load capacitance, input slope, output load, and / or environmental factors (such as coupling between networks and / or process, voltage, and / or temperature (PVT) variations). Therefore, it can be difficult to accurately calculate arrival times based on circuit design. Instead, the analysis tool 108 (and / or one or more other tools in the EDA tool 102) can determine the arrival time as an arrival time range. The analysis tool 108 can determine (e.g., calculate) the arrival time range based in whole or in part on variable factors such as those described above. In one example, the analysis tool 108 calculates the arrival time range based on the structure of the netlist and the internal delays of the CL gates and the interconnect delays between the CL gates, which can be retrieved and / or derived from one or more data sources. As an example, the analysis tool 108 can determine the internal delays of the CL gates based on one or more specific characteristics of the library cell specific characteristics.

[0046] In Figure 3AIn the example, the analysis tool 108 can determine the arrival time range of the data input 318 of the CL XOR gate 310 based on the minimum and maximum arrival times of the data input 318. The optimizer tool 116 can determine the minimum and maximum arrival times of the data input 318 based on the respective minimum and maximum values of the delays 338, 344, 326, 346, 328, 329, and 330, as further described above. The analysis tool 108 can determine the minimum and maximum arrival times of the data input 318 by accumulating the minimum and maximum values of the delays 338, 344, 326, 346, 328, 329, and 330. The accumulated minimum and maximum delays can account for the cumulative effect of the minimum and maximum values of the delays 338, 344, 326, 346, 328, 329, and 330. The analysis tool 108 can determine the arrival time range of the data input 316 of the CL XOR gate 310 in a similar manner based on the minimum and maximum values of the delays 338, 344, and 332.

[0047] In an embodiment, Figure 1 the glitch metric tool 120 in defines a glitch-induced window (GIW) 124 based on the arrival time ranges of the inputs 316 and 318. The glitch metric tool 120 can define the GIW 124 based on the minimum possible / potential values and the maximum possible / potential values of the delays 338, 344, 322, 326, 346, 328, 329, and 330. In other words, the GIW 124 represents the time interval during which the signal at the input to the CL gate deviates due to the structure of the netlist 106. The switching signal deviation is a determinant of glitch induction and reduction.

[0048] The analysis tool 108 can determine the arrival time range (also referred to herein as the propagation arrival or the propagation late arrival) based on the netlist 106. Depending on the level of detail of the netlist 106, the analysis tool 108 can retrieve detailed delay information and / or can use predefined generalized delay information. For example, in the case where the netlist 106 is a technology-mapped netlist of gate-level components (i.e., technology-specific logic gates), the analysis tool 108 can retrieve gate-level delay information from Figure 1 the logic library 130 (e.g., the cell library) in. In the case where the circuit design 104 includes a higher-level non-technology-mapped netlist (e.g., a netlist of primitive logic gates (such as AND, OR, XOR, inverters, and / or other types of logic gates)), the analysis tool 108 can use predefined delay values for the respective types or can use predefined 1-gate delay values.

[0049] Analysis tool 108 can retrieve latency information from the latency table 132 of the logic library 130. The latency table 132 can list latencies as a function of one or more variables such as input transition time, output load capacitance, logic type, temperature handling, and / or other factors. Analysis tool 108 can calculate internal latency based on the table entries. Alternatively or additionally, analysis tool 108 can retrieve internal latency information and / or interconnect latency information from a file that can be formatted according to the Standard Delay Format (SDF) promulgated by the Institute of Electrical and Electronics Engineers (IEEE). SDF represents and interprets timing data for use at various stages of the EDA process. The SDF file can include internal latency, timing constraint values, interconnect / network latency, and / or technology parameters. The SDF file can include separate sections for internal latency and interconnect latency.

[0050] The glitch metric tool 120 can define (e.g., calculate or construct) the GIW 124 for a CL gate (e.g., for a predetermined CL gate 150) of the circuit design 104 based on the structure of the netlist 106. The glitch metric tool 120 can define the GIW 124 independent of the timing constraints of the circuit design 104. In the case where the analysis tool 108 calculates interconnect latency and / or internal latency for timing analysis, the glitch metric tool 120 can utilize the calculated interconnect latency and / or internal latency to determine the arrival time range (i.e., to propagate glitch arrival) for glitch analysis.

[0051] Figure 4A is a diagram of the GIW 124-1 for the CL XOR gate 310 according to an embodiment. Figure 4B is a diagram of another GIW 124-2 for the CL XOR gate 310 according to an embodiment. Figure 4C is a diagram of another GIW 124-3 for the CL XOR gate 310 according to an embodiment.

[0052] In Figure 4AIn the example, GIW 124-1 is illustrated as a rectangle having a width ΔA1 and a height ΔB1. ΔA1 represents the arrival time range of input 316, and analysis tool 108 can determine the arrival time range of this input 316 based on the minimum and maximum values of delays 338, 344, 326, 346, 328, 329, and 330, as further described above. ΔA1 represents the difference between the minimum arrival time 420 and the maximum arrival time 422 of input 316. ΔB1 represents the arrival time range of input 318. Analysis tool 108 can determine ΔB1 based on the minimum and maximum values of delays 338, 344, and 332, as further described above. For a CL gate including more than two inputs, the glitch metric tool 120 can select a first input with the lowest lower end of the arrival time range, a second input with the highest upper end of the latest arrival time range, and can calculate the GIW 124 for the CL gate based on the lower end of the arrival time range of the first input and the upper end of the arrival time window of the second input.

[0053] The glitch metric tool 120 can determine a glitch band 128-1 for the CL XOR gate 310. The width 431 of the glitch band 410 represents the internal delays 360 and 362 of the CL XOR gate 310, which can be determined as further described above. The CL XOR gate 310 absorbs the difference in the arrival times of inputs 316 and 318 within the glitch band 128-1. In other words, when the deviation between the signals at inputs 316 and 318 is small enough or zero, there is no glitch at the output 314 of the CL XOR gate 310. The line 421 (i.e., y = x) represents the situation where the difference in the arrival times of inputs 316 and 318 is zero (i.e., the ideal behavior where the signals at inputs 316 and 318 are synchronized with each other). The position of GIW 124-1 relative to the glitch band 128-1 indicates the degree to which the CL XOR gate 310 absorbs glitches considering the arrival time ranges of data inputs 316 and 318. Examples are provided below with reference to Figure 4A , Figure 4B , Figure 4C , Figure 5A and Figure 5B .

[0054] Figure 5AIllustrated are timing diagrams 502 to 518 corresponding to points 402 to 418 of GIW 124-1 according to an embodiment. Timing diagram 502 corresponds to point 402, where input 316 transitions at minimum arrival time 420 and input 318 transitions at minimum arrival time 424. Timing diagram 512 corresponds to point 412, where input 316 transitions at maximum arrival time 422 and input 318 transitions at maximum arrival time 426. Similarly, the other timing diagrams 504, 506, 508, 510, 514, 516, and 518 respectively illustrate the transitions of input 316 and input 318 at points 404, 406, 408, 410, 414, 416, and 418.

[0055] Figure 5B Illustrated are timing diagrams 506, 510, and 518 corresponding to points 406, 410, and 418 along line 421 of GIW 124-1 according to an embodiment. Timing diagrams 506, 510, and 518 correspond to ideal behavior, where the arrival times of data input 316 and data input 318 are synchronized with each other.

[0056] In Figure 4A , the width ΔA1 and / or the height ΔB1 may change after a modification to the circuit design 104 that affects the CL XOR gate 310. Such a modification may include, for example but not limited to, reducing the interconnect length between the output of the CL inverter gate 306 and the input 334 of the CL NAND gate 308, replacing the CL NAND gate 308 with a CL NAND gate having a greater drive power than the CL NAND gate 308, and / or other modifications. Figure 4A The GIW 124-1 in Figure 4B may represent the CL XOR gate 310 before modification, and Figure 4C The GIW 124-2 in Figure 4B and the GIW 124-2 in Figure 4B may represent the CL XOR gate 310 after corresponding incremental modifications to the circuit design 104. In Figure 4A , the width ΔA2 of GIW 124-2 is less than the width ΔA1 of GIW 124-1, and the height ΔB2 is less than the height ΔB1 of GIW 124-1. Thus, Figure 4BIn , the percentage of GIW 124-2 within the burr band 128-1 (i.e., Figure 4B the shaded area 458 in ) is larger than that of the shaded area 428 of GIW 124-1.

[0057] The area percentage of GIW 124 located within the burr band 128-1 represents the likelihood that the burr will be absorbed by the corresponding CL gate. In Figure 4A , the area percentage of GIW 124-1 (i.e., the shaded area 428) within the burr band 128-1 represents the likelihood that the burr will be absorbed by the CL XOR gate 310. In Figure 4B , the area percentage of GIW 124-2 within the shaded area 458 represents the likelihood that the burr will be absorbed by the CL XOR gate 310. Increasing the area percentage of GIW 124 within the burr band 128-1 (i.e., as shown in Figure 4B ) increases the likelihood that the burr will be absorbed by the CL XOR gate 310. In other words, Figure 4B 's example indicates that, relative to Figure 4A 's example, the modification results in a higher burr absorption percentage. In Figure 4C , the width ΔA3 of GIW 124-3 is less than the width ΔA2 of GIW 124-2, and the height ΔB3 is less than the height ΔB2 of GIW 124-2. Additionally, in Figure 4C , the entire GIW 124-3 is within the burr band 128-1. Thus, Figure 4C 's example represents a further improvement in burr absorption (i.e., complete burr absorption).

[0058] During incremental updates, the burr metric tool 120 calculates the burr factor (GF) 126 based on GIW 124-1, 124-2, and 124-3. The GF 126 serves as a relative metric for the switching / burr activity of the CL gates for the design instance (i.e., the current state of the circuit design 104 / netlist 106), indicating the burrs that can be absorbed. In an embodiment, during incremental updates, the burr metric tool 120 calculates the GF 126 based on the overlapping region of the corresponding burr band 128-1 to determine whether the modification of the circuit design 104 improves burr absorption.

[0059] In Figure 4A , the burr metric tool 120 can calculate the GF 126 for the CL XOR gate 310 based on the area of the shaded area 428 of GIW 124-1. In an embodiment, the burr metric tool 120 calculates the GF 126 for the CL XOR gate 310 as the ratio of the area of the shaded area 428 to the total area of GIW 124-1:

[0060] GF = (Area of the shaded region 428) / (Area of GIW 124-1)

[0061] The metric GF 126 indicates the ratio of the eliminated glitches to the induced glitches, where the latter is indicated by the area of GIW 124-1. Thus, the eliminated glitches are estimated as the GF ratio of the induced glitches, i.e., Eliminated glitches = Induced glitches * GF. Therefore, the final net glitches on any instance = Induced glitches - Eliminated glitches = Induced glitches - Induced glitches * GF.

[0062] During incremental updates, a decrease in GF represents the eliminated glitch activity for the corresponding CL gate. During incremental glitch analysis, the EDA tool 102 or a subset thereof can track changes in GIW 124 and / or changes in GF 126 to systematically guide optimizations (e.g., reducing the area of GIW 124, moving GIW into the glitch band 128-1, and / or increasing the width 431 of the glitch band 128-1). For example, the optimizer tool 116 can use GIW 124 and / or GF 126 as a cost function (e.g., making decisions regarding modifications to the circuit design 104 to suppress glitches or alter glitches to reduce the impact of glitches on the total power consumption).

[0063] In an embodiment, the EDA tool 102 or a subset thereof (e.g., the optimizer tool 116) tracks the modifications made to the circuit design 104 (e.g., changes made to the netlist 106) as modifications 112 and correlates the modifications 112 with GF 126 and / or with changes in GF 126. The optimizer tool 116 can consider changes in GF 126 of the CL gate as an optimization criterion 118. In the case where the netlist includes a library cell for the CL gate, the library cell can be replaced with another library cell to increase the width of the glitch band 128-1, which effectively increases glitch elimination.

[0064] During incremental optimization, the width of the glitch band 128-1 can be increased by modifying the characteristics of the CL XOR gate 310 (e.g., by using a different library cell for the CL XOR gate 310). Increasing the width of the glitch band 128-1 can help increase GF (i.e., effectively increase the extent to which the CL XOR gate 310 absorbs glitches).

[0065] GIW 124, GF 126, and the glitch band 128 are characteristics of a design instance. In other words, the circuit design 104 can include multiple instances of a particular logic gate. In such a case, GIW 124, GF 126, and the glitch band 128 can vary between instances of the logic gate based on factors associated with the respective instances (e.g., layout location, connectivity, process, voltage, temperature, and / or factors).

[0066] Figure 6 It is a diagram of the CL network 600 designed according to the circuit of the embodiment. Figure 6 It includes timing windows 606-10 and 606-12 for performance / timing optimization (e.g., setup and hold times for sequential logic gates), and GIW 124-14 to GIW 124-20 for incremental glitch analysis. In an embodiment, the EDA tool 102 or a subset thereof simultaneously tracks changes in the GIW and changes in the timing windows. In Figure 6 the example of, the EDA tool 102 or a subset thereof can optimize / modify the circuit CL network 600 based on GIW124-10 and GIW 124-12 at the input of the CL gate 602, and the timing windows 606-10 and the timing window 606-12, and can track changes caused in GIW 124-10 and GIW 124-12 and the timing windows 606-10 and the timing window 606-12. The EDA tool 102 or a subset thereof can also track changes in the GIW and the timing windows (e.g., GIW124-14 to GIW 124-20 and the timing windows 606-14 to the timing window 606-20) within the fan-out cone of the CL gate 602. Figure 6 The figure illustrates that the incremental glitch update can be coupled to (i.e., can affect) the timing update. Since the glitch is a second-order effect of the arrival change, the arrival time may not change at the input of the CL gate 602, but the glitch activity can propagate from the CL gate 602.

[0067] The following references Figure 7 describe Figures 1 to 6 . Figure 7 The figure illustrates a method 700 for incremental glitch analysis according to an embodiment. The following references Figures 1 to 6 describe the method 700. However, the method 700 is not limited to Figures 1 to 6 the example of.

[0068] At 702, the analysis tool 108 performs a pre-optimization analysis of the circuit design 104 to determine the initial values of the PPA parameters 110 and the glitch metrics 122 or a subset thereof. In an embodiment, the analysis tool 108 determines the initial values of at least the power parameter 110-2 and one or more glitch metrics 122. If the circuit design 104 is to be optimized for performance and / or area as well as power, the analysis tool 108 can also determine the initial values of the performance parameter 110-1 (e.g., timing / frequency parameter) and / or the area parameter 110-3.

[0069] In an embodiment, during pre-optimization analysis, analysis tool 108 determines initial values of glitch switching 140 and / or glitch switching power 142. Glitch switching 140 represents non-intended switching activity (i.e., glitches). Glitch switching power 142 represents the power consumed due to glitch switching 140. Analysis tool 108 may determine the initial value of glitch switching 140 based on one or more of a variety of methods (such as, for example but not limited to, simulation operation of circuit design 104, GIW-based estimation methods, and / or delay-shift Monte Carlo methods). Analysis tool 108 may determine the initial value of glitch switching power 142 based on the dynamic power caused by glitch switching 140. Analysis tool 108 may monitor glitch switching at the output of the CL network and / or within the fan-in and / or fan-out cones of the CL gates. Analysis tool 108 may identify glitch switching 140 with a relatively high level (e.g., frequency) (i.e., glitch hotspots) and / or identify regions of circuit design 104 and / or CL gates of circuit design 104 that are the sources of such glitch hotspots.

[0070] During pre-optimization analysis or at the end of pre-optimization analysis, analysis tool 108 or glitch metric tool 120 may identify or select CL gates of circuit design 104 (i.e., predetermined CL gates 150) based on the initial values of glitch switching 140 and / or glitch switching power 142 for tracking and analysis during incremental optimization. Glitch metric tool 120 may calculate the GIW 124, GF 126, and / or glitch band 128 of predetermined CL gates 150.

[0071] The pre-optimization analysis at 702 may be relatively comprehensive / exhaustive and thus time-consuming (e.g., relative to what is acceptable / tolerable during optimization). Analysis tool 108 may determine initial values of PPA parameters 110 and glitch metrics 122 or subsets thereof by analyzing the entire circuit design 104. Analysis tool 108 may determine the initial values of PPA parameters 110 and glitch metrics 122 by simulating, emulating, and / or prototyping circuit design 104 (e.g., based on netlist 106) and / or by calculating initial values based on netlist 106.

[0072] After the pre-optimization analysis at 702, optimizer tool 116 incrementally optimizes circuit design 104 at 704, as analysis tool 108 and glitch metric tool 120 track modifications 112 to circuit design 104 and update PPA parameters 110 and glitch metrics 122 at 706, as described below.

[0073] At 708, the optimizer tool 116 modifies the circuit design 104 (e.g., the netlist 106) to improve the initial values of the PPA parameters 110 and / or the glitch metrics 122. The optimizer tool 116 can, for example but not limited to, reroute tracks (i.e., signal, power, and / or clock tracks), resize gates / transistors, insert delay elements, and / or perform other modifications. The optimization can include balancing competing optimization criteria 118.

[0074] At 710, the EDA tool 102 or a subset thereof tracks the modification to the circuit design 104 from 708 as the modification 112.

[0075] At 712, the analysis tool 108 updates the PPA parameters 110 (or a subset thereof). The analysis tool 108 can perform an incremental analysis or a partial analysis of the circuit design 104 in view of the modification 112. For example, the analysis tool 108 can analyze the part of the circuit design 104 that is affected by the most recent modification 112 (e.g., a part of the netlist 106). The analysis tool 108 can update the PPA parameters 110 by simulating, emulating, and / or prototyping a part of the circuit design 104 and / or by calculating the updated values based on the most recent modification 112. The analysis tool 108 can simulate, emulate, and / or prototype a part of the circuit design 104 relatively quickly (i.e., much faster than simulating, emulating, and / or prototyping the entire circuit design 104).

[0076] At 714, the glitch metrics tool 120 updates the glitch metrics 122 for a predetermined CL gate 150. In one example, the analysis tool 108 recalculates the difference in arrival times and / or the late arrival time range for the predetermined CL gate 150, and the glitch metrics tool 120 recalculates the glitch metrics 122 based on the recalculated difference in arrival times and / or the late arrival time range. Thus, for glitch optimization, the EDA tool 102 can dynamically monitor changes in the glitch metrics 122 of the predetermined CL gate 150 (and the CL gates within the fan-in and / or fan-out code of the predetermined CL gate 150) as the predetermined CL gate 150 is modified (and / or as the CL gates within the fan-in and / or fan-out code of the predetermined CL gate 150 are modified), and can continue to optimize / modify the predetermined CL gate 150 in view of the dynamic changes in the glitch metrics 122.

[0077] The glitch metrics tool 120 can also dynamically update the predetermined CL gate 150 based on the modification 112 (e.g., to include CL gates that may or potentially be affected by the modification 112, and / or to include GL gates within the fan-in and / or fan-out cones of the CL gates that may or potentially be affected by the modification 112).

[0078] At 720, analysis tool 108 determines whether to retain the modification from 708 based on the updated PPA parameters 110 and glitch metrics 122 from 706 and the optimization criteria 118. If the updated glitch metrics of 714 are improved compared to the previous glitch metrics and / or if the updated PPA parameters 110 and / or glitch metrics 122 meet the optimization criteria 118, analysis tool 108 may determine to retain the modification from 708.

[0079] If analysis tool 108 determines to retain the modification from 708, the process proceeds to 721, where analysis tool 108 determines whether to continue modifying circuit design 104. If analysis tool 108 determines to continue modifying circuit design 104, the process returns to 708c for a subsequent round of optimization using incremental glitch analysis. The optimization using incremental glitch analysis (i.e., 704 and 706) may be repeated until analysis tool 108 determines to stop modifying circuit design 104. When analysis tool 108 determines to stop modifying circuit design 104 at 722, circuit design 104 is passed to the subsequent design phase and / or fabrication phase at 724.

[0080] Figure 8 FIG. illustrates a method 800 of incremental glitch analysis according to an embodiment. The following is referenced Figures 1 to 6 to describe method 800. However, method 800 is not limited to Figures 1 to 6 the examples of.

[0081] At 802, analysis tool 108 performs a pre-optimization analysis of circuit design 104, such as described in 702 above with reference to Figure 7 .

[0082] At 804, optimizer tool 116 modifies circuit design 104 (e.g., netlist 106), such as described in 708 above with reference to Figure 7 .

[0083] At 806, EDA tool 102 or a subset thereof tracks the modification 112 to circuit design 104, such as described in 710 above with reference to Figure 7 .

[0084] At 808, analysis tool 108 updates performance parameters 110-1 and power parameters 110-2 based on the modification 112, such as described in 712 above with reference to Figure 7 . Analysis tool 108 may also update area parameter 110-3.

[0085] At 810, glitch metrics tool 120 propagates arrivals (i.e., late arrivals and glitch arrivals) to determine the difference in arrival times of inputs to the CL gates of circuit design 104, such as described in 714 above with reference to Figure 7 .

[0086] At 812, the glitch metric tool 120 defines a GIW 124 for a CL gate (e.g., for a predetermined CL gate 150) of the circuit design 104, such as that described in 714 above with reference to Figure 7 the above.

[0087] At 814, the glitch metric tool 120 calculates a GF 126 for a CL gate (e.g., for a predetermined CL gate 150) of the circuit design 104, such as that described in 714 above with reference to Figure 7 the above.

[0088] At 816, the glitch metric tool 120 uses the GF for a CL gate (e.g., for a predetermined CL gate 150) of the circuit design 104 to calculate and update the glitch transition 140, such as that described in 714 above with reference to Figure 7 the above.

[0089] At 818, the glitch metric tool 120 calculates the glitch transition power 142 for a CL gate (e.g., for a predetermined CL gate 150) of the circuit design 104, such as that described in 714 above with reference to Figure 7 the above.

[0090] At 820, the analysis tool 108 determines whether to retain the modification from 804 based on the updated PPA parameters of 808, the GIW from 812, the GF from 814, the glitch transition from 816, the glitch power from 818, and the optimization criteria 118. If the analysis tool 108 determines to retain the modification from 804, the circuit design 104 is passed to a subsequent design phase and / or fabrication phase at 822. If the analysis tool 108 determines to discard the modification from 804, the process returns to 704 for a subsequent round of optimization using incremental glitch analysis.

[0091] Figure 9 Illustrated is a set of example processes 900 used during the design, verification, and fabrication of a work in progress (such as an integrated circuit) for transforming and validating design data and instructions representative of an integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" represents the term "electronic design automation". These processes begin with creating a product idea 910 using information provided by a designer, which is transformed to create a work in progress using a set of EDA processes 912. When the design is complete, the design is taped out 934, at which time the artwork (e.g., geometric patterns) of the integrated circuit is sent to a fabrication facility to create a mask set, which is then used to fabricate the integrated circuit. After tape out, a semiconductor die 936 is fabricated, and packaging and assembly processes 938 are performed to produce a finished integrated circuit 940.

[0092] The specification scope for a circuit or electronic structure can range from low-level transistor material layouts to high-level description languages. Using a hardware description language (“HDL”) (such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera), circuits and systems can be designed using a high-level representation. The HDL description can be converted into a logic-level register transfer level (“RTL”) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level, as a more detailed description, adds more useful details (such as more details of the module containing the description) to the design description. Each lower representation level, as a more detailed description, can be computer-generated, exported from a design library, or created by another design automation process. An example of a specification language for the lower representation level language that specifies a more detailed description is SPICE, which is used for the detailed description of circuits with many analog components. Descriptions at each representation level are used by the corresponding system (e.g., a formal verification system) of that layer. The design process can use Figure 9 the sequence depicted in

[0093] During system design 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be partitioned into different types of modules or components.

[0094] During logic design and functional verification 916, the modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specification is checked. For example, it can be verified that the components of the circuit generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs (such as test bench generators, static HDL checkers, and formal verifiers). In some embodiments, a special system using components referred to as “emulators” or “prototyping systems” is used to accelerate functional verification.

[0095] During synthesis and design testing 918, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graphical structure, where the edges of the graphical structure represent the components of the circuit, and where the nodes of the graphical structure represent the way the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that the EDA product can use to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the specification requirements.

[0096] During netlist verification 920, the netlist is checked to conform to timing constraints and correspond to the HDL code. During design planning 922, an overall floorplan for the integrated circuit is constructed and timing and top-level routing are analyzed.

[0097] During placement or physical implementation 924, physical placement (the positioning of circuit elements such as transistors or capacitors) and routing (connecting circuit components via multiple conductors) occur, and cells can be selected from a library to enable a specified logic function. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function such as a flip-flop or latch. As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled as physical structures and in simulations. Parameters such as dimensions are specified for the selected cells (based on "standard cells"), and the parameters can be accessed in a database for use by EDA products.

[0098] During analysis and extraction 926, the circuit function is verified at the layout level, allowing refinement of the layout design. During physical verification 928, the layout design is checked to ensure that design constraints (such as DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit device function matches the HDL design specification. During resolution enhancement 930, the geometry of the layout is transformed to improve the manufacturing of the circuit design.

[0099] During tapeout, data is created for the production of a lithography mask (after applying lithography enhancements if appropriate). During mask data preparation 932, the "tapeout" data is used to produce a lithography mask that is used to produce the finished integrated circuit.

[0100] A storage subsystem of a computer system (such as Figure 11 computer system 1100 or Figure 10 host system 1007) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as products for developing cells for a library and physical and logical designs using that library.

[0101] Figure 10A diagram depicting an example simulation environment 1000. The simulation environment 1000 can be configured to verify the functionality of a circuit design. The simulation environment 1000 can include a host system 1007 (e.g., a computer as part of an EDA system) and a simulation system 1002 (e.g., a set of programmable devices such as field programmable gate arrays (FPGAs) or processors). The host system constructs the simulation system to simulate the circuit design by using a compiler 1010, thereby generating data and information. The circuit design to be simulated is also referred to as the design under test ("DUT"), and the data and information from the simulation are used to verify the functionality of the DUT.

[0102] The host system 1007 can include one or more processors. In embodiments where the host system includes multiple processors, the functions performed by the host system described herein can be distributed among the multiple processors. The host system 1007 can include a compiler 1010 to transform a specification written in a description language representing the DUT and produce data (e.g., binary data) and information that are used to construct the simulation system 1002 to simulate the DUT. The compiler 1010 can transform, change, restructure, add new functionality to the DUT, and / or control the timing of the DUT.

[0103] The host system 1007 and the simulation system 1002 exchange data and information using signals carried by a simulation connection. The connection can be, but is not limited to, one or more cables (such as a cable having a pin structure compatible with the recommended standard 232 (RS232) or the universal serial bus (USB) protocol). The connection can be a wired communication medium or network (such as a local area network or a wide area network (such as the Internet)). The connection can be a wireless communication medium using a wireless protocol (such as Bluetooth or IEEE 1002.11) or a network having one or more access points. The host system 1007 and the simulation system 1002 can exchange data and information through a third device (such as a network server).

[0104] The simulation system 1002 includes multiple FPGAs (or other modules) such as FPGA 1004 1 and 1004 2 and additional FPGAs up to FPGA 1004 NEach FPGA may include one or more FPGA interfaces through which the FPGA is connected to other FPGAs (and potentially other emulation components) to enable the FPGAs to exchange signals. The FPGA interfaces may be referred to as input / output pins or FPGA pads. Although an emulator may include FPGAs, embodiments of the emulator may include other types of logic blocks instead of FPGAs, or used with FPGAs for emulating a DUT. For example, the emulation system 1002 may include custom FPGAs, application-specific ASICs for emulation or prototyping, memories, and input / output devices.

[0105] A programmable device may include an array of programmable logic blocks and a hierarchy of interconnects that may enable the programmable logic blocks to be interconnected according to the descriptions in the HDL code. Each of the programmable logic blocks may enable complex combinational functions or enable logic gates (such as AND and XOR logic blocks). In some embodiments, the logic blocks may also include memory elements / devices, which may be simple latches, flip-flops, or other memory blocks. Depending on the lengths of the interconnects between different logic blocks, signals may arrive at the input terminals of the logic blocks at different times and may thus be temporarily stored in the memory elements / devices.

[0106] FPGA 1004 1 to FPGA 804 N may be placed on one or more boards 1012 1 and 1012 2 and up to additional boards of board 1012 M Multiple boards may be placed into the emulation unit 1014 1 . The boards within the emulation unit may be connected using the back of the emulation unit or any other type of connection. Additionally, multiple emulation units (e.g., 1014 1 and 1014 2 to 1014 K ) may be connected to each other to form a multi-emulation unit system.

[0107] For a DUT to be emulated, the host system 1007 transmits one or more bit files to the emulation system 1002. The bit files may specify the description of the DUT and may further specify the DUT partitions created by the host system 1007 using trace and injection logic, the mapping of the partitions to the FPGAs of the emulator, and the design constraints. Using the bit files, the emulator configures the FPGAs to perform the functions of the DUT. In some embodiments, one or more FPGAs of the emulator may have trace and injection logic built into the silicon of the FPGA. In such embodiments, the FPGAs may not be configured by the host system to emulate the trace and injection logic.

[0108] The host system 1007 receives a description of the DUT to be emulated. In some embodiments, the DUT description is in a description language (e.g., Register Transfer Language (RTL)). In some embodiments, the DUT description is in a netlist-level file or a mixture of a netlist-level file and an HDL file. If part or all of the DUT description is in HDL, then the host system can synthesize the DUT description to create a gate-level netlist using the DUT description. The host system can use the netlist of the DUT to partition the DUT into multiple partitions, where one or more of the partitions include trace and injection logic. The trace and injection logic traces interface signals exchanged via the interfaces of the FPGA. Additionally, the trace and injection logic can inject the traced interface signals into the logic of the FPGA. The host system maps each partition to an FPGA of the emulator. In some embodiments, the trace and injection logic is included in selected partitions of the FPGA group. The trace and injection logic can be built into one or more of the FPGAs of the emulator. The host system can synthesize multiplexers to be mapped into the FPGAs. The trace and injection logic can use the multiplexers to inject interface signals into the DUT logic.

[0109] The host system creates a bit file that describes each partition of the DUT and the mapping of the partitions to the FPGAs. For partitions that include trace and injection logic, the bit file also describes the included logic. The bit file can include placement and routing information and design constraints. The host system stores the bit file and information describing which FPGAs will emulate each component of the DUT (e.g., which FPGA each component is mapped to).

[0110] Upon request, the host system transmits the bit file to the emulator. The host system signals the emulator to start the emulation of the DUT. During the emulation of the DUT or at the end of the emulation, the host system receives emulation results from the emulator via an emulation connection. The emulation results are data and information generated by the emulator during the emulation of the DUT, which include the interface signals traced by the trace and injection logic of each FPGA and the status of the interface signals. The host system can store the emulation results and / or transmit the emulation results to another processing system.

[0111] After DUT simulation, a circuit designer may request to debug components of the DUT. If such a request is made, the circuit designer may specify a time period of the simulation to be debugged. The host system uses the stored information to identify which FPGAs are simulating the component. The host system retrieves the stored interface signals associated with the time period, which are traced by the trace and injection logic of each identified FPGA. The host system signals the emulator to re - simulate the identified FPGAs. The host system transmits the retrieved interface signals to the emulator to re - simulate the component during the specified time period. The trace and injection logic of each identified FPGA injects its corresponding interface signals received from the host system into the logic of the DUT mapped to that FPGA. In the case of multiple re - simulations of the FPGA, the merged results produce a complete debug view.

[0112] The host system receives from the simulation system the signals traced by the logic of the identified FPGAs during re - simulation of the component. The host system stores the signals received from the emulator. The signals traced during re - simulation may have a higher sampling rate than the sampling rate during the initial simulation. For example, during the initial simulation, the traced signals may include the saved state of the component once every X milliseconds. However, during re - simulation, the traced signals may include the saved state once every Y milliseconds, where Y is less than X. If the circuit designer requests to view the waveform of the signals traced during re - simulation, the host system may retrieve the stored signals and display a graph of the signals. For example, the host system may generate the waveform of the signals. Thereafter, the circuit designer may request to re - simulate the same component or re - simulate another component during a different time period.

[0113] The host system 1007 and / or the compiler 1010 may include subsystems such as, but not limited to, a design synthesizer subsystem, a mapping subsystem, a run - time subsystem, a results subsystem, a debug subsystem, a waveform subsystem, and a storage subsystem. The subsystems may be constructed and enabled as single or multiple modules, or more than two subsystems may be constructed as one module. These subsystems together construct the emulator and monitor the simulation results.

[0114] The design synthesizer subsystem converts the HDL representing the DUT 1005 into gate - level logic. For a DUT to be simulated, the design synthesizer subsystem receives a description of the DUT. If the description of the DUT is in HDL (e.g., RTL or other representation level) completely or partially, the design synthesizer subsystem synthesizes the HDL of the DUT to create a gate - level netlist, where the gate - level netlist has a description of the DUT in gate - level logic.

[0115] The mapping subsystem partitions the DUT and maps the partitions into the emulator FPGA. The mapping subsystem partitions the gate-level DUT into multiple partitions using the netlist of the DUT. For each partition, the mapping subsystem retrieves the gate-level description of the trace and injection logic and adds the logic to the partition. As described above, the trace and injection logic included in the partition is used to trace the signals exchanged via the interface of the FPGA to which the partition is mapped (trace interface signals). The trace and injection logic can be added to the DUT before partitioning. For example, the design synthesizer subsystem can add the trace and injection logic before or after synthesizing the HDL of the DUT.

[0116] In addition to including the trace and injection logic, the mapping subsystem can also include additional trace logic in the partition to trace the states of certain DUT components that are not traced by the trace and injection. The mapping subsystem can include the additional trace logic in the DUT before partitioning or in the partition after partitioning. The design synthesizer subsystem can include the additional trace logic in the HDL description of the DUT before synthesizing the HDL description.

[0117] The mapping subsystem maps each partition of the DUT to the FPGA of the emulator. For partitioning and mapping, the mapping subsystem uses design rules, design constraints (e.g., timing or logic constraints), and information about the emulator. For the components of the DUT, the mapping subsystem stores in the storage subsystem the information that describes which FPGA will simulate each component.

[0118] Using the partitioning and mapping, the mapping subsystem generates one or more bit files that describe the created partitions and the logical mapping to each FPGA of the emulator. The bit file can include additional information such as the constraints of the DUT and the connections between the FPGAs and the routing information of the connections within each FPGA. The mapping subsystem can generate a bit file for each partition of the DUT and can store the bit file in the storage subsystem. Once there is a request from the circuit designer, the mapping subsystem transmits the bit file to the emulator, and the emulator can use the bit file to construct the FPGA to simulate the DUT.

[0119] If the emulator includes a dedicated ASIC that includes the trace and injection logic, the mapping subsystem can generate a specific structure that connects the dedicated ASIC to the DUT. In some embodiments, the mapping subsystem can save the information of the signals being traced / injected and the information of the location where the information is stored on the dedicated ASIC.

[0120] The runtime subsystem controls the simulation executed by the emulator. The runtime subsystem can cause the emulator to start or stop executing the simulation. Additionally, the runtime subsystem can provide input signals and data to the emulator. The input signals can be provided directly to the emulator through connections or indirectly through other input signal devices. For example, the host system can control the input signal device to provide input signals to the emulator. The input signal device can be, for example, a test board (directly or through a cable), a signal generator, another emulator, or another host system.

[0121] The results subsystem processes the simulation results generated by the emulator. During and / or after the simulation, the results subsystem receives the simulation results generated during the simulation from the emulator. The simulation results include the signals traced during the simulation. In particular, the simulation results include the interface signals traced by the trace and injection logic simulated by each FPGA, and can include the signals traced by additional logic included in the DUT. Each traced signal can span multiple cycles of the simulation. The traced signals include multiple states, and each state is associated with the time of the simulation. The results subsystem stores the traced signals in the storage subsystem. For each stored signal, the results subsystem can store information indicating which FPGA generated the traced signal.

[0122] The debug subsystem allows a circuit designer to debug DUT components. After the emulator has simulated the DUT and the results subsystem has received the interface signals traced by the trace and injection logic during the simulation, the circuit designer can request to debug a component of the DUT by re-simulating the component for a specific period of time. In the request to debug the component, the circuit designer identifies the component and indicates the period of the simulation to be debugged. The circuit designer's request can include a sampling rate, which indicates the frequency at which the logic of the traced signals should save the state of the component being debugged.

[0123] The debug subsystem uses the information stored in the storage subsystem by the mapping subsystem to identify one or more FPGAs of the emulator that are simulating the component. For each identified FPGA, the debug subsystem retrieves from the storage subsystem the interface signals traced by the trace and injection logic of the FPGA during the period of time indicated by the circuit designer. For example, the debug subsystem retrieves the states traced by the trace and injection logic associated with that period of time.

[0124] The debug subsystem transmits the retrieved interface signals to the emulator. The debug subsystem instructs the debug subsystem to use the identified FPGAs, and instructs the trace and injection logic of each identified FPGA to inject its corresponding trace signals into the logic of the FPGA to re - simulate the component within the requested time period. The debug subsystem can also transmit the sampling rate provided by the circuit designer to the emulator so that the trace logic can trace the state at appropriate intervals.

[0125] To debug a component, the emulator can use the FPGA to which the component has been mapped. Additionally, re - simulation of the component can be performed at any time point specified by the circuit designer.

[0126] For the identified FPGAs, the debug subsystem can transmit instructions to the emulator to load multiple emulator FPGAs with the same configuration as the identified FPGAs. The debug subsystem additionally signals the emulator to use multiple FPGAs in parallel. Each of the multiple FPGAs is used with a different time window of the interface signals to generate a larger time window in a shorter amount of time. For example, the identified FPGA may take more than an hour to use a certain number of cycles. However, if multiple FPGAs have the same data and structure as the identified FPGA, and each of these FPGAs runs a subset of the cycles, the emulator can take a few minutes to have the FPGAs jointly use all the cycles.

[0127] The circuit designer can identify the hierarchy or list of DUT signals to be re - simulated. To enable this, the debug subsystem determines the FPGAs required to simulate the signal hierarchy or list, retrieves the necessary interface signals, and transmits the retrieved interface signals to the emulator for re - simulation. Thus, the circuit designer can identify any element (e.g., component, device, or signal) of the DUT to be debugged / re - simulated.

[0128] The waveform subsystem generates waveforms using the traced signals. If the circuit designer requests to view the waveforms of the signals traced during the simulation run, the host system retrieves the signals from the storage subsystem. The waveform subsystem displays the graphs of the signals. For one or more signals, when the signals are received from the emulator, the waveform subsystem can automatically generate the graphs of the signals.

[0129] Figure 11Illustrated is an example machine of computer system 1100 within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0130] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing, by sequencing or otherwise, a set of instructions that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0131] Example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1118, which communicate with each other via a bus 1130.

[0132] Processing device 1102 represents one or more processors (such as a microprocessor, a central processing unit, etc.). More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1102 can also be one or more special-purpose processing devices (such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc.). Processing device 1102 can be configured to execute instructions 1126 for performing the operations and steps described herein.

[0133] The computer system 1100 may also include a network interface device 1108 to communicate over a network 1120. The computer system 1100 may also include a video display unit 1110 (such as a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1112 (such as a keyboard), a cursor control device 1114 (such as a mouse), a graphics processing unit 1122, a signal generation device 1116 (such as a speaker), a graphics processing unit 1122, a video processing unit 1128, and an audio processing unit 1132.

[0134] The data storage device 1118 may include a machine-readable storage medium 1124 (also referred to as a non-transitory computer-readable medium) on which is stored a set or sets of instructions 1126 or software embodying one or more of the methods or functions described herein. The instructions 1126 may also reside, completely or at least partially, within the main memory 1104 and / or within the processing device 1102 during execution by the computer system 1100, and the main memory 1104 and the processing device 1102 also constitute machine-readable storage media.

[0135] In some embodiments, the instructions 1126 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) storing a set or sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine and the processing device 1102 to perform one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0136] Some of the foregoing detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is a series of operations that results in a desired outcome. These operations are operations that require physical manipulation of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. These signals may be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0137] However, it should be noted that all these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. Unless stated otherwise as apparent from the present disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers and memories of the computer system and transforms them into other data similarly represented as physical quantities within the memories or registers of the computer system or other such information storage devices.

[0138] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to the computer system bus.

[0139] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. Additionally, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure described herein.

[0140] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic devices) to perform the processes according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer) readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash devices, etc.

[0141] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. Obviously, various modifications can be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Where the present disclosure refers to some elements in the singular tense, more than one element may be depicted in the drawings and the same elements are labeled with the same numbers. Therefore, the present disclosure and the drawings should be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A non-transitory computer readable medium comprising stored instructions which, when executed by a processor, cause the processor to: determining a first glitch induction window GIW for a first combinatorial logic CL gate based on a range of arrival times of a first input and a second input of the first CL gate of the circuit design after a modification to the circuit design affects the first CL gate; and A determination is made based on the first GIW whether to retain the modification to the circuit design.

2. The non-transitory computer readable medium of claim 1 , wherein the stored instructions, when executed by the processor, further cause the processor to: determining a width of the first GIW based on the arrival time range of the first input; and A length of the first GIW is determined based on the arrival time range of the second input.

3. The non-transitory computer readable medium of claim 2, wherein the stored instructions, when executed by the processor, further cause the processor to: Whether to retain the modification is determined based on a position of the first GIW relative to a glitch band of the first CL gate, wherein a width of the glitch band represents an internal delay of the first CL gate.

4. The non-transitory computer readable medium of claim 3, wherein the stored instructions, when executed by the processor, further cause the processor to: determining a burr factor based on an area of ​​the first GIW within the burr zone; and A determination is made based on the glitch factor whether to retain the modification to the circuit design.

5. The non-transitory computer readable medium of claim 4, wherein the stored instructions, when executed by the processor, further cause the processor to: The burr factor is determined based on the area of ​​the first GIW within the burr zone and a total area of ​​the first GIW.

6. The non-transitory computer readable medium of claim 1 , wherein the stored instructions, when executed by the processor, further cause the processor to: prior to said modifying said circuit design, determining a second GIW for said CL gate; and Whether to retain the modification is determined based on the first GIW and the second GIW.

7. The non-transitory computer readable medium of claim 1 , wherein the stored instructions, when executed by the processor, further cause the processor to: calculating a second GIW for a second CL gate that is affected by the modification to the circuit design, wherein the second CL gate is within a fan-out cone of the first CL gate; and Whether to retain the modification to the circuit design is determined further based on the second GIW of the second CL gate.

8. The non-transitory computer readable medium of claim 1 , wherein the stored instructions, when executed by the processor, further cause the processor to: Prior to said modifying of said circuit design, determining parameters and glitch metrics of said circuit design, wherein said parameters include one or more of a timing parameter, a power consumption parameter, and an area parameter, and wherein said glitch metrics include one or more of a glitch switching associated with said first CL gate and a glitch power associated with said glitch switching; updating said parameters and said glitch indicator after said modification of said circuit design; and Whether to retain the modification to the circuit design is further determined based on the updated parameters and the updated glitch indicator.

9. A method comprising: determining a first glitch factor for a first combinatorial logic CL gate of the circuit design based on a range of arrival times at a first input and a second input of the first CL gate and an internal delay of the first CL gate; performing a first incremental modification to the circuit design, wherein the first incremental modification affects the first CL gate; updating the first glitch factor for the first CL gate after the first incremental modification; as well as A determination is made whether to retain the first incremental modification to the circuit design based on the updated first glitch factor for the first CL gate and an optimization criterion.

10. The method of claim 9, wherein determining the first glitch factor comprises: determining a first glitch induction window GIW for the first CL gate based on the arrival time range at the first input and the second input of the first CL gate; determining a glitch band of the first CL gate based on the internal delay of the first CL gate; as well as The first glitch factor is determined based on an area of ​​the first GIW located within the glitch zone.

11. The method of claim 10, wherein determining the first GIW comprises: determining a width of the first GIW based on the range of arrival times at the first input of the first CL gate; as well as A length of the first GIW is determined based on the range of arrival times at the second input of the first CL gate.

12. The method of claim 9, wherein performing the first incremental modification comprises replacing the first CL gate with a replacement CL gate, and wherein updating the first glitch factor comprises: determining a second GIW of the replacement CL gate based on a range of arrival times at the first input and the second input of the replacement CL gate; determining a glitch band of the replacement CL gate based on the internal delay of the replacement CL gate; as well as The first glitch factor is updated based on the second GIW area of ​​the replacement CL located within the glitch zone of the replacement CL.

13. The method according to claim 9, further comprising: determining parameters and glitch metrics of the circuit design before performing the first incremental modification, wherein the parameters include one or more of a timing parameter, a power consumption parameter, and an area parameter, and wherein the glitch metrics include one or more of a glitch switching associated with the first CL gate and a glitch power associated with the glitch switching; After performing the first incremental modification, updating the parameter and the glitch indicator; and Whether to retain the first incremental modification is further determined based on the updated parameters and the updated glitch indicator.

14. The method of claim 13, wherein determining the parameters and the glitch indicator of the circuit design before performing the first incremental modification comprises one or more of: simulating the operation of the circuit design; simulating the operation of the circuit design; as well as The operation of the circuit design is prototyped.

15. The method according to claim 13, further comprising: performing a second incremental modification to the circuit design, wherein the second incremental modification affects the first CL gate; updating the parameter and the glitch indicator after the second incremental modification; as well as Whether to retain the second incremental modification is determined based on the corresponding updated parameters, the updated glitch indicators, the updated glitch factors, and the optimization criteria.

16. The method according to claim 9, further comprising: determining, before the first incremental modification, a second glitch factor for the second CL gate based on a range of arrival times of the first input and the second input of the second CL gate within a fan-out cone of the first CL gate and an internal delay of the second CL gate; updating the second glitch factor for the second CL gate after the first incremental modification; as well as Whether to retain the first incremental modification to the circuit design is determined further based on the updated second glitch factor for the second CL gate.

17. A system comprising: a memory storing instructions; as well as a processor coupled to the memory and executing the instructions, wherein when the instructions are executed, the processor, determining a glitch factor for a combinational logic CL gate of a circuit based on a range of arrival times at a first input and a second input of the CL gate and an internal delay of the CL gate; updating the glitch factor for the CL gate following a modification to the circuit design that affects the CL gate; as well as A determination is made whether to retain the incremental modification to the circuit design based on the updated glitch factor and an optimization criterion for the CL gate.

18. The system of claim 17, wherein the instructions, when executed, further cause the processor to: determining a glitch induction window GIW for the CL gate based on the arrival time range at the first input and the second input of the CL gate; determining a glitch band of the CL gate based on the internal delay of the CL gate; and The glitch factor is determined based on an area of ​​the GIW located within the glitch zone.

19. The system of claim 18, wherein the instructions, when executed, further cause the processor to: determining a width of the GIW based on the range of arrival times at the first input of the CL gate; and The length of the GIW is determined based on the range of arrival times at the second input of the CL gate.

20. The system of claim 18, wherein the modification to the circuit design replaces the CL gate with a replacement CL gate, and wherein the instructions, when executed, further cause the processor to update the glitch factor by: determining a GIW of the replacement CL gate based on a range of arrival times at a first input and a second input of the replacement CL gate; determining a glitch band of the replacement CL gate based on the internal delay of the replacement CL gate; and The glitch factor is updated based on an area of ​​the GIW of the replacement CL that is within the glitch band of the replacement CL.

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