An Efficient Method and System for Simplifying Digital Logic Circuits

Abstract

The present invention discloses a method and a system for efficiently simplifying digital logic circuits. The present invention performs multiple random simulations on the same digital logic circuit, and takes the nodes with the same simulation results each time as a candidate set; performs incremental simulations on the nodes in the candidate set to obtain an equivalent class set; screens out the nodes located at a high level and with constant simulation results, and obtains the values of the primary input nodes through SAT solving; uses the values of the primary input nodes to simulate the original digital logic circuit, filters out the nodes in the equivalent class set with different simulation result values, and further obtains an optimized equivalent class set; based on the optimized equivalent class set, uses a SAT solver to test all node pairs to simplify the original digital logic circuit. The present invention reduces the number of calls to the SAT solver through innovative incremental simulation, hierarchical optimization, and hybrid verification technologies, helps improve the chip design efficiency, reduces the amount of ineffective work and the number of design iterations, and thus shortens the chip design cycle.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and particularly relates to a method and system for efficiently simplifying digital logic circuits. Background Art

[0002] With the continuous improvement of the complexity of integrated circuit design, the optimization and simplification of digital logic circuits have become one of the core challenges in the field of electronic design automation (EDA). Efficient logic simplification techniques can significantly reduce circuit power consumption, area, and delay, thus meeting the stringent requirements of modern chip design for performance and cost. In this context, graph structure representation methods based on Boolean expressions, such as the And-Inverter Graph (AIG), have been widely used in logic synthesis and equivalence verification due to their simplicity and ease of operation. AIG provides an intuitive framework for the expression and transformation of logical functions by representing logical "AND" operations with nodes and signal connections and their inversion relationships with edges.

[0003] Boolean Satisfiability (SAT) solving technology, as a core tool for logic verification, plays a key role in equivalence class identification and circuit optimization. Traditional methods verify the logical equivalence between nodes through SAT scanning technology: for a pair of nodes to be compared, an exclusive-OR logic is constructed and the SAT solver is called. If there is no input combination that makes the outputs different, the nodes are determined to be equivalent and merged. However, with the exponential growth of circuit scale, such methods face severe efficiency bottlenecks. Specifically, traditional SAT scanning needs to traverse all possible node pairs, resulting in a quadratic growth of time complexity. Especially when dealing with very large-scale integrated circuits, the consumption of computing resources is unbearable.

[0004] In addition, existing technologies attempt to pre-screen equivalence classes through random simulation to reduce the number of calls to the SAT solver. However, the effectiveness of random simulation drops sharply in deep logic nodes. The quality of simulation results is limited by the randomness of input patterns and it is difficult to cover potential differences in critical paths, resulting in a large number of false equivalence classes remaining. To make up for this defect, existing solutions have to frequently call the SAT solver for secondary verification, which instead exacerbates the overall time overhead. Especially in high-level logic nodes, traditional simulation strategies cannot effectively capture complex logical relationships, causing the optimization process to fall into redundant iterations and severely restricting the efficiency of circuit simplification.

[0005] In summary, there are two core defects in the existing digital logic circuit simplification technology: First, the SAT scanning method based on all-node pairs is computationally inefficient in large-scale circuits; second, the quality and coverage of random simulation are insufficient, making it difficult to effectively reduce the size of equivalent classes. These problems lead to a long and time-consuming logic optimization process, making it difficult to meet the requirements of modern EDA tools for efficiently processing ultra-large-scale circuits. Therefore, there is an urgent need for a new method that can significantly reduce the invocation frequency of the SAT solver and improve the effectiveness of the simulation process while ensuring the optimization accuracy, thereby breaking through the efficiency bottleneck of the existing technology. Summary of the Invention

[0006] The object of the present invention is to provide an efficient method and system for simplifying digital logic circuits in view of the deficiencies of the existing technology.

[0007] The present invention is implemented as follows. In the first aspect, the present invention provides an efficient method for simplifying digital logic circuits, and the method includes:

[0008] Perform multiple random simulations on the same digital logic circuit, and take the nodes with the same simulation results each time as a candidate set;

[0009] Perform incremental simulation on the nodes in the candidate set to obtain an equivalent class set;

[0010] Arrange all the nodes in the equivalent class set in reverse hierarchical order, screen out the nodes located at the high level and with constant simulation results, and then obtain the values of the primary input nodes through SAT solving;

[0011] Simulate the original digital logic circuit with the values of the primary input nodes, filter out the nodes in the equivalent class set with different simulation result values, and further obtain an optimized equivalent class set;

[0012] Based on the optimized equivalent class set, use the SAT solver to test all node pairs to simplify the original digital logic circuit.

[0013] Preferably, the digital logic circuit is expressed in the form of an AIG graph;

[0014] Preferably, the specific process of taking the nodes with the same simulation results each time as a candidate set is as follows:

[0015] Record the simulation result value and index of each node of the digital logic circuit. The nodes with the same simulation result value are used as an initial equivalent class, and at the same time, record the node first visited in the current initial equivalent class as the head node;

[0016] Use the index value of the head node as the common index of all nodes in the current initial equivalent class;

[0017] If the simulation result value of a node other than the head node is a constant, its index label is marked as empty, indicating that they do not belong to any equivalence class and do not participate in the processing of equivalence classes; otherwise, the index label points to the head node.

[0018] Preferably, the incremental simulation process includes a process of constructing a representative node set, a process of verifying non-head nodes in the candidate set and filtering conflicts;

[0019] The process of constructing the representative node set is specifically:

[0020] S2-1-1 Define the head node in the candidate set as , and other nodes as , ∈[1,M], M+1 represents the total number of nodes in the candidate set;

[0021] S2-1-2 Create an empty queue L for each candidate set, and initialize and load the head node to the head of the queue L, denoted as , and set the value of the head node = 0, and assign the equivalence flag bit as 0;

[0022] S2-1-3 Determine whether the current queue L is empty. If it is empty, end; if not, take out the node , ∈[1,n], n represents the total number of nodes in the queue L. According to the value of the current node , perform differential assignment on the left fan-in node and the right fan-in node of the node , and put the non-primary input nodes in the two nodes , at the end of the queue L. At the same time, store the nodes , , into the representative node set; repeat the current step S2-1-3, and update i = i + 1; where, the value of the node in the representative node set is denoted as the initial value

[0023] The process of verifying non-head nodes in the candidate set and filtering conflicts is specifically:

[0024] S2-2-1 Create an empty queue Q for the current candidate set, and initialize and load any non-head node in the candidate set, denoted as , and set the value of this node = 1;

[0025] S2-2-2 determines whether the current queue Q is empty. If it is empty, execute step S2-2-4; if it is not empty, take the current node from the queue Q. , ∈[1,N], N represents the total number of nodes in the queue Q, according to the current node The value of , for nodes Left fan-in node , right fan-in node Perform differentiated assignment;

[0026] S2-2-3 Search for the node in the representative node set 、 If there are no nodes that are completely equivalent in logical function, there is no need to judge the conflict and the two nodes can be directly 、 Put the non-main input node in the queue Q at the end and repeat the current step S2-2-2; if there is a conflict, determine whether there is a conflict. If not, put the two nodes 、 Put the non-main input node in the queue Q at the end, repeat the current step S2-2-2, if there is a conflict, update the equivalent flag position to 1 and clear the queue Q, and execute step S2-2-4;

[0027] S2-2-4, continue to judge whether the equivalent flag is assigned to 1, if so, keep it 、 , then execute step S2-2-5; otherwise, remove it from the candidate set , then execute step S2-2-5;

[0028] S2-2-5. Assign 0 to the equivalence flag position, update m=m+1, take the next non-head node from the candidate set, and set the value of the node to 1. Return to execute step S2-2-2 until all non-head nodes in the candidate set are traversed. Finally, the nodes retained in the candidate set form the equivalence class set.

[0029] More preferably, in the process of building the representative node set, Left fan-in node , right fan-in node The specific process of differentiated assignment includes:

[0030] If the node The value of = 1, then the left fan-in node , right fan-in node The value of 、 All are assigned a value of 1;

[0031] If the node Value of = 0, then use a pseudo-random number generator to select one of the fan-in nodes , or r, that is, the left fan-in node or the right fan-in node , and assign the value of the fan-in node to 0. Assign 0.

[0032] More preferably, during the process of validating non-head nodes in the candidate set and filtering conflicts, for the left fan-in node of the node , right fan-in node , the specific differential assignment is as follows:

[0033] If the value of the node is = 1, then the values of the left fan-in node , right fan-in node are , both assigned 1;

[0034] If the value of the node is = 0, then use a pseudo-random number generator to select one of the fan-in nodes , or r, that is, the left fan-in node or the right fan-in node , and assign the value of the fan-in node to 0. Assign 0.

[0035] More preferably, the conflict determination condition during the process of validating non-head nodes in the candidate set and filtering conflicts:

[0036] If the initial value is the same as the current value, it is considered not in conflict, otherwise it is in conflict.

[0037] Preferably, the process of using a SAT solver to test all node pairs based on the optimized equivalence class set includes:

[0038] For the same optimized equivalence class set, take the head node S2 and any other node S3 to establish an exclusive OR gate, perform SAT solving for each group of exclusive OR gates. If it can be solved, it proves that the nodes S2 and S3 are not equivalent. If it cannot be solved, it proves that the nodes S2 and S3 are equivalent, and optimize away the node S3;

[0039] Then transfer all the connection relationships of the optimized away nodes to the head node in the current optimized equivalence class set.

[0040] Second aspect, the present invention provides an efficient and simplified digital logic circuit system, the system comprising:

[0041] A candidate set construction module, responsible for performing multiple random simulations on the same digital logic circuit, and taking the nodes with the same simulation results each time as a candidate set;

[0042] An equivalent class set construction module, responsible for performing incremental simulations on the nodes in the candidate set to obtain an equivalent class set;

[0043] An optimized equivalent class set construction module, responsible for arranging all the nodes in the equivalent class set in reverse hierarchical order, screening out the nodes located at a high level and with constant simulation results, and then obtaining the values of the primary input nodes through SAT solving; using the values of the primary input nodes to simulate the original digital logic circuit, filtering out the nodes in the equivalent class set with different simulation result values, and further obtaining an optimized equivalent class set;

[0044] A simplification module, responsible for simplifying the original digital logic circuit based on the optimized equivalent class set by using a SAT solver to test all node pairs.

[0045] Third aspect, the present invention provides an electronic device, comprising a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, and the processor executing the machine-executable instructions to implement the method.

[0046] The beneficial effects of the present invention at least include:

[0047] By introducing an incremental simulation mechanism, the present invention gradually screens and eliminates false equivalent nodes in the candidate set generation stage, effectively narrowing the range of nodes that need to be verified by the SAT solver. It can gradually collect and analyze the node states during the simulation process, find non-equivalent nodes, so as to obtain effective simulation data, and adjust and optimize the nodes in the equivalent class according to the simulation results. The characteristic of this method lies in its gradually refined simulation process and result-based optimization strategy. The advantage is that it improves the accuracy and efficiency of optimization while reducing redundancy. In particular, reducing the size of the equivalent class through incremental simulation can reduce the number of calls to the SAT solver, providing a more efficient AIG graph for the subsequent optimization stage. This process dynamically updates the traversal queue and only performs local simulation backtracking on the conflict nodes, avoiding the redundant calculation of full-circuit repeated simulation.

[0048] In addition, the present invention also arranges nodes in reverse order according to the logical hierarchy, and preferentially processes the nodes with higher positions in the logical hierarchy (i.e., the high-level nodes closer to the output end), so as to quickly identify and optimize the nodes that have the greatest impact on the circuit function, that is, it can quickly lock the critical paths that have a significant impact on the circuit function. For these high-level nodes, if their simulation results are constants, a SAT solver is used to find a set of valid simulation result values for equivalence class splitting. This method not only improves the pertinence and efficiency of optimization, but also can reduce subsequent SAT solving calls, saving time and computing resources, thereby improving the efficiency of the entire circuit optimization process.

[0049] In summary, through the innovative incremental simulation, hierarchical optimization and hybrid verification technologies, the present invention has achieved a double breakthrough in efficiency and accuracy in the process of simplifying digital logic circuits, providing strong technical support for high-performance chip design and the development of automation tools. Brief Description of the Drawings

[0050] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0051] Figure 1 is the flowchart of the method provided by the embodiment of the present invention.

[0052] Figure 2 is the construction process of the node set in the embodiment of the present invention.

[0053] Figure 3 is the non-head node filtering process in the verification candidate set in the embodiment of the present invention.

[0054] Figure 4 is a schematic diagram of the AIG incremental simulation in the embodiment of the present invention.

[0055] Figure 5 is a schematic diagram of a method for establishing a SAT solver in the embodiment of the present invention. Detailed Embodiments

[0056] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0057] According to an embodiment of the present invention, there is provided an embodiment of an SAT scan for efficiently simplifying a logic network. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0058] See the attached Figure 1 , this embodiment provides a method for efficiently simplifying a digital logic circuit, including:

[0059] Step S1: Perform multiple random simulations on the same digital logic circuit, and take the nodes with the same simulation results each time as a candidate set;

[0060] The digital logic circuit is expressed in the form of an AIG graph; according to the logic function description in the original digital logic circuit, its logic function is simplified into "logical AND" and "logical NOT" operations, which are represented by nodes and edges in the AIG graph respectively, that is, each node represents the value of the "logical AND" function definition, and each edge represents the connection relationship between nodes. At the same time, when the edge is flipped, it represents the "logical NOT" function, so as to realize the logic function of the digital circuit; during the simulation process, the output value (logical 0 or 1) of each node is recorded as the simulation result vector. For example, if the initial simulation bit number of a node is 100 bits, the simulation result of node S can be represented as a 100-bit binary sequence.

[0061] Step S2: Perform incremental simulation on the nodes in the candidate set, filter out the false candidate nodes, and obtain an equivalent class set;

[0062] Step S3: Arrange all the nodes in the equivalent class set in reverse order by level, and select the nodes located at the high level and with constant simulation results for SAT solving to obtain the values of the main input nodes;

[0063] Step S4: Use the values of the main input nodes to simulate the original digital logic circuit, filter out the nodes in the equivalent class set with different simulation result values, and further obtain an optimized equivalent class set; based on the optimized equivalent class set, use an SAT solver to test all node pairs to simplify the original digital logic circuit.

[0064] As an example, the specific process of step S1 of taking the nodes with the same simulation results each time as a candidate set:

[0065] Record the simulation result value and index (such as hash value) for each node of the digital logic circuit. Nodes with the same simulation result value form an initial equivalence class. At the same time, record the first node visited in the current initial equivalence class as the head node, and use the index value of the head node as the common index for all nodes in the current initial equivalence class;

[0066] If the simulation result value of other nodes that are not the head node is a constant, such as logic 0 or logic 1, their index labels are marked as empty, indicating that they do not belong to any equivalence class and do not participate in the processing of equivalence classes; otherwise, the index label points to the head node.

[0067] As an example, see Appendix Figures 2-3 , the incremental simulation process described in step S2 is as follows:

[0068] S2-1. Construct a representative node set, see Appendix Figure 2

[0069] S2-1-1. Define the head node in the candidate set as , and other nodes as , ∈[1,M], where M + 1 represents the total number of nodes in the candidate set;

[0070] S2-1-2. Create an empty queue L for each candidate set, and initialize by loading the head node to the head of the queue L, denoted as , set the value of the head node = 0, and assign the equivalence flag bit as 0;

[0071] S2-1-3. Determine whether the current queue L is empty. If it is empty, end; if not, take out the node (first-in, first-out principle), ∈[1,n], where n represents the total number of nodes in the queue L. According to the value of the current node , for the left fan-in node and right fan-in node of the node , perform differential assignment, and put the non-primary input nodes among the two nodes , at the end of the queue L, and at the same time store the nodes , , into the representative node set; repeat the current step S2-1-3, and update i = i + 1; where, the value of the node in the representative node set is denoted as the initial value

[0072] The left fan-in node of the node ​ , right fan-in node The differential assignment is specifically as follows:

[0073] If the value of node = 1 (i.e., logical high level), then the values of the left fan-in node and the right fan-in node , are both assigned 1;

[0074] If the value of node = 0 (i.e., logical low level), then use a pseudo-random number generator to select one of the fan-in nodes , or r, that is, the left fan-in node or the right fan-in node , and assign the value of the fan-in node to 0; S2-2. Verify non-head nodes in the candidate set and filter conflicts, see Appendix Figure 3

[0075] S2-2-1 Create an empty queue Q for the current candidate set, initialize and load any non-head node in the candidate set, denoted as , and set the value

[0076] of this node to 1; S2-2-2 Determine whether the current queue Q is empty. If it is empty, execute step S2-2-4; if it is not empty, remove the current node from the queue Q, of the left fan-in node and the right fan-in node for differential assignment;

[0077] S2-2-3 Search for nodes in the representative node set that are logically equivalent (i.e., have the same response to all input vectors) to nodes , . If none exist, there is no need to judge conflicts, and directly put the non-primary input nodes in the two nodes , at the end of the queue Q, and repeat the current step S2-2-2; if they exist, judge whether there are conflicts. If there are no conflicts, put the two nodes , ​Put the non-primary input nodes in the queue Q at the end, repeat the current step S2-2-2. If there is a conflict, update the equivalent flag bit to 1 and empty the queue Q, then execute step S2-2-4;

[0078] The pair of nodes The left fan-in node of , the right fan-in node The specific differential assignment is as follows:

[0079] If the value of the node is = 1 (i.e., logical high level), then the values of the left fan-in node , the right fan-in node are , both assigned 1;

[0080] If the value of the node is = 0 (i.e., logical low level), then use a pseudo-random number generator to select one of the fan-in nodes , or r, that is, the left fan-in node or the right fan-in node , and assign the value of the fan-in node as 0;

[0081] Conflict determination condition:

[0082] If the initial value is the same as the current value, it is considered not in conflict; otherwise, it is in conflict. For example, if the initial value of the node is 1 and the current value is 0, then there is a conflict.

[0083] S2-2-4. Continue to determine whether the equivalent flag bit assignment is 1. If so, retain , , and then execute step S2-2-5; otherwise, remove from the candidate set, and then execute step S2-2-5;

[0084] S2-2-5. Assign the equivalent flag bit to 0, update m = m + 1, take out the next non-head node from the candidate set, and set the value of this node to 1, then return to execute step S2-2-2 until all non-head nodes in the candidate set are traversed. The nodes finally retained in the candidate set form the equivalent class set.

[0085] As an example, step S3 includes the following steps:

[0086] Arrange the optimized equivalent class nodes in reverse order by level, collect the high-level nodes close to the final output node of the circuit, then filter out the nodes with the simulation result value of all 0s (i.e., constants), call the SAT solver to solve these nodes, and then return the values of the main input nodes. Use these values to simulate the original digital logic circuit, which can make the simulation values of the high-level nodes be 1.

[0087] Node level division: Divide the nodes by logical depth. The output node is defined as the highest level, and the main input node is the lowest level.

[0088] Reverse order arrangement: Process the nodes from the high level to the low level in turn, and give priority to optimizing the critical paths that have a significant impact on the output.

[0089] As an example, the process of using the SAT solver to test all node pairs based on the optimized equivalent class set described in step S4 includes:

[0090] For the same optimized equivalent class set, take the head node S2 and any other node S3 to establish an exclusive OR gate (XORgate), perform SAT solving on each group of exclusive OR gates. If it can be solved, it proves that nodes S2 and S3 are not equivalent. If it cannot be solved, it proves that nodes S2 and S3 are equivalent, and optimize node S3;

[0091] Then all the connection relationships of the optimized-out nodes are transferred to the head node in the current optimized equivalent class set, redirected to node S2, and the circuit structure is simplified.

[0092] Figure 4 It is a schematic diagram of the AIG incremental simulation in the embodiment of the present invention, showing the value-taking situation during the downward traversal when the equivalent class nodes take opposite values. After the simulation is completed, the simulation values of the two top-level nodes are 010. Through a mapping, the two nodes are put into the same equivalent class. Then, let the next bit of one node be 0 and the other node be 1. For the node taking 1, its two input edges are not inverted, so both input nodes can only be 1. For the node taking 0, only one of the nodes corresponding to the two input edges needs to take 0 to satisfy the condition. Pass it down in the way shown in the figure. After repeated operations, if there is no such value-taking, the incremental simulation fails; otherwise, record the value-taking for subsequent simulation.

[0093] In the SAT scanning process of the present invention, the SAT solver is used to assist in the division of equivalent classes, thereby improving the quality of equivalent classes and shortening the entire optimization time.

[0094] Before establishing the SAT solver, first reverse-order the obtained node sequence, collect some high-level nodes, observe the simulation result values obtained from random simulation. If the simulation result values of these nodes are all 0, that is, the switching rate is 0, record the positions of these nodes and create a SAT solver.

[0095] Among them, the switching rate is mathematically described as follows:

[0096]

[0097] Among them is the number of switching times, and is the total number of bits.

[0098] The magnitude of the average value of the switching rate reflects to a certain extent the quality of the simulation. Among them, the mathematical description of the average switching rate is as follows:

[0099]

[0100] where N is the number of simulation gates, is the switching rate of a single gate.

[0101] Figure 5 is a schematic diagram of a method for establishing a SAT solver in an embodiment of the present invention. As Figure 5 shown, a SAT solver is only established for high-level eligible nodes. After traversing the high-level nodes, all solvers are solved. Then, according to the values obtained by the solvers, the simulation result values saved in the circuit are updated.

[0102] The input received by the SAT solver in this embodiment is a sum-of-products expression, such as (a + b)(b + c), where each element can be an input signal or its negated form. Since this embodiment is based on AIG, before using the SAT solver, it is necessary to convert the AIG-based logic into the sum-of-products form. For this purpose, a conversion tool is used. This tool can convert a multi-input single-output logic gate circuit into a sum-of-products expression for use as the input of the SAT solver. In this process, the result of the exclusive-OR logic is converted into a sum-of-products expression and input into the SAT solver to determine whether there is at least one set of input signal combinations that makes the output logic 1.

[0103] Among them, each gate will be added to the sum-of-products expression. For a two-input AND gate, its conversion rule is mathematically described as follows:

[0104]

[0105] Each parenthesis represents a clause. The SAT solver receives such clauses as input and finally outputs information on whether it is satisfiable.

[0106] To accurately detect whether two nodes in an AIG are logically equivalent, this method proposes a systematic technical process. First, for each pair of equivalent-class nodes to be compared, an exclusive-OR circuit is constructed to determine the logical difference between them. This exclusive-OR circuit is established to capture the behavioral differences between the two nodes under all possible input combinations. Subsequently, these local circuits are converted into the sum-of-products form, which represents a logic function as the sum of multiple product terms, and each product term corresponds to a specific set of input conditions.

[0107] In this method, a SAT solver is used to verify whether there exists at least one combination of input signals such that the outputs of the two nodes are different, that is, the output of the exclusive-OR circuit is 1. If the result returned by the SAT solver is no solution, it means that under all possible input combinations, the outputs of the two nodes are always the same, so they are logically equivalent.

[0108] After confirming the equivalence of the nodes, non-head nodes can be marked as deletable nodes. In the case of logical equivalence, the functions of non-head nodes can be completely replaced by the head nodes. During the construction process of the AIG, the head nodes are used to replace these marked non-head nodes, thereby optimizing the circuit structure and reducing logic gates.

[0109] This invention compares with the internationally advanced synthesis tool abc, selects the best SAT scanning method and &fraig instruction among them. The experimental circuit uses a part of the open-source test circuit benchmark. The experimental results are shown in Table 1. The &fraig instruction simplifies the network through simple random simulation and SAT solver interaction. Compared with the original &fraig instruction, the new algorithm reduces the average time used in the first five circuits by more than 14%, and the effect is more obvious in logically complex circuits.

[0110] Table 1 Time used for simplifying different circuits by different methods

[0111] (Unit: seconds)

[0112]

[0113] This embodiment also provides an efficient digital logic circuit simplification system, and the system includes:

[0114] A candidate set construction module, which is responsible for performing multiple random simulations on the same digital logic circuit and taking the nodes with the same simulation results each time as a candidate set;

[0115] An equivalent class set construction module, which is responsible for performing incremental simulations on the nodes in the candidate set to obtain an equivalent class set;

[0116] The optimized equivalence class set construction module is responsible for arranging all nodes in the equivalence class set in reverse hierarchical order, screening out the nodes located at the high level with constant simulation results, and then obtaining the values of the primary input nodes through SAT solving; using the values of the primary input nodes to simulate the original digital logic circuit, filtering out the nodes in the equivalence class set with different simulation result values, and further obtaining the optimized equivalence class set.

[0117] The simplification module is responsible for simplifying the original digital logic circuit based on the optimized equivalence class set by using a SAT solver to test all node pairs.

[0118] The present invention provides an electronic device, including a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method.

[0119] The memory configuration involved in the present invention may include fast random access memory (RAM) and non-volatile storage media, such as disk storage devices like hard disks. The system establishes a communication connection with at least one external network element through at least one communication interface (which may be wired or wireless), supporting data exchange in various network environments such as the Internet, wide area network, local area network, or metropolitan area network.

[0120] The bus can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0121] Among them, the memory is used to save the program code. When the processor receives the instructions to execute these programs, it will run the programs stored in the memory. The method flow defined in any embodiment described in the present invention can be integrated into the operation of the processor or implemented by the processor. In short, after receiving the execution command, the processor will execute the program in the memory to implement the method disclosed in the present invention.

[0122] The processor can be an integrated circuit chip with signal processing functions. When implementing the method of the present invention, each step can be realized by the hardware logic circuit inside the processor or software instructions. The processor may be a general-purpose processor, such as a central processing unit (CPU), a network processor (NP), etc., or may be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate and transistor logic devices, discrete hardware components. These processors can implement or execute various methods, steps, and logical processes disclosed in the present invention.

[0123] The general-purpose processor can be a microprocessor or any standard processor. The method steps of the present invention can be directly executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be stored in a mature storage medium such as a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), or an electrically erasable programmable memory (EEPROM). These storage media are located within the memory, from which the processor reads information and combines it with its hardware to complete the steps of the above method.

[0124] An embodiment of the present invention provides a computer program product stored in a readable storage medium, which contains a series of program codes. The instructions contained in these codes can implement the processes described in the foregoing method embodiments. The specific implementation details have been described in detail in the previous method embodiments and will not be repeated here. In short, such a computer program product enables the storage medium to be used to execute the method disclosed in the present invention.

[0125] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A method for efficiently simplifying digital logic circuits, characterized in that, The method includes: Performing multiple random simulations on the same digital logic circuit, and taking the nodes with the same simulation results each time as a candidate set; Performing incremental simulation on the nodes in the candidate set to obtain an equivalent class set; the incremental simulation process includes a process of constructing a representative node set, a process of verifying non-head nodes in the candidate set and filtering conflicts; Arranging all the nodes in the equivalent class set in reverse hierarchical order, screening out the nodes located at a high level and with constant simulation results, and then obtaining the values of the primary input nodes through SAT solving; Simulating the original digital logic circuit with the values of the primary input nodes, filtering out the nodes in the equivalent class set with different simulation result values, and further obtaining an optimized equivalent class set; Based on the optimized equivalent class set, using a SAT solver to test all node pairs to simplify the original digital logic circuit.

2. The method according to claim 1, characterized in that, The digital logic circuit is expressed in the form of an AIG graph.

3. The method according to claim 1, characterized in that, The specific process of taking the nodes with the same simulation results each time as a candidate set is as follows: Recording the simulation result values and indexes of each node of the digital logic circuit, taking the nodes with the same simulation result values as an initial equivalent class, and at the same time recording the node first visited in the current initial equivalent class as the head node; Taking the index value of the head node as the common index of all nodes in the current initial equivalent class; If the simulation result value of other non-head nodes is a constant, their index labels are marked as empty, indicating that they do not belong to any equivalent class and do not participate in the processing of the equivalent class; otherwise, the index label points to the head node.

4. The method according to claim 1, wherein The specific process of constructing the representative node set is: S2-1-1. Define the head node in the candidate set as , and define other nodes as , ∈ [1, M], where M + 1 represents the total number of nodes in the candidate set; S2-1-2. Create an empty queue L for each candidate set and initialize the loading head node to the head of the queue L, denoted as , set the value of the head node = 0, and assign the equivalence flag bit to 0; S2-1-3. Determine whether the current queue L is empty. If it is empty, end; if not, remove a node from the queue L , ∈[1, n], where n represents the total number of nodes in the queue L. According to the value of the current node take value , for the node left fan-in node , right fan-in node perform differential assignment, and put the non-primary input nodes in the two nodes , at the end of the queue L. At the same time, store the nodes , , into the representative node set; repeat the current step S2-1-3, and update i = i + 1; where the value of the nodes in the representative node set is recorded as the initial value; The specific process of verifying non-head nodes in the candidate set and filtering conflicts is: S2-2-1. Create an empty queue Q for the current candidate set, and initialize by loading any non-head node in the candidate set , denoted as , and set the value of this node = 1; S2-2-2. Determine whether the current queue Q is empty. If it is empty, execute step S2-2-4; if not, remove the current node from the queue Q , ∈[1, N], where N represents the total number of nodes in the queue Q. According to the value of the current node , , perform differential assignment on the left fan-in node and the right fan-in node of the node . S2-2-3. Search for nodes in the representative node set that are logically equivalent to node . . If no such nodes exist, there is no need to judge for conflicts. Directly put the non-primary input nodes in the two nodes . at the end of the queue Q, and repeat step S2-2-2. If such nodes exist, judge whether there are conflicts. If there are no conflicts, put the non-primary input nodes in the two nodes . at the end of the queue Q, and repeat step S2-2-2. If there are conflicts, update the equivalent flag to 1 and clear the queue Q, and execute step S2-2-4. S2-2-4. Continue to judge whether the equivalent flag bit assignment is 1. If it is, retain it. , , and then execute step S2-2-5; otherwise, remove it from the candidate set. , and then execute step S2-2-5; S2-2-5. Assign the equivalent flag bit value 0, update m = m + 1, take the next non-head node from the candidate set, set the value of this node to 1, and return to execute step S2-2-2 until all non-head nodes in the candidate set are traversed. Finally, the nodes remaining in the candidate set form an equivalent class set.

5. The method according to claim 4, wherein During the process of constructing the representative node set for a node 's left fan-in node , right fan-in node The specific process of differential assignment includes: If the node takes a value = 1, then the values of the left fan-in node and the right fan-in node , are both assigned the value 1; If the node takes a value = 0, then one of the fan-in nodes , or r, i.e., the left fan-in node or the right fan-in node is selected using a pseudo-random number generator, and the value of the fan-in node is assigned 0.

6. The method according to claim 4, wherein During the process of validating non-head nodes in the candidate set and filtering conflicts, for the node 's left fan-in node , right fan-in node , the differential assignment is specifically as follows: If the value of the node is = 1, then the values of the left fan-in node , the right fan-in node are , both assigned 1; If the node takes a value = 0, then one of the fan-in nodes , or r, i.e., the left fan-in node or the right fan-in node is selected using a pseudo-random number generator, and the value of the fan-in node is assigned 0.

7. The method according to claim 4, wherein The conflict determination condition in the process of verifying non-head nodes in the candidate set and filtering conflicts is: If the initial value is the same as the current value, it is considered non-conflicting; otherwise, it is conflicting.

8. The method according to claim 1, wherein The process of using a SAT solver to test all node pairs based on the optimized equivalent class set includes: For the same optimized equivalent class set, take the head node S2 and any other node S3 to establish an exclusive OR gate, perform SAT solving on each group of exclusive OR gates. If it can be solved, it proves that the nodes S2 and S3 are not equivalent. If it cannot be solved, it proves that the nodes S2 and S3 are equivalent, and optimize the node S3; Then all the connection relationships of the optimized node are transferred to the head node in the current optimized equivalent class set.

9. An efficient simplified digital logic circuit system based on the method according to any one of claims 1-8, characterized in that, The system includes: A candidate set construction module, responsible for performing multiple random simulations on the same digital logic circuit, and taking the nodes with the same simulation results each time as a candidate set; An equivalent class set construction module, responsible for performing incremental simulation on the nodes in the candidate set to obtain an equivalent class set; The optimized equivalence class set construction module is responsible for arranging all nodes in the equivalence class set in reverse order by level, screening out the nodes located at the high level with constant simulation results, and then obtaining the values of the primary input nodes through SAT solving; using the values of the primary input nodes to simulate the original digital logic circuit, filtering out the nodes in the equivalence class set with different simulation result values, and further obtaining the optimized equivalence class set. The simplification module is responsible for simplifying the original digital logic circuit by using a SAT solver to test all node pairs based on the optimized equivalence class set.

10. An electronic device, characterized in that, It includes a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method according to any one of claims 1-8.

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