Chip verification method, chip test method and cross-language simulation system

Abstract

The invention relates to a chip verification method, a chip test method and a cross-language simulation system, which are applied to the cross-language simulation system, the cross-language simulation system comprises a first processing end and a second processing end, and the second processing end executes a test case of a chip based on a first description language. And the first processing end generates a test result of the test case based on the second description language. The chip verification method is applied to a first processing end, and comprises the following steps: acquiring an actual level signal output by a second processing end according to a simulation state of a test case of a chip; acquiring a preset level signal corresponding to the simulation state; and when it is detected that the actual level signal is consistent with the preset level signal, obtaining a test result of the test case according to the simulation state corresponding to the actual level signal. By adopting the method, the problems of low chip verification efficiency and poor verification comprehensiveness can be solved.

Description

Technical Field

[0001] This application relates to the field of chip verification, and in particular, to a chip verification method, a chip testing method, and a cross-language simulation system. Background Art

[0002] UVM (Universal Verification Methodology) verification and C code verification are two relatively isolated methods. UVM verification is widely used in the verification of various IPs and SoCs (System on Chip) due to its standardized and highly portable characteristics. However, in the chip development work involving CPUs (Central Processing Units), C code is used as the relatively mainstream verification method. Among them, the program execution of the CPU depends on the loaded hex file and can enter the WFI (Wait for Interrupt) state after running. However, the operation of the CPU program lacks an overall test end mechanism, and there is a problem of difficulty in implementing the end mechanism. The UVM environment can call C code functions in the way of DPI-C (Direct Programming Interface–C). However, as the main controller, the C code of the CPU lacks a corresponding mechanism to control the UVM side. Moreover, adding additional verification judgment code to the C code has very limited judgment methods, which is not conducive to the overall verification development work, greatly increases the complexity of the C code, and seriously reduces the efficiency and comprehensiveness of chip verification work.

[0003] In view of the problem of low chip verification efficiency and poor verification comprehensiveness in the related art, no effective solution has been proposed yet. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a chip verification method, a chip testing method, and a cross-language simulation system that can solve the problems of low chip verification efficiency and poor verification comprehensiveness.

[0005] In a first aspect, a chip verification method is provided in this embodiment, which is applied to a first processing end of a cross-language simulation system. The cross-language simulation system further includes a second processing end. Among them, the second processing end executes test cases of the chip based on a first description language, and the first processing end generates test results of the test cases based on a second description language. The method includes:

[0006] Obtain an actual level signal output by the second processing end according to the simulation state of the test case of the chip;

[0007] Obtain a preset level signal corresponding to the simulation state;

[0008] When it is detected that the actual level signal is consistent with the preset level signal, obtain the test result of the test case according to the simulation state corresponding to the actual level signal.

[0009] In some embodiments, the obtaining the test result of the test case according to the simulation state corresponding to the actual level signal includes:

[0010] Judge whether the simulation of the test case is ended according to the simulation state.

[0011] In some embodiments, the obtaining the test result of the test case according to the simulation state corresponding to the actual level signal includes:

[0012] Generate log information of the test case according to the actual level signal;

[0013] Obtain the test result according to the log information.

[0014] In some embodiments, the obtaining the actual level signal output by the second processing end according to the simulation state of the test case of the chip includes:

[0015] When the second processing end writes the actual level signal to the address bus connected to the interaction interface according to the simulation state of the test case, obtain the actual level signal from the interaction interface.

[0016] In some embodiments, the obtaining the actual level signal from the interaction interface includes:

[0017] Obtain the actual level signal from an interface group including a plurality of the interaction interfaces; wherein, each of the interface groups is respectively used to receive the actual level signal output by the second processing end according to the simulation state during the execution of different test cases.

[0018] In a second aspect, in this embodiment, a chip testing method is provided, which is applied to the second processing end of a cross-language simulation system. The cross-language simulation system further includes a first processing end. Wherein, the second processing end executes the test case of the chip based on a first description language, and the first processing end generates the test result of the test case based on a second description language. The method includes:

[0019] Obtain the simulation state of the test case;

[0020] Generate and send an actual level signal to the first processing end according to the simulation state, so that the first processing end obtains the actual level signal, and when the actual level signal is consistent with the preset level signal corresponding to the simulation state, obtain the test result of the test case according to the simulation state corresponding to the actual level signal.

[0021] In some embodiments, before sending the actual level signal to the first processing end, the chip testing method includes:

[0022] Obtain a target write value corresponding to the simulation state according to the association relationship between the simulation state and the preset write value;

[0023] Generate the actual level signal according to the target write value.

[0024] In some embodiments, the generating and sending the actual level signal to the first processing end according to the simulation state includes:

[0025] Write the actual level signal to the address bus connected to the interaction interface, so that the first processing end obtains the actual level signal from the interaction interface.

[0026] In a third aspect, in this embodiment, a cross-language simulation system is provided. The cross-language simulation system includes a second processing end and a first processing end; wherein,

[0027] The second processing end executes the test case of the chip based on the first description language, obtains the simulation state of the test case, and outputs an actual level signal to the first processing end according to the simulation state;

[0028] The first processing end obtains the actual level signal output by the second processing end based on the second description language; obtains the preset level signal corresponding to the simulation state; and when it is detected that the actual level signal is consistent with the preset level signal, obtains the test result of the test case according to the simulation state corresponding to the actual level signal.

[0029] In some embodiments, the first description language is C language and the second description language is SV language.

[0030] In the above chip verification method, chip testing method, and cross-language simulation system, the first processing end obtains the current simulation state of the test case for chip verification by acquiring the actual level signal output by the second processing end; enabling the first processing end to obtain the test result of the test case in a timely manner according to the test case state corresponding to the actual level signal, improving the chip verification efficiency; and also making it possible for the first processing end to obtain multiple test case states, avoiding the problem of poor operability of the first processing end for simulation execution, and improving the comprehensiveness of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is an application environment diagram of the hardware structure block diagram of the chip verification method in an embodiment of the present application;

[0032] Figure 2 It is a flowchart of the chip verification method in an embodiment of the present application;

[0033] Figure 3 It is a flowchart of the chip simulation method in an embodiment of the present application;

[0034] Figure 4 It is a structure block diagram of the cross-language simulation system in an embodiment of the present application;

[0035] Figure 5 It is an execution diagram of the cross-language simulation system in an embodiment of the present application;

[0036] Figure 6 It is an internal structure diagram of a computer device in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meanings understood by those with ordinary skills in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these", etc. do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "containing", "having" and any variants thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device containing a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The words such as "connected", "linked", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly connected or indirectly connected. The "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0039] The cross-language simulation system in the following embodiments of this application includes a first processing end and a second processing end. The second processing end executes the test cases of the chip based on the first description language, and the first processing end generates the test results of the test cases based on the second description language. Among them, the chip may include one or more CPUs; the test cases are used to verify the chip. When verifying and judging the test cases based on the hardware description language to obtain the verification result, the code complexity is relatively low. Optionally, the first description language can be set as the software description language; the second description language is set as the hardware description language to improve the efficiency of chip verification and development work. It can be understood that the first description language and the second description language can also be set according to application requirements, and no limitation is made here.

[0040] In this embodiment, the first processing end can be executed based on a terminal, a computer or a similar computing device. For example, it runs on the terminal. Figure 1 It is the hardware structure block diagram of the chip verification method executed by the second processing end in an embodiment of this application. As Figure 1 shown, the terminal may include one or more ( Figure 1Only one processor 102 and a memory 104 for storing data are shown. Among them, the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 The structure shown is only illustrative and does not limit the structure of the above terminal. For example, the terminal may further include more or fewer components than Figure 1 shown therein, or have a different configuration from Figure 1 shown.

[0041] The memory 104 can be used to store computer programs. For example, software programs and modules of application software, such as the computer program corresponding to the chip verification method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely set relative to the processor 102, and these remote memories can be connected to the terminal through a network. Examples of the above network include, but are not limited to, the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0042] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by the communication provider of the terminal. In one instance, the transmission device 106 includes a network adapter (abbreviated as NIC), which can be connected to other network devices through a base station and thus communicate with the Internet. In one instance, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0043] In one embodiment, Figure 2 A chip verification method is provided, which is applied to the first processing end of a cross-language simulation system. In this embodiment, it is exemplified that the first processing end is deployed on a terminal. It can be understood that the first processing end can also be deployed on a server, or deployed in a system including a terminal and a server, and implemented through the interaction between the terminal and the server. In this embodiment, as Figure 2 shown, the chip verification method includes the following steps:

[0044] Step S202, obtaining an actual level signal output by the second processing end according to the simulation state of the test case of the chip.

[0045] Among them, the simulation status is used to indicate the execution stage and status of the test case. The simulation status includes, but is not limited to, the test case not starting simulation, the test case being in simulation preparation, the test case simulation being completed, the test case simulation being paused, the test case simulation failing, etc. The actual level signals output by the second processing end include, but are not limited to, signals such as clock signals, reset signals, write signals, selection signals, enable signals, etc. Different simulation statuses correspond to different actual level signals. Optionally, the second processing end predefines the level signals corresponding to different simulation statuses of the test case. The second processing end monitors the simulation status of the test case currently being simulated and outputs the corresponding actual level signal to the first processing end according to the monitored simulation status of the test case.

[0046] Optionally, the first processing end and the second processing end implement the transmission of the actual level signal in the form of an interaction interface: the second processing end writes the actual level signal to the interaction address; the first processing end accesses the interaction address through the address bus in the interaction interface and obtains the simulation status of the test case monitored by the second processing end in real time by obtaining one or more actual level signals output by the interaction interface.

[0047] Step S204, obtain the preset level signal corresponding to the simulation status.

[0048] Among them, different simulation statuses correspond to different preset level signals; the preset level signals under the same simulation status correspond to the actual level signals. Optionally, the first processing end predefines the preset level signals corresponding to each of the multiple simulation statuses of the test case. Optionally, the preset level signal is the write signal among the actual level signals.

[0049] Step S206, when it is detected that the actual level signal is consistent with the preset level signal, obtain the test result of the test case according to the simulation status corresponding to the actual level signal.

[0050] Among them, the test result of the test case includes the end determination based on the simulation of the test case; the test result can also include further analysis and processing of the simulation status corresponding to the actual level signal. Optionally, when there are multiple preset level signals, if the actual level signal is consistent with any one of the preset level signals, the first processing end generates the test result of the test case.

[0051] Optionally, before obtaining the actual level signal output by the second processing end according to the simulation status of the test case of the chip, the first processing end configures the environment and initializes the variable parameters. After ensuring that all necessary settings and initialization operations are completed, the first processing end pauses working, and takes the event that the detected actual level signal is consistent with the preset level signal as the trigger event. When the event that the actual level signal is consistent with the preset level signal is triggered, the operation of obtaining the test result of the test case according to the signal is executed.

[0052] In the above chip verification method, the first processing end obtains the simulation status of the test case monitored by the second processing end by obtaining the actual level signal, and obtains the test result of the test case according to the simulation status. Without the need for the test case simulation end to determine the test case, the chip verification efficiency can be improved; the problem of poor operability in the program simulation of the second processing end is avoided, making it possible for the first processing end to obtain the states of multiple test cases and improving the comprehensiveness of chip verification; the problems of low chip verification efficiency and poor verification comprehensiveness are solved.

[0053] In one embodiment, obtaining the actual level signal output by the second processing end according to the simulation status of the test case of the chip includes: when the second processing end writes the actual level signal to the address bus connected to the interaction interface according to the simulation status of the test case, obtaining the actual level signal from the interaction interface.

[0054] Among them, one or more interaction interfaces can be set, and the first processing end receives the actual level signal output by the second processing end through each interaction interface. Multiple interaction interfaces can respectively receive the actual level signals corresponding to different test case simulation statuses. Multiple interaction interfaces can also respectively receive the actual level signals corresponding to the simulation status of the same test case. Optionally, based on the interaction interface being used to detect the interaction address corresponding to the address bus, when the second processing end writes the level signal to the interaction address, communication between the second processing end and the first processing end is realized. In this embodiment, by introducing the interface to obtain the actual level signal, the implementation method is simple and stable.

[0055] Further, obtaining the actual level signal from the interaction interface includes: obtaining the actual level signal from an interface group including multiple interaction interfaces; wherein each interface group is respectively used to receive the actual level signal output by the second processing end according to the simulation status during the execution of different test cases.

[0056] Optionally, multiple interaction interfaces included in the interface group respectively receive the following signals: a clock signal, a reset signal, a write enable signal, a selection signal, and an enable signal. Among them, a set of levels output by the interface group within a specified time can be obtained based on the clock signal. Exemplarily, when the CPU is cm7 (Cortex-M7 processor), the second processing end writes a signal value to the interaction address corresponding to the uart module according to the simulation state when the CPU executes the test case; when the CPU is cm4 (Cortex-M4 processor), the second processing end writes a signal value to the interaction address corresponding to the timer module according to the simulation state when the CPU executes the test case. The first processing end monitors the written values in the interaction address corresponding to the uart module and the interaction address corresponding to the timer module, and respectively introduces the apb interface signals of uart and timer.

[0057] Among them, the interface group corresponding to uart and the received signals are as follows: Uart_apb_clk = `UART_PATH.pclk; Uart_apb_rstn = `UART_PATH.presetn; Uart_apb_write = `UART_PATH.pwrite; Uart_apb_sel = `UART_PATH.psel; Uart_apb_enable = `UART_PATH.penable. The interface group corresponding to timer and the received signals are as follows: Timer_apb_clk = `TIMER_PATH.pclk; imer_apb_rstn = `TIMER_PATH.presetn; timer_apb_write = `TIMER.pwrite; timer_apb_sel = `TIMER.psel; Timer_apb_enable = `TIMER.penable. Among them, the left side of the equation is the name of the interaction interface, and the right side of the equation is the received signal. Among the above interfaces, clk is the clock signal for synchronizing circuit operations; rstn is the reset signal for initializing the circuit state of the first processing end; write is the write enable signal for indicating whether the current is a write operation; sel is the selection signal for selecting different data paths; enable is the enable signal for enabling or disabling the uart and timer modules. Through the above interface group, the written value of the interaction address can be determined in combination with control signals such as enable and reset.

[0058] In this embodiment, the simulation states of multiple test cases corresponding to different addresses are obtained in units of interface groups, realizing the determination and processing of multiple test cases and improving the test coverage.

[0059] In one embodiment, obtaining the test result of a test case based on a signal includes: obtaining the test result of a test case based on the simulation state corresponding to the actual level signal, including: determining whether the simulation of the test case has ended according to the simulation state.

[0060] Optionally, when it is determined that the simulation of the test case fails according to the simulation state corresponding to the actual level signal, end the simulation and generate a first test result; when it is determined that the simulation of the test case does not fail according to the simulation state corresponding to the actual level signal, obtain the second test result of the test case based on the signal.

[0061] Wherein, obtain a first preset level signal corresponding to the situation where the simulation of the test case fails, and obtain a second preset level signal corresponding to the situation where the simulation of the test case does not fail. When the actual level signal is the first preset level signal, end the simulation of the test case and obtain the test result of the test case based on the signal. For example, the simulation can be ended by performing a cleanup operation; generate an error message based on the actual level signal to help the user quickly locate the source or location of the problem. When the actual level signal is the second preset level signal, the simulation state of the test case includes that the simulation of the test case passes, the simulation of the test case pauses, the simulation of the test case ends, etc., and the step of obtaining the test result of the test case based on the signal can be directly executed.

[0062] Exemplarily, taking the simulation of a test case related to the uart module as an example, the second processing module determines the simulation state of the CPU based on the following code:

[0063] Always(posedge uart_apb_clk or negedge uart_apb_rstn)begin

[0064] If(!Uart_apb_rstn)begin

[0065] Uart_data<=uart_apb_wdata;

[0066] End

[0067] Else if(uart_apb_sel&uart_apb_write&uart_apb_enable)begin

[0068] Uart_data<=uart_apb_wdata;

[0069] If(uart_data==ZXC_PASS||uart_data==ZXC_FALL||uart_data==

[0070] ZXC_FINISHED) begin

[0071] If (uart_data == ZXC_FAIL) begin `uvm_fatal() end -> case_finish;

[0072] end

[0073] end

[0074] end

[0075] End

[0076] Among them, the preset simulation states include ZXC_PASS, ZXC_FALL, ZXC_FINISHED, and the actual level signals include: uart_apb_clk, uart_apb_rstn, uart_apb_sel, uart_apb_write, uart_apb_enable, uart_data. Based on the above code, when it is detected that uart_data is consistent with any one of the preset level signals, it is further determined whether uart_data conforms to ZXC_FAIL. If uart_data conforms to ZXC_FAIL, it is determined that the test case simulation fails, and a first test result is generated based on the function uvm_fatal to provide an error report to the user, and the simulation is indicated to end through the function case_finish.

[0077] Furthermore, the above code can be added to the running program as a waiting event. Taking the UVM framework as an example of the first processing end framework, the waiting event will be added to the run_phase or main_pahse of uvm_base_test to trigger the waiting event. If the waiting event is added to the run_phase, the implementation code is as follows:

[0078] Task run_pahse(uvm_pahse pahse);

[0079] Phase.raise_objection(this);

[0080] #delay;

[0081] @case_finish;

[0082] Phase.drop_objection(this);

[0083] endtask

[0084] In this embodiment, the first processing end determines and processes the simulation results, reducing the burden on the second processing end and improving the chip verification efficiency at the same time.

[0085] In one embodiment, the test result of the test case is obtained according to the simulation state corresponding to the actual level signal, including: generating the log information of the test case according to the actual level signal; obtaining the test result according to the log information.

[0086] Among them, the log information includes but is not limited to information such as the actual level signal, the signal acquisition time, and the execution status of the test case. The log information can be analyzed by writing a script to generate a report including the test result. Optionally, a log tool or macro is built into the first processing end, and the log information is obtained by recording through the log tool or macro. Optionally, the corresponding log file is printed according to the signal value of the actual level signal to obtain the log information.

[0087] In this embodiment, according to the event that the actual level signal is consistent with the preset level signal, the step of triggering the generation of the log information corresponding to the test case is performed, and the simulation process is helped to be tracked through the log information.

[0088] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above-mentioned embodiments of the chip verification method are implemented.

[0089] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned embodiments of the chip verification method are implemented.

[0090] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned embodiments of the chip verification method are implemented.

[0091] In one embodiment, as Figure 3 shown, a flowchart of a chip testing method is provided. The chip testing method is applied to the second processing end of a cross-language simulation system. In this embodiment, an example is given with the second processing end deployed on a terminal. It can be understood that the second processing end can be deployed inside the terminal, or on a server, or in a system including a terminal and a server, and is realized through the interaction between the terminal and the server. In this embodiment, as Figure 3 shown, the chip testing method includes the following steps:

[0092] Step S302, obtaining the simulation state of the test case.

[0093] Among them, multiple different test cases can be executed, and the second processing end obtains the simulation states of multiple different test cases through monitoring. Optionally, the chip is provided with a CPU. The second processing end can obtain the simulation states of one or more CPUs executing test cases.

[0094] Step S304, generate and send an actual level signal to the first processing end according to the simulation state, so that the first processing end obtains the actual level signal, and when the actual level signal is consistent with the preset level signal corresponding to the simulation state, obtain the test result of the test case according to the simulation state corresponding to the actual level signal.

[0095] Among them, different simulation states correspond to different actual level signals. Optionally, if the chip modules tested by the test cases are different, the interaction addresses corresponding to the output of the actual level signals are also different. The second processing end monitors the simulation state of the test case; determines the interaction address according to the module tested by the test case; writes the actual level signal into the interaction address.

[0096] In this embodiment, by sending the actual level signal corresponding to the simulation state of the test case to the first processing end, enabling the first processing end to obtain the simulation state of the test case can improve the chip verification efficiency; and it avoids the problem of poor operability of the second processing end, improving the comprehensiveness of chip verification.

[0097] In one embodiment, before sending the actual level signal to the first processing end, the chip testing method includes: obtaining a target write value corresponding to the simulation state according to the association relationship between the simulation state and the preset write value; generating an actual level signal according to the target write value.

[0098] Among them, different simulation states correspond to different preset write values. Optionally, define a first relationship between the simulation state and the write value; map the simulation state based on the first relationship to obtain a target write value corresponding to the simulation state; convert the target write value into a signal to obtain an actual level signal.

[0099] In this embodiment, by obtaining the association relationship between the simulation state and the preset write value, the first processing end can send the monitored simulation state to the second processing end based on simple logic.

[0100] In one embodiment, generating and sending an actual level signal to the first processing end according to the simulation state includes: writing the actual level signal into the address bus connected to the interaction interface, so that the first processing end obtains the actual level signal from the interaction interface.

[0101] Among them, if the CPUs for executing test cases are different, the addresses corresponding to the actual level signals written are different. The second processing end can define the signal values corresponding to different simulation states, define multiple interaction addresses corresponding to different CPUs, and optionally define the second relationship between the CPU for executing test cases and the interaction addresses. Based on the second relationship, map the CPU for executing test cases to obtain the interaction address corresponding to the actual level signal, and write the actual level signal to the address bus corresponding to the interaction address.

[0102] Exemplarily, the second processing end specifies the signal values and interaction addresses corresponding to different simulation states through macro definitions. For example, the simulation states include: ZXC_PASS (simulation passed), ZXC_FAIL (simulation failed), ZXC_FINISHED (simulation failed), ZXC_START (simulation started); define the signal values for the above simulation states as: 0x04, 0x08, 0x0c, 0x10 respectively. The execution code is as follows:

[0103] #define ZXC_PASS 0x04

[0104] #define ZXC_FAIL 0x08

[0105] #define ZXC_FINISHED 0x0c

[0106] #define ZXC_START 0x10

[0107] Optionally, specify the interaction addresses corresponding to the modules verified by different test cases through macro definitions. For example, the modules include UART and TIMER. The execution code is as follows:

[0108] #define UART_SPECIFIED_ADDR 0x00001000

[0109] #define TIMER_SPECIFIED_ADDR 0x00001000

[0110] Furthermore, when writing the signal values corresponding to the simulation states to the interaction addresses, specify the printing addresses according to different macros. Taking uart and time as examples: when the cpu is cm7, write the signal values related to the simulation state to the interaction address corresponding to the uart module; when the cpu is cm4, write the signal values related to the simulation state to the interaction address corresponding to the timer. The function definition for writing the signal values corresponding to the simulation states is as follows:

[0111] Void sim_pass(){

[0112] #ifdef CPU_CM7

[0113] *(volatile int*)UART_SPECIFIED_ADDR = ZXC_PASS

[0114] #elif CPU_M4

[0115] *(volatile int*)TIMER_SPECIFIED_ADDR = ZXC_PASS

[0116] }

[0117] Void sim_fail(){

[0118] #ifdef CPU_CM7

[0119] *(volatile int*)UART_SPECIFIED_ADDR = ZXC_FAIL

[0120] #elif CPU_M4

[0121] *(volatile int*)TIMER_SPECIFIED_ADDR = ZXC_FAIL

[0122] }

[0123] Void sim_finish(){

[0124] #ifdef CPU_CM7

[0125] *(volatile int*)UART_SPECIFIED_ADDR = ZXC_FINISHED

[0126] #elif CPU_M4

[0127] *(volatile int*)TIMER_SPECIFIED_ADDR = ZXC_FINISHED

[0128] }

[0129] In this embodiment, by obtaining the first relationship and the second relationship, the signal values and interaction addresses corresponding to different simulation states and simulation modules are distinguished, so that the first processing end can distinguish the execution results of different test cases through the actual level signals.

[0130] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above-mentioned embodiments of the chip test method are implemented.

[0131] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned embodiments of the chip testing methods are implemented.

[0132] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps in the above-mentioned embodiments of the chip testing methods are implemented.

[0133] Based on the same inventive concept, an embodiment of the present application further provides a cross-language simulation system for implementing the above-mentioned chip verification method and chip simulation method. The solution provided by the device for solving the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the cross-language simulation system provided below can refer to the limitations on the chip verification method and chip simulation method in the above text, and will not be repeated here.

[0134] In one embodiment, as Figure 4 shown, a cross-language simulation system is provided. The cross-language simulation system includes a second processing end and a first processing end; wherein, the second processing end executes a test case of a chip based on a first description language, obtains the simulation state of the test case, and outputs an actual level signal to the first processing end according to the simulation state; the first processing end obtains the actual level signal output by the second processing end based on a second description language; obtains a preset level signal corresponding to the simulation state; and when it is detected that the actual level signal is consistent with the preset level signal, obtains the test result of the test case according to the simulation state corresponding to the actual level signal.

[0135] In some of these embodiments, the first processing end obtains the test result of the test case according to the simulation state corresponding to the actual level signal, including: judging whether the simulation of the test case is ended according to the simulation state.

[0136] In some of these embodiments, the first processing end obtains the test result of the test case according to the simulation state corresponding to the actual level signal, including: generating log information of the test case according to the actual level signal; and obtaining the test result according to the log information.

[0137] In some of these embodiments, the first processing end obtains the actual level signal output by the second processing end according to the simulation state of the test case of the chip, including: when the second processing end writes the actual level signal to the address bus connected to the interaction interface according to the simulation state of the test case, obtaining the actual level signal from the interaction interface. Optionally, obtaining the actual level signal from the interaction interface includes: obtaining the actual level signal from an interface group including a plurality of interaction interfaces; wherein each interface group is respectively used to receive the actual level signal output by the second processing end according to the simulation state when different test cases are executed.

[0138] In some of these embodiments, before the second processing end sends the actual level signal to the first processing end, the chip testing method includes: obtaining the target write value corresponding to the simulation state according to the correlation between the simulation state and the preset write value; generating the actual level signal according to the target write value. Optionally, the second processing end generates and sends the actual level signal to the first processing end according to the simulation state, including: writing the actual level signal to the address bus connected to the interaction interface, so that the first processing end obtains the actual level signal from the interaction interface.

[0139] In one embodiment, the first description language is C language and the second description language is SV language. Among them, SystemVerilog (SV language) can be used to verify the design of complex digital circuits. Using C code for CPU chip development is the mainstream verification method. Setting the first description language as C language can improve the practicability of the cross-language simulation system.

[0140] In one embodiment, Figure 5 A schematic diagram of the execution of a cross-language simulation system is provided, as Figure 5 shown. The cside is the second processing end of the cross-language simulation system, and the sv side is the first processing end of the cross-language simulation system. The sv side is constructed based on the UVM framework.

[0141] For the c side, the four simulation states of "case pass" (the test case simulation passes), "case fail" (the test case simulation fails), "case quit" (the test case simulation pauses), and "case start" (the test case simulation starts) are respectively agreed as different fixed write values, and the interaction address for the interaction between the c side and the sv side is specified, that is Figure 5The fixed address in it. Among them, according to the actual needs during chip verification, multiple interaction addresses can be set according to different CPUs for simulation. Optionally, for the c side, monitor the simulation state of the CPU and write the corresponding write values of "case pass", "case fail", "case quit", and "case start" to the fixed address according to the simulation state. It can be understood that the types of simulation states can be increased according to requirements to achieve the effect of diversified functions in the cross-language simulation system environment.

[0142] In the UVM framework, sv side creates and initializes the following multiple phases: build_phase; connect_phase; end_of_elaboration_phase; start_of_simulation_phase. Subsequently, wait for the trigger event in the run_phase or main_phase. Among them, sv side continuously monitors the write value of the fixed address by obtaining the signals of the interaction interface, and the trigger event is that the value of the monitored actual level signal corresponds to one of the simulation states of "case pass", "case fail", "case quit", and "case start". After the trigger is triggered, print the corresponding log according to the value of the actual level signal to obtain the log information. Exemplarily, it can be determined whether the test case passes according to the printed log information.

[0143] After the trigger is triggered, sv side can continue to run the subsequent program normally. As Figure 5 shown, the subsequent program includes extract_phase (data collection and summary), check_phase (test result check), final_phase (resource release), and report_phase (generate a report containing the test results). According to application needs, additional operations can also be added to the subsequent program, such as check orphan items and report results. Further, additional operations can be performed in the phase cycle corresponding to post_main_phase or final_phase to expand the subsequent processing function of sv side for test cases.

[0144] In this embodiment, the cross-language simulation system transfers the result determination and processing of the test case to sv side through the trigger method, which can make full use of the superiority of UVM and improve the scalability and test efficiency of the test case.

[0145] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0146] Each module in the above cross-language simulation system can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0147] In one embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 6 shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, and a display unit. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used for the processor to exchange information with external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it is used to implement a chip verification method or a chip simulation method. The display unit of the computer device is used to form a visually visible picture, which can be a display screen or a projection device. The display screen can be a liquid crystal display screen or an electronic ink display screen.

[0148] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0149] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0150] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A chip verification method, characterized in that: A method for applying to a first processing end of a cross-language simulation system, wherein the cross-language simulation system further comprises a second processing end, wherein the second processing end executes a test case of a chip based on a first description language, and the first processing end generates a test result of the test case based on a second description language, wherein the method comprises: Acquire an actual level signal output by the second processing end according to a simulation state of a test case of the chip; Acquire a preset level signal corresponding to the simulation state; When it is detected that the actual level signal is consistent with the preset level signal, the test result of the test case is obtained according to the simulation state corresponding to the actual level signal.

2. The chip verification method according to claim 1, characterized in that: The obtaining the test result of the test case according to the simulation state corresponding to the actual level signal includes: Determine whether the simulation of the test case is completed according to the simulation status.

3. The chip verification method according to claim 1, characterized in that: The obtaining the test result of the test case according to the simulation state corresponding to the actual level signal includes: Generate log information of the test case according to the actual level signal; The test result is obtained according to the log information.

4. The chip verification method according to claim 1, characterized in that: The obtaining of the actual level signal output by the second processing end according to the simulation state of the test case of the chip includes: When the second processing end writes the actual level signal to an address bus connected to an interactive interface according to a simulation state of the test case, the actual level signal is acquired from the interactive interface.

5. The chip verification method according to claim 4, characterized in that: The obtaining the actual level signal from the interactive interface includes: The actual level signal is obtained from an interface group including a plurality of the interactive interfaces; wherein each of the interface groups is used to receive the actual level signal output by the second processing end according to the simulation state when executing different test cases.

6. A chip testing method, characterized in that: A second processing end applied to a cross-language simulation system, the cross-language simulation system further comprising a first processing end, wherein the second processing end executes a test case of a chip based on a first description language, and the first processing end generates a test result of the test case based on a second description language, the method comprising: Obtaining a simulation state of the test case; Generate and send an actual level signal to the first processing end according to the simulation state, so that the first processing end obtains the actual level signal, and when the actual level signal is consistent with a preset level signal corresponding to the simulation state, obtain the test result of the test case according to the simulation state corresponding to the actual level signal.

7. The chip testing method according to claim 6, characterized in that: Before sending the actual level signal to the first processing end, the chip testing method includes: According to the association relationship between the simulation state and the preset write value, a target write value corresponding to the simulation state is obtained; The actual level signal is generated according to the target write value.

8. The chip testing method according to claim 6 or 7, characterized in that: The step of generating and sending an actual level signal to the first processing end according to the simulation state includes: The actual level signal is written into an address bus connected to an interactive interface, so that the first processing end obtains the actual level signal from the interactive interface.

9. A cross-language simulation system, characterized in that: The cross-language simulation system includes a second processing end and a first processing end; wherein, The second processing end executes a test case of the chip based on the first description language, obtains a simulation state of the test case, and outputs an actual level signal to the first processing end according to the simulation state; The first processing end obtains the actual level signal output by the second processing end based on a second description language; obtains a preset level signal corresponding to the simulation state; and when it is detected that the actual level signal is consistent with the preset level signal, obtains the test result of the test case according to the simulation state corresponding to the actual level signal.

10. The cross-language simulation system according to claim 9, characterized in that: The first description language is C language, and the second description language is SV language.

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