Method and device for modeling crack defect TSV equivalent circuit

Abstract

The invention discloses a modeling method and device for a crack defect TSV equivalent circuit. The modeling method comprises the steps that a crack defect TSV structure is designed; wherein the crack defect TSV structure comprises a metal layer, an insulating layer, a substrate layer and a crack defect; establishing a distributed crack defect TSV equivalent circuit model, wherein the model comprises a plurality of TSV sub-modules with the same structure and a crack capacitor Crack; determining parameters of a metal layer, an insulating layer, a substrate layer and crack defects in the crack defect TSV structure according to the RLGC parameters in the distributed crack defect TSV equivalent circuit model; and when the simulation results of the crack defect TSV structure and the distributed crack defect TSV equivalent circuit model meet a preset error requirement, taking the distributed crack defect TSV equivalent circuit model as a target model. The target model constructed by the method can accurately describe the characteristics of the TSV with crack defects, and can reflect more detailed high-frequency characteristics.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a method and device for modeling an equivalent circuit of a TSV with crack defects. Background Art

[0002] Through-Silicon Via (TSV) is a key technology for three-dimensional integrated circuits, which realizes the vertical interconnection of multi-layer chips, improves the integration of circuits by stacking in the vertical direction, and improves the signal transmission speed by shortening the length of interconnection lines, thereby improving the quality and performance of the overall system. Compared with the traditional two-dimensional planar packaging method, three-dimensional integration technology has the advantages of reducing delay, improving performance, reducing power consumption, reducing the packaging size and ultimately reducing costs, and has been vigorously developed in recent years, and the process technology has become increasingly mature. Due to the complex process, incomplete filling of copper or the influence of mechanical stress during the manufacturing process of TSV will form crack defects. Crack defects will cause the conductive path of TSV to be disconnected, resulting in partial reflection of the transmitted signal and hindering the flow of current.

[0003] There are also more and more studies on the equivalent circuit model of distributed crack defect TSV. For example: some literature considers the silicon substrate and establishes an equivalent circuit model for the internal crack defects of TSV and the crack defects extending to the insulating layer and the substrate. The crack defects are modeled as resistors and inductors in series with the self-resistance and self-inductance of TSV. The crack defects extending to the insulating layer and the substrate will increase the substrate parasitic effect and increase the values of the substrate equivalent series resistance and inductance. There is also literature that proposes an equivalent circuit model for partial crack defects. The crack defects are modeled as capacitors in parallel with very high resistors, and the calculation formulas for the equivalent resistance and capacitance of partial crack defect TSV are proposed. Using the Raphael simulation tool, the resistance and capacitance values of 25 different crack heights are extracted respectively, and the simulation values are compared with the proposed calculation formulas, and the fitting degree is greater than 98%. However, the existing equivalent circuit models all adopt the lumped modeling method, lacking a distributed modeling method that can obtain more detailed high-frequency characteristics, and there is still great room for improvement in the equivalent circuit modeling method of crack defect TSV. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method and device for modeling an equivalent circuit of a TSV with crack defects.

[0005] The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, the present invention provides a method for modeling an equivalent circuit of a TSV with crack defects, the method comprising:

[0007] Design a TSV structure with crack defects; wherein, the TSV structure with crack defects includes a metal layer, an insulating layer, a substrate layer, and crack defects;

[0008] Establish a distributed crack defect TSV equivalent circuit model according to the TSV structure with crack defects; the distributed crack defect TSV equivalent circuit model includes multiple TSV sub-modules with the same structure and a crack capacitance C crack ;

[0009] Determine the parameters of the metal layer, insulating layer, substrate layer, and crack defects in the TSV structure with crack defects respectively according to the RLGC parameters in the distributed crack defect TSV equivalent circuit model;

[0010] When the simulation results of the TSV structure with crack defects and the distributed crack defect TSV equivalent circuit model respectively meet the preset error requirements, use the distributed crack defect TSV equivalent circuit model as the target model.

[0011] Optionally, the multiple TSV sub-modules and the crack capacitance C crack are connected in series.

[0012] Optionally, each of the multiple TSV sub-modules includes: a resistor R TSV , an inductor L TSV , a conductance G INS , a conductance G Si , a capacitance C ox , and a capacitance C Si ; the first end of the resistor R TSV is connected to the first end of the inductor L TSV , the second end of the inductor L TSV is connected to the second end of the resistor R TSV in the next TSV sub-module, the first end of the resistor R TSV is also connected to the first end of the conductance G INS , the first end of the conductance G INS is connected to the upper plate of the capacitance C ox , the second end of the conductance G INS is connected to the lower plate of the capacitance C ox , the second end of the conductance G INS is also connected to the first end of the conductance G Si , the first end of the conductance G Si is connected to the upper plate of the capacitance C Si , the second end of the conductance G Si is connected to the lower plate of the capacitance C Si , and the second end of the conductance G INS is also grounded.

[0013] Optionally, the fringe capacitance in the RLGC parameters is expressed as follows:

[0014]

[0015] where C fringing represents the fringe capacitance, ε 0 represents the permittivity of free space, ε r,ox represents the permittivity of silicon dioxide, r TSV represents the radius of the metal layer, and k represents the crack factor.

[0016] Optionally, the crack factor is expressed as follows:

[0017] k = h crack / r TSV ;

[0018] where h crack represents the height of the crack defect.

[0019] Optionally, the parallel - plate capacitance in the RLGC parameters is expressed as follows:

[0020]

[0021] where C parallel represents the parallel - plate capacitance, and ε air represents the permittivity of air.

[0022] Optionally, the crack capacitance in the RLGC parameters is obtained from the fringe capacitance and the parallel - plate capacitance, and the crack capacitance is expressed as follows:

[0023]

[0024] where C crack represents the crack capacitance.

[0025] In a second aspect, the present invention provides a modeling device for a crack - defect TSV equivalent circuit, and the device includes:

[0026] A structure design module for designing a crack - defect TSV structure; wherein the crack - defect TSV structure includes a metal layer, an insulating layer, a substrate layer, and a crack defect;

[0027] A model establishment module for establishing a distributed crack - defect TSV equivalent circuit model according to the crack - defect TSV structure;

[0028] A parameter determination module for determining the parameters of the metal layer, the insulating layer, the substrate layer, and the crack defect in the crack - defect TSV structure respectively according to the RLGC parameters in the distributed crack - defect TSV equivalent circuit model;

[0029] A target model determination module, configured to use the distributed crack defect TSV equivalent circuit model as the target model when the simulation results of the crack defect TSV structure and the distributed crack defect TSV equivalent circuit model respectively meet the preset error requirements.

[0030] The technical solution provided by the embodiments of the present invention may include the following beneficial effects:

[0031] In the above technical solution, the present invention establishes a distributed crack defect TSV equivalent circuit model, which can more accurately describe the characteristics of the crack defect TSV; based on the analytical expressions of the RLGC parameters in the obtained distributed crack defect TSV equivalent circuit model, a crack defect TSV structure is built and simulated in HFSS, and the distributed crack defect TSV equivalent circuit model is simulated in ADS. According to the simulation results and the preset error requirements, a target model that can locate the size and position of the crack defect inside the TSV is obtained.

[0032] The following will further elaborate on the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0033] Figure 1 is a flowchart of a method for modeling a crack defect TSV equivalent circuit provided by an embodiment of the present invention;

[0034] Figure 2 is a schematic diagram of a crack defect TSV structure provided by an embodiment of the present invention;

[0035] Figure 3 is a schematic diagram of the structure of a distributed crack defect TSV equivalent circuit model provided by an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of a curve of the capacitance value of a crack capacitance varying with a crack factor provided by an embodiment of the present invention;

[0037] Figure 5a is an S of a crack defect TSV structure provided by an embodiment of the present invention 11 schematic diagram of the curve varying with the crack factor k;

[0038] Figure 5b is an S of a crack defect TSV structure provided by an embodiment of the present invention 21 schematic diagram of the curve varying with the crack factor k;

[0039] Figure 6a is an S of a crack defect TSV provided by an embodiment of the present invention 11 schematic diagram of the curve varying with the crack defect position x;

[0040] Figure 6bIt is an S of a TSV with crack defects provided by an embodiment of the present invention 21 Schematic diagram of the curve varying with the crack defect position x

[0041] Figure 7 It is a modeling device for the equivalent circuit of a TSV with crack defects provided by an embodiment of the present invention Specific embodiments

[0042] The following further describes the present invention in detail with specific embodiments, but the embodiments of the present invention are not limited thereto

[0043] Figure 1 It is a flowchart of a modeling method for the equivalent circuit of a TSV with crack defects provided by an embodiment of the present invention. As Figure 1 shown, the method may include the following steps

[0044] S101. Design the TSV structure with crack defects; wherein, the TSV structure with crack defects includes a metal layer, an insulating layer, a substrate layer, and a crack defect

[0045] It can be understood that Figure 2 It is a schematic diagram of a TSV structure with crack defects provided by an embodiment of the present invention. As Figure 2 shown, the yellow cylinder is the metal layer, the gray torus is the insulating layer, the transparent cuboid is the substrate layer, and the white cylinder in the middle of the yellow cylinder is the crack defect. Based on this structure, the subsequent process parameters and dielectric materials are further designed. The selection of each layer of materials in the TSV structure with crack defects can be determined according to the actual situation. For example, the metal layer is a solid cylindrical metal column, and the material is generally copper, mainly because of its good process compatibility; the insulating layer material is the key factor to prevent signal leakage to the substrate layer. The greater the resistivity of the material, the more difficult it is for the signal to leak to the substrate layer under the same size. Generally, the insulating layer material is silicon dioxide; the substrate layer can be made of silicon; the crack defect is a cylindrical air cavity

[0046] S102. Establish a distributed equivalent circuit model of the TSV with crack defects according to the TSV structure with crack defects; the distributed equivalent circuit model of the TSV with crack defects includes multiple TSV sub-modules with the same structure and a crack capacitance C crack .

[0047] Optionally Figure 3 It is a schematic diagram of the structure of a distributed equivalent circuit model of the TSV with crack defects provided by an embodiment of the present invention. As Figure 3 shown, multiple TSV sub-modules and a crack capacitance C crack are connected in series

[0048] Optionally, each of the multiple TSV sub-modules includes: a resistor R TSV and an inductor LTSV , conductance G INS , conductance G Si , capacitance C ox and capacitance C Si ; resistance R TSV The first end of the resistance R is connected to the first end of the inductor L TSV The first end of the inductor L TSV The second end is connected to the second end of the resistance R in the next TSV sub-module TSV The first end of the resistance R TSV is also connected to the first end of the conductance G INS The first end of the conductance G INS The first end is connected to the upper plate of the capacitance C ox The first end of the conductance G INS The second end is connected to the lower plate of the capacitance C ox The second end of the conductance G INS is also connected to the first end of the conductance G Si The first end of the conductance G Si The first end is connected to the upper plate of the capacitance C Si The first end of the conductance G Si The second end is connected to the lower plate of the capacitance C Si The second end of the conductance G INS is also grounded.

[0049] It can be understood that the TSV is divided into n equal parts, and each part is represented by a lumped model. They are connected in series to characterize the characteristics of the entire TSV; this model includes four parameters: resistance R, inductance L, conductance G, and capacitance C; referring to Figure 2 , for a TSV with a metal layer radius of r TSV , a metal layer height of h TSV , and a metal layer resistivity of ρ Cu , the height of each part of the TSV is l TSV , where h TSV = n×l TSV ; when using distributed modeling, the length l TSV of each section of the TSV crack = h 1 ; the selection of the segmentation number n is centered on the small section with crack defects and segmented upwards and downwards; x is the TSV length normalization parameter, x = 0, then the defect is located at the source end; x = 0.5, then the defect is located at the midpoint of the TSV; x = 1, then the defect is located at the terminal end; the number of upper segments n TSV = x(h TSV / l 2 ), and the number of lower segments n TSV = (1 - x)(h TSV / l 1 and n 2 are integers, then the total number of segments n = n1 +n 2 +1; n 1 or n 2 is not an integer, then the total number of segments n = [n 1 +[n 2 +1 + x 0 . Where, [] is the integer function, x 0 is the number of non-integer parts of n 1 and n 2 .

[0050] The DC resistance R of the metal layer resistance TSV-dc The calculation formula is:

[0051]

[0052] As the frequency increases, the current in the conductor changes faster and faster, and the distribution of the current density on the TSV cross-section is uneven. The current is concentrated near the conductor surface, resulting in the skin effect, which increases the resistance of the conductor. Under the influence of the skin effect, the high-frequency parasitic resistance R of the TSV TSV-ac The calculation formula is:

[0053]

[0054]

[0055] Among them, δ represents the skin depth of the TSV, f represents the operating frequency of the TSV, μ 0 represents the vacuum permeability, μ r,Cu represents the magnetic permeability of the metal layer. The total resistance R of the metal layer TSV The calculation formula is:

[0056]

[0057] The inductance depends on the position of the current loop. For the single TSV analysis, the current loop is at infinity. The inductance L of the metal layer TSV The calculation formula is:

[0058]

[0059] Among them, ln(·) represents the natural logarithm with the constant e as the base.

[0060] The metal layer, insulation layer and substrate layer will form a parasitic capacitance with MOS characteristics. The TSV capacitance is essentially composed of the insulation layer capacitance C ox , parasitic MOS capacitance C dep and substrate capacitance C sub . The calculation formula is:

[0061]

[0062] Among them, ε 0 represents the vacuum permittivity, and ε r,ox represents the dielectric constant of silicon dioxide, and ε r,Si represents the dielectric constant of silicon.

[0063] The total capacitance C of the substrate Si is essentially the series of the parasitic MOS capacitance and the substrate capacitance, and its calculation formula is:

[0064]

[0065] Among them, t ox is the thickness of the insulating layer, w dep is the depletion layer width on the semiconductor side, N A is the impurity concentration, n i is the intrinsic carrier concentration, V th is the thermal voltage, q is the electron charge amount, and r substrate is the substrate thickness.

[0066] The crack defect disconnects the conductive path of the TSV, partially reflects the transmitted signal and hinders the current flow. The fringe capacitance in the RLGC parameters is expressed as follows:

[0067]

[0068] Among them, C fringing represents the fringe capacitance, r TSV represents the radius of the metal layer, and k represents the crack factor.

[0069] The crack factor is expressed as follows:

[0070] k = h crack / r TSV ;

[0071] Among them, h crack represents the height of the crack defect.

[0072] The larger the ratio of the TSV radius to the crack height, the larger the fringe capacitance. When the height of the crack defect becomes 8π times the TSV radius, the fringe capacitance can be eliminated, and the influence of the fringe capacitance cannot be ignored. The parallel plate capacitance in the RLGC parameters is expressed as follows:

[0073]

[0074] Among them, C parallel represents the parallel plate capacitance, and ε air represents the air permittivity.

[0075] The crack capacitance in the RLGC parameters is obtained from the edge capacitance and the parallel - plate capacitance, and the crack capacitance is expressed as follows:

[0076]

[0077] Among them, C crack represents the crack capacitance.

[0078] The TSV conductance refers to the leakage conductance G INS of the insulating layer and the parasitic conductance G Si of the silicon substrate, and the calculation formula is:

[0079]

[0080] Among them, represents the conductivity of silicon dioxide.

[0081] S103. Determine the parameters of the metal layer, insulating layer, substrate layer, and crack defect in the crack - defect TSV structure respectively according to the RLGC parameters in the distributed crack - defect TSV equivalent circuit model.

[0082] It can be understood that according to the RLGC parameters, the parameters of the metal layer, insulating layer, substrate layer, and crack defect in the crack - defect TSV structure can be determined respectively. As Figure 2 shown, in the crack - defect TSV of the embodiment of the present invention, the radius of the metal layer is r TSV , the thickness of the insulating layer is t ox , the thickness of the outermost substrate layer is r substrate , the heights of the metal layer, insulating layer, and substrate layer are the same, all h TSV , the radius of the crack defect is r TSV , and the height of the crack defect is h crack .

[0083] S104. When the simulation results of the crack - defect TSV structure and the distributed crack - defect TSV equivalent circuit model respectively meet the preset error requirements, take the distributed crack - defect TSV equivalent circuit model as the target model.

[0084] It is understandable that the distributed crack defect TSV equivalent circuit model is preliminarily designed through the above steps. To verify whether the designed distributed crack defect TSV equivalent circuit model meets the design purpose, the designed crack defect TSV structure can be built in HFSS (High Frequency Structure Simulator), an excitation can be applied to it, and simulation analysis can be carried out. At the same time, the distributed crack defect TSV equivalent circuit model is built in ADS (Advanced Design System) for simulation analysis. The accuracy of the distributed crack defect TSV equivalent circuit model can be determined by adjusting the size and position of the crack defect.

[0085] When the HFSS simulation results and the ADS simulation results meet the preset error requirements, the designed distributed crack defect TSV equivalent circuit model is used as the target model; it shows that the designed distributed crack defect TSV equivalent circuit model can meet the requirements at this time and no further correction is required; if the preset error requirements are not met, return to S102 to rebuild until the HFSS simulation results and the ADS simulation results meet the preset error requirements.

[0086] In one implementation Figure 4 is a schematic diagram of the curve of the capacitance value of a crack capacitance changing with the crack factor provided by an embodiment of the present invention. As Figure 4 shown, as the crack factor k increases, that is, as the crack height increases, the crack capacitance gradually decreases, and the decreasing amplitude becomes slower and slower. As the crack height increases, the edge effect weakens and the edge capacitance decreases. The crack capacitance gets closer and closer to the parallel plate capacitance, and has an approximately inverse relationship with the crack factor.

[0087] Figure 5a is the S 11 curve of a crack defect TSV structure changing with the crack factor k provided by an embodiment of the present invention. Figure 5b is the S 21 curve of a crack defect TSV structure changing with the crack factor k provided by an embodiment of the present invention. According to Figure 5a and Figure 5b shown, when the crack factor k remains unchanged, in the low-frequency range, that is, within 1 GHz, the amplitude of the S 11 curve is within -0.5 dB, and the amplitude of the S 21 curve is below -40 dB, and the signal can hardly be transmitted. The crack defect completely truncates the TSV into two independent parts. In this case, the DC signal cannot pass through the TSV, and the AC signal can be transmitted to the other end of the TSV through the coupling method. In the low-frequency range, the capacitance coupling ability of the signal is poor, and the signal is difficult to reach the other end of the TSV. Since the capacitance coupling effect will increase with the increase of frequency, as the frequency increases, S11 The curve amplitude gradually decreases, S 21 The curve amplitude gradually increases. At the same time, as the crack factor k increases, S 11 The curve amplitude increases, S 21 The curve amplitude decreases. The increase in the crack factor leads to a continuous decrease in the crack capacitance. The smaller the crack capacitance, the weaker the capacitive coupling effect, and the more difficult it is for signal transmission.

[0088] Figure 6a is an S of a cracked defect TSV provided by an embodiment of the present invention 11 Schematic diagram of the curve varying with the crack defect position x Figure 6b is an S of a cracked defect TSV provided by an embodiment of the present invention 21 Schematic diagram of the curve varying with the crack defect position x. As x increases, that is, the crack defect position is far from the source end, S 21 The curve amplitude significantly decreases, S 21 The curve amplitude significantly increases. The farther the crack position is from the source end, the longer the signal limited conduction path, the less the signal reflected back to the source end, and the better the signal transmission performance.

[0089] Figure 7 is a modeling device for the equivalent circuit of a cracked defect TSV provided by an embodiment of the present invention, as Figure 7 shown. The device 700 may include:

[0090] A structure design module 701 for designing the cracked defect TSV structure; wherein, the cracked defect TSV structure includes a metal layer, an insulating layer, a substrate layer, and a crack defect;

[0091] A model establishment module 702 for establishing a distributed cracked defect TSV equivalent circuit model according to the cracked defect TSV structure;

[0092] A parameter determination module 703 for determining the parameters of the metal layer, insulating layer, substrate layer, and crack defect in the cracked defect TSV structure respectively according to the RLGC parameters in the distributed cracked defect TSV equivalent circuit model;

[0093] A target model determination module 704 for taking the distributed cracked defect TSV equivalent circuit model as the target model when the simulation results of the cracked defect TSV structure and the distributed cracked defect TSV equivalent circuit model respectively meet the preset error requirements.

[0094] In the above technical solution, the present invention establishes a distributed crack defect TSV equivalent circuit model, which can more accurately describe the characteristics of the crack defect TSV; based on the analytical expressions of the RLGC parameters in the obtained distributed crack defect TSV equivalent circuit model, a crack defect TSV structure is built and simulated in HFSS, and the distributed crack defect TSV equivalent circuit model is simulated in ADS. According to the simulation results and the preset error requirements, a target model capable of locating the size and position of the crack defect inside the TSV is obtained.

[0095] For the specific processing procedures of each module of the device, please refer to the relevant content in the first aspect and will not be elaborated here.

[0096] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0097] Although the present invention is described herein in connection with various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosed content. In the description of the present invention, the term "including" does not exclude other components or steps, the term "a" or "one" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more, unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0098] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A modeling method for a crack defect TSV equivalent circuit, characterized in that: The method comprises: Designing a crack defect TSV structure; wherein the crack defect TSV structure includes a metal layer, an insulating layer, a substrate layer and a crack defect; A distributed crack defect TSV equivalent circuit model is established according to the crack defect TSV structure; the distributed crack defect TSV equivalent circuit model includes a plurality of TSV sub-modules with the same structure and a crack capacitor C crack ; Determine the parameters of the metal layer, the insulating layer, the substrate layer and the crack defect in the crack defect TSV structure according to the RLGC parameters in the distributed crack defect TSV equivalent circuit model; When the simulation results of the crack defect TSV structure and the distributed crack defect TSV equivalent circuit model respectively meet the preset error requirements, the distributed crack defect TSV equivalent circuit model is used as the target model.

2. The modeling method of crack defect TSV equivalent circuit according to claim 1, characterized in that: The plurality of TSV submodules and the crack capacitor C crack By connecting in series.

3. The method for modeling a crack defect TSV equivalent circuit according to claim 2, characterized in that: The plurality of TSV sub-modules each include: a resistor R TSV 、Inductance L TSV , conductivity G INS , conductivity G Si , capacitor C ox and capacitor C Si The resistor R TSV The first end of the inductor L is connected TSV The first end of the inductor L TSV The second end is connected to the resistor R in the next TSV submodule TSV The second end of the resistor R TSV The first end is also connected to the conductance G INS The first end, the conductance G INS The first end of the capacitor C ox The upper plate, the conductance G INS The second end of the capacitor C ox The lower plate, the conductance G INS The second end is also connected to the conductance G Si The first end, the conductance G Si The first end of the capacitor C Si The upper plate, the conductance G Si The second end of the capacitor C Si The lower plate, the conductance G INS The second end is also grounded.

4. The method for modeling a crack defect TSV equivalent circuit according to claim 1, characterized in that: The edge capacitance in the RLGC parameter is expressed as follows: Among them, C fringing represents the edge capacitance, ε0 represents the vacuum dielectric constant, ε r,ox represents the dielectric constant of silicon dioxide, r TSV represents the radius of the metal layer, and k represents the crack factor.

5. The method for modeling a crack defect TSV equivalent circuit according to claim 4, characterized in that: The crack factor is expressed as follows: k=h crack / r TSV ; Among them, h crack Indicates the height of the crack defect.

6. The method for modeling a crack defect TSV equivalent circuit according to claim 5, characterized in that: The parallel plate capacitance in the RLGC parameter is expressed as follows: Among them, C parallel represents the parallel plate capacitance, ε air Represents the dielectric constant of air.

7. The method for modeling a crack defect TSV equivalent circuit according to claim 6, characterized in that: The crack capacitance in the RLGC parameter is obtained according to the edge capacitance and the parallel plate capacitance, and the crack capacitance is expressed as follows: Among them, C crack represents the crack capacitance.

8. A modeling device for a crack defect TSV equivalent circuit, characterized in that: The device comprises: A structure design module, used for designing a crack defect TSV structure; wherein the crack defect TSV structure includes a metal layer, an insulating layer, a substrate layer and a crack defect; A model building module, used to build a distributed crack defect TSV equivalent circuit model according to the crack defect TSV structure; A parameter determination module, used to determine the parameters of the metal layer, the insulating layer, the substrate layer and the crack defect in the crack defect TSV structure according to the RLGC parameters in the distributed crack defect TSV equivalent circuit model; The target model determination module is used to use the distributed crack defect TSV equivalent circuit model as the target model when the simulation results of the crack defect TSV structure and the distributed crack defect TSV equivalent circuit model respectively meet the preset error requirements.

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