2.5 D packaging Die-to-Die simultaneous escape wiring method based on pattern matching binary tree

Abstract

The invention discloses a 2.5 D packaged Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree, and the method comprises the steps: dividing an interconnection network among a plurality of Dies into a plurality of groups of simultaneous escape wiring models with two die interconnection, and according to the separation characteristics of a power supply and a grounding network for a signal network, carrying out the simultaneous escape wiring of the multiple groups of two die interconnection; dividing the signal line nets in each group of models into a plurality of line net sets; fan-out line sequence planning and layer distribution are carried out on each line network set based on a pattern matching binary tree, specifically, a wiring mode is set, the pattern matching binary tree is constructed, and pattern matching binary tree backtracking is carried out; and finally, wiring is completed based on fan-out line sequence planning and layer allocation results. The invention provides a line sequence planning and layer allocation collaborative planning technology for Die-to-Die simultaneous escape wiring under 2.5 D IC packaging, aims to solve the common line sequence and layer allocation problem in the traditional Die-to-Die wiring process, realizes automation of the wiring process through an optimized line sequence planning and layer allocation strategy, and improves the wiring efficiency. And the wiring quality and efficiency are obviously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit wiring, and particularly relates to a 2.5D package Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree. Background Art

[0002] As the transistor size gradually approaches its physical limit, the process difficulty of semiconductor chips gradually increases, and the R & D and manufacturing costs also increase significantly. The semiconductor industry has gradually entered the post-Moore era, and 2.5D / 3D IC (Integrated Circuit) has emerged in the technology development direction. The interconnection of Die-to-Die (chip die to chip die) is realized through the scheme of advanced packaging (Interposer, TSV). The design scheme of advanced packaging can further reduce the distance of device interconnection, not only improving the electrical performance, but also realizing diversified integration, including realizing various forms of microsystem packaging through the method of heterogeneous integration.

[0003] In a typical 2.5D IC package, connecting multiple Bumps (bumps) on different chips usually involves long and parallel inter-chip networks. The parallel inter-chip networks may cause serious coupling effects between signals, thereby reducing signal integrity and circuit performance. To reduce this interference, power and ground nets (usually power layers and ground layers) are usually used in the design to surround the signal lines to form a "shielding" structure, as Figure 1 shown. This approach places the power and ground signal layers above, below, or beside the signal lines to play an isolation role, thereby reducing the impact of the coupling effect.

[0004] Currently, the wiring process of Die-to-Die mostly relies on manual operation in actual industrial applications, which not only results in a long production cycle, but also significantly increases the production cost. This traditional manual wiring method has low efficiency, is easily affected by human factors, causes an extended design cycle, and is difficult to ensure the accuracy and consistency of wiring. Therefore, researching and implementing Die-to-Die automatic wiring technology is of great significance. The automatic wiring technology can effectively shorten the design cycle, improve the automation degree of the wiring process, and enhance production efficiency and yield.

[0005] By introducing Die-to-Die automatic routing technology, complex and delicate routing tasks can be completed in a shorter time, greatly accelerating the project process. This can not only significantly shorten the design cycle and reduce manual intervention, but also quickly promote the production and market launch of products while ensuring the routing quality. Automatic routing can also reduce errors in manual operations, improve routing accuracy and consistency, thereby optimizing the production process and reducing production costs. With the wide application of automatic routing technology, enterprises will be able to improve the efficiency of product R & D, accelerate the launch of new products, and thus enhance their market competitiveness. In the increasingly fierce market competition, automatic routing technology will become an important tool to enhance the core competitiveness of enterprises, helping enterprises to shorten the development cycle, reduce costs, and ensure product quality and technological leadership at the same time.

[0006] However, in the 2.5D IC packaging scenario, there are still some technical problems that need to be solved urgently. Similar to the PCB array pin distribution, in the 2.5D IC packaging scenario, for the arrayed pins, including Grid Pin Array and Staggered Pin Array, although the simultaneous escape routing pin distribution in the scenario and the PCB is relatively similar, the pre-allocated routing nets in 2.5D IC packaging are more complex and densely distributed, and the nets on different Dies usually involve longer and parallel topological relationships. Therefore, the existing automatic routing algorithms for PCB simultaneous escape routing cannot be directly applied to the Die-to-Die routing problem in 2.5D packaging. Currently, the research on the Die-to-Die automatic routing problem in the 2.5D IC packaging scenario is still in the initial exploration stage, and there is no suitable automatic routing algorithm to support it. Therefore, it is urgent to conduct a more in-depth study on the Die-to-Die simultaneous escape routing problem in 2.5D IC packaging. For the Die-to-Die routing scenario in 2.5D packaging, the existing research still needs to be further explored in the following aspects:

[0007] (1) In the Global Routing stage, determining the fan-out line order on the fan-out boundary is one of the keys to simultaneous escape routing. The correct fan-out line order is the prerequisite for successful routing in the channel area and the fan-out area. Although existing research has discussed the simultaneous escape routing line order in the PCB scenario, due to the more complex and densely distributed nets in 2.5D IC packaging, the existing research cannot be directly applied to this scenario. Therefore, how to determine the fan-out line order on the fan-out boundary still needs further research.

[0008] (2) Reasonably planning the layer allocation of all wire networks can effectively reduce the topological crossovers in single-layer wiring and rationally allocate layer resources. The lack of a layer allocation step may lead to crossovers or local congestion during the wiring process based on heuristic A* search or wire exploration wiring algorithms, resulting in unreasonable resource utilization.

[0009] Therefore, it is necessary to conduct more in-depth research and improvement on the above problems, which is crucial for promoting the development of 2.5D IC packaging technology. Summary of the Invention

[0010] The object of the present invention is to provide a 2.5D package Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree to solve the wire order planning and layer allocation problems of Die-to-Die simultaneous escape wiring under 2.5D IC packaging.

[0011] The following is the first aspect of the present invention, which provides a 2.5D package Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree. The method includes:

[0012] Split the interconnect wire networks between multiple Dies into multiple sets of Die-to-Die simultaneous escape wiring models for two Dies, and divide the signal wire networks in each set of models into multiple wire network sets according to the separation characteristics of the power and ground networks for the signal wire networks;

[0013] For each wire network set, perform fan-out wire order planning and layer allocation based on the pattern matching binary tree, specifically including:

[0014] Set the wiring pattern: Let the Dies to which the wire network set belongs be D 1 and D 2 , and the corresponding Pad sets be P1 and P2 respectively; number P1 in ascending order according to the physical position, and number P2 according to the wire network connection relationship; then the wiring pattern includes an increasing subsequence IS pattern and a decreasing subsequence DS pattern;

[0015] Construct a pattern matching binary tree: Sort P2 in ascending order according to the physical position to obtain an initial sequence with corresponding numbers, and expand the initial sequence in the form of a binary tree according to the wiring pattern to construct a pattern matching binary tree, so as to allocate a wire network set into multiple wire network sequences and complete the fan-out wire order planning; wherein, each node of the pattern matching binary tree corresponds to a wire network sequence, and each path corresponds to a set of wire network sequences of this wire network set that satisfy the wiring pattern, thereby obtaining multiple sets of wire network sequences that satisfy the wiring pattern;

[0016] Backtracking of the pattern matching binary tree: Combine each set of wire network sequences that satisfy the wiring pattern with each other through backtracking of the pattern matching binary tree and allocate them on different layers, and select a set of wire network sequences with the goal of minimizing the total number of layers to complete the layer allocation;

[0017] Finally, complete the wiring based on the fan-out wire sequence planning and layer assignment results.

[0018] In some embodiments, the interconnection wire networks between multiple Dies are split into multiple two-Die interconnected simultaneous escape wiring models, and according to the separation characteristics of the power and ground wire networks from the signal wire networks, the signal wire networks in each group of models are divided into multiple wire network sets, including:

[0019] Divide the interconnection wire networks into multiple groups of two-Die interconnections according to the connection relationships between the Dies;

[0020] For each pair of Dies in each group, sort the Pads in the Die;

[0021] Traverse all the Pads in each group, and divide the signal wires separated by the power and ground wire networks into different groups, thereby obtaining multiple two-dimensional arrays, with each two-dimensional array corresponding to a wire network set.

[0022] In some embodiments, if P1 is sorted and numbered from left to right according to the physical position, and P2 is numbered according to the wire network connection relationship; then the increasing subsequence IS mode is that the order on the fan-out boundary increases from left to right according to the sorting of the Pad numbers in the Die, and is distributed from top to bottom on the boundary; the decreasing subsequence DS mode is that the order on the fan-out boundary decreases from left to right according to the sorting of the Pad numbers in the Die, and is distributed from top to bottom on the boundary.

[0023] In some embodiments, the structure of the pattern matching binary tree is composed as follows:

[0024] (1) The root node of the tree: The root node of the tree is the initial sequence;

[0025] (2) The left child node of each node: The increasing subsequence obtained from the sequence of the parent node, corresponding to the increasing subsequence IS mode, and the remaining sequence in the parent node after removing this increasing subsequence;

[0026] (3) The right child node of each node: The decreasing subsequence obtained from the sequence of the parent node, corresponding to the decreasing subsequence DS mode, and the remaining sequence in the parent node after removing this decreasing subsequence.

[0027] In some embodiments, constructing the pattern matching binary tree includes:

[0028] (1) Sort P2 according to the physical position to obtain the initial sequence with corresponding numbers, and set the initial sequence as the root node;

[0029] (2) Find the longest increasing subsequence (LIS) of the sequence of the parent node. If the number of nets in the LIS is greater than the boundary capacity, obtain the increasing subsequence IS according to the increasing subsequence cost function, remove the increasing subsequence IS from the sequence to get the remaining sequence, and place the increasing subsequence IS and the remaining sequence in the left child node;

[0030] Among them, the increasing subsequence cost function is as follows:

[0031]

[0032] In the formula, cost is the cost, E max is the upper fan-out boundary of D 2 , y i is the y-coordinate of the Pad in the i-th group of nets D2, is the i-th group of nets D 1 and D 2 is the absolute value of the difference between the Pads in, and α, β are the weights of the two terms;

[0033] Calculate the cost of each Pad from the above formula, sort them from small to large according to the cost values, and select the longest increasing subsequence IS that meets the boundary capacity;

[0034] (3) Find the longest decreasing subsequence (LDS) of the sequence of the parent node. If the number of nets in the LDS is greater than the boundary capacity, obtain the decreasing subsequence DS according to the decreasing subsequence cost function, remove the decreasing subsequence DS from the sequence to get the remaining sequence, and place the decreasing subsequence DS and the remaining sequence in the right child node;

[0035] Among them, the decreasing subsequence cost function is as follows:

[0036]

[0037] In the formula, E min is the lower fan-out boundary of D 2 ;

[0038] (4) Traverse all leaf nodes without child nodes, and repeat the expansion of the left and right child nodes until the remaining sequences of all leaf nodes are empty.

[0039] In some embodiments, the pattern matching binary tree backtracking includes:

[0040] (1) Backtrack from the leaf node to the parent node until reaching the root node to obtain the IS or DS net sequence of each node on this path;

[0041] (2) Classify the allocated wire net sequences into a first type of wire net sequence T1 and a second type of wire net sequence T2. Among them, for the first type of wire net sequence T1, the number of wire nets in the wire net sequence is equal to the number of wire nets that the boundary can accommodate, and this wire net sequence is allocated separately on one layer. For the second type of wire net sequence T2, the number of wire nets in the wire net sequence is less than the number of wire nets that the boundary can accommodate. This wire net sequence can be allocated on the same layer as other wire net sequences, but it is required to satisfy the inequality:

[0042]

[0043] In the formula, S size is the number of wire nets in a single second type of wire net sequence, linewdth is the wire width, viasize is the size of the via, clearance is the distance between the via and the wire, C is the total capacity of the boundary, and i is the number of second type of wire net sequences allocated on the same layer;

[0044] (3) Allocate the first type of wire net sequence to a separate layer;

[0045] (4) Sort all the second type of wire net sequences according to the number of wire nets, select the sequence with the largest number of wire nets among the wire net sequences to be allocated, combine this sequence with other sequences in turn, and require it to satisfy the inequality in step (2). Then remove the several sequences that meet the conditions from the sequences to be allocated;

[0046] (5) Repeat step (4) until the sequence to be allocated is empty;

[0047] (6) Repeat steps (1) to (4) until the hierarchical results of all leaf nodes are obtained, and select the backtracking result with the smallest required number of layers as the layer allocation result.

[0048] In some embodiments, routing is completed based on the fan-out wire order planning and the layer allocation result, including:

[0049] Construct a Hanan grid routing map;

[0050] Fan out and punch holes for each Pad to the specified layer of this Pad;

[0051] Perform coarse-grained routing. During the routing process, it is required to avoid crossing the routing obstacles. After the routing is completed, set the routing result of this Pad as a routing obstacle.

[0052] According to the second aspect of the present invention, a 2.5D IC is provided. This 2.5D IC uses the 2.5D packaging Die-to-Die simultaneous escape routing method based on the pattern matching binary tree described in any item of the first aspect for routing.

[0053] According to a third aspect of the present invention, there is provided a computer device, comprising: a processor and a memory, the memory storing a program or instructions executable on the processor, and when the program or instructions are executed by the processor, the steps of the 2.5D package Die-to-Die simultaneous escape routing method based on a pattern matching binary tree described in any one of the first aspects are implemented.

[0054] According to a fourth aspect of the present invention, there is provided a readable storage medium, on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of the 2.5D package Die-to-Die simultaneous escape routing method based on a pattern matching binary tree described in any one of the first aspects are implemented.

[0055] Generally speaking, compared with the prior art by the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0056] The present invention proposes a co-planning technology for wire sequence planning and layer assignment of Die-to-Die simultaneous escape routing in 2.5D IC packaging, aiming to solve the problem of unreasonable wire sequence and layer assignment commonly found in the traditional Die-to-Die routing process. Through optimized wire sequence planning and layer assignment strategies, this technology not only realizes the automation of the routing process, but also significantly improves the routing quality and efficiency. Reasonable wire sequence planning can avoid unnecessary routing conflicts and reduce the crossing of routing paths, thereby effectively improving the performance and reliability of routing. At the same time, the optimization of the layer assignment strategy minimizes the occupation of routing resources, greatly improves the routing accuracy, and reduces the routing complexity. This technology can effectively improve the limitations of traditional routing methods, improve routing performance and reliability, and provide strong technical support for the design and manufacturing of the next generation of high-performance integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 FIG. is a schematic diagram of a typical structure of a chip in a 2.5D package provided by an embodiment of the present application;

[0058] Figure 2 FIG. is a schematic diagram of the overall process of a 2.5D package Die-to-Die simultaneous escape routing method based on a pattern matching binary tree provided by an embodiment of the present application;

[0059] Figure 3 FIG. is a routing pattern diagram provided by an embodiment of the present application; wherein, Figure 3 in (a) is the IS pattern diagram of D 1 ; Figure 3 in (b) is the IS pattern diagram of D 2 ; Figure 3 in (c) is the DS pattern diagram of D 1 ; Figure 3 in (d) is D2 DS mode diagram;

[0060] Figure 4 This is an actual measurement example diagram provided by an embodiment of the present application; wherein, Figure 4 (a) in it is the left device D 1 actual measurement example diagram of, Figure 4 (b) in it is the right device D 2 actual measurement example diagram of;

[0061] Figure 5 This is a pattern matching binary tree structure diagram provided by an embodiment of the present application;

[0062] Figure 6 This is a line sequence allocation result schematic diagram provided by an embodiment of the present application;

[0063] Figure 7 This is a Hanan grid construction schematic diagram provided by an embodiment of the present application;

[0064] Figure 8 This is a global routing diagram of Die to Die simultaneous escape routing provided by an embodiment of the present application; wherein, Figure 8 (a) in it is the wiring diagram of the MB layer, Figure 8 (b) in it is the wiring diagram of the RDL1 layer, Figure 8 (c) in it is the wiring diagram of the RDL2 layer;

[0065] Figure 9 This is a hardware structure schematic diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0066] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments provided in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

[0067] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without making creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some designs, manufacturing or production changes made on the basis of the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.

[0068] As used herein, the mention of "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appearing at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present application may be combined with other embodiments without conflict.

[0069] Unless otherwise defined, the technical terms or scientific terms involved in the present application shall have the ordinary meaning understood by those with ordinary skills in the technical field to which the present application pertains. The words such as "a", "an", "one", "the" and the like involved in the present application do not indicate a limitation in quantity and may represent a singular or plural number. The terms "including", "comprising", "having" and any variations thereof involved in the present application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connected", "coupled" and the like involved in the present application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in the present application refers to two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The terms "first", "second", "third" and the like involved in the present application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0070] The present application designs a global routing plan for Die-to-Die simultaneous escape routing under 2.5D IC packaging, specifically involving the layer assignment of the nets in the escape area, the determination of the wire order at the escape boundary, and the global routing of the Redistribution Layer (RDL).

[0071] As Figure 2 shown, the present application proposes a 2.5D packaging Die-to-Die simultaneous escape routing method based on a pattern matching binary tree, specifically as follows:

[0072] 1. Overall framework

[0073] The overall framework is as Figure 2As shown, it is divided into three parts: preprocessing of Die-to-Die netlist data in 2.5D IC packaging, wire order planning and layer assignment method based on pattern matching binary tree, and global routing. First, in the preprocessing stage, the initial group division is completed according to the given netlist information. Then comes the wire order and layer co-planning stage. First, the routing pattern is determined, then a pattern matching binary tree is constructed to assign the routing pattern to the nets of the current group, plan the wire order of the nets on the fan-out boundary, and then comes the backtracking stage of the pattern matching binary tree. According to the capacity of the fan-out boundary and the obtained fan-out order, the layer division is carried out to ensure that the topologies of the fan-out areas and channel areas of the nets on each layer do not cross. Finally, a Hanan grid is constructed to perform global routing on the nets after wire order planning and layer assignment.

[0074] 2. Preprocessing

[0075] The input netlist information may contain the interconnecting nets between multiple Dies. First, these interconnect models of multiple Dies need to be split into multiple two-Die interconnecting and escaping routing models. This can not only simplify the complexity of the problem but also better handle the allocation of routing resources. Since the scale of the nets to be processed is large, in the data preprocessing stage, according to the separation characteristics of the signal nets by the power and ground signal layers, the signal nets are divided into multiple data processing units, each unit contains a group of Pad nets, and each group is processed separately.

[0076] The input of the preprocessing stage is all device information D[1…n] and netlist information N[1…t], and the output is the grouping result of all Pads. The main steps of the preprocessing are as follows:

[0077] (1) According to the connection relationship between devices, the devices are divided into pairs as groups G[1…m];

[0078] (2) For each pair of devices, the Pads in the devices are sorted to get P[1…m];

[0079] (3) Traverse all Pads, and divide the ordinary signal lines separated by the power and ground nets into groups to obtain a two-dimensional array Pgroup[1…m][1…n].

[0080] 3. Co-planning of Escape Wire Order and Layer Assignment

[0081] In multi-layer escape routing, the wire order of fan-out mainly determines the pin order of each signal line at the fan-out boundary, that is, the front-back relationship of the signal fan-out points on the boundary. The layer assignment mainly determines on which layer each signal line is routed. A reasonable layer assignment result can effectively solve the topological cross relationship between wire networks and can also solve the situation where the boundary capacity is insufficient to support the fan-out of all wire networks. During design, it is necessary to ensure that the signals of these pins can be smoothly and effectively fanned out to the fan-out boundary of the chip, and the topology of the channel area should not cross. For the boundary area where multiple Pads need to be fanned out, a reasonable order can avoid collisions and overlaps between signal lines, thereby reducing the design complexity.

[0082] This application proposes a method for collaborative planning of fan-out wire order and layer assignment based on a pattern-matching binary tree. Briefly speaking, for a simultaneous escape routing model with two Dies interconnected, first, a routing pattern is given. Each wire network set after preprocessing can first obtain the assignment of the fan-out wire order in a single layer according to the given routing pattern, and it can be ensured that the signal lines are routed in the RDL layer according to the routing pattern. Then, the initial sequence is expanded in the form of a binary tree according to the routing pattern, and by backtracking and matching various patterns, the layer can be minimized, thus completing the collaborative planning of fan-out wire order and layer assignment.

[0083] 3.1 Routing Pattern

[0084] By presetting the routing pattern, it can be used to guide the assignment of the fan-out wire order in a single layer. The routing pattern is essentially a pattern of the fan-out point order of Pads, that is, in a group of Pad wire network sequences, a group of wire networks that conform to the routing pattern are selected to form a subsequence. Then, the fan-out order of all wire networks in this subsequence is determined, and the wire networks in this subsequence are all assigned to the same layer. The routing pattern can avoid possible topological crosses and congestion phenomena during the routing process by planning the fan-out point order of each Pad, and can also improve the overall routing efficiency and reduce the complexity during the routing process by optimizing the routing path.

[0085] For a given set of wire networks N[1…n], the Dies to which the two-terminal wire networks in N belong are D 1 and D 2 , respectively. The Pad sets of this set of wire networks on D 1 and D 2 are P 1 and P 2 , respectively. First, P 1 is sorted from left to right according to the physical position and renumbered, and then P 2 is renumbered according to the wire network connection relationship. Then, the routing pattern can be defined as:

[0086] (1) The order on the fan - out boundary increases from left to right according to the sorting of the Pad numbers within the Die and is distributed from top to bottom on the boundary, that is, an increasing subsequence (IS), as shown in (a) and (b) of Figure 3 ;

[0087] (2) The order on the fan - out boundary decreases from left to right according to the sorting of the Pad numbers within the Die and is distributed from top to bottom on the boundary, that is, a decreasing subsequence (DS), as shown in (c) and (d) of Figure 3 .

[0088] 3.2 Pattern - matching binary tree

[0089] In escape routing, a reasonable fan - out order can effectively avoid the intersection of routing paths, thereby reducing routing conflicts and avoiding routing congestion. The construction process of the pattern - matching binary tree is the process of assigning the fan - out line order for a single - layer netlist, and the backtracking process of the pattern - matching binary tree is the layer - assignment process of assigning the fan - out line order of a single - layer netlist to specific layers.

[0090] After renumbering all the nets, re - sort all the nets in 2 from left to right to obtain an initial sequence of nets. Figure 4 is an example that may be encountered in an actual scenario. Among them, Figure 4 (a) in is the actual test case diagram of the left device D 1 , Figure 4 (b) in is the actual test case diagram of the right device D 2 . As shown in Figure 4 , given a set of nets N[1…n], where the capacity of the fan - out boundary is 9, that is, a single layer can accommodate at most 9 nets. First, renumber the nets in the two devices, and then arrange all the nets in 2 in the order from left to right according to their physical positions to obtain a net sequence. The obtained initial sequence is 2, 1, 3, 4, 5, 6, 7, 8, 10, 9, 12, 11, 14, 13, 16, 15, 18, 17.

[0091] The root node of the pattern - matching binary tree is the initial sequence obtained after renumbering. The left branch of the tree matches the IS pattern, and the right branch of the tree matches the DS pattern. Extending to the left means finding the IS of the sequence in the parent node and removing the IS from the sequence to obtain the remaining sequence. Extending to the right means finding the DS of the sequence in the parent node and removing the DS from the sequence to obtain the remaining sequence. This binary tree is continuously extended until the remaining sequence of the child node is empty. The structure diagram of the tree is as shown in Figure 5 .

[0092] The structure of the tree is composed as follows:

[0093] (1) Root node of the tree: The root node of the tree is the obtained initial sequence initSequence;

[0094] (2) Left child node of each node: The increasing subsequence obtained from the sequence of the parent node, corresponding to the IS mode, and the remaining sequence in the parent node after removing the IS;

[0095] (3) Right child node of each node: The decreasing subsequence obtained from the sequence of the parent node, corresponding to the DS mode, and the remaining sequence in the parent node after removing the DS.

[0096] Each node of the pattern matching binary tree corresponds to a net sequence, and each path corresponds to a set of net sequences of the net set that satisfy the routing pattern, so that multiple sets of net sequences that satisfy the routing pattern can be obtained (the number of sets is equal to the number of paths). Moreover, the net sequences corresponding to all nodes on each path are combined together to form the net set.

[0097] 3.2.1 Construction of the pattern matching binary tree

[0098] First, determine the root node, set the initial sequence obtained after renumbering and reordering as the root node, and then expand the root node into two child nodes, the left and the right. The process of determining the left child node is as follows: Find the longest increasing subsequence (LIS) of the sequence of the parent node. However, the number of nets in the obtained LIS may be greater than the boundary capacity, which is not allowed. If the number of nets in the obtained LIS is greater than the boundary capacity, then calculate the cost of each Pad in the LIS, sort them in ascending order according to the cost values, and select the largest increasing subsequence (IS) that meets the boundary capacity. The cost function is:

[0099]

[0100] In the formula, E max is the upper boundary of the fan-out in D 2 , y i is the y - coordinate of the Pad in the i - th group of nets D2, is the i - th group of nets D 1 and D 2 is the absolute value of the difference of the Pads in them, and α, β are the weights of the two terms;

[0101] The process of determining the right child node is similar to that of the left child node. First, find the longest decreasing subsequence (LDS) of the parent node. If the number of nets in the LDS is greater than the boundary capacity, then select a DS sequence with the lowest cost according to the cost function. The cost function is:

[0102]

[0103] Similar to Formula 3-1, where E min is the lower boundary of the fan-out in D 2 .

[0104] Then, for leaf nodes, determine whether the sequence of the current node is empty. If it is not empty, continue to expand the node into left and right child nodes according to the above method until the remaining sequences of all leaf nodes are empty.

[0105] It should be noted that finding the longest increasing subsequence or the longest decreasing subsequence of a sequence is a prior art.

[0106] The specific steps for constructing the pattern matching binary tree are as follows:

[0107] (1) Sort the Pads in D 2 from left to right and top to bottom to obtain the initial sequence initSequence, and set the initial sequence as the root node;

[0108] (2) Calculate the LIS for the sequence of the parent node. If the number of nets in the LIS is greater than the boundary capacity, obtain the IS according to Formula 3-1, and remove the IS from the sequence to get the remaining sequence. Place the IS and the remaining sequence in the left child node;

[0109] (3) Calculate the LDS for the sequence of the parent node. If the number of nets in the LDS is greater than the boundary capacity, obtain the DS sequence according to Formula 3-2, and remove the DS from the sequence to get the remaining sequence. Place the DS and the remaining sequence in the right child node;

[0110] (4) Traverse all leaf nodes without child nodes, and repeat the expansion of left and right child nodes until the remaining sequences of all leaf nodes are empty;

[0111] The pseudo-code for constructing the pattern matching binary tree is shown in Table 1.

[0112] Table 1 Pseudo-code for constructing the pattern matching binary tree

[0113]

[0114]

[0115] 3.2.2 Backtracking of the pattern matching binary tree

[0116] To meet specific topological requirements, multiple netlists sequences that have been well - allocated according to the routing pattern are allocated on different layers when the fan - out boundary capacity permits. After wire - order planning, multiple groups of netlist sequences that meet the routing pattern can be obtained. Now, these netlist sequences need to be combined with each other and allocated on different layers, and it is ensured that the number of nets on the same layer does not exceed the boundary capacity. This is the backtracking function of the pattern - matching binary tree.

[0117] The goal of the backtracking process of the pattern - matching binary tree is to minimize the number of layers. Each IS or DS in a child node can be divided into two categories according to the number of nets: The first category is that the number of nets in the sequence is equal to the number of nets that the boundary can accommodate, then this sequence is allocated on a single layer, and the number of layers required for this sequence is fixed; The second - category sequence has a number of nets less than the boundary capacity. This netlist sequence can be allocated on the same layer as other netlist sequences, but it is required to satisfy the inequality:

[0118] ∑ i (S size )*(linewidth + clearance)+(i + 1)*(viasize + clearance)<C Formula 3 - 3

[0119] In the formula, S size is the number of nets in a single second - category sequence, linewidth is the line width, viasize is the size of the via, clearance is the distance between the via and the line, C is the boundary capacity, and i is the number of second - category sequences allocated on the same layer. The meaning of this formula is that the sum of the number of nets in the second - category sequences allocated on the same layer plus the interval requirements between each group of second - category sequences is less than the boundary capacity. Therefore, the goal of the backtracking process of the pattern - matching binary tree can be simplified as: Starting from each leaf node, backtracking to the root node, obtaining multiple backtracking results, and reasonably combining and allocating the second - category netlist sequences among them to minimize the layer resources required for the second - category sequences.

[0120] The greedy strategy can be adopted to allocate and combine the second - category nets. In each step of the selection, the local optimal solution is pursued, and finally a solution close to the global optimal solution can be obtained. The specific steps of the backtracking process of the pattern - matching binary tree are as follows:

[0121] (1) Backtrack from the leaf node to the parent node until reaching the root node to obtain the IS or DS netlist sequences N[1…s][1…t] of each node;

[0122] (2) Classify the allocated netlist sequences N[1…s][1…t] into the first - category and second - category netlist sequences T1 and T2;

[0123] (3) Allocate the first - category nets to a separate layer;

[0124] (4) Sort all the second - type sequences according to the number of wire networks, select the sequence with the largest number of wire networks in the sequences to be assigned, combine this sequence with other sequences in turn, and require that formula 3 - 3 is satisfied. Then remove the several sequences that meet the conditions from the sequences to be assigned;

[0125] (5) Repeat step (4) until the sequences to be assigned are empty.

[0126] (6) Repeat steps (1), (2), (3), and (4) until the hierarchical results of all leaf nodes are obtained. Select the backtracking result with the smallest required layer as the layer assignment result.

[0127] It should be noted that when combining this sequence with other sequences in turn in step (4), it is also possible not to select the sequence with the largest number of wire networks in the sequences to be assigned, but to combine them by other methods.

[0128] The pseudo - code for the backtracking stage of the pattern - matching binary tree is shown in Table 2.

[0129] Table 2 Pseudo - code table for the backtracking stage of the pattern - matching binary tree

[0130]

[0131]

[0132]

[0133] The final result obtained after the test case undergoes the wire - order planning and layer assignment processing of constructing the pattern - matching binary tree is: 2, 3, 5, 7, 9, 11, 13, 15, 17 are in the same layer, 1, 4, 6, 8, 10, 12, 14, 16, 18 are in the same layer, as Figure 6 shown. Then the wire - order planning and layer assignment result of this test case is: the fan - out order of the wire networks assigned to the RDL1 layer on the boundary from top to bottom is 2, 3, 5, 7, 9, 11, 13, 15, 17 respectively, and the fan - out order of the wire networks assigned to the RDL2 layer on the boundary from top to bottom is 1, 4, 6, 8, 10, 12, 14, 16, 18 respectively.

[0134] 4 Global Routing

[0135] The purpose of global routing is to provide routing guidelines for the next - stage detailed routing. Global routing needs to consider the routability of detailed routing and have a high running speed. Since most scenarios are regularly distributed Pad arrays, such as Grid PinArray and Staggered Pin Array, Hanan grids are used as the global - routing units. The construction of Hanan grids is as Figure 7, where the white rectangles are Pads and the blue rectangles are routable resources. Coarse-grained routing using the Hanan grid can effectively record the physical location of each route, effectively avoid route crossings during the routing process, and can calculate the congestion degree and detect potential congestion risks.

[0136] The overall routing algorithm of this application ensures topological compatibility through wire order planning and layer assignment, and then uses the Hanan grid as the basic routing unit to perform coarse-grained routing to obtain grid paths, which guide the routing areas of detailed routing. Each set of nets has a unique path, and the Hanan grids passed through are determined. From this, the nets passing through each Hanan grid can be obtained.

[0137] The overall routing diagram of the embodiment of this application is represented by G(V, E). V is composed of the four vertices of the Hanan grid, which contains the location information of the Pads and determines the physical location of a specific Cell through the four vertices. E represents the edge information of each Cell, which contains the adjacent Cell information of a Cell. In a Cell, another adjacent Cell can be indexed through the edge. Each net has a unique path and will leave a routing trace in the Cell. Whether the route crosses is determined by judging whether the current route crosses the existing routing path.

[0138] The specific steps of the overall routing are as follows:

[0139] (1) Net preprocessing;

[0140] (2) Wire order planning and layer assignment;

[0141] (3) Construct a Hanan grid routing map;

[0142] (4) Fan out and punch each Pad to the specified layer of the Pad;

[0143] (5) Perform coarse-grained routing. During the routing process, it is required to avoid crossing routing obstacles. After the routing is completed, set the routing result of the Pad as a routing obstacle.

[0144] The overall routing pseudocode is shown in Table 3.

[0145] Table 3 Overall routing pseudocode Table 3

[0146]

[0147]

[0148] 5 Final result display

[0149] The overall routing result based on this algorithm is as Figure 8 shown, Figure 8Among them, (a) is the trace of the Metallic Bonding (MB) layer. The MB layer includes rectangular pads, traces of the MB layer, and fan-out vias. Figure 8 Among them, (b) is the RDL1 layer. Drilling holes in the pads assigned to the RDL2 layer will pass through the RDL1 layer, so holes will be left on the RDL1 layer. The RDL1 layer includes holes of the pads assigned to the RDL1 layer, holes of the pads assigned to the RDL2 layer, and traces of the RDL1 layer. Figure 8 Among them, (c) is the RDL2 layer. The RDL2 layer includes holes of the pads assigned to the RDL2 layer and traces of the RDL2 layer.

[0150] In addition, combined with Figure 2 the 2.5D package Die-to-Die simultaneous escape routing method based on the pattern matching binary tree described in the embodiments of the present application can be implemented by a computer device. Figure 9 It is a schematic diagram of the hardware structure of the computer device according to the embodiments of the present application. As Figure 9 shown, the device may include a processor 301 and a memory 302 storing computer program instructions.

[0151] Specifically, the above-mentioned processor 301 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured as one or more integrated circuits implementing the embodiments of the present application.

[0152] Among them, the memory 302 may include a mass storage for data or instructions. By way of example and not limitation, the memory 302 may include a hard disk drive (HDD), a floppy disk drive, a solid state drive (SSD), a flash memory, an optical disc, a magneto-optical disc, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. In appropriate cases, the memory 302 may include removable or non-removable (or fixed) media. In appropriate cases, the memory 302 may be internal or external to the data processing device. In a particular embodiment, the memory 302 is non-volatile memory. In a particular embodiment, the memory 302 includes a read-only memory (ROM) and a random access memory (RAM). In appropriate cases, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or a flash memory, or a combination of two or more of these. In appropriate cases, the RAM may be a static random access memory (SRAM) or a dynamic random access memory (DRAM), where the DRAM may be a fast page mode dynamic random access memory (FPMDRAM), an extended date out dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0153] The memory 302 can be used to store or cache various data files required for processing and / or communication, as well as possible computer program instructions executed by the processor 301.

[0154] The processor 301 reads and executes the computer program instructions stored in the memory 302 to implement any one of the 2.5D package Die-to-Die simultaneous escape routing methods based on pattern matching binary trees in the above embodiments.

[0155] In some embodiments, the point cloud generation device may further include a communication interface 303 and a bus 300. Among them, as Figure 9 shown, the processor 301, the memory 302, and the communication interface 303 are connected through the bus 300 and complete communication with each other.

[0156] The communication interface 303 is used to implement communication between various modules, devices, units, and / or devices in the embodiments of the present application. The communication interface 303 can also implement data communication with other components such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0157] The bus 300 includes hardware, software, or both, and couples components of the point cloud generation device to each other. The bus 300 includes, but is not limited to, at least one of the following: Data Bus, Address Bus, Control Bus, Expansion Bus, Local Bus. By way of example and not limitation, the bus 300 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable bus or a combination of two or more of these. In a suitable case, the bus 300 may include one or more buses. Although the embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0158] The computer device can execute the 2.5D package Die-to-Die simultaneous escape routing method based on the pattern matching binary tree in the embodiments of the present application based on the rendering device, so as to implement the combination Figure 2 of the 2.5D package Die-to-Die simultaneous escape routing method described based on the pattern matching binary tree.

[0159] In addition, in combination with the 2.5D packaging Die-to-Die simultaneous escape routing method based on the pattern matching binary tree in the above embodiments, the embodiments of the present application can provide a computer-readable storage medium to implement. Computer program instructions are stored on the computer-readable storage medium; when the computer program instructions are executed by a processor, any one of the 2.5D packaging Die-to-Die simultaneous escape routing methods based on the pattern matching binary tree in the above embodiments is implemented.

[0160] In summary, the line sequence planning and layer assignment collaborative planning technology for Die-to-Die simultaneous escape routing under 2.5D IC packaging proposed in the present application aims to solve the problem of unreasonable line sequence and layer assignment commonly found in the traditional Die-to-Die routing process. Through the optimized line sequence planning and layer assignment strategies, this technology not only realizes the automation of the routing process, but also significantly improves the routing quality and efficiency. A reasonable line sequence planning can avoid unnecessary routing conflicts and reduce the crossing of routing paths, thereby effectively improving the performance and reliability of routing. At the same time, the optimization of the layer assignment strategy minimizes the occupation of routing resources, greatly improves the routing accuracy, and reduces the routing complexity. This technology can effectively improve the limitations of traditional routing methods, improve the routing performance and reliability, and provide strong technical support for the design and manufacture of the next generation of high-performance integrated circuits.

[0161] It should be noted that the technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification. In addition, according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present application.

[0162] Those skilled in the art can easily understand that the above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree, characterized in that: The method includes: The interconnection nets between multiple dies are split into multiple groups of two-die interconnection simultaneous escape wiring models, and the signal nets in each group of models are divided into multiple net sets according to the separation characteristics of the power supply and ground nets for the signal nets; For each network set, fan-out line sequence planning and layer allocation are performed based on the pattern matching binary tree, including: Set the wiring mode: Set the Dies to which the wire net sets belong to D1 and D2, and the corresponding Pad sets to P1 and P2; sort and number P1 according to the physical position, and number P2 according to the wire net connection relationship; the wiring mode includes the ascending subsequence IS mode and the descending subsequence DS mode; Construct a pattern matching binary tree: Sort P2 by physical position to obtain an initial sequence of corresponding numbers, expand the initial sequence in the form of a binary tree according to the wiring mode to construct a pattern matching binary tree, so as to allocate a wire net set into multiple wire net sequences and complete the fan-out wire sequence planning; wherein each node of the pattern matching binary tree corresponds to a wire net sequence, and each path corresponds to a set of wire net sequences that meet the wiring mode of the wire net set, thereby obtaining multiple sets of wire net sequences that meet the wiring mode; Pattern matching binary tree backtracking: By backtracking the pattern matching binary tree, each group of wire net sequences that meet the wiring pattern are combined and allocated to different layers, and a group of wire net sequences is selected with the goal of minimizing the total number of layers to complete the layer allocation; Finally, routing is completed based on the fan-out line sequence planning and layer assignment results.

2. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: The interconnection nets between multiple dies are split into multiple groups of two-die interconnection simultaneous escape routing models, and according to the separation characteristics of the power and ground nets on the signal nets, the signal nets in each group of models are divided into multiple net sets, including: According to the connection relationship between Dies, the interconnection network is divided into multiple groups of two Die interconnections; For each set of two Dies, sort the Pads in the Dies; All pads in each group are traversed, and the signal lines separated by the power supply and ground network are divided into different groups, so as to obtain multiple two-dimensional arrays, each of which corresponds to a line network set.

3. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: If P1 is sorted and numbered from left to right according to the physical position, and P2 is numbered according to the line network connection relationship; then the ascending subsequence IS mode is the sequence on the fan-out boundary, which increases from left to right according to the sequence of the pad numbers in the Die, and is distributed from top to bottom on the boundary; the descending subsequence DS mode is the sequence on the fan-out boundary, which decreases from left to right according to the sequence of the pad numbers in the Die, and is distributed from top to bottom on the boundary.

4. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: The structure of the pattern matching binary tree is as follows: (1) Root node of the tree: The root node of the tree is the initial sequence; (2) The left child of each node: the ascending subsequence obtained from the sequence of the parent node, the corresponding ascending subsequence IS pattern, and the remaining sequence after removing the ascending subsequence from the remaining sequence in the parent node; (3) The right child node of each node: the descending subsequence obtained from the sequence of the parent node, the corresponding descending subsequence DS pattern, and the remaining sequence in the parent node after removing the descending subsequence.

5. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: Construct a pattern matching binary tree, including: (1) Sort P2 by physical position to obtain the initial sequence of corresponding numbers, and set the initial sequence as the root node; (2) Find the maximum ascending subsequence LIS of the parent node sequence. If the number of network lines of the maximum ascending subsequence LIS is greater than the boundary capacity, obtain the ascending subsequence IS according to the ascending subsequence cost function, and remove the ascending subsequence IS from the sequence to obtain the remaining sequence. Put the ascending subsequence IS and the remaining sequence into the left child node; Among them, the ascending subsequence cost function is as follows: In the formula, cost is the cost, E max is the upper boundary of the fan-out in D2, y i is the y coordinate of the pad in the i-th group of mesh D2, is the absolute value of the difference between the Pads in the i-th group of lines D1 and D2, α and β are the weights of the two items; Calculate the cost of each Pad from the above formula, and sort them from small to large according to the cost value, and select the largest ascending subsequence IS that meets the boundary capacity; (3) Find the maximum descending subsequence LDS of the parent node sequence. If the number of network lines of the maximum descending subsequence LDS is greater than the boundary capacity, obtain the descending subsequence DS according to the descending subsequence cost function, remove the descending subsequence DS from the sequence to obtain the remaining sequence, and put the descending subsequence DS and the remaining sequence into the right child node; Among them, the cost function of the descending subsequence is as follows: In the formula, E min is the fan-out lower boundary in D2; (4) Traverse all leaf nodes without child nodes and repeatedly expand the left and right child nodes until the remaining sequences of all leaf nodes are empty.

6. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: Pattern matching binary tree backtracking, including: (1) Trace back from the leaf node to the parent node until the root node is reached, and obtain the IS or DS network sequence of each node on the path; (2) The allocated mesh sequences are classified into first-class mesh sequences T1 and second-class mesh sequences T2. The first-class mesh sequence T1 is a mesh sequence whose number of meshes is equal to the number of meshes that can be accommodated by the boundary, and the mesh sequence is allocated to a single layer. The second-class mesh sequence T2 is a mesh sequence whose number of meshes is less than the number of meshes that can be accommodated by the boundary, and the mesh sequence can be allocated to the same layer as other mesh sequences, but the inequality is required to be satisfied: In the formula, S size is the number of nets in a single second-class net sequence, linewidth is the line width, viasize is the hole size, clearance is the distance from the hole to the line, C is the total capacity of the boundary, and i is the number of second-class net sequences allocated on the same layer; (3) assigning the first type of wire mesh sequence to a single layer; (4) Sort all the second-category network sequences according to the number of network, select the sequence with the largest number of network in the network sequence to be allocated, combine this sequence with other sequences in turn, and require that the inequality in step (2) is satisfied, and then remove several sequences that meet the conditions from the sequence to be allocated; (5) Repeat step (4) until the sequence to be allocated is empty; (6) Repeat steps (1) to (4) until the stratification results of all leaf nodes are obtained, and select the smallest backtracking result of the required layer as the layer allocation result.

7. The 2.5D package Die-to-Die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that: Complete routing based on fan-out line sequence planning and layer assignment results, including: Construct Hanan grid wiring map; Each pad is fanned out to the specified layer of the pad; Perform coarse-grained routing. During the routing process, it is required to avoid crossing routing obstacles. After the routing is completed, the routing result of the pad is set as a routing obstacle.

8. A 2.5D IC, characterized in that: The 2.5D IC is routed using the 2.5D package Die-to-Die simultaneous escape routing method based on a pattern matching binary tree as described in any one of claims 1 to 7.

9. A computer device, characterized in that: include: A processor and a memory, the memory storing programs or instructions that can be run on the processor, and the programs or instructions when executed by the processor implement the steps of the 2.5D packaging Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: A program or instruction is stored thereon, and when the program or instruction is executed by a processor, the steps of the 2.5D packaging Die-to-Die simultaneous escape wiring method based on a pattern matching binary tree as described in any one of claims 1 to 7 are implemented.

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