Method and device for eliminating rule violation of odd-numbered rings in cooperation with layout and wiring, equipment and medium

Abstract

The invention provides a layout and wiring cooperative odd ring violation elimination method and device, equipment and a medium, and is applied to the technical field of integrated circuit layout and wiring, systematic traversal is carried out on each standard unit, areas where power connection or grounding through holes are possibly placed are created, potential odd ring violation is detected for the areas, and the layout and wiring cooperative odd ring violation elimination method and device are applied to the integrated circuit layout and wiring technology. According to the layout legalization method and the layout legalization system, through a cooperative feedback mechanism between layout and wiring, the odd number ring problem which cannot be solved in the wiring stage can be eliminated in advance, and the layout legalization efficiency is improved. The design efficiency is obviously improved, the design flow of the integrated circuit is optimized, and the design cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit layout and routing, and particularly relates to a method, device, equipment, and medium for jointly eliminating odd-loop violations in layout and routing. Background Art

[0002] With the continuous reduction of semiconductor manufacturing process nodes, the spacing between adjacent vias is getting smaller and smaller, making it difficult to meet the minimum resolution requirements of the lithography system. For this reason, the double-patterning technology (DPT) has emerged. It decomposes the complex pattern originally designed on one mask layer onto multiple different mask layers to ensure that the via spacing within each mask layer is greater than the minimum resolution of the lithography system.

[0003] In integrated circuit design, when an odd number of vias form a closed loop and the spacing between each adjacent via is less than the minimum lithography spacing, these vias cannot be split, and this phenomenon is called "odd-loop violation".

[0004] Currently, the solutions to odd-loop violations mainly focus on the routing stage, that is, during detailed routing, the wires in the area where odd-loop violations occur are removed and re-routed. However, since the power / ground vias (pg vias) are fixed during the layout stage, the existing methods cannot completely eliminate odd-loop violations.

[0005] Based on this, a new integrated circuit layout and routing design method is needed. Summary of the Invention

[0006] In view of this, the embodiments of the present specification provide a method, device, equipment, and medium for jointly eliminating odd-loop violations in layout and routing. By identifying and avoiding potential odd-loop violation problems during the layout stage, the odd-loops that cannot be solved during the routing stage are eliminated, optimizing the integrated circuit design process and improving production efficiency and the quality of the final product.

[0007] The embodiments of the present specification provide the following technical solutions:

[0008] The embodiments of the present specification provide an integrated circuit layout and routing method for jointly eliminating odd-loop violations, including:

[0009] Performing the following traversal on each standard cell to determine the prohibited area where power / ground vias cannot be placed:

[0010] According to the physical structure of the existing vias in the standard cell, create areas where power / ground vias may be placed to obtain candidate areas;

[0011] Perform odd - loop violation detection on the candidate regions to determine whether the pre - placed power - connected or ground - connected vias and the functional vias form an odd - loop violation;

[0012] If an odd - loop violation is formed, mark the corresponding candidate region as a prohibited region so that the placement of power - connected or ground - connected vias in the layout legalization stage skips the prohibited region.

[0013] An embodiment of this specification also provides an integrated - circuit layout and routing collaborative odd - loop violation elimination device, which includes a candidate region generation module and an odd - loop violation detection module;

[0014] The candidate region generation module creates regions where power - connected or ground - connected vias may be placed according to the physical structure of the existing vias in the standard cells to obtain candidate regions;

[0015] The odd - loop violation detection module is used to perform odd - loop violation detection on the candidate regions to determine whether the pre - placed power - connected or ground - connected vias and the functional vias form an odd - loop violation;

[0016] If an odd - loop violation is formed, mark the corresponding candidate region as a prohibited region.

[0017] An embodiment of this specification also provides an electronic device, including:

[0018] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute: the integrated - circuit layout and routing collaborative odd - loop violation elimination method as described in any one of this application.

[0019] An embodiment of this specification also provides a computer storage medium, which stores computer - executable instructions, and when the computer - executable instructions are executed by a processor, they execute: the integrated - circuit layout and routing collaborative odd - loop violation elimination method as described in any one of this application.

[0020] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above - mentioned technical solutions adopted in the embodiments of this specification at least include:

[0021] By systematically traversing each standard cell, regions where power or ground vias can be placed are created, and potential odd - loop violations are detected in these regions. Forbidden regions where power or ground vias cannot be placed are marked, so that these forbidden regions can be avoided when placing power or ground vias during the layout legalization stage. Through the collaborative feedback mechanism between layout and routing, odd - loop problems that cannot be solved during the routing stage can be eliminated in advance, significantly improving the design efficiency, optimizing the integrated - circuit design process, and reducing the design cost. Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 is the method flow of collaborative elimination of odd - loop violations in integrated - circuit layout and routing in the present application Figure 1 ;

[0024] Figure 2 is the flowchart of odd - loop violation detection in the present application;

[0025] Figure 3 is the method flow of collaborative elimination of odd - loop violations in integrated - circuit layout and routing in the present application Figure 2 . Detailed Embodiments

[0026] The embodiments of the present application will be described in detail below with reference to the drawings.

[0027] The following uses specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0028] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is for illustrative purposes only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement an apparatus and / or practice a method. Additionally, this apparatus and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0029] It should also be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of this application. The diagrams only show the components related to this application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that these examples can be practiced without these specific details.

[0031] In the current integrated circuit design process, the placement stage and the routing stage are processed separately and independently.

[0032] The current traditional design process is to perform placement first and then routing, with each stage executed strictly linearly. In the placement legalization stage, the initial placement generated in the placement stage is optimized to meet specific design rules and constraints (such as minimum spacing, alignment requirements, etc.) to determine the final positions of the standard cells; after placement legalization, pin access vias are created for the input / output pins of each standard cell to establish electrical connections in the subsequent routing stage.

[0033] If an odd - loop violation problem (formed by an odd number of vias forming a closed loop with a spacing less than the lithography requirement) is detected in the routing stage, it is necessary to re - route the odd - loop violation area. However, since the power - ground vias (pgvias) are fixed in the placement stage, the odd - loop violation problem caused by them cannot be eliminated by routing adjustment, and repeated rework increases the iteration cost.

[0034] In view of this, the inventors discovered through research and improvement exploration that the current method of removing and rerouting the odd-ring violation areas and simply adjusting the signal vias cannot eliminate the odd-ring violation problem, and unresolved odd-ring violations can lead to lithography failures or electrical shorts, thereby reducing the chip manufacturing yield.

[0035] Based on this, the embodiments of this specification propose a method for collaboratively eliminating odd-ring violations in integrated circuit layout and routing. The overall idea is: first, create pin access vias, then systematically traverse each standard cell, create candidate areas where power or ground vias (Power / Ground via, pg via) may be placed based on the via positions and lithography rules, and perform odd-ring violation detection, mark the candidate areas where odd-ring violations are detected as forbidden areas (forbidden boxes), and then guide the placement of power or ground vias in the layout legalization stage to avoid these prohibited areas, so that the violation areas of pg via can be resolved in the layout stage, avoiding the burden of repairing odd-ring violations encountered in the routing stage, significantly improving the efficiency of the entire design process, reducing design iterations, reducing costs, and ultimately improving the quality and reliability of integrated circuit products.

[0036] It should be noted that the present application creates pin access before the layout legalization stage and determines prohibited areas where power or ground vias cannot be placed, so that the risk of potential odd-numbered ring violations can be considered in the layout stage, and the illegal positions of pg vias can be eliminated in advance, effectively preventing the occurrence of odd-numbered ring violations, solving problems that are difficult to solve in the wiring stage with traditional solutions, and significantly improving the accuracy and reliability of the design.

[0037] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0038] like Figure 1 As shown, the embodiment of this specification provides a method for collaboratively eliminating odd-numbered ring violations in integrated circuit layout and routing, including:

[0039] Perform the following traversal on each standard cell to determine the prohibited areas where power or ground vias cannot be placed:

[0040] Step S1, creating an area where a power supply or ground via may be placed according to the physical structure of the existing via in the standard cell, and obtaining a candidate area;

[0041] Specifically, each standard cell is carefully inspected, and the physical structure of the existing through-holes (such as position and shape information) is used to simulate the placement of power or ground vias (Power / Ground via, pg via) to determine possible candidate areas.

[0042] Step S2: Perform odd - loop violation detection on the candidate regions to determine whether the pre - placed power - supply or ground vias and functional vias form an odd - loop violation.

[0043] If an odd - loop violation is formed, mark the corresponding candidate region as a prohibited region, so that the placement of power - supply or ground vias in the layout legalization stage skips the prohibited region.

[0044] Specifically, perform odd - loop violation detection on these possible candidate regions to evaluate whether placing vias will cause an odd - loop violation with functional vias. If the detection result indicates a violation risk, the corresponding candidate region will be marked as a prohibited region (forbidden box) to guide the subsequent layout process to avoid placing vias in these regions.

[0045] In some embodiments, the standard cells are generated by rotating or flipping the basic cells in the basic cell library.

[0046] Perform the following operations on each basic cell in the basic cell library:

[0047] According to the internal structure of each basic cell, logically deduce the candidate regions where power - supply or ground vias may be placed, perform odd - loop violation detection on the candidate regions, and mark the candidate regions where power - supply or ground vias cannot be placed as prohibited regions.

[0048] Through coordinate transformation, adapt the marked prohibited regions in the basic cell to all standard cells generated by rotation or flipping operations to ensure the correct inheritance of the prohibited regions.

[0049] Specifically, by centrally managing the prohibited regions in the standard cell library design stage, the efficiency and reliability of the layout stage can be significantly improved.

[0050] In the standard cell library, the basic cell (libcell) is the basic cell template that constitutes the standard cell template (such as AND gate, flip - flop, etc.), and has a fixed internal structure (including via positions, metal - layer connections, etc.).

[0051] The standard cells are generated by flipping the libcell at different angles, that is, only changing the orientation of the standard cell to adapt to the layout requirements without changing the relative positions of the vias.

[0052] During the libcell design phase, the pg via regions that may cause odd - loop violations are logically deduced and marked in advance as forbidden regions (forbidden box). Since the standard cells generated by flipping later inherit the internal structure of the libcell, including the relative positions of the vias, the standard cell instances generated by flipping will automatically inherit the forbidden box of the original libcell. That is, there is no need to create a forbidden box for each flipped cell separately. It can be defined only once at the libcell level, simplifying the design process and thus saving a large amount of design time and resources.

[0053] For example, a libcell contains a pg via, and there is an area around it that forms an odd loop (marked as forbidden box). When this libcell is rotated 180° to generate a new standard cell, the position of the pg via will rotate with the overall rotation, that is, the relative position of the forbidden box will also rotate synchronously, so that odd - loop violations can still be effectively avoided in the new direction.

[0054] In some embodiments, when detecting odd - loop violations in the candidate region, if the functional via only has obstacle vias, the current power - connected or ground - connected via is detected for odd - loop with all obstacle vias. If an odd - loop violation occurs, the corresponding candidate region is marked as a forbidden region;

[0055] If the functional via includes obstacle vias and pin - access vias, the current power - connected or ground - connected via, all obstacle vias, and all pin - access vias are detected for odd - loop in sequence. If the combinations of all pin - access vias all result in odd - loop violations, the corresponding candidate region is marked as a forbidden region.

[0056] As Figure 2 shown, each pg via is detected for odd - loop with other functional vias (such as obstacle vias, pin - access vias). If there is no pin - access via, the current pg via is detected for odd - loop with all obstacle vias (obs via) in the standard cell. Check whether the distance between the pg via and all obs vias is less than the minimum distance of the lithography process. If a closed loop composed of an odd number of vias is formed, that is, a violation occurs, the pgvia region is marked as forbidden box.

[0057] For example: The current pg via forms a triangular loop with two obs vias and the distance violates the rule, so it is forbidden to place a pg via here.

[0058] If there are pin access vias, perform odd - loop detection on the current pg via, all obstacle vias (obsvia) in the standard cell, and each pin access via on the pin in sequence. If an odd loop is generated for each pin access via, it means there is no selectable pin access via on that pin, and the pg via area is marked as a forbidden box.

[0059] For example, if the current pg via forms three odd loops with an obs via and three different pin access vias respectively, placing a pg via in this area is prohibited, and this area is marked as a forbidden box.

[0060] If there is at least one pin access via that does not form an odd loop, a pg via can still be placed in this area.

[0061] Combined with the above - mentioned embodiments, after all standard cells are traversed, as Figure 3 shown, all forbidden areas are passed to the layout legalization stage to guide the placement position of power - or ground - connection vias (pg via) to avoid the forbidden areas, so as to avoid odd - loop violations that cannot be eliminated during the detailed routing stage after layout is completed.

[0062] In implementation, during the routing stage, detect odd - loop violations that may be caused by the fixation of pg via, mark the violated areas as forbidden areas (forbidden box), and feedback these forbidden areas to the layout legalization stage.

[0063] It is used to guide the placement position of pg via. That is, during the layout legalization stage, skip the forbidden areas and select other legal positions to place pg via.

[0064] When the layout legalization stage is about to place a pg via, it will check whether the candidate position is within the previously marked forbidden area. If the candidate position is a forbidden area, skip this position and select other legal areas to place pg via, fundamentally solving the problem of odd - loop violations, thus avoiding odd - loop problems that cannot be repaired due to the fixation of pg via during the detailed routing stage, and improving the quality of integrated - circuit design and the success rate of manufacturing.

[0065] Based on the same inventive concept, the present application also provides an integrated - circuit layout - and - routing collaborative odd - loop - violation elimination device, which includes: a candidate - area generation module and an odd - loop - violation detection module;

[0066] The candidate region generation module creates regions where power supply or ground vias may be placed based on the physical structure of existing vias in standard cells, obtaining candidate regions.

[0067] The odd loop violation detection module is used to detect odd loop violations in the candidate regions, and determine whether odd loop violations are formed between the pre-placed power supply or ground vias and functional vias.

[0068] If an odd loop violation is formed, the corresponding candidate region is marked as a prohibited region.

[0069] In some embodiments, the integrated circuit layout and routing collaborative odd loop violation elimination device further includes:

[0070] A prohibited region transfer module;

[0071] The prohibited region transfer module is used to transfer all prohibited regions to the layout legalization stage after all standard cells have been traversed, to guide the placement of power supply or ground vias.

[0072] In some embodiments, the odd loop violation detection module also determines the type of functional vias. If only obstacle vias exist, odd loop detection is performed between the current power supply or ground via and all obstacle vias. If an odd loop violation occurs, the corresponding candidate region is marked as a prohibited region;

[0073] If both obstacle vias and pin access vias exist, odd loop detection is performed in sequence between the current power supply or ground via, all obstacle vias, and all pin access vias. If all combinations of pin access vias result in odd loop violations, the corresponding candidate region is marked as a prohibited region.

[0074] Based on the same inventive concept, the present application also provides an electronic device, including:

[0075] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit layout and routing collaborative odd loop violation elimination method as described in any one of the embodiments of the present application, or the integrated circuit layout legalization stage placement method.

[0076] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they execute: the integrated circuit layout and routing collaborative odd loop violation elimination method as described in any one of the embodiments of the present application, or the integrated circuit layout legalization stage placement method.

[0077] It should be noted that the computer storage medium may include, but is not limited to: portable disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0078] In a possible implementation manner, the present invention can also provide a form of implementing data processing as a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute several steps in the method described in any one of the foregoing embodiments.

[0079] Among them, the program code for executing the present invention can be written in any combination of one or more programming languages. The program code can be completely executed on the user device, partially executed on the user device, executed as an independent software package, partially executed on the user device and partially executed on a remote device, or completely executed on a remote device.

[0080] According to the odd-ring rule, the present application creates non-placeable regions for pg vias for each standard cell. The generation of odd-ring violations is avoided in the layout stage, and odd-rings that cannot be solved in the routing stage are eliminated, greatly improving the efficiency and quality of detecting and eliminating odd-ring violations in the detailed routing stage. At the same time, the present invention is also applicable to Triple-Patterning Technology (MPT).

[0081] In this specification, the same or similar parts among the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the foregoing embodiments.

[0082] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for collaboratively eliminating odd-numbered loop violations in integrated circuit layout and routing, characterized in that: include: Perform the following traversal on each standard cell to determine the prohibited areas where power or ground vias cannot be placed: According to the physical structure of the existing through holes in the standard cell, create an area where the power supply or ground through hole may be placed to obtain a candidate area; Performing odd-ring violation detection on the candidate area to determine whether the pre-placed power supply or ground vias and functional vias form an odd-ring violation; If an odd-numbered ring violation is formed, the corresponding candidate area is marked as a prohibited area, so that the layout legalization stage skips the prohibited area when placing power or ground vias.

2. The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations method according to claim 1, characterized in that: Generate the standard cell by rotating or flipping a basic cell in a basic cell library; For each basic unit in the basic unit library, the following operations are performed: According to the internal structure of each basic unit, a candidate area where a power supply or ground via may be placed is logically deduced, and an odd-ring violation detection is performed on the candidate area, and the candidate area where a power supply or ground via cannot be placed is marked as a prohibited area; The marked forbidden areas in the base cell are adapted to all standard cells generated by rotation or flipping operations through coordinate transformation to ensure the correct inheritance of the forbidden areas.

3. The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations method according to claim 1, characterized in that: When performing odd-ring violation detection on the candidate area, if the functional through hole only has an obstacle through hole, the current power supply or ground through hole and all obstacle through holes are subjected to odd-ring detection, and if an odd-ring violation occurs, the corresponding candidate area is marked as a prohibited area; If the functional through holes include obstacle through holes and pin access through holes, the current power or ground through hole, all obstacle through holes and all pin access through holes are subjected to odd-numbered ring detection in turn. If the combination of all pin access through holes results in an odd-numbered ring violation, the corresponding candidate area is marked as a prohibited area.

4. The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations method according to claim 1, characterized in that: The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations method also includes: After all standard cells are traversed, all prohibited areas are passed to the layout legalization stage to guide the placement of power or ground vias to avoid the prohibited areas.

5. An integrated circuit layout and routing collaborative elimination of odd-numbered loop violations device, characterized in that: The integrated circuit layout and routing collaborative elimination of odd-numbered loop violation device comprises: a candidate area generation module and an odd-numbered loop violation detection module; The candidate region generation module creates regions where power or ground vias may be placed based on the physical structure of existing vias in the standard cell to obtain candidate regions; The odd-ring violation detection module is used to perform odd-ring violation detection on the candidate area to determine whether the pre-placed power supply or ground vias and functional vias form an odd-ring violation; If an odd ring violation is formed, the corresponding candidate area is marked as a prohibited area.

6. The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations device according to claim 5, characterized in that: The integrated circuit layout and routing collaborative elimination of odd-numbered ring violations device also includes: a prohibited area transfer module; The forbidden area transfer module is used to transfer all forbidden areas to the layout legalization stage after all standard cells are traversed, so as to guide the power supply or grounding through holes to avoid the forbidden areas when they are placed.

7. The integrated circuit layout and routing collaborative elimination of odd-numbered loop violations device according to claim 5, characterized in that: The odd-numbered loop violation detection module further determines the type of functional through holes. If only obstacle through holes exist, the current power supply or ground through hole and all obstacle through holes are subjected to odd-numbered loop detection. If an odd-numbered loop violation occurs, the corresponding candidate area is marked as a prohibited area. If both obstacle vias and pin access vias exist, the current power or ground via, all obstacle vias, and all pin access vias are sequentially subjected to odd-numbered loop detection. If the combination of all pin access vias results in an odd-numbered loop violation, the corresponding candidate area is marked as a prohibited area.

8. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit layout and routing collaborative elimination of odd-loop violations method as described in any one of claims 1-4.

9. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, they perform: the integrated circuit layout and routing collaborative elimination of odd-loop violations method according to any one of claims 1-4.

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