Integrated circuit chip timing optimization method, apparatus, device, and medium

Abstract

The application relates to a method and device, equipment and medium for timing optimization of an integrated circuit core particle, the method comprising the following steps: based on a back-end layout result of the core particle, analyzing timing of the core particle according to total negative timing margin of all paths in setup time, total negative timing margin of all paths in hold time, negative timing margin of all paths in the worst case of the setup time and negative timing margin of all paths in the worst case of the hold time generated by an OpenSTA tool, and when a violation occurs, readjusting a preliminary core particle division scheme to determine an iterative division scheme until timing of the core particle meets a requirement; when the iterative division scheme meets the timing optimization requirement, recording and saving the current iterative division scheme, and continuing to perform regular division on integrated circuit modules at the same level until all preliminary core particle division schemes at the level are completely traversed. The application can greatly shorten a design cycle and significantly improve automation and flexibility.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to an integrated circuit chip timing optimization method, corresponding apparatus, electronic equipment, and computer-readable storage medium. Background Technology

[0002] With the continuous development of integrated circuit technology, Moore's Law is gradually approaching its physical limits, posing unprecedented challenges and opportunities to the global semiconductor industry, especially China's chip industry. In the era dominated by American companies, Moore's Law promoted the construction of its IC industry's software and hardware ecosystem. However, as technology nodes continue to shrink and manufacturing costs rise sharply, issues such as chip yield, thermal management, poor scalability, verification challenges, and integration difficulties are becoming increasingly prominent.

[0003] In the post-Moore's Law era, to perpetuate Moore's Law and address issues such as short-channel effects, high leakage current, and subthreshold swing limitations faced by nanoscale devices, new device technologies, marked by FinFET technology, have emerged. The transition of CMOS devices from planar to three-dimensional FinFET is an inevitable choice for solving power consumption problems, while traditional CMOS miniaturization may be facing its end. Devices based on new principles, structures, or materials will break through the constraints of Moore's Law, bringing new solutions for performance improvements.

[0004] Against this backdrop, recent research focus in academia has shifted to Chiplet technology, proposing new chip building schemes that fundamentally change the future direction of chip design. Chiplet technology optimizes performance and cost by combining chips with different functions. This modular design not only improves design flexibility and scalability but also promotes innovation and diversification in chip design.

[0005] However, in the crucial technology of chip partitioning and placement, existing technologies mainly focus on how to effectively partition chips based on their physical and timing constraints to optimize the overall chip performance, power consumption, and area. But current chip partitioning is based on manual partitioning using design experience. This method lacks a hierarchical optimization strategy, making it impossible to effectively optimize chips at different levels. Furthermore, the separation of physical and timing optimization, and the lack of a method that comprehensively considers both, may result in suboptimal timing performance when the placement scheme meets physical constraints. In addition, existing technologies often employ a one-time partitioning method, lacking an iterative optimization process, and cannot dynamically adjust based on timing results, making it difficult to achieve optimal timing performance.

[0006] In summary, current core partitioning methods in existing technologies are all based on manual partitioning using design experience. This method lacks a hierarchical optimization strategy, resulting in the inability to effectively optimize cores at different levels. Furthermore, the separation of physical and temporal optimization, and the lack of a comprehensive approach to both, may lead to suboptimal temporal performance in layout schemes while meeting physical constraints. The applicant has explored solutions to address these issues. Summary of the Invention

[0007] The purpose of this application is to solve the above-mentioned problems by providing an integrated circuit chip timing optimization method, corresponding apparatus, electronic device and computer-readable storage medium.

[0008] To achieve the various objectives of this application, the following technical solution is adopted:

[0009] A timing optimization method for integrated circuit chips, proposed to meet one of the purposes of this application, includes:

[0010] In response to the instruction to perform chip timing optimization on the integrated circuit, the system obtains the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and uses logic hierarchy analysis to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine a preliminary logic partitioning scheme.

[0011] Based on the aforementioned preliminary logical partitioning scheme, combined with physical core partitioning, a preliminary core partitioning scheme is generated according to area constraints. The DREAMPlace tool is called to perform core layout, and the total negative timing margin and worst-case negative timing margin on all paths within the core are optimized in the timing optimization module to determine the core back-end layout result.

[0012] Based on the core backend layout results, the timing of the core is analyzed according to the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time of all paths generated by the OpenSTA tool. When a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements.

[0013] When the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all preliminary chip partitioning schemes at that level have been completely traversed.

[0014] Optionally, after obtaining the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and using logical hierarchy analysis to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine a preliminary logical partitioning scheme, the following steps are included:

[0015] In the initial stage, a preliminary logical partitioning scheme is obtained and used as the initial classification set;

[0016] Using hierarchical information and input module partitioning constraints, the preliminary logical partitioning scheme is integrated into the initial classification set, and combined with physical core partitioning, the preliminary core partitioning scheme is generated based on area constraints.

[0017] Optionally, the timing analysis of the core is performed based on the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time of all paths generated by the OpenSTA tool. If a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements. This step includes:

[0018] Write and use the corresponding TCL scripts in the OpenSTA tool to retrieve the underlying files of the required environment and call the corresponding timing analysis module inside OpenSTA to perform the final timing analysis and obtain the corresponding quantization results;

[0019] By analyzing four data points generated by OpenSTA—total negative timing margin in setup time, total negative timing margin in hold time, negative timing margin in worst-case setup time of all paths, and negative timing margin in worst-case hold time of all paths—it is determined whether the timing of the chip has reached the ideal state.

[0020] Optionally, the step of determining whether the timing of the chip has reached the ideal state by analyzing four data points: the total negative timing margin of all paths generated by OpenSTA in terms of setup time, the total negative timing margin of all paths in terms of hold time, the negative timing margin of the worst-case setup time of all paths, and the negative timing margin of the worst-case hold time of all paths, includes:

[0021] Determine whether all four data points generated by OpenSTA are positive: the total negative timing margin in setup time for all paths, the total negative timing margin in hold time for all paths, the negative timing margin in worst-case setup time for all paths, and the negative timing margin in worst-case hold time for all paths.

[0022] If all values ​​are positive, it means that the timing of all paths meets the requirements, and the timing of this chip has reached an ideal state.

[0023] If a negative number appears, it indicates that the chip has at least one path violation, and the timing of the chip is not ideal.

[0024] Optionally, when the iterative partitioning scheme meets the timing optimization requirements, the following steps are taken: recording and saving the current iterative partitioning scheme, and continuing to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed:

[0025] If at least one path of the core is violated, then return to the initial preliminary logical partitioning scheme and readjust the partitioning strategy;

[0026] The step of re-executing the logical hierarchy analysis to initially divide each integrated circuit module according to the performance parameters, the power consumption parameters, and the area parameters is to determine the initial logical partitioning scheme.

[0027] Then, check four data points generated by the OpenSTA tool: the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of all paths in the worst case of setup time, and the negative timing margin of all paths in the worst case of hold time. Continue this process until the timing of the chip meets the requirements.

[0028] When the result is optimal, the current partitioning scheme is recorded and saved, and the modules at the same level are further regularized and partitioned until all possible partitions at that level have been completely traversed.

[0029] Optionally, when the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all preliminary chip partitioning schemes at that level have been completely traversed. This includes the following steps:

[0030] Obtain the preset full-chip gate netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file;

[0031] Based on the full-chip gate netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file, the total negative timing margin and worst-case negative timing margin on all paths within the chip are progressively optimized in a hierarchical iteration process to determine the layout file and chip partition file corresponding to the chip.

[0032] Optionally, when the iterative partitioning scheme meets the timing optimization requirements, the step of recording and saving the current iterative partitioning scheme, and continuing to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed includes:

[0033] The connection ratio in the module set is calculated based on the floorplan data before the input layout and the given chip I / O positions, and is used as the preference candidate set index.

[0034] Combining the size of the core region of the core particle, the minimum area of ​​any core particle, the utilization rate of each core particle and the aspect ratio constraint, the layout is proportionally allocated according to the total area of ​​the divided modules. At the same time, a relaxation coefficient is added to achieve the generality of the layout scheme. Then, the modules with higher preference candidate index values ​​are prioritized to be divided into adjacent parts, and the corresponding physical area scheme is output.

[0035] An integrated circuit chip timing optimization apparatus provided for another purpose of this application includes:

[0036] The preliminary logic partitioning module is configured to respond to instructions for chip timing optimization of integrated circuits, obtain the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and use logic hierarchy analysis to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine the preliminary logic partitioning scheme;

[0037] The core particle timing optimization module is configured to generate a preliminary core particle partitioning scheme based on the preliminary logical partitioning scheme and combined with the physical core particle partitioning, according to the area constraints, call the DREAMPlace tool to perform core particle layout, and optimize the total negative timing margin and worst negative timing margin on all paths inside the core particle in the timing optimization module to determine the core particle back-end layout result.

[0038] The partitioning scheme adjustment module is configured to analyze the timing of the core based on the core backend layout results, according to the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of the worst-case setup time of all paths, and the negative timing margin of the worst-case hold time of all paths generated by the OpenSTA tool. When a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements.

[0039] The partitioning scheme traversal module is configured to record and save the current iterative partitioning scheme when the iterative partitioning scheme meets the timing optimization requirements, and continue to perform regular partitioning on the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed.

[0040] An electronic device provided for another purpose of this application includes a central processing unit and a memory, wherein the central processing unit is configured to invoke and run a computer program stored in the memory to perform the steps of the integrated circuit chip timing optimization method of this application.

[0041] A computer-readable storage medium is provided for another purpose of this application, which stores, in the form of computer-readable instructions, a computer program implemented according to the integrated circuit chip timing optimization method, which, when called by a computer, executes the steps included in the corresponding method.

[0042] Compared to existing technologies, the current core partitioning methods in this application are all based on design experience and are done manually. This method lacks a hierarchical optimization strategy, resulting in the inability to effectively optimize cores at different levels. Furthermore, the separation of physical and timing optimization, and the lack of a comprehensive approach that considers both, may lead to suboptimal timing performance when the layout scheme meets physical constraints. This application addresses these issues by providing the following beneficial effects, including but not limited to:

[0043] Firstly, this application can significantly improve the efficiency of integrated circuit chip timing optimization. Existing chip partitioning and layout optimization methods often rely on manual experience and simple optimization algorithms. This manual partitioning method has limitations, especially when facing complex designs and changing constraints, where it is inefficient and prone to missing the optimal solution. However, through a hierarchical iterative strategy, this application first performs a coarse partitioning at a high level and then gradually refines it at a lower level, which can efficiently solve complex problems. This staged optimization approach greatly improves the speed of chip partitioning and also improves the accuracy of the chip partitioning process.

[0044] Secondly, the integrated circuit chip timing optimization method of this application can comprehensively optimize both physical and timing constraints. In the traditional chip partitioning process, physical and timing constraints are often considered separately. This may lead to the neglect of timing performance while meeting physical layout requirements, or vice versa, resulting in the final design failing to meet both key requirements simultaneously. However, this application can consider both physical and timing constraints simultaneously. By comprehensively optimizing both during the design process, it can better balance the physical layout and timing performance of the chip, thereby reducing performance trade-offs. This comprehensive approach ensures design feasibility and achieves more optimized overall performance, meeting the demands of modern chip design for high performance and low power consumption.

[0045] Third, the integrated circuit chip timing optimization method of this application can significantly improve automation and flexibility. Existing chip partitioning methods usually require a lot of manual intervention and adjustments. Although some optimizations can be made based on design experience, they still have the limitation of being highly dependent on human intervention and are not easy to adapt to different design requirements and constraints. In contrast, this application can quickly respond to changes in different designs and automatically complete partitioning and optimization. This not only improves the efficiency of the design process but also greatly enhances the flexibility of the system, enabling it to adapt to more diverse needs and design environments. At the same time, it reduces manual intervention and lowers the risk of human error.

[0046] Fourth, the integrated circuit chip timing optimization method of this application can significantly shorten the design cycle. In traditional design processes, especially in the chip partitioning and placement stages, it may require multiple iterations to find a satisfactory solution, which is time-consuming and prone to design rework. By introducing hierarchical optimization and a strategy that comprehensively considers physical and timing constraints, this application reduces the number of design iterations and can identify and solve potential problems in the early stages of design. Early optimization reduces the need for later modifications, thereby significantly shortening the design cycle. This has significant commercial value for the rapidly developing semiconductor industry, helping companies gain a competitive edge in a fiercely competitive market.

[0047] Furthermore, compared to existing technologies, this application introduces key technologies such as hierarchical iterative optimization, comprehensive physical and timing constraints, and automated design processes, providing significant improvements in chip partitioning and layout optimization. These improvements not only enhance design efficiency and quality but also shorten the design cycle, reduce human error, and increase design flexibility and adaptability. These effects enable chip design to better meet the challenges of the post-Moore's Law era, fulfilling the requirements for higher performance, lower power consumption, and more complex designs. Attached Figure Description

[0048] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0049] Figure 1 This is a flowchart illustrating the integrated circuit chip timing optimization method in the embodiments of this application;

[0050] Figure 2 This is an exemplary network architecture used in the integrated circuit chip timing optimization system in the embodiments of this application;

[0051] Figure 3 This is a schematic diagram showing how modules with similar functions are grouped together in the same core in an embodiment of this application;

[0052] Figure 4This is a schematic block diagram of the integrated circuit chip timing optimization device in the embodiments of this application;

[0053] Figure 5 This is a schematic diagram of the structure of the computer device in the embodiments of this application. Detailed Implementation

[0054] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0055] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0056] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0057] Those skilled in the art will understand that the terms "client," "terminal," and "terminal device" as used herein include both devices that receive wireless signals, devices that only possess wireless signal receiver capabilities without transmission capabilities, and devices with receiving and transmitting hardware, devices that have receiving and transmitting hardware capable of bidirectional communication over a bidirectional communication link. Such devices may include: cellular or other communication devices such as personal computers or tablets, having single-line displays, multi-line displays, or cellular or other communication devices without multi-line displays; PCS (Personal Communications Service) that can combine voice, data processing, fax, and / or data communication capabilities; PDA (Personal Digital Assistant) that may include a radio frequency receiver, pager, internet / intranet access, web browser, notepad, calendar, and / or GPS (Global Positioning System) receiver; and conventional laptops and / or handheld computers or other devices that have and / or include radio frequency receivers. As used herein, "client," "terminal," and "terminal device" can be portable, transportable, installed in a means of transportation (air, sea, and / or land), or suitable and / or configured to operate locally and / or in a distributed manner, operating in any other location on Earth and / or in space. "Client," "terminal," and "terminal device" as used herein can also be a communication terminal, an internet access terminal, or a music / video playback terminal, such as a PDA, a MID (Mobile Internet Device), and / or a mobile phone with music / video playback capabilities, or a smart TV, set-top box, etc.

[0058] The hardware referred to by the names "server," "client," and "service node" in this application is essentially an electronic device with the equivalent capabilities of a personal computer. It is a hardware device with the necessary components revealed by the von Neumann architecture, such as a central processing unit (including an arithmetic logic unit and a control unit), memory, input devices, and output devices. The computer program is stored in its memory, and the central processing unit loads the program stored in the secondary storage into the main memory to run it, execute the instructions in the program, and interact with the input and output devices to complete specific functions.

[0059] It should be noted that the concept of "server" used in this application can also be extended to the case of server clusters. Based on the network deployment principles understood by those skilled in the art, the servers should be logically divided. Physically, these servers can be independent of each other but accessible through interfaces, or they can be integrated into a single physical computer or a computer cluster. Those skilled in the art should understand this flexibility and should not use it to constrain the implementation of the network deployment method in this application.

[0060] One or more of the technical features of this application, unless explicitly specified herein, can be deployed on a server and accessed by a client remotely calling the online service interface provided by the server, or can be directly deployed and run on a client for access.

[0061] Unless otherwise specified, the neural network models referenced or potentially referenced in this application may be deployed on a remote server and invoked remotely on the client, or deployed on a client with the capability to invoke directly. In some embodiments, when running on the client, the corresponding intelligence may be acquired through transfer learning in order to reduce the requirements on the client's hardware resources and avoid excessive consumption of the client's hardware resources.

[0062] Unless otherwise specified, all data involved in this application may be stored remotely on a server or on a local terminal device, as long as it is suitable for use by the technical solution of this application.

[0063] Those skilled in the art will understand that although the various methods in this application are described based on the same concept and thus present commonality among them, they can be performed independently unless otherwise specified. Similarly, the various embodiments disclosed in this application are all based on the same inventive concept; therefore, concepts expressed in the same way, as well as concepts that are appropriately changed for convenience but are expressed differently, should be understood equivalently.

[0064] Unless otherwise expressly stated, the various embodiments disclosed in this application can be combined in a cross-cutting manner to flexibly construct new embodiments, as long as such combination does not depart from the inventive spirit of this application and can meet the needs of the prior art or solve a certain deficiency in the prior art. Those skilled in the art should be aware of such modifications.

[0065] Please see Figure 1 In one embodiment of the integrated circuit chip timing optimization method of this application, the method includes:

[0066] Step S10: In response to the instruction to perform chip timing optimization on the integrated circuit, obtain the performance parameters, power consumption parameters and area parameters of each integrated circuit module, and use logic hierarchy analysis to perform preliminary division of each integrated circuit module based on the performance parameters, power consumption parameters and area parameters to determine a preliminary logic division scheme;

[0067] Please see Figure 2 The integrated circuit chip timing optimization system in the terminal device can respond to the instruction to optimize the chip timing of the integrated circuit, obtain the performance parameters, power consumption parameters and area parameters of each integrated circuit module, and use logic hierarchy analysis to perform preliminary division of each integrated circuit module based on the performance parameters, power consumption parameters and area parameters to determine the preliminary logic division scheme;

[0068] In some embodiments, the chip-level hierarchical iterative timing optimization architecture mainly includes: The chip-level hierarchical iterative timing optimization architecture is a sophisticated integrated circuit design flow designed to optimize performance, power consumption, and area (PPA). This architecture improves the efficiency and quality of chip design through collaboratively working modules. Specifically, the information acquisition module is responsible for processing input data and constraints, including data format conversion and information organization, ensuring the accuracy of subsequent processing. The partitioning module, based on a predefined hierarchical structure and constraints, allocates modules from the .def file to corresponding chiplets, constructing the basic framework for modular design and optimization. The placement module performs timing optimization on the initial partitioning scheme, ensuring that the physical placement scheme meets the timing requirements of signal transmission, thereby reducing latency and improving overall performance. The iteration module further refines this, optimizing the partitioning scheme through hierarchical iteration to obtain the optimal backend partitioning and module placement scheme. Furthermore, the architecture integrates an interruption mechanism for optimizing the number of iterations. This mechanism can automatically terminate the iteration process when preset conditions are met, thereby effectively controlling the design cycle and cost while ensuring design quality.

[0069] Step S20: Based on the preliminary logical partitioning scheme, combined with physical core partitioning, a preliminary core partitioning scheme is generated according to the area constraint. The DREAMPlace tool is called to perform core layout, and the total negative timing margin and worst-case negative timing margin on all paths inside the core are optimized in the timing optimization module to determine the core back-end layout result.

[0070] The performance parameters, power consumption parameters, and area parameters of each integrated circuit module are obtained. Logical hierarchy analysis is used to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine a preliminary logical partitioning scheme. Based on the preliminary logical partitioning scheme and combined with physical chip partitioning, a preliminary chip partitioning scheme is generated according to area constraints. The DREAMPlace tool is called to perform chip placement. In the timing optimization module, the total negative timing margin and worst-case negative timing margin on all paths inside the chip are optimized to determine the chip back-end placement result.

[0071] In some embodiments, after obtaining the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and using logical hierarchy analysis to initially divide the integrated circuit modules according to the performance parameters, power consumption parameters, and area parameters to determine a preliminary logical partitioning scheme, the following steps are included:

[0072] Step S201: Obtain a preliminary logical partitioning scheme in the initial stage and use it as the initial classification set;

[0073] Step S202: Using hierarchical information and input module partitioning constraints, the preliminary logical partitioning scheme is integrated into the initial classification set, and combined with physical core partitioning, the preliminary core partitioning scheme is generated based on area constraints.

[0074] Specifically, in the front-end design phase, the architecture performs preliminary partitioning of integrated circuit modules through logical hierarchy analysis to meet performance, power consumption, and area (PPA) standards. The preliminary logical partitioning scheme is obtained in the initial stage and used as the initial classification set. By utilizing hierarchical information, the algorithm can effectively compress the search space and reduce computational complexity. Then, based on the input module partitioning constraints, the algorithm integrates the logical partitioning scheme into the initial classification set and, combined with physical chip partitioning, generates an initial chip partitioning scheme based on area constraints.

[0075] After obtaining the initial partitioning scheme, the DREAMPlace tool is used to perform chip placement in conjunction with the process documents (lef, lib), and the partitioned chip scheme is physically laid out. Simultaneously, the built-in timing optimization module optimizes the TNS (Total Negative Slack) and WNS (Worst Negative Slack) within the chip to obtain the chip backend placement result. Here, TNS (Total Negative Slack) represents the total negative timing margin across all paths within the chip, and WNS (Worst Negative Slack) represents the worst-case negative timing margin across all paths within the chip.

[0076] Step S30: Based on the core back-end layout results, analyze the timing of the core according to the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of the worst-case setup time of all paths, and the negative timing margin of the worst-case hold time of all paths generated by the OpenSTA tool. If a violation occurs, readjust the initial core partitioning scheme to determine an iterative partitioning scheme until the timing of the core meets the requirements.

[0077] Based on the initial logical partitioning scheme, combined with physical core partitioning, an initial core partitioning scheme is generated according to area constraints. The DREAMPlace tool is called for core placement, and the total negative timing margin and worst-case negative timing margin on all paths within the core are optimized in the timing optimization module. After determining the core backend placement result, based on the core backend placement result, the timing of the core is analyzed according to the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time generated by the OpenSTA tool. When a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements.

[0078] In some embodiments, the timing analysis of the core is performed based on the total negative timing margin in setup time of all paths generated by the OpenSTA tool, the total negative timing margin in hold time of all paths, the worst-case negative timing margin in setup time of all paths, and the worst-case negative timing margin in hold time of all paths. The step of readjusting the initial core partitioning scheme to determine an iterative partitioning scheme when a violation occurs, until the timing of the core meets the requirements, includes:

[0079] Step S301: Write and use the corresponding tcl script in the OpenSTA tool to retrieve the underlying files of the required environment and call the corresponding timing analysis module inside OpenSTA to perform the final timing analysis and obtain the corresponding quantization results.

[0080] Step S302: By analyzing four data points generated by OpenSTA—total negative timing margin in setup time, total negative timing margin in hold time, negative timing margin in worst-case setup time of all paths, and negative timing margin in worst-case hold time of all paths—it is determined whether the timing of the chip has reached the ideal state.

[0081] In a further embodiment, the step of determining whether the timing of the chip has reached the ideal state by analyzing four data points: the total negative timing margin of all paths generated by OpenSTA in terms of setup time, the total negative timing margin of all paths in terms of hold time, the negative timing margin of all paths in the worst-case setup time, and the negative timing margin of all paths in the worst-case hold time. This includes:

[0082] Step S3021: Determine whether the four data points generated by OpenSTA are all positive: the total negative timing margin in setup time for all paths, the total negative timing margin in hold time for all paths, the negative timing margin in worst-case setup time for all paths, and the negative timing margin in worst-case hold time for all paths.

[0083] Step S3022: If all are positive numbers, it means that the timing of all paths meets the requirements, and the timing of the chip has reached the ideal state.

[0084] Step S3023: If a negative number appears, it means that the chip has at least one path violation, and the timing of the chip is not ideal.

[0085] Specifically, the corresponding Tcl scripts are written and used in the OpenSTA tool to retrieve the underlying files of the required environment and call the corresponding timing analysis module inside OpenSTA to perform the final timing analysis, and then obtain the corresponding quantization results. By analyzing the four data points TNS_early, TNS_late, WNS_early, and WNS_late generated by OpenSTA, it is determined whether the timing of the chip has reached the ideal state, providing accurate timing basis for iterative optimization. Among them, WNS_late represents the negative timing margin in the worst case of setup time in all paths, TNS_late represents the total negative timing margin in setup time of all paths, WNS_early represents the negative timing margin in the worst case of hold time in all paths, and TNS_early represents the total negative timing margin in hold time of all paths.

[0086] Determine whether the four data points TNS_early, TNS_late, WNS_early, and WNS_late generated by the OpenSTA tool are all positive. If they are all positive, it means that the timing of all paths of the chip meets the requirements. If a negative number appears, it means that at least one path of the chip has a violation. This is used to determine whether the timing of the chip has reached the ideal state, providing accurate timing basis for iterative optimization.

[0087] During the core-particle partitioning stage, hierarchical iteration is completed, allowing for cross-core-particle layout optimization. The iterative algorithm utilizes module hierarchical information, treating the module hierarchy as set information, and partitions each component into sets based on this hierarchical information. For example... Figure 3 As shown, hierarchical modules are arranged in sets from low to high, and multiple sets of low-level modules are gradually merged. Modules with similar functions are placed in the same core to optimize timing performance.

[0088] Step S40: When the iterative partitioning scheme meets the timing optimization requirements, record and save the current iterative partitioning scheme, and continue to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at this level have been completely traversed.

[0089] Based on the chip backend layout results, the timing of the chip is analyzed according to the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time of all paths generated by the OpenSTA tool. When violations occur, the initial chip partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the chip meets the requirements. When the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all initial chip partitioning schemes at that level have been completely traversed.

[0090] In some embodiments, when the iterative partitioning scheme meets the timing optimization requirements, the step of recording and saving the current iterative partitioning scheme, and continuing to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed includes:

[0091] Step S401: If at least one path of the core particle is violated, then return to the initial preliminary logical partitioning scheme and readjust the partitioning strategy;

[0092] Step S402: Re-execute the step of using logical hierarchy analysis to initially divide each integrated circuit module according to the performance parameters, the power consumption parameters and the area parameters to determine the preliminary logical partitioning scheme;

[0093] Step S403: Then check the four data points generated by the OpenSTA tool: total negative timing margin in setup time for all paths, total negative timing margin in hold time for all paths, negative timing margin in worst-case setup time for all paths, and negative timing margin in worst-case hold time for all paths. Continue this process until the timing of the chip meets the requirements.

[0094] Step S404: When the result reaches the optimal, the current partitioning scheme is recorded and saved, and the modules at the same level are further regularized and partitioned until all possible partitions at that level have been completely traversed.

[0095] In a further embodiment, when the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all preliminary chip partitioning schemes at that level have been completely traversed. This includes the following steps:

[0096] Step S4001: Obtain the preset full-chip gate circuit netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file;

[0097] Step S4002: Based on the full-chip gate circuit netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file, perform stepwise timing optimization of the total negative timing margin and worst-case negative timing margin on all paths within the chip in hierarchical iteration, so as to determine the layout file and chip partition file corresponding to the chip.

[0098] In a further embodiment, when the iterative partitioning scheme meets the timing optimization requirements, the step of recording and saving the current iterative partitioning scheme, and continuing to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed includes:

[0099] Step S100: Calculate the connection ratio in the module set based on the floorplan data before the input layout and the given chip I / O positions, as the preference candidate set index;

[0100] Step S200: Combining the size of the core region of the core particle, the minimum area of ​​any core particle, the utilization rate of each core particle and the aspect ratio constraint, the total area of ​​the divided modules is allocated proportionally, and a relaxation coefficient is added at the same time to achieve the generality of the layout scheme. Then, the modules with higher preference candidate index values ​​are prioritized to be divided into adjacent parts, and the corresponding physical area scheme is output.

[0101] Specifically, after initial combination schemes are formed, these schemes are incorporated into a candidate set and iterated within a compressed hierarchical design space to explore partitioning schemes for each core particle. This iterative process aims to achieve time-series optimization across core particles. In each iteration, the partitioning schemes are laid out using the DREAMPlace tool, and corresponding evaluation metrics are generated.

[0102] When the optimal result is achieved, the current partitioning scheme is recorded and saved. Subsequently, the algorithm continues to regularize and partition modules at the same level until all possible partitions at that level have been completely traversed. This process achieves rapid boundary convergence based on the hierarchical structure, providing a foundation for iterative advancement of the partitioning scheme to higher levels. Simultaneously, this optimization process also involves layout optimization within the chip and across chip components, considering the clustering characteristics of the chip system. Throughout the iteration process, this architecture comprehensively considers the full-chip gate netlist file, process file, layout file, timing constraint file, physical constraint file, and partitioning constraint file, achieving gradual timing optimization of TNS and WNS in hierarchical iteration.

[0103] By analyzing four data points generated by the OpenSTA tool—total negative timing margin in setup time, total negative timing margin in hold time, negative timing margin in worst-case setup time of all paths, and negative timing margin in worst-case hold time of all paths—if a violation occurs, the process returns to the original partitioning scheme module and the partitioning strategy is readjusted.

[0104] Through steps S3021 to S3023 above, the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of all paths in the worst case of setup time, and the negative timing margin of all paths in the worst case of hold time are detected, and so on, until the timing of the chip meets the requirements.

[0105] When the optimal result is achieved, the current partitioning scheme is recorded and saved. Subsequently, the algorithm continues to regularize and partition modules at the same level until all possible partitions at that level have been completely traversed. This process achieves rapid boundary convergence based on the hierarchical structure, providing a foundation for iterative advancement of the partitioning scheme to higher levels. Simultaneously, this optimization process also involves layout optimization within the core and across core systems, considering the clustering characteristics of the core system. Throughout the iteration process, this architecture comprehensively considers layout files, gate-level netlist information, process files, and physical and timing constraint files, achieving gradual timing optimization of TNS and WNS in hierarchical iterations.

[0106] In the area partitioning scheme, the connection ratio in the module set is calculated based on the floorplan data before layout and the given chip I / O positions, serving as the preference candidate set index. Then, combined with area constraints (core area size, minimum area of ​​any core, utilization rate of each core, and aspect ratio constraints), the modules are proportionally allocated according to the total area of ​​the partitioned modules. A relaxation coefficient is added during allocation to achieve generality in the layout scheme. Modules with higher preference candidate index values ​​are then prioritized for partitioning into adjacent parts, and the corresponding physical area scheme is output.

[0107] To balance optimization iteration time with backend design time, the algorithm incorporates a stopping condition: it automatically stops after a preset number of iterations, obtaining the current optimal partitioning scheme as the timing optimization scheme for the core's internal and external modules. This approach not only improves design efficiency but also ensures design quality and performance.

[0108] In some embodiments, the full-chip gate netlist file contains a full-chip gate netlist, which is organized hierarchically by module; the process file contains technical parameters and timing models involved in the design; the layout file contains floorplan data before placement and the given chip I / O locations; the timing constraint file contains all relevant timing constraints; the physical constraint file contains the size of the core area, the minimum area of ​​any core, the utilization rate of each core, and aspect ratio constraints; the partitioning constraint file contains partitioning constraints for the cores; the layout file is used to specify the physical cell placement data after placement; the core partitioning file is used to specify the shape and location information of each core, as well as the integrated circuit modules contained in each core.

[0109] In some embodiments, DREAMPlace is a deep learning-based integrated circuit (IC) physical placement tool primarily used in the chip placement stage. Developed by researchers at Stanford University, it aims to improve the efficiency and quality of placement optimization in IC design. This tool utilizes deep learning (especially deep reinforcement learning) to optimize the chip placement process, with the goal of improving chip performance, power consumption, and area.

[0110] OpenSTA (Open Source Static Timing Analysis) is an open-source static timing analysis tool widely used in integrated circuit (IC) design, especially in the timing verification phase of digital circuit design. Its main function is to help designers analyze and verify the timing characteristics of circuits, ensuring that the circuits operate stably under given clock constraints.

[0111] Floorplan data refers to the layout planning data in integrated circuit (IC) design. It describes the physical location and arrangement of various functional modules (such as logic cells, memory, input / output ports, etc.) within the chip. In IC design, floorplan is the first step in the entire physical design process, providing the basic framework for subsequent steps (such as placement, routing, timing analysis, etc.) of the chip.

[0112] As can be seen from the above embodiments, compared with the prior art, the current core partitioning in the prior art is based on manual partitioning according to design experience. This method lacks a hierarchical optimization strategy, resulting in the inability to effectively optimize cores at different levels. At the same time, the separation of physical and timing optimization, and the lack of a method that comprehensively considers both, may lead to problems such as unsatisfactory timing performance of the layout scheme when satisfying physical constraints. The present application includes, but is not limited to, the following beneficial effects:

[0113] Firstly, this application can significantly improve the efficiency of integrated circuit chip timing optimization. Existing chip partitioning and layout optimization methods often rely on manual experience and simple optimization algorithms. This manual partitioning method has limitations, especially when facing complex designs and changing constraints, where it is inefficient and prone to missing the optimal solution. However, through a hierarchical iterative strategy, this application first performs a coarse partitioning at a high level and then gradually refines it at a lower level, which can efficiently solve complex problems. This staged optimization approach greatly improves the speed of chip partitioning and also improves the accuracy of the chip partitioning process.

[0114] Secondly, the integrated circuit chip timing optimization method of this application can comprehensively optimize both physical and timing constraints. In the traditional chip partitioning process, physical and timing constraints are often considered separately. This may lead to the neglect of timing performance while meeting physical layout requirements, or vice versa, resulting in the final design failing to meet both key requirements simultaneously. However, this application can consider both physical and timing constraints simultaneously. By comprehensively optimizing both during the design process, it can better balance the physical layout and timing performance of the chip, thereby reducing performance trade-offs. This comprehensive approach ensures design feasibility and achieves more optimized overall performance, meeting the demands of modern chip design for high performance and low power consumption.

[0115] Third, the integrated circuit chip timing optimization method of this application can significantly improve automation and flexibility. Existing chip partitioning methods usually require a lot of manual intervention and adjustments. Although some optimizations can be made based on design experience, they still have the limitation of being highly dependent on human intervention and are not easy to adapt to different design requirements and constraints. In contrast, this application can quickly respond to changes in different designs and automatically complete partitioning and optimization. This not only improves the efficiency of the design process but also greatly enhances the flexibility of the system, enabling it to adapt to more diverse needs and design environments. At the same time, it reduces manual intervention and lowers the risk of human error.

[0116] Fourth, the integrated circuit chip timing optimization method of this application can significantly shorten the design cycle. In traditional design processes, especially in the chip partitioning and placement stages, it may require multiple iterations to find a satisfactory solution, which is time-consuming and prone to design rework. By introducing hierarchical optimization and a strategy that comprehensively considers physical and timing constraints, this application reduces the number of design iterations and can identify and solve potential problems in the early stages of design. Early optimization reduces the need for later modifications, thereby significantly shortening the design cycle. This has significant commercial value for the rapidly developing semiconductor industry, helping companies gain a competitive edge in a fiercely competitive market.

[0117] Furthermore, compared to existing technologies, this application introduces key technologies such as hierarchical iterative optimization, comprehensive physical and timing constraints, and automated design processes, providing significant improvements in chip partitioning and layout optimization. These improvements not only enhance design efficiency and quality but also shorten the design cycle, reduce human error, and increase design flexibility and adaptability. These effects enable chip design to better meet the challenges of the post-Moore's Law era, fulfilling the requirements for higher performance, lower power consumption, and more complex designs.

[0118] Please see Figure 4This application provides an integrated circuit chip timing optimization device, comprising a preliminary logic partitioning module 1100, a chip timing optimization module 1200, a partitioning scheme adjustment module 1300, and a partitioning scheme traversal module 1400. The preliminary logic partitioning module 1100 is configured to respond to an instruction for chip timing optimization of the integrated circuit, acquire performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and perform preliminary partitioning of the integrated circuit modules based on the performance parameters, power consumption parameters, and area parameters using logic hierarchy analysis to determine a preliminary logic partitioning scheme. The chip timing optimization module 1200 is configured to generate a preliminary chip partitioning scheme based on the preliminary logic partitioning scheme, combined with physical chip partitioning, and according to area constraints, call the DREAMPlace tool for chip placement, and optimize the total negative timing margin and worst-case negative timing margin on all paths within the chip in the timing optimization module to determine the chip back-end placement result. The partitioning scheme adjustment module 1300... 300 is configured to analyze the timing of the chip based on the chip backend layout results, according to the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the worst-case negative timing margin of setup time in all paths, and the worst-case negative timing margin of hold time in all paths generated by the OpenSTA tool, and readjust the initial chip partitioning scheme to determine an iterative partitioning scheme when a violation occurs, until the timing of the chip meets the requirements; the partitioning scheme traversal module 1400 is configured to record and save the current iterative partitioning scheme when the iterative partitioning scheme meets the timing optimization requirements, and continue to perform regular partitioning on the integrated circuit modules at the same level until all initial chip partitioning schemes at that level have been completely traversed.

[0119] Based on any embodiment of this application, please refer to Figure 5 Another embodiment of this application also provides an electronic device, which can be implemented by a computer device, such as... Figure 5 The diagram shows the internal structure of a computer device. The computer device includes a processor, a computer-readable storage medium, a memory, and a network interface connected via a system bus. The computer-readable storage medium stores an operating system, a database, and computer-readable instructions. The database may store control information sequences. When the computer-readable instructions are executed by the processor, they enable the processor to implement an integrated circuit chip timing optimization method. The processor of the computer device provides computing and control capabilities, supporting the operation of the entire computer device. The memory of the computer device may store computer-readable instructions. When these computer-readable instructions are executed by the processor, they enable the processor to execute the integrated circuit chip timing optimization method of this application. The network interface of the computer device is used for communication with a terminal. Those skilled in the art will understand that… Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0120] In this embodiment, the processor is used to execute... Figure 4 The specific functions of each module are defined within the device, and the memory stores the program code and various data required to execute these modules or sub-modules. The network interface is used for data transmission between the user terminal and the server. In this embodiment, the memory stores the program code and data required to execute all modules in the integrated circuit chip timing optimization device of this application, and the server can call the server's program code and data to execute the functions of all modules.

[0121] This application also provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the integrated circuit chip timing optimization method described in any embodiment of this application.

[0122] This application also provides a computer program product, including a computer program / instructions that, when executed by one or more processors, implement the steps of the integrated circuit chip timing optimization method described in any embodiment of this application.

[0123] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The aforementioned storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0124] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for optimizing the timing of integrated circuit chips, characterized in that, include: In response to the instruction to perform chip timing optimization on the integrated circuit, the system obtains the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and uses logic hierarchy analysis to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine a preliminary logic partitioning scheme. Based on the aforementioned preliminary logical partitioning scheme, combined with physical core partitioning, a preliminary core partitioning scheme is generated according to area constraints. The DREAMPlace tool is called to perform core layout, and the total negative timing margin and worst-case negative timing margin on all paths within the core are optimized in the timing optimization module to determine the core back-end layout result. Based on the core backend layout results, the timing of the core is analyzed according to the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time of all paths generated by the OpenSTA tool. When a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements. When the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the integrated circuit modules at the same level are further regularized and partitioned until all preliminary chip partitioning schemes at that level are completely traversed. This includes: calculating the connection ratio in the module set based on the floorplan data before the input layout and the given chip I / O position as the preference candidate set index; combining the size of the core region of the chip, the minimum area of ​​any chip, the utilization rate of each chip and the aspect ratio constraint, allocating the modules proportionally according to the total area of ​​the partitioned modules, and adding a relaxation coefficient at the same time to achieve the generality of the layout scheme; then prioritizing the partitioning of modules with high preference candidate index values ​​into adjacent parts, and outputting the corresponding physical area scheme.

2. The integrated circuit chip timing optimization method according to claim 1, characterized in that, After obtaining the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and using logical hierarchy analysis to initially divide the integrated circuit modules based on the performance parameters, power consumption parameters, and area parameters to determine a preliminary logical partitioning scheme, the following steps are included: In the initial stage, a preliminary logical partitioning scheme is obtained and used as the initial classification set; Using hierarchical information and input module partitioning constraints, the preliminary logical partitioning scheme is integrated into the initial classification set, and combined with physical core partitioning, the preliminary core partitioning scheme is generated based on area constraints.

3. The integrated circuit chip timing optimization method according to claim 1, characterized in that, The timing analysis of the core is performed based on the total negative timing margin in setup time, the total negative timing margin in hold time, the worst-case negative timing margin in setup time, and the worst-case negative timing margin in hold time of all paths generated by the OpenSTA tool. The process involves readjusting the initial core partitioning scheme to determine an iterative partitioning scheme when violations occur, until the timing of the core meets the requirements. This includes the following steps: Write and use the corresponding TCL scripts in the OpenSTA tool to retrieve the underlying files of the required environment and call the corresponding timing analysis module inside OpenSTA to perform the final timing analysis and obtain the corresponding quantization results; By analyzing four data points generated by OpenSTA—total negative timing margin in setup time, total negative timing margin in hold time, negative timing margin in worst-case setup time of all paths, and negative timing margin in worst-case hold time of all paths—it is determined whether the timing of the chip has reached the ideal state.

4. The integrated circuit chip timing optimization method according to claim 3, characterized in that, The steps to determine whether the timing of the chip has reached the ideal state by analyzing four data points generated by OpenSTA: the total negative timing margin in setup time for all paths, the total negative timing margin in hold time for all paths, the negative timing margin in worst-case setup time for all paths, and the negative timing margin in worst-case hold time for all paths. These steps include: Determine whether all four data points generated by OpenSTA are positive: the total negative timing margin in setup time for all paths, the total negative timing margin in hold time for all paths, the negative timing margin in worst-case setup time for all paths, and the negative timing margin in worst-case hold time for all paths. If all values ​​are positive, it means that the timing of all paths meets the requirements, and the timing of this chip has reached an ideal state. If a negative number appears, it indicates that the chip has at least one path violation, and the timing of the chip is not ideal.

5. The integrated circuit chip timing optimization method according to claim 4, characterized in that, When the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all preliminary chip partitioning schemes at that level have been completely traversed. This includes the following steps: If at least one path of the core is violated, then return to the initial preliminary logical partitioning scheme and readjust the partitioning strategy; The step of re-executing the logical hierarchy analysis to initially divide each integrated circuit module according to the performance parameters, the power consumption parameters, and the area parameters is to determine the initial logical partitioning scheme. Then, check four data points generated by the OpenSTA tool: the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of all paths in the worst case of setup time, and the negative timing margin of all paths in the worst case of hold time. Continue this process until the timing of the chip meets the requirements. When the result is optimal, the current partitioning scheme is recorded and saved, and the modules at the same level are further regularized and partitioned until all possible partitions at that level have been completely traversed.

6. The integrated circuit chip timing optimization method according to claim 1, characterized in that, When the iterative partitioning scheme meets the timing optimization requirements, the current iterative partitioning scheme is recorded and saved, and the regular partitioning of integrated circuit modules at the same level continues until all preliminary chip partitioning schemes at that level have been completely traversed. This includes the following steps: Obtain the preset full-chip gate netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file; Based on the full-chip gate netlist file, process file, layout file, timing constraint file, physical constraint file, and partition constraint file, the total negative timing margin and worst-case negative timing margin on all paths within the chip are progressively optimized in a hierarchical iteration process to determine the layout file and chip partition file corresponding to the chip.

7. An integrated circuit chip timing optimization device, characterized in that, include: The preliminary logic partitioning module is configured to respond to instructions for chip timing optimization of integrated circuits, obtain the performance parameters, power consumption parameters, and area parameters of each integrated circuit module, and use logic hierarchy analysis to perform preliminary partitioning of each integrated circuit module based on the performance parameters, power consumption parameters, and area parameters to determine the preliminary logic partitioning scheme; The core particle timing optimization module is configured to generate a preliminary core particle partitioning scheme based on the preliminary logical partitioning scheme and combined with the physical core particle partitioning, according to the area constraints, call the DREAMPlace tool to perform core particle layout, and optimize the total negative timing margin and worst negative timing margin on all paths inside the core particle in the timing optimization module to determine the core particle back-end layout result. The partitioning scheme adjustment module is configured to analyze the timing of the core based on the core backend layout results, according to the total negative timing margin of all paths in setup time, the total negative timing margin of all paths in hold time, the negative timing margin of the worst-case setup time of all paths, and the negative timing margin of the worst-case hold time of all paths generated by the OpenSTA tool. When a violation occurs, the initial core partitioning scheme is readjusted to determine an iterative partitioning scheme until the timing of the core meets the requirements. The partitioning scheme traversal module is configured to record and save the current iterative partitioning scheme when the iterative partitioning scheme meets the timing optimization requirements, and continue to regularize and partition the integrated circuit modules at the same level until all preliminary chip partitioning schemes at that level have been completely traversed. This includes: calculating the connection ratio in the module set based on the floorplan data before the input layout and the given chip I / O positions as the preference candidate set index; combining the size of the core region of the chip, the minimum area of ​​any chip, the utilization rate of each chip, and the aspect ratio constraint, allocating the partitioned modules proportionally according to the total area of ​​the partitioned modules, and adding a relaxation coefficient at the same time to achieve the generality of the layout scheme, and then prioritizing the partitioning of modules with high preference candidate index values ​​in adjacent parts, and outputting the corresponding physical area scheme.

8. An electronic device comprising a central processing unit and a memory, characterized in that, The central processing unit is used to invoke and run a computer program stored in the memory to perform the steps of the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, It stores, in the form of computer-readable instructions, a computer program implemented according to any one of claims 1 to 6, which, when invoked by a computer, executes the steps included in the corresponding method.

Images