Display device having pixel driving circuit

Abstract

The invention relates to a display device having a pixel driving circuit. A display device including a plurality of pixel areas is provided. A light emitting device and a pixel driving circuit electrically connected to the light emitting device may be disposed in each pixel region. The pixel driving circuit may include a driving thin film transistor. A semiconductor pattern driving the thin film transistor may include a first active region and a second active region parallel to the first active region. A first sub-gate of the driving thin film transistor may be disposed on a first active channel of the first active region and a second active channel of the second active region. The driving thin film transistor may include a second sub-gate between the semiconductor pattern and the first sub-gate. The second active region may include a portion disposed outside the second sub-gate. Accordingly, in the display device, the quality of a low grayscale image may be improved, and the driving current generated by the driving thin film transistor may be increased.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example but not limited to, to a display device in which a pixel driving circuit electrically connected to a light-emitting device is provided in each pixel region. Background Art

[0002] Generally, a display device provides an image to a user. For example, the display device may include a plurality of pixel regions. Each pixel region may implement a specific color. For example, a light-emitting device may be provided in each pixel region. The light-emitting device may emit light that displays a specific color. For example, the light-emitting device may include a light-emitting layer between a first electrode and a second electrode.

[0003] A pixel driving circuit electrically connected to the light-emitting device may be provided in each pixel region. For example, the operation of the light-emitting device in each pixel region may be controlled by a pixel driving circuit in the corresponding pixel region. The pixel driving circuit of each pixel region may provide a driving current corresponding to a data signal to the light-emitting device of the corresponding pixel region in one frame according to a gate signal. For example, the pixel driving circuit of each pixel region may include a driving thin-film transistor and at least one switching thin-film transistor.

[0004] The driving thin-film transistor of each pixel region may generate a driving current corresponding to the data signal. For example, the gray level of the color implemented by each pixel region may be determined by the driving current generated by the driving thin-film transistor of the corresponding pixel region. Therefore, in the display device, the driving thin-film transistor of each pixel region may have different electrical characteristics from the switching thin-film transistor of the corresponding pixel region. Therefore, in the display device, the process of forming a pixel driving circuit in each pixel may be complex. In addition, in the display device, the quality of the image may deteriorate due to differences in the characteristics of the driving thin-film transistors in each pixel region.

[0005] The description provided in this background art section should not be assumed to be prior art merely because it is mentioned in or related to the background art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0007] One aspect of the present disclosure is to provide a display device capable of simplifying the process of forming a pixel driving circuit in each pixel region.

[0008] Another aspect of the present disclosure is to provide a display device capable of increasing both the S factor of a driving thin film transistor in each pixel region and the driving current generated by the driving thin film transistor.

[0009] Additional advantages, aspects, and features of the present disclosure will be set forth in part in the following description, and in part will be obvious to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The aspects and other advantages of the present disclosure may be realized and obtained by the structures particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0010] To achieve these aspects and other advantages, and in accordance with the purpose of the present disclosure, as implemented and broadly described herein, there is provided a display device including a semiconductor pattern. The semiconductor pattern includes a first active region and a second active region. The second active region is disposed parallel to the first active region. A first sub-gate is disposed on the semiconductor pattern. The first sub-gate overlaps a first active channel of the first active region and a second active channel of the second active region. A second sub-gate is disposed between the semiconductor pattern and the first sub-gate. The second sub-gate is insulated from the semiconductor pattern. A first active drain of the first active region and a second active drain of the second active region are electrically connected to a drain electrode. A first active source of the first active region and a second active source of the second active region are electrically connected to a source electrode. The width of the second sub-gate over the second active channel is less than the width of the second sub-gate over the first active channel.

[0011] The width of the second sub-gate over the first active channel may be greater than the width of the first sub-gate over the first active channel.

[0012] The second sub-gate may be electrically connected to the first sub-gate. The first sub-gate and the second sub-gate may be disposed on different layers.

[0013] The first sub-gate may be disposed on a different layer from the drain electrode and the source electrode.

[0014] The second active channel may include a first sub-channel and a second sub-channel. The first sub-channel may overlap the second sub-gate. The second sub-channel may be disposed outside the second sub-gate. The distance between the first sub-channel and the second sub-gate may be less than the distance between the second sub-channel and the first sub-gate.

[0015] The resistance of the second sub-channel may be the same as the resistance of the first sub-channel.

[0016] The second active channel may include a third sub-channel disposed outside the second sub-gate. The distance between the third sub-channel and the first sub-gate may be greater than the distance between the first sub-channel and the second sub-gate. The first sub-channel may be disposed between the second sub-channel and the third sub-channel.

[0017] The semiconductor pattern may be made of an oxide semiconductor. The amount of oxygen contained in the second active channel may be the same as the amount of oxygen contained in the first active channel.

[0018] In another embodiment, a display device including a device substrate is provided. A first thin film transistor, a second thin film transistor, and a light emitting device are disposed on a pixel region of the device substrate. The first thin film transistor includes a first semiconductor pattern and a first gate electrode. The second thin film transistor includes a second semiconductor pattern and a second gate electrode. The light emitting device is electrically connected to the second thin film transistor. The second gate electrode includes a first sub-gate and a second sub-gate. The first sub-gate overlaps a channel region of the second semiconductor pattern. The second sub-gate is disposed between the second semiconductor pattern and the first sub-gate. The channel region of the second semiconductor pattern includes a first active channel and a second active channel. The first active channel includes a portion overlapping the second sub-gate. The second active channel is disposed outside the second sub-gate. The resistance of the second active channel is less than the resistance of the first active channel. The first active channel includes a first sub-channel and a second sub-channel. The first sub-channel overlaps the second sub-gate. The second sub-channel is disposed outside the second sub-gate.

[0019] The resistance of the second sub-channel may be the same as the resistance of the second active channel.

[0020] The second sub-gate may include a material different from that of the first sub-gate.

[0021] The first gate electrode may include the same material as the second sub-gate.

[0022] A first gate insulating layer may be disposed between the second semiconductor pattern and the second sub-gate. A second gate insulating layer may be disposed between the second sub-gate and the first sub-gate. The first gate electrode may be disposed between the first gate insulating layer and the second gate insulating layer.

[0023] An upper interlayer insulating layer may be disposed on the second gate insulating layer. The upper interlayer insulating layer may cover the first sub-gate. A storage capacitor may be disposed on the pixel region of the device substrate. The storage capacitor may include a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode. The first capacitor electrode may be disposed between the first gate insulating layer and the second gate insulating layer. The second capacitor electrode may be disposed between the second gate insulating layer and the upper interlayer insulating layer. The third capacitor electrode may be disposed on the upper interlayer insulating layer.

[0024] The channel region of the first semiconductor pattern may have a greater resistance than the drain region and the source region of the first semiconductor pattern. The first sub-channel may have the same resistance as the channel region of the first semiconductor pattern.

[0025] Other systems, methods, features and advantages will be or will become apparent to those of ordinary skill in the art upon review of the following figures and detailed description. All such additional systems, methods, features and advantages are intended to be included within this specification, within the scope of the present disclosure, and protected by the appended claims. Any content in this section shall not be construed as a limitation on these claims. Other aspects and advantages are discussed in connection with the embodiments of the present disclosure.

[0026] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concept claimed. Brief Description of the Drawings

[0027] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0028] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure;

[0029] Figure 2 is a diagram showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0030] Figure 3 is a diagram showing a cross-section of a pixel region in a display device according to an embodiment of the present disclosure and a cross-section taken along Figure 1 I-I';

[0031] Figure 4 is a plan view showing a second thin film transistor of a pixel region in a display device according to an embodiment of the present disclosure;

[0032] Figure 5 is a diagram showing cross-sections taken along Figure 4 II-II' and III-III';

[0033] Figure 6 is a diagram showing a cross-section taken along Figure 4 IV-IV';

[0034] Figure 7 is Figure 5 an enlarged view of the K1 region in;

[0035] Figure 8 is Figure 5 an enlarged view of the K2 region in;

[0036] Figure 9is a graph showing drive currents according to voltages applied to gate electrodes in accordance with the structure of thin film transistors; and

[0037] Figures 10 to 22 is a diagram showing a display device according to another embodiment of the present disclosure.

[0038] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals are understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their illustration, may be exaggerated. Detailed Description

[0039] Now, embodiments of the present disclosure will be described in detail, examples of which may be shown in the drawings. In the following description, when a detailed description of well-known functions or configurations related to the present document is determined to unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. Like reference numerals designate like elements throughout. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0040] Hereinafter, details related to the above objects, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood through the following detailed description with reference to the drawings illustrating some example embodiments of the present disclosure. Here, example embodiments of the present disclosure are provided so that the present disclosure may be sufficiently thorough and complete and may assist those skilled in the art in fully understanding the scope of the present disclosure. Thus, the present disclosure may be implemented in other forms and is not limited to the embodiments described below. Any implementation described herein as an "example" is not necessarily to be construed as preferred or advantageous over other implementations.

[0041] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing various example embodiments of the present disclosure are by way of example only. Thus, the present disclosure is not limited to the illustration in the drawings. Unless otherwise specified, the same reference numerals refer to the same or similar elements throughout the specification. In the following description, when a detailed description of a related well-known function or configuration may unnecessarily obscure the focus of the present disclosure, the detailed description of such well-known function or configuration may be omitted.

[0042] When interpreting an element, even if there is no explicit description of an error or tolerance range, the element is interpreted as including an error or tolerance range.

[0043] In addition, throughout the specification and the drawings, the same or highly similar elements may be denoted by the same reference numerals, and for convenience, the lengths and thicknesses of layers and regions may be exaggerated. It will be understood that when a first element is referred to as being “on” a second element, although the first element may be disposed on the second element to be in contact with the second element, a third element may be interposed between the first element and the second element.

[0044] When describing positional relationships, for example, when using terms such as “on,” “above,” “below,” “over,” “under,” “beneath,” “lower,” “adjacent to,” “close to,” or “next to,” “beside,” “adjacent,” to describe the positional relationship between two components, one or more other components may be disposed between the two components, unless more restrictive terms such as “immediately,” “directly,” or “closely” are used. For example, when a structure is described as being “on,” “above,” “under,” “over,” “beneath,” “below,” “adjacent to,” “close to,” or “next to” another structure, “beside” another structure, “adjacent” to another structure, this description should be interpreted to include the case where the structures are in contact with each other and the case where a third structure is disposed or interposed therebetween. In addition, the terms “left,” “right,” “top,” “bottom,” “downward,” “upward,” “upper,” “lower,” etc. refer to any reference system.

[0045] Here, terms such as, for example, “first,” “second,” “A,” “B,” “(a),” “(b)” may be used to distinguish any one element from another element. However, without departing from the technical spirit of the present disclosure, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0046] The terms used in the specification of the present disclosure are merely used to describe specific embodiments and are not intended to limit the scope of the present disclosure. For example, an element described in the singular form is intended to include a plurality of elements, unless the context clearly indicates otherwise. Additionally, in the specification of the present disclosure, it will also be understood that the terms “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed of” specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations.

[0047] Furthermore, unless “directly” is used, the terms “connected” and “coupled” may include two components being “connected” or “coupled” through one or more other components disposed between the two components.

[0048] The features of the various embodiments of the present disclosure can be partially or fully coupled or combined with each other and can interoperate with each other and be technically driven in various ways as can be fully understood by those skilled in the art. The embodiments of the present disclosure can be implemented independently of each other or can be implemented together in a mutually dependent relationship.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as idealized or overly formal meanings unless expressly so defined herein. For example, the term "component" or "unit" can be applied, for example, to a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described function, as should be understood by one of ordinary skill in the art.

[0050] (Embodiment)

[0051] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, all components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0052] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure. Figure 2 is a diagram showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure.

[0053] Referring to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, the display panel DP may include a plurality of pixel regions PA. Various signals may be provided in each pixel region PA through signal wirings GL, DL, and PL. For example, the signal wirings GL, DL, and PL may include a gate line GL that sequentially applies a gate signal to each pixel region PA, a data line DL that applies a data signal to each pixel region PA, and a power voltage supply line PL that supplies a power voltage to each pixel region PA. The gate line GL may be electrically connected to a gate driver GD. The data line DL may be electrically connected to a data driver DD. The power voltage supply line PL may be electrically connected to a power supply unit PU.

[0054] The gate driver GD and the data driver DD can be controlled by the timing controller TC. For example, the gate driver GD can receive a clock signal, a reset signal, and a start signal from the timing controller TC, and the data driver DD can receive digital video data and a source timing signal from the timing controller TC.

[0055] The display panel DP may include a display area AA provided with a pixel area PA and a border area BZ adjacent to the display area AA (e.g., provided outside the display area AA). The border area BZ may be provided outside the pixel area PA. For example, the border area BZ may surround the display area AA. Each of the signal wirings GL, DL, and PL may be electrically connected to each pixel area PA across at least a part of the border area BZ.

[0056] At least one of the gate driver GD, the data driver DD, the power supply unit PU, and the timing controller TC may be provided on the border area BZ of the display panel DP. For example, a display device according to an embodiment of the present disclosure may be a GIP (gate-in-panel) type display device in which the gate driver GD is formed on the border area BZ of the display panel DP.

[0057] Each pixel area PA may implement a specific color. For example, the light-emitting device 500 and the pixel driving circuit DC electrically connected to the light-emitting device 500 may be provided in each pixel area PA. The pixel driving circuit DC of each pixel area PA may be electrically connected to the signal wirings GL, DL, and PL. For example, the pixel driving circuit DC of each pixel area PA may be electrically connected to one of the gate lines GL, one of the data lines DL, and one of the power voltage supply lines PL. The pixel driving circuit DC of each pixel area PA may supply a driving current corresponding to a data signal to the light-emitting device 500 of the corresponding pixel area PA in one frame according to a gate signal. For example, the pixel driving circuit DC of each pixel area PA may include a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst, but is not limited thereto, and the pixel driving circuit DC may include more or fewer elements than those shown. For example, 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, 8T2C structures are also possible. And more or fewer transistors and capacitors may be included in the pixel driving circuit DC.

[0058] Figure 3 is a diagram showing a cross-section of a pixel area in a display device according to an embodiment of the present disclosure and a cross-section taken along Figure 1 the I-I' thereof.

[0059] Referring to Figure 2 and Figure 3, the first thin film transistor TR1 of each pixel region PA can send a data signal to the second thin film transistor TR2 of the corresponding pixel region PA according to a gate signal. For example, the first thin film transistor TR1 of each pixel region PA can be a switching thin film transistor. The first thin film transistor TR1 of each pixel region PA can include a first semiconductor pattern 211, a first gate electrode 213, a first drain electrode 215, and a first source electrode 217. For example, the first gate electrode 213 of each pixel region PA can be electrically connected to the corresponding gate line GL, and the first drain electrode 215 of each pixel region PA can be electrically connected to the corresponding data line DL.

[0060] The first semiconductor pattern 211 can include a semiconductor material. For example, the first semiconductor pattern 211 can include an oxide semiconductor such as IGZO. In another example, the oxide semiconductor can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto. The first semiconductor pattern 211 can include a first drain region, a first channel region, and a first source region. The first channel region can be disposed between the first drain region and the first source region. The first drain region and the first source region can have a smaller resistance than the first channel region. For example, the first drain region and the first source region can include a conductive region of the oxide semiconductor. The first channel region can be an unconducted region of the oxide semiconductor.

[0061] The first gate electrode 213 can be disposed on a part of the first semiconductor pattern 211. For example, the first gate electrode 213 can overlap with the first channel region of the first semiconductor pattern 211. The first drain region and the first source region of the first semiconductor pattern 211 can be disposed outside the first gate electrode 213. The first gate electrode 213 can include a conductive material. For example, the first gate electrode 213 can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The first gate electrode 213 can be spaced apart from the first semiconductor pattern 211. The first gate electrode 213 can be insulated from the first semiconductor pattern 211. For example, the first drain region of the first semiconductor pattern 211 can be electrically connected to the first source region of the first semiconductor pattern 211 according to the voltage applied to the first gate electrode 213.

[0062] The first drain electrode 215 may include a conductive material. For example, the first drain electrode 215 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The first drain electrode 215 may include a different material from the first gate electrode 213. For example, the first drain electrode 215 may be disposed on a different layer from the first gate electrode 213. The first drain electrode 215 may be insulated from the first gate electrode 213. The first drain electrode 215 may be electrically connected to the first drain region of the first semiconductor pattern 211.

[0063] The first source electrode 217 may include a conductive material. For example, the first source electrode 217 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The first source electrode 217 may include a different material from the first gate electrode 213. For example, the first source electrode 217 may be disposed on a different layer from the first gate electrode 213. The first source electrode 217 may be insulated from the first gate electrode 213. The first source electrode 217 may be disposed on the same layer as the first drain electrode 215. The first source electrode 217 may include the same material as the first drain electrode 215. The first source electrode 217 may be formed by the same process as the first drain electrode 215. For example, the first source electrode 217 may be formed simultaneously with the first drain electrode 215. The first source electrode 217 may be spaced apart from the first drain electrode 215. The first source electrode 217 may be electrically connected to the first source region of the first semiconductor pattern 211.

[0064] Figure 4 is a plan view of a second thin film transistor in a pixel region of a display device according to an embodiment of the present disclosure. Figure 5 is a view showing along Figure 4 cross-sections taken along II-II' and III-III'. Figure 6 is a view showing along Figure 4 cross-sections taken along IV-IV'. Figure 7 is Figure 5 an enlarged view of the K1 region in Figure 8 is Figure 5 an enlarged view of the K2 region in

[0065] Referring to Figures 2 to 8, the second thin-film transistor TR2 of each pixel region PA can generate a driving current corresponding to the data signal. For example, the second thin-film transistor TR2 of each pixel region PA can be a driving thin-film transistor. The second thin-film transistor TR2 of each pixel region PA can include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 of each pixel region PA can be electrically connected to the first source electrode 217 of the corresponding pixel region PA, and the second drain electrode 225 of each pixel region PA can be electrically connected to the corresponding power supply voltage providing line PL.

[0066] The second semiconductor pattern 221 can include a first active region A1 and a second active region A2, as Figure 4 , Figure 7 and Figure 8 shown. The second active region A2 can be arranged side by side with the first active region A1. The second active region A2 can extend parallel to the first active region A1. For example, the length of the second active region A2 can be the same as the length of the first active region A1. The second active region A2 can have the same width as the first active region A1. For example, the side surface of the second active region A2 can be in direct contact with the side surface of the first active region A1.

[0067] The first active region A1 can include a semiconductor material. For example, the first active region A1 can include an oxide semiconductor such as IGZO. The first active region A1 can include the same material as the first semiconductor pattern 211. The first active region A1 can be disposed on the same layer as the first semiconductor pattern 211. The first active region A1 can be formed by the same process as the first semiconductor pattern 211. For example, the first active region A1 can be formed simultaneously with the first semiconductor pattern 211.

[0068] The first active region A1 can include a first active channel 221c1 between a first active drain 221d1 and a first active source 221s1. The first active drain 221d1 and the first active source 221s1 can have a smaller resistance than the first active channel 221c1. For example, the first active drain 221d1 and the first active source 221s1 can include a conductive region of an oxide semiconductor. The first active channel 221c1 can be a non-conductive region of the oxide semiconductor. For example, the first active channel 221c1 can have the same resistance as the first channel region.

[0069] The second active region A2 may include a semiconductor material. For example, the second active region A2 may include an oxide semiconductor such as IGZO. The second active region A2 may include the same material as the first active region A1. The second active region A2 may be disposed on the same layer as the first active region A1. The second active region A2 may be formed by the same process as the first active region A1. For example, the second active region A2 may be formed simultaneously with the first active region A1. The interface between the first active region A1 and the second active region A2 may not be recognized.

[0070] The second active region A2 may include a second active channel 221c2 between a second active drain 221d2 and a second active source 221s2. The second active drain 221d2 and the second active source 221s2 may have a smaller resistance than the second active channel 221c2. For example, the second active drain 221d2 and the second active source 221s2 may include conductive regions of an oxide semiconductor. The second active channel 221c2 may be a non-conductive region of the oxide semiconductor.

[0071] The second active drain 221d2 may be in direct contact with the first active drain 221d1. The first active drain 221d1 and the second active drain 221d2 may constitute the second drain region of the second semiconductor pattern 221. For example, the length of the second active drain 221d2 may be the same as the length of the first active drain 221d1. The resistance of the second active drain 221d2 may be the same as the resistance of the first active drain 221d1. For example, the second active drain 221d2 may be formed simultaneously with the first active drain 221d1.

[0072] The second active source 221s2 may be in direct contact with the first active source 221s1. The first active source 221s1 and the second active source 221s2 may constitute the second source region of the second semiconductor pattern 221. For example, the length of the second active source 221s2 may be the same as the length of the first active source 221s1. The second active source 221s2 may have the same resistance as the first active source 221s1. For example, the second active source 221s2 may be formed simultaneously with the first active source 221s1.

[0073] The second active channel 221c2 can be in direct contact with the first active channel 221c1. The first active channel 221c1 and the second active channel 221c2 can form a second channel region 221c of the second semiconductor pattern 221. For example, the length of the second active channel 221c2 can be the same as the length of the first active channel 221c1. The second active channel 221c2 can have the same resistance as the first active channel 221c1. For example, the amount of oxygen contained in the second active channel 221c2 can be the same as the amount of oxygen contained in the first active channel 221c1.

[0074] The second gate electrode 223 can be disposed on a part of the second semiconductor pattern 221. For example, the second gate electrode 223 can be disposed on the second channel region 221c of the second semiconductor pattern 221. The second drain region and the second source region of the second semiconductor pattern 221 can be disposed outside the second gate electrode 223. The second gate electrode 223 can include a first sub-gate 223a and a second sub-gate 223b.

[0075] The first sub-gate 223a can be disposed on the second channel region 221c of the second semiconductor pattern 221. For example, the first active channel 221c1 and the second active channel 221c2 of the second semiconductor pattern 221 can overlap with the first sub-gate 223a. The second drain region and the second source region of the second semiconductor pattern 221 can be disposed outside the first sub-gate 223a. The first sub-gate 223a can include a conductive material. For example, the first sub-gate 223a can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The first sub-gate 223a can be insulated from the second semiconductor pattern 221.

[0076] The second sub-gate 223b can extend parallel to the first sub-gate 223a. The second sub-gate 223b can be disposed on a different layer from the first sub-gate 223a. For example, the second sub-gate 223b can be disposed between the second semiconductor pattern 221 and the first sub-gate 223a. The second sub-gate 223b can include a conductive material. For example, the second sub-gate 223b can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The second sub-gate 223b can include a different material from the first sub-gate 223a. The second sub-gate 223b can be insulated from the second semiconductor pattern 221.

[0077] The second sub-gate 223b may overlap with the first active channel 221c1 of the second semiconductor pattern 221. For example, the second sub-gate 223b may include a region disposed between the first active channel 221c1 of the second semiconductor pattern 221 and the first sub-gate 223a. The width of the second sub-gate 223b over the first active channel 221c1 may be greater than the width of the first sub-gate 223a over the first active channel 221c1. For example, the first active channel 221c1 of the second semiconductor pattern 221 may have a conductivity corresponding to the voltage applied to the second sub-gate 223b. The first active drain 221d1 may be electrically connected to the first active source 221s1 according to the voltage applied to the second sub-gate 223b.

[0078] The second sub-gate 223b may include a region over the second active channel 221c2 of the second semiconductor pattern 221. The width of the second sub-gate 223b over the second active channel 221c2 may be less than the width of the second sub-gate 223b over the first active channel 221c1. A portion of the second active channel 221c2 may be disposed outside the second sub-gate 223b. For example, the second active channel 221c2 may include a first sub-channel SC1, a second sub-channel SC2, and a third sub-channel SC3 arranged side by side between the second active drain 221d2 and the second active source 221s2. The second sub-gate 223b may overlap with the first sub-channel SC1 of the second active channel 221c2, and the second sub-channel SC2 and the third sub-channel SC3 of the second active channel 221c2 may be disposed outside the second sub-gate 223b. The first sub-channel SC1 of the second active channel 221c2 may have a conductivity corresponding to the voltage applied to the second sub-gate 223b, and the second sub-channel SC2 and the third sub-channel SC3 of the second active channel 221c2 may have a conductivity corresponding to the voltage applied to the first sub-gate 223a.

[0079] The first sub-channel SC1 may be disposed between the second sub-channel SC2 and the third sub-channel SC3. For example, the second sub-channel SC2 may be disposed between the second active drain 221d2 and the first sub-channel SC1, and the third sub-channel SC3 may be disposed between the first sub-channel SC1 and the second active source 221s2. The resistance of the second sub-channel SC2 and the resistance of the third sub-channel SC3 may be the same as the resistance of the first sub-channel SC1. The distance between the first sub-channel SC1 and the second sub-gate 223b may be less than the distance between the second sub-channel SC2 and the first sub-gate 223a and the distance between the third sub-channel SC3 and the first sub-gate 223a.

[0080] In a general thin film transistor, the voltage applied to the gate electrode when a channel is formed in the channel region of the semiconductor pattern is defined as the threshold voltage. The threshold voltage of the thin film transistor is proportional to the distance between the semiconductor pattern and the gate electrode of the corresponding thin film transistor. For example, in a display device according to an embodiment of the present disclosure, the first threshold voltage applied to the second sub-gate 223b when a channel is formed in the first sub-channel SC1 may be lower than the second threshold voltage applied to the first sub-gate 223a when channels are formed in the second sub-channel SC2 and the third sub-channel SC3. Therefore, in the display device according to the embodiment of the present disclosure, the channel of the first sub-channel SC1 may be formed before the channels of the second sub-channel SC2 and the third sub-channel SC3. In addition, in the display device according to the embodiment of the present disclosure, when the channels of the second sub-channel SC2 and the third sub-channel SC3 are not formed, the second active drain 221d2 may not be electrically connected to the second active source 221s2. For example, if a voltage between the first threshold voltage and the second threshold voltage is applied to the first sub-gate 223a and the second sub-gate 223b, the channel of the first active channel 221c1 and the channel of the first sub-channel SC1 may be formed, but the channels of the second sub-channel SC2 and the third sub-channel SC3 may not be formed. Therefore, in the display device according to the embodiment of the present disclosure, when a voltage between the first threshold voltage and the second threshold voltage is applied to the first sub-gate 223a and the second sub-gate 223b, the first active drain 221d1 may be electrically connected to the first active source 221s1, while the second active drain 221d2 may not be electrically connected to the second active source 221s2.

[0081] In a display device according to an embodiment of the present disclosure, when a low gray-scale image is implemented, a voltage between the first threshold voltage and the second threshold voltage may be applied to the first sub-gate 223a and the second sub-gate 223b of each pixel region PA. Therefore, in the display device according to the embodiment of the present disclosure, when a low gray-scale image is implemented, only the first active region A1 of the second semiconductor pattern 221 in each pixel may be activated. For example, in a display device according to an embodiment of the present disclosure, when a low gray-scale image is implemented, the driving current applied to the light-emitting device 500 of each pixel region PA may be reduced. In addition, in the display device according to the embodiment of the present disclosure, when a low gray-scale image is implemented, the deviation of the driving current generated by the second thin film transistor TR2 of each pixel region PA may be reduced. Therefore, in the display device according to the embodiment of the present disclosure, the quality of the low gray-scale image may be improved.

[0082] In a display device according to an embodiment of the present disclosure, when a voltage higher than a second threshold voltage is applied to a first sub-gate 223a and a second sub-gate 223b of each pixel region PA, a channel of a second sub-channel SC2 and a channel of a third sub-channel SC3 can be formed, and a second active drain 221d2 can be electrically connected to a second active source 221s2. For example, in a display device according to an embodiment of the present disclosure, when a voltage higher than a second threshold voltage is applied to the first sub-gate 223a and the second sub-gate 223b of each pixel region PA to implement a high gray-scale image, both a first active channel 221c1 and a second active channel 221c2 in each pixel region PA can be activated. For example, in a display device according to an embodiment of the present disclosure, when a high gray-scale image is implemented, a driving current generated by a second thin-film transistor TR2 of each pixel region PA can be increased. Therefore, in a display device according to an embodiment of the present disclosure, both the quality of a low gray-scale image and the quality of a high gray-scale image can be improved.

[0083] In addition, in a display device according to an embodiment of the present disclosure, a channel of a second sub-channel SC2 and a channel of a third sub-channel SC3 in each pixel region PA can be used as an effective channel of a second active channel 221c2. Generally, a driving current generated by a thin-film transistor can be inversely proportional to a channel length of the corresponding thin-film transistor. Therefore, in a display device according to an embodiment of the present disclosure, a driving current generated in a second active channel 221c2 of each pixel region PA can be greater than a driving current generated in a first active channel 221c1 of the corresponding pixel region PA. Therefore, in a display device according to an embodiment of the present disclosure, the efficiency of a second thin-film transistor TR2 in each pixel region PA can be improved.

[0084] Figure 9 is a graph showing driving currents according to voltages applied to gate electrodes in a first comparative example thin-film transistor ① including only a channel region in which a channel is formed by a first threshold voltage, a second comparative example thin-film transistor ② including only a channel region in which a channel is formed by a second threshold voltage, and a second thin-film transistor TR2 according to an embodiment of the present disclosure. Here, a channel region of the first comparative example thin-film transistor ①, a channel region of the second comparative example thin-film transistor ②, and a second channel region 221c of the second thin-film transistor TR2 according to an embodiment of the present disclosure can be formed to have the same length and the same width.

[0085] Refer to Figure 9, the threshold voltage of the second thin film transistor TR2 according to an embodiment of the present disclosure can be lower than the threshold voltage of the first comparative example thin film transistor ① and the threshold voltage of the second comparative example thin film transistor ②. In addition, the driving current generated by the second thin film transistor TR2 according to an embodiment of the present disclosure at a high voltage can be greater than the driving current generated by the first comparative example thin film transistor ① and the driving current generated by the second comparative example thin film transistor ② at a high voltage. In addition, in a section where a relatively low voltage is applied, the second thin film transistor TR2 according to an embodiment of the present disclosure can have a smaller increase in the driving current according to the increase in voltage than the first comparative example thin film transistor ① and the second comparative example thin film transistor ②. In the display device according to an embodiment of the present disclosure, the driving current applied to the light emitting device 500 in each pixel region PA can be effectively controlled according to the gray scale of the realized image without deteriorating the characteristics of the second thin film transistor TR2 in the corresponding pixel region PA. Therefore, in the display device according to an embodiment of the present disclosure, power consumption can be reduced by low power driving.

[0086] Referring to Figures 2 to 8 , the second sub-gate 223b can include the same material as the first gate electrode 213. The second sub-gate 223b can be disposed on the same layer as the first gate electrode 213. The second sub-gate 223b can be formed by the same process as the first gate electrode 213. For example, the second sub-gate 223b can be formed simultaneously with the first gate electrode 213. The first sub-gate 223a can include a different material from the first gate electrode 213. The first sub-gate 223a can be disposed on a different layer from the first gate electrode 213.

[0087] The second sub-gate 223b can be electrically connected to the first sub-gate 223a. For example, the second gate electrode 223 can include a connection gate 223c that electrically connects the first sub-gate 223a to the second sub-gate 223b. The electrical connection between the first sub-gate 223a and the second sub-gate 223b can be made outside the second semiconductor pattern 221. For example, the connection gate 223c can be disposed outside the second semiconductor pattern 221. The second semiconductor pattern 221 can not overlap with the connection gate 223c. Therefore, in the display device according to an embodiment of the present disclosure, the channel of the second channel region 221c can not be formed through the connection gate 223c. Therefore, in the display device according to an embodiment of the present disclosure, deviation of the characteristics of the second thin film transistor TR2 in each pixel region PA due to the connection gate 223c of the corresponding pixel region PA can be prevented or reduced.

[0088] The connecting gate 223c may be disposed on a different layer from the first sub-gate 223a and the second sub-gate 223b. The connecting gate 223c may include a different material from the first sub-gate 223a and the second sub-gate 223b. For example, the connecting gate 223c may be disposed on the same layer as the first drain electrode 215 and the first source electrode 217. The connecting gate 223c may include the same material as the first drain electrode 215 and the first source electrode 217. The connecting gate 223c may be formed by the same process as the first drain electrode 215 and the first source electrode 217. For example, the connecting gate 223c may be formed simultaneously with the first drain electrode 215 and the first source electrode 217. Accordingly, in the display device according to an embodiment of the present disclosure, a reduction in process efficiency due to the process of forming the second gate electrode 223 may be minimized or reduced.

[0089] The second drain electrode 225 may include a conductive material. For example, the second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The second drain electrode 225 may include a different material from the first sub-gate 223a and the second sub-gate 223b. The second drain electrode 225 may be disposed on a different layer from the first sub-gate 223a and the second sub-gate 223b. For example, the second drain electrode 225 may be disposed on the same layer as the connecting gate 223c. The second drain electrode 225 may include the same material as the connecting gate 223c. The second drain electrode 225 may be formed by the same process as the connecting gate 223c. For example, the second drain electrode 225 may be formed simultaneously with the connecting gate 223c. The second drain electrode 225 may be spaced apart from the connecting gate 223c. The second drain electrode 225 may be insulated from the second gate electrode 223. The second drain electrode 225 may be electrically connected to the second active drain 221d2 and the first active drain 221d1 of the second semiconductor pattern 221.

[0090] The second source electrode 227 may include a conductive material. For example, the second source electrode 227 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The second source electrode 227 may include a material different from that of the first sub-gate 223a and the second sub-gate 223b. The second source electrode 227 may be disposed on a different layer from the first sub-gate 223a and the second sub-gate 223b. For example, the second source electrode 227 may be disposed on the same layer as the second drain electrode 225. The second source electrode 227 may include the same material as the second drain electrode 225. The second source electrode 227 may be formed by the same process as the second drain electrode 225. For example, the second source electrode 227 may be formed simultaneously with the second drain electrode 225. The second source electrode 227 may be spaced apart from the connection gate 223c and the second drain electrode 225. The second source electrode 227 may be insulated from the second gate electrode 223. The second source electrode 227 may be electrically connected to the second active source 221s2 and the first active source 221s1 of the second semiconductor pattern 221.

[0091] The storage capacitor Cst of each pixel region PA may maintain a signal applied to the second gate electrode 223 of the corresponding pixel region PA for one frame. For example, the storage capacitor Cst of each pixel region PA may be electrically connected between the second gate electrode 223 and the second source electrode 227 of the corresponding pixel region PA. The storage capacitor Cst of each pixel region PA may have a stacked structure of capacitor electrodes 251, 252, and 253. The storage capacitor Cst of each pixel region PA may be formed by using the process of forming the first thin film transistor TR1 and the second thin film transistor TR2 of the corresponding pixel region PA. For example, the storage capacitor Cst of each pixel region PA may include a first capacitor electrode 251 disposed on the same layer as the second sub-gate 223b, a second capacitor electrode 252 disposed on the same layer as the first sub-gate 223a, and a third capacitor electrode 253 disposed on the same layer as the second source electrode 227. Accordingly, in the display device according to an embodiment of the present disclosure, the size occupied by the storage capacitor Cst in each pixel region PA may be minimized or reduced without degrading process efficiency.

[0092] The gate driver GD formed in the border area BZ may include at least one circuit thin film transistor 290. The circuit thin film transistor 290 may be a switching thin film transistor. For example, the circuit thin film transistor 290 may include a circuit semiconductor pattern 291, a circuit gate electrode 293, a circuit drain electrode 295, and a circuit source electrode 297.

[0093] The circuit semiconductor pattern 291 may include a semiconductor material. The circuit semiconductor pattern 291 may include a material different from the first semiconductor pattern 211, the first active region A1, and the second active region A2 of each pixel region PA. For example, the circuit semiconductor pattern 291 may include low-temperature polycrystalline silicon (LTPS). The circuit semiconductor pattern 291 may be disposed on a different layer from the first semiconductor pattern 211, the first active region A1, and the second active region A2 of each pixel region PA. However, the present disclosure is not limited thereto, and the circuit semiconductor pattern 291 may include a material the same as that of the first semiconductor pattern 211 or the second semiconductor pattern 221, and / or may be disposed on the same layer as the first semiconductor pattern 211 or the second semiconductor pattern 221.

[0094] The circuit semiconductor pattern 291 may include a circuit drain region, a circuit channel region, and a circuit source region. The circuit channel region may be disposed between the circuit drain region and the circuit source region. The circuit drain region and the circuit source region may have a lower resistance than the circuit channel region. For example, the circuit drain region and the circuit source region may include conductive impurities. The circuit channel region may be a region not doped with conductive impurities.

[0095] The circuit gate electrode 293 may be disposed on a part of the circuit semiconductor pattern 291. For example, the circuit gate electrode 293 may overlap with the circuit channel region of the circuit semiconductor pattern 291. The circuit drain region and the circuit source region of the circuit semiconductor pattern 291 may be disposed outside the circuit gate electrode 293. The circuit gate electrode 293 may include a conductive material. For example, the circuit gate electrode 293 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The circuit gate electrode 293 may be insulated from the circuit semiconductor pattern 291. The circuit drain region of the circuit semiconductor pattern 291 may be electrically connected to the circuit source region of the circuit semiconductor pattern 291 according to the voltage applied to the circuit gate electrode 293.

[0096] The circuit gate electrode 293 may include a material different from the first gate electrode 213, the first sub-gate 223a, and the second sub-gate 223b of each pixel region PA. The circuit gate electrode 293 may be disposed on a different layer from the first gate electrode 213, the first sub-gate 223a, and the second sub-gate 223b of each pixel region PA.

[0097] The circuit drain electrode 295 may include a conductive material. For example, the circuit drain electrode 295 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The circuit drain electrode 295 may include a material different from that of the circuit gate electrode 293. For example, the circuit drain electrode 295 may be disposed on a different layer from the circuit gate electrode 293. The circuit drain electrode 295 may be insulated from the circuit gate electrode 293. For example, the circuit drain electrode 295 may be disposed on the same layer as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may include the same material as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be formed by the same process as the first drain electrode 215 of each pixel region PA. For example, the circuit drain electrode 295 may be formed simultaneously with the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be electrically connected to the drain region of the circuit semiconductor pattern 291.

[0098] The circuit source electrode 297 may include a conductive material. For example, the circuit source electrode 297 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). The circuit source electrode 297 may include a material different from that of the circuit gate electrode 293. For example, the circuit source electrode 297 may be disposed on a different layer from the circuit gate electrode 293. The circuit source electrode 297 may be insulated from the circuit gate electrode 293. For example, the circuit source electrode 297 may be disposed on the same layer as the circuit drain electrode 295. The circuit source electrode 297 may include the same material as the circuit drain electrode 295. The circuit source electrode 297 may be formed by the same process as the circuit drain electrode 295. For example, the circuit source electrode 297 may be formed simultaneously with the circuit drain electrode 295. The circuit source electrode 297 may be spaced apart from the circuit drain electrode 295. The circuit source electrode 297 may be electrically connected to the source region of the circuit semiconductor pattern 291.

[0099] The pixel driving circuit DC and the circuit thin film transistor 290 of each pixel region PA can be supported by the device substrate 100. For example, the storage capacitor Cst, the first thin film transistor TR1, and the second thin film transistor TR2 of the pixel driving circuit DC in each pixel region PA can be disposed on the corresponding pixel region PA of the device substrate 100. The circuit thin film transistor 290 can be disposed on the border region BZ of the device substrate 100. The device substrate 100 can include an insulating material. For example, the device substrate 100 can include glass or plastic. In another example, the device substrate 100 can include a flexible polymer film. For example, the flexible polymer film can be made of any one of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cycloolefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are only examples and are not necessarily limited thereto.

[0100] A plurality of insulating layers 110, 121, 122, 123, 130, 140, 150, 160, 170, 180, and 190 for preventing or reducing unnecessary electrical connections can be disposed on the device substrate 100. For example, the lower buffer layer 110, the lower gate insulating layer 121, the first upper gate insulating layer 122, the second upper gate insulating layer 123, the lower interlayer insulating layer 130, the separation insulating layer 140, the upper buffer layer 150, the upper interlayer insulating layer 160, the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190 can be disposed on the device substrate 100. It should be noted that although Figures 2 to 8 an example of the layer structure of the display device according to the present disclosure is shown, the embodiments of the present disclosure are not limited thereto. For example, one or more of the plurality of insulating layers 110, 121, 122, 123, 130, 140, 150, 160, 170, 180, and 190 can be omitted, changed, or replaced with other layers. Therefore, Figures 2 to 8 the shown structure is provided only by way of example, and the present disclosure is not limited thereto.

[0101] The lower buffer layer 110 may be disposed adjacent to the device substrate 100. The lower buffer layer 110 may prevent or reduce contamination caused by the device substrate 100 during the process of forming the pixel driving circuit DC and the circuit thin film transistor 290 in each pixel region PA. For example, the upper surface of the device substrate 100 facing the pixel driving circuit DC and the circuit thin film transistor 290 in each pixel region PA may be completely covered by the lower buffer layer 110. The lower buffer layer 110 may be in direct contact with the upper surface of the device substrate 100. The pixel driving circuit DC and the circuit thin film transistor 290 in each pixel region PA may be disposed on the lower buffer layer 110. For example, the lower buffer layer 110 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower buffer layer 110 may have a multilayer structure. For example, the lower buffer layer 110 may have a stacked structure of an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx).

[0102] The lower gate insulating layer 121 may be disposed on the lower buffer layer 110. The circuit gate electrode 293 may be insulated from the circuit semiconductor pattern 291 through the lower gate insulating layer 121. For example, the circuit semiconductor pattern 291 may be disposed between the lower buffer layer 110 and the lower gate insulating layer 121. The lower gate insulating layer 121 may cover the circuit semiconductor pattern 291. The circuit gate electrode 293 may be disposed on the lower gate insulating layer 121. The lower gate insulating layer 121 may include an insulating material. For example, the lower gate insulating layer 121 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0103] The lower interlayer insulating layer 130 may be disposed on the lower gate insulating layer 121. The circuit drain electrode 295 and the circuit source electrode 297 may be insulated from the circuit gate electrode 293 through the lower interlayer insulating layer 130. For example, the circuit gate electrode 293 may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130. The lower interlayer insulating layer 130 may cover the circuit gate electrode 293. The circuit drain electrode 295 and the circuit source electrode 297 may be disposed on the lower interlayer insulating layer 130. The lower interlayer insulating layer 130 may include an insulating material. For example, the lower interlayer insulating layer 130 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0104] The first light-blocking pattern 310 may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130 of each pixel region PA. The first light-blocking pattern 310 of each pixel region PA may include a material that absorbs or reflects light. For example, the first light-blocking pattern 310 of each pixel region PA may include a metal. The first light-blocking pattern 310 of each pixel region PA may include the same material as the circuit gate electrode 293. The first light-blocking pattern 310 of each pixel region PA may be disposed on the same layer as the circuit gate electrode 293. The first light-blocking pattern 310 of each pixel region PA may be formed by the same process as the circuit gate electrode 293. For example, the first light-blocking pattern 310 of each pixel region PA may be formed simultaneously with the circuit gate electrode 293.

[0105] The first light-blocking pattern 310 of each pixel region PA may overlap with the first semiconductor pattern 211 of the corresponding pixel region PA. For example, light propagating through the device substrate 100 toward the first semiconductor pattern 211 of each pixel region PA may be blocked by the first light-blocking pattern 310 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to prevent or reduce the characteristics of the first thin-film transistor TR1 in each pixel region PA from being changed due to external light introduced through the device substrate 100.

[0106] A specific voltage may be applied to the first light-blocking pattern 310 of each pixel region PA. For example, the first light-blocking pattern 310 of each pixel region PA may be electrically connected to the first gate electrode 213 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, the first light-blocking pattern 310 of each pixel region PA may be used as the gate electrode of the first thin-film transistor TR1 in the corresponding pixel region PA. The first semiconductor pattern 211 of each pixel region PA may be disposed between the first light-blocking pattern 310 and the first gate electrode 213 of the corresponding pixel region PA. For example, in the display device according to an embodiment of the present disclosure, a channel of the first semiconductor pattern 211 may be formed by a voltage applied to the first light-blocking pattern 310 of the corresponding pixel region PA and a voltage applied to the first gate electrode 213 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to increase the response speed of the first thin-film transistor TR1 in each pixel region PA.

[0107] The isolation insulating layer 140 may be disposed on the lower interlayer insulating layer 130. The isolation insulating layer 140 may prevent or reduce the deterioration and damage of the circuit semiconductor pattern 291 caused by the process of forming the pixel driving circuit DC in each pixel region PA. For example, the first thin film transistor TR1, the second thin film transistor TR2, and the storage capacitor Cst of each pixel region PA may be disposed on the isolation insulating layer 140. The isolation insulating layer 140 may include an insulating material. For example, the isolation insulating layer 140 may be an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The isolation insulating layer 140 may have a multilayer structure. For example, the isolation insulating layer 140 may have a stacked structure of an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx). The thickness of the isolation insulating layer 140 may be greater than the thickness of the lower interlayer insulating layer 130. Accordingly, in the display device according to an embodiment of the present disclosure, damage to the circuit semiconductor pattern 291 caused by the process of forming the pixel driving circuit DC of each pixel region PA can be effectively prevented or reduced.

[0108] The upper buffer layer 150 may be disposed on the isolation insulating layer 140. The upper buffer layer 150 may include an insulating material. For example, the upper buffer layer 150 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The second light blocking pattern 320 may be disposed between the isolation insulating layer 140 and the upper buffer layer 150 in each pixel region PA. For example, the upper buffer layer 150 may prevent or reduce contamination caused by the second light blocking pattern 320 of each pixel region PA during the process of forming the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. For example, the pixel driving circuit DC of each pixel region PA may be disposed on the upper buffer layer 150.

[0109] The second light-blocking pattern 320 of each pixel region PA may include a material that absorbs or reflects light. For example, the second light-blocking pattern 320 of each pixel region PA may include a metal. The second light-blocking pattern 320 of each pixel region PA may overlap with the second semiconductor pattern 221 of the corresponding pixel region PA. For example, light that propagates through the device substrate 100 and toward the second semiconductor pattern 221 of each pixel region PA may be blocked by the second light-blocking pattern 320 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to prevent or reduce the characteristics of the second thin-film transistor TR2 in each pixel region PA from being changed due to external light introduced through the device substrate 100. For example, in the display device according to an embodiment of the present disclosure, it is possible to prevent or reduce the deviation of the characteristics of the second thin-film transistor TR2 due to external light. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to prevent or reduce the degradation of image quality due to external light.

[0110] A specific voltage may be applied to the second light-blocking pattern 320 of each pixel region PA. For example, the second light-blocking pattern 320 of each pixel region PA may be electrically connected to the second drain electrode 225 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to effectively prevent or reduce the characteristics of the second thin-film transistor TR2 in each pixel region PA from being changed due to external light.

[0111] The distance between the second light-blocking pattern 320 and the second semiconductor pattern 221 in the pixel region PA may be less than the distance between the first light-blocking pattern 310 and the first semiconductor pattern 211 in the corresponding pixel region PA. Generally, the change amount of the effective gate voltage of a thin-film transistor provided on a conductive pattern may be determined by the following formula. Here, ΔV eff represents the change amount of the effective gate voltage, ΔV GAT represents the change amount of the voltage applied to the gate electrode, C1 represents the capacitance of a parasitic capacitor formed between the semiconductor pattern and the conductive pattern of the corresponding thin-film transistor, C2 represents the capacitance of a parasitic capacitor formed between the semiconductor pattern and the gate electrode of the corresponding thin-film transistor, and C ACT represents the capacitance of a parasitic capacitor formed by the voltage applied to the drain region and the source region of the corresponding thin-film transistor.

[0112] [Formula]

[0113]

[0114] The capacitance of a capacitor is inversely proportional to the distance between the conductors constituting the corresponding capacitor. In the display device according to an embodiment of the present disclosure, the capacitance of the parasitic capacitor formed between the second light blocking pattern 320 and the second semiconductor pattern 221 in each pixel region PA may be greater than the capacitance of the parasitic capacitor formed between the first semiconductor pattern 211 and the first light blocking pattern 310 in the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, the amount of change in the effective gate voltage of the second thin film transistor TR2 in each pixel region PA may be less than the amount of change in the effective gate voltage of the first thin film transistor TR1 in the corresponding pixel region PA. In a general thin film transistor, when the amount of change in the effective gate voltage decreases, the amount of change in the current according to the change in the voltage applied to the gate electrode of the corresponding thin film transistor may decrease, and the S-factor of the corresponding thin film transistor may increase. Here, the S-factor of a thin film transistor refers to the inverse ratio of the amount of change in the current generated by the corresponding thin film transistor and the amount of change in the voltage applied to the gate electrode of the corresponding thin film transistor. For example, in the display device according to an embodiment of the present disclosure, the S-factor of the second thin film transistor TR2 in each pixel region PA and the amount of change in the driving current generated by the second thin film transistor TR2 in each pixel region PA according to the change in the voltage applied to the second gate electrode 223 of the corresponding pixel region PA may decrease. Accordingly, in the display device according to an embodiment of the present disclosure, it is possible to prevent or reduce the occurrence of stains due to brightness deviation and improve the image quality.

[0115] The first upper gate insulating layer 122 may be disposed on the upper buffer layer 150. The first gate electrode 213 of each pixel region PA may be insulated from the first semiconductor pattern 211 of the corresponding pixel region PA through the first upper gate insulating layer 122. The second sub-gate 223b of each pixel region PA may be insulated from the first active region A1 and the second active region A2 of the corresponding pixel region PA through the first upper gate insulating layer 122. For example, the first upper gate insulating layer 122 may cover the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. The first gate electrode 213 and the second sub-gate 223b of each pixel region PA may be disposed on the first upper gate insulating layer 122. The first upper gate insulating layer 122 may include an insulating material. For example, the first upper gate insulating layer 122 may be an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0116] The second upper gate insulating layer 123 may be disposed on the first upper gate insulating layer 122. The first sub-gate 223a of each pixel region PA may be spaced apart from the second sub-gate 223b of the corresponding pixel region PA through the second upper gate insulating layer 123. For example, the second upper gate insulating layer 123 may cover the first gate electrode 213 and the second sub-gate 223b of each pixel region PA. The first sub-gate 223a of each pixel region PA may be disposed on the second upper gate insulating layer 123. The second upper gate insulating layer 123 may include an insulating material. For example, the second upper gate insulating layer 123 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The second upper gate insulating layer 123 may include the same material as the first upper gate insulating layer 122. For example, the interface between the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may not be recognized.

[0117] In each pixel region PA, only the first upper gate insulating layer 122 may be disposed between the first active channel 221c1 and the second sub-gate 223b, and between the first sub-channel SC1 of the second active channel 221c2 and the second sub-gate 223b. In each pixel region PA, the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may be disposed between the second sub-channel SC2 of the second active channel 221c2 and the first sub-gate 223a, and between the third sub-channel SC3 of the second active channel 221c2 and the first sub-gate 223a. For example, the distance between the first sub-channel SC1 and the second sub-gate 223b in each pixel region PA may be equal to the distance between the first active channel 221c1 and the second sub-gate 223b in the corresponding pixel region PA, and the distance between the second sub-channel SC2 and the first sub-gate 223a, and the distance between the third sub-channel SC3 and the first sub-gate 223a in each pixel region PA may be greater than the distance between the first sub-channel SC1 and the second sub-gate 223b in the corresponding pixel region PA. For example, in a display device according to an embodiment of the present disclosure, the capacitance of the parasitic capacitor formed between the second sub-channel SC2 and the first sub-gate 223a in each pixel region PA, and the capacitance of the parasitic capacitor formed between the third sub-channel SC3 and the first sub-gate 223a may be smaller than the capacitance of the parasitic capacitor formed between the first active channel 221c1 and the second sub-gate 223b in the corresponding pixel region PA. Therefore, in a display device according to an embodiment of the present disclosure, the S factor of the second thin film transistor TR2 in each pixel region PA may be increased by the distance between the second sub-channel SC2 and the first sub-gate 223a, and the distance between the third sub-channel SC3 and the first sub-gate 223a in the pixel region PA. For example, in a display device according to an embodiment of the present disclosure, the change amount of the current flowing through the second active region A2 of the corresponding pixel region PA according to the change amount of the voltage applied to the first sub-gate 223a of each pixel region PA may not be large. Therefore, in a display device according to an embodiment of the present disclosure, the characteristic deviation of the second thin film transistor TR2 can be effectively prevented or reduced.

[0118] The upper interlayer insulating layer 160 may be disposed on the second upper gate insulating layer 123. The upper interlayer insulating layer 160 may cover the first sub-gate 223a of each pixel region PA. The upper interlayer insulating layer 160 may include an insulating material. For example, the upper interlayer insulating layer 160 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0119] The first drain electrode 215, the first source electrode 217, the second drain electrode 225, the second source electrode 227, and the connection gate 223c of each pixel region PA may be disposed on the upper interlayer insulating layer 160. For example, the first drain electrode 215 and the first source electrode 217 of each pixel region PA may be insulated from the first gate electrode 213 of the corresponding pixel region PA through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The connection gate 223c of each pixel region PA may be spaced apart from the first sub-gate 223a of the corresponding pixel region PA through the upper interlayer insulating layer 160. For example, the first sub-gate 223a of each pixel region PA may be insulated from the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA through the upper interlayer insulating layer 160.

[0120] The first drain electrode 215 of each pixel region PA may be electrically connected to the first drain region of the first semiconductor pattern 211 in the corresponding pixel region PA through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The first source electrode 217 of each pixel region PA may be electrically connected to the first source region of the first semiconductor pattern 211 in the corresponding pixel region PA through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The second drain electrode 225 of each pixel region PA may be electrically connected to the first active drain 221d1 and the second active drain 221d2 of the second semiconductor pattern 221 in the corresponding pixel region PA through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The second source electrode 227 of each pixel region PA may be electrically connected to the first active source 221s1 and the second active source 221s2 of the second semiconductor pattern 221 in the corresponding pixel region PA through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160.

[0121] The second upper gate insulating layer 123 and the upper interlayer insulating layer 160 may include first contact holes that partially expose the second sub-gate 223b of each pixel region PA. The upper interlayer insulating layer 160 may include second contact holes that partially expose the first sub-gate 223a of each pixel region PA. The connection gate 223c of each pixel region may be connected to the second sub-gate 223b of the corresponding pixel region PA through one of the first contact holes. The connection gate 223c of each pixel region may be connected to the first sub-gate 223a of the corresponding pixel region PA through one of the second contact holes. The first contact holes and the second contact holes may be formed simultaneously with the contact holes that connect the second drain electrode 225 of each pixel region PA to the first active drain 221d1 and the second active drain 221d2 of the corresponding pixel region PA and the contact holes that connect the second source electrode 227 of each pixel region PA to the first active source 221s1 and the second active source 221s2 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, a reduction in process efficiency due to the process of forming the second gate electrode 223 of each pixel region PA may be minimized or reduced.

[0122] The first capacitor electrode 251 of each pixel region PA may be spaced apart from the second capacitor electrode 252 of the corresponding pixel region PA by the second upper gate insulating layer 123. For example, the first capacitor electrode 251 of each pixel region PA may be disposed between the first upper gate insulating layer 122 and the second upper gate insulating layer 123. The second capacitor electrode 252 of each pixel region PA may be spaced apart from the third capacitor electrode 253 of the corresponding pixel region PA by the upper interlayer insulating layer 160. For example, the second capacitor electrode of each pixel region PA may be disposed between the second upper gate insulating layer 123 and the upper interlayer insulating layer 160. The third capacitor electrode of each pixel region PA may be disposed on the upper interlayer insulating layer 160.

[0123] The circuit drain electrode 295 and the circuit source electrode 297 may be disposed on the upper interlayer insulating layer 160. For example, the circuit drain electrode 295 may be connected to the circuit drain region of the circuit semiconductor pattern 291 by passing through the lower gate insulating layer 121, the lower interlayer insulating layer 130, the separation insulating layer 140, the upper buffer layer 150, the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160, and the circuit source electrode 297 may be connected to the circuit source region of the circuit semiconductor pattern 291 by passing through the lower gate insulating layer 121, the lower interlayer insulating layer 130, the separation insulating layer 140, the upper buffer layer 150, the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. Accordingly, in the display device according to an embodiment of the present disclosure, a reduction in process efficiency due to the process of forming the circuit thin film transistor 290 may be minimized or reduced.

[0124] The lower planarization layer 170 may be disposed on the upper interlayer insulating layer 160. The upper planarization layer 180 may be disposed on the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may eliminate the thickness difference caused by the pixel driving circuit DC of each pixel region PA. For example, the upper surface of the upper planarization layer 180 opposite to the device substrate 100 may be a flat surface. The first drain electrode 215, the first source electrode 217, the second drain electrode 225, the second source electrode 227, the connection gate 223c, and the third capacitor electrode 253 of each pixel region PA may be covered by the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may extend onto the border region BZ of the device substrate 100. For example, the lower planarization layer 170 and the upper planarization layer 180 may be stacked on the circuit drain electrode 295 and the circuit source electrode 297. The thickness difference caused by the circuit thin film transistor 290 may be removed by the lower planarization layer 170 and the upper planarization layer 180.

[0125] The lower planarization layer 170 and the upper planarization layer 180 may include an insulating material. The lower planarization layer 170 and the upper planarization layer 180 may include a material different from that of the upper interlayer insulating layer 160. The lower planarization layer 170 and the upper planarization layer 180 may have a material with relatively high fluidity. For example, the lower planarization layer 170 and the upper planarization layer 180 may include an organic insulating material. The upper planarization layer 180 may include the same material as the lower planarization layer 170. For example, the interface between the lower planarization layer 170 and the upper planarization layer 180 may not be recognized. For example, one or both of the lower planarization layer 170 and the upper planarization layer 180 may be made of one or more materials selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, unsaturated polyester resin, polystyrene resin, polyphenylene sulfide resin, and benzocyclobutene, but the embodiments are not limited thereto.

[0126] The light-emitting device 500 of each pixel region PA may be disposed on the upper planarization layer 180 of the corresponding pixel region PA. For example, the light-emitting device 500 of each pixel region PA may be supported by the corresponding pixel region PA of the device substrate 100. The light-emitting device 500 of each pixel region PA may emit light of a specific color for display. For example, the light-emitting device 500 of each pixel region PA may include a first electrode 510, a light-emitting layer 520, and a second electrode 530 that are sequentially stacked on the upper planarization layer 180 of the corresponding pixel region PA.

[0127] The first electrode 510 may include a conductive material. The first electrode 510 may include a material having a high reflectivity. For example, the first electrode 510 may include a metal such as aluminum (Al) or silver (Ag). The first electrode 510 may have a multilayer structure. For example, the first electrode 510 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO and IZO.

[0128] The light-emitting layer 520 may generate light having a brightness corresponding to the voltage difference between the first electrode 510 and the second electrode 530. For example, the light-emitting layer 520 may include at least one light-emitting material layer (EML). The light-emitting material layer may include a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic light-emitting material, but the present disclosure is not limited thereto.

[0129] The light-emitting layer 520 may include at least one functional layer for smoothly providing holes or electrons. For example, the light-emitting layer 520 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in the display device according to an embodiment of the present disclosure, the efficiency of the light-emitting layer 520 may be improved.

[0130] The second electrode 530 may include a conductive material. The second electrode 530 may include a material different from that of the first electrode 510. The transmittance of the second electrode 530 may be greater than that of the first electrode 510. For example, the second electrode 530 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. Therefore, in the display device according to an embodiment of the present disclosure, the light generated by the light-emitting layer 520 may be emitted to the outside through the second electrode 530.

[0131] The light-emitting device 500 of each pixel region PA can be electrically connected to the second thin-film transistor TR2 of the corresponding pixel region PA. For example, the first electrode 510 of each pixel region PA can be electrically connected to the second source electrode 227 of the corresponding pixel region PA. The first electrode 510 of each pixel region PA can include a portion that is in direct contact with the upper surface of the upper planarization layer 180 on the corresponding pixel region PA. The light-emitting layer 520 and the second electrode 530 of each pixel region PA can be stacked on the portion of the corresponding first electrode 510 that is in direct contact with the upper surface of the upper planarization layer 180. Accordingly, in the display device according to an embodiment of the present disclosure, luminance deviation according to the light generation position of the light emitted from the light-emitting device 500 of each pixel region PA can be prevented or reduced.

[0132] The intermediate electrode 400 that electrically connects the first electrode 510 of each pixel region PA to the second source electrode 227 of the corresponding pixel region PA can be disposed between the lower planarization layer 170 and the upper planarization layer 180. The intermediate electrode 400 can include a conductive material. For example, the intermediate electrode 400 can include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and / or tungsten (W). Each intermediate electrode 400 can be in direct contact with the second source electrode 227 and the first electrode 510 in one of the pixel regions PA. For example, the first electrode 510 of each pixel region PA can be in contact with one of the intermediate electrodes 400 by penetrating the upper planarization layer 180, and each intermediate electrode 400 can be in contact with the second source electrode 227 in one of the pixel regions PA by penetrating the lower planarization layer 170. Accordingly, in the display device according to an embodiment of the present disclosure, the first electrode 510 of each pixel region PA can be stably connected to the second source electrode 227 of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, the reliability of the electrical connection between the pixel driving circuit DC and the light-emitting device 500 in each pixel region PA can be improved. However, the present disclosure is not limited thereto. For example, the intermediate electrode 400 can be omitted, and the first electrode 510 of each pixel region PA can be directly connected to the second source electrode 227 of the corresponding pixel region PA.

[0133] The bank insulating layer 190 may be disposed on the upper planarization layer 180. The bank insulating layer 190 may define a light-emitting region in each pixel region PA. For example, the first electrode 510 of each pixel region PA may be partially exposed by the bank insulating layer 190. The portion of each first electrode 510 exposed by the bank insulating layer 190 may be a region in direct contact with the upper surface of the upper planarization layer 180. For example, the light-emitting layer 520 and the second electrode 530 of each pixel region PA may be stacked on the portion of the corresponding first electrode 510 exposed by the bank insulating layer 190. The edge of the first electrode 510 in each pixel region PA may be covered by the bank insulating layer 190. For example, the first electrode 510 of each pixel region PA may be insulated from the first electrode 510 of an adjacent pixel region PA through the bank insulating layer 190. The bank insulating layer 190 may include an insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin. Alternatively, the bank insulating layer 190 may include an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. For example, the bank insulating layer 190 may include an organic insulating material. The bank insulating layer 190 may include a material different from that of the upper planarization layer 180. In addition, the bank insulating layer 190 may be made of an insulating material containing a black material. The bank insulating layer 190 may be made of, for example, a transparent carbon-based mixture. Specifically, the bank insulating layer 190 may contain carbon black, but is not limited thereto. The bank insulating layer 190 may also be made of a transparent insulating material.

[0134] The light emitted from the light-emitting device 500 of each pixel region PA may display a color different from the light emitted from the light-emitting device 500 of an adjacent pixel region PA. For example, the light-emitting layer 520 of each pixel region PA may be spaced apart from the light-emitting layer 520 of an adjacent pixel region PA. The light-emitting layer 520 of each pixel region PA may include an end portion on the bank insulating layer 190. For example, the light-emitting layer 520 of each pixel region PA may include a material different from that of the light-emitting layer 520 of an adjacent pixel region PA.

[0135] The voltage applied to the second electrode 530 of each pixel region PA may be the same as the voltage applied to the second electrode 530 of an adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA may be electrically connected to the second electrode 530 of an adjacent pixel region PA. The second electrode 530 of each pixel region PA may include the same material as the second electrode 530 of an adjacent pixel region PA. The second electrode 530 of each pixel region PA may be formed by the same process as the second electrode 530 of an adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA may be formed simultaneously with the second electrode 530 of an adjacent pixel region PA. The second electrode 530 of each pixel region PA may be in direct contact with the second electrode 530 of an adjacent pixel region PA. For example, the bank insulating layer 190 may be covered by the second electrode 530. Thus, in a display device according to an embodiment of the present disclosure, the process of forming the second electrode 530 in each pixel region PA may be simplified. In addition, in a display device according to an embodiment of the present disclosure, the luminance of the light generated by the light-emitting layer 520 in each pixel region PA may be adjusted by a data signal applied to a pixel driving circuit DC in the corresponding pixel region PA.

[0136] The encapsulation unit 600 may be disposed on the light-emitting device 500 of each pixel region PA. The encapsulation unit 600 may prevent or reduce damage to the light-emitting device 500 due to external moisture and impact. The encapsulation unit 600 may have a multilayer structure. For example, the encapsulation unit 600 may include a first encapsulation layer 610, a second encapsulation layer 620, and a third encapsulation layer 630 stacked in sequence, but the present disclosure is not limited thereto. The first encapsulation layer 610, the second encapsulation layer 620, and the third encapsulation layer 630 may include insulating materials. The second encapsulation layer 620 may include a material different from that of the first encapsulation layer 610 and the third encapsulation layer 630. For example, the first encapsulation layer 610 and the third encapsulation layer 630 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx) that can be deposited at low temperatures, and the second encapsulation layer 620 may include an organic insulating material. The thickness difference caused by the light-emitting device 500 of each pixel region PA may be removed by the second encapsulation layer 620. For example, the upper surface of the encapsulation unit 600 opposite to the device substrate 100 may be a flat surface. Thus, in a display device according to an embodiment of the present disclosure, damage to the light-emitting device 500 in each pixel region PA due to external moisture and impact may be effectively prevented or reduced.

[0137] Therefore, a display device according to an embodiment of the present disclosure may include a pixel driving circuit DC respectively connected to a light emitting device 500, wherein a second thin film transistor TR2 of each pixel driving circuit DC may include a second gate electrode 223 on a part of a second semiconductor pattern 221, wherein the second gate electrode 223 may include a first sub-gate 223a overlapping a second channel region 221c of the second semiconductor pattern 221 and a second sub-gate 223b disposed between the second semiconductor pattern 221 and the first sub-gate 223a, and wherein the second channel region 221c may include a first active channel 221c1 completely overlapping the second sub-gate 223b and a second active channel 221c2 partially overlapping the second sub-gate 223b. Therefore, in a display device according to an embodiment of the present disclosure, the driving current generated by the second thin film transistor TR2 in each pixel driving circuit DC can be reduced to implement a low gray level image without degrading the characteristics of the second thin film transistor TR2 in each pixel region PA. In addition, in a display device according to an embodiment of the present disclosure, the S factor of the second thin film transistor TR2 in each pixel driving circuit DC can be increased. Therefore, in a display device according to an embodiment of the present disclosure, the efficiency of the second thin film transistor TR2 of each pixel driving circuit DC can be improved. Further, in a display device according to an embodiment of the present disclosure, the reliability of each pixel driving circuit DC and the image quality can be improved.

[0138] A display device according to an embodiment of the present disclosure is described such that the pixel driving circuit DC of each pixel region PA may include a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst. However, in a display device according to another embodiment of the present disclosure, the pixel driving circuit DC of each pixel region PA may include a driving thin film transistor and at least one switching thin film transistor. For example, in a display device according to another embodiment of the present disclosure, the pixel driving circuit DC of each pixel region PA may further include a third thin film transistor for initializing the storage capacitor Cst according to a gate signal. The third thin film transistor of each pixel region PA may include a third semiconductor pattern, a third gate electrode, a third drain electrode, and a third source electrode. For example, the third gate electrode of each pixel region PA may be electrically connected to a corresponding gate line GL, the third drain electrode of each pixel region PA may be electrically connected to an initial line to which an initial signal is applied, and the third source electrode of each pixel region PA may be electrically connected to the storage capacitor Cst of the corresponding pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC can be improved.

[0139] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 in each pixel driving circuit DC may vary depending on the configuration of the corresponding pixel driving circuit DC and / or the types of the corresponding thin film transistors TR1 and TR2. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each pixel driving circuit DC may be electrically connected to the first drain electrode 215 of the corresponding pixel driving circuit DC. Therefore, in a display device according to another embodiment of the present disclosure, the degrees of freedom of the types of each thin film transistor TR1 and TR2 and the configuration of each pixel driving circuit DC can be increased.

[0140] A display device according to an embodiment of the present disclosure is described such that the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA may be made of an oxide semiconductor. However, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 of each pixel region PA may include a material different from that of the first semiconductor pattern 211 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the first semiconductor pattern 211 of each pixel region PA may include amorphous silicon (a-Si) or polycrystalline silicon (poly-Si). The first thin film transistor TR1 of each pixel region PA may be formed to have the same structure as the circuit thin film transistor 290. For example, the first semiconductor pattern 211 of each pixel region PA may be disposed between the lower buffer layer 110 and the lower gate insulating layer 121, and the first gate electrode 213 of each pixel region PA may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130. The first semiconductor pattern 211 of each pixel region PA may include the same material as the circuit semiconductor pattern 291. For example, the first semiconductor pattern of each pixel region PA may include low temperature polycrystalline silicon (LTPS). In a display device according to another embodiment of the present disclosure, the first light blocking pattern 310 of each pixel region PA may not be formed. Therefore, in a display device according to another embodiment of the present disclosure, the degrees of freedom of the types of each thin film transistor TR1 and TR2 and the configuration of each pixel driving circuit DC can be increased.

[0141] A display device according to an embodiment of the present disclosure is described such that the first active region A1 of each pixel region PA may be disposed between the second active region A2 of the corresponding pixel region PA and the connection gate 223c. However, in a display device according to another embodiment of the present disclosure, the second active region A2 of each pixel region PA may be disposed between the first active region A1 of the corresponding pixel region PA and the connection gate 223c, as Figure 10As shown. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom in the positions of the first active region A1 and the second active region A2 in each pixel region PA can be increased.

[0142] A display device according to an embodiment of the present disclosure has been described such that the first sub-gate 223a of each pixel region PA can be disposed on a different layer from the second source electrode 227, the first drain electrode 215, the first source electrode 217, and the second drain electrode 225 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the first sub-gate 223a of each pixel region PA can be disposed on the same layer as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA, as Figure 11 and Figure 12 shown. The first sub-gate 223a of each pixel region PA can include the same material as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. The first sub-gate 223a of each pixel region PA can be formed by the same process as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. For example, the first sub-gate 223a of each pixel region PA can be formed simultaneously with the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. The first sub-gate 223a of each pixel region PA can be spaced apart from the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. For example, the first sub-gate 223a of each pixel region PA can be in direct contact with the second sub-gate 223b of the corresponding pixel region PA by passing through the second upper gate insulating layer 123. Accordingly, in a display device according to another embodiment of the present disclosure, a reduction in process efficiency caused by the process of forming the second gate electrode 223 in each pixel region PA can be minimized or reduced, and the efficiency of the second thin film transistor TR2 in each pixel region PA can be increased.

[0143] In a display device according to another embodiment of the present disclosure, a first capacitor electrode 251 of each pixel region PA may be disposed on the same layer as a second light-blocking pattern 320 of the corresponding pixel region PA, a second capacitor electrode 252 of each pixel region PA may be disposed on the same layer as a second sub-gate 223b of the corresponding pixel region PA, and a third capacitor electrode of each pixel region PA may be disposed on the same layer as a first sub-gate 223a of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, a storage capacitor Cst of each pixel region PA may include a first capacitor electrode 251 between a separation insulating layer 140 and an upper buffer layer 150, a second capacitor electrode 252 between a first upper gate insulating layer 122 and a second upper gate insulating layer 123, and a third capacitor electrode 253 between the second upper gate insulating layer 123 and a lower planarization layer 170. Accordingly, in a display device according to another embodiment of the present disclosure, an increase in the size of the storage capacitor in each pixel region PA according to the position of the first sub-gate 223a in the corresponding pixel region PA may be minimized or reduced. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the pixel driving circuit DC in each pixel region PA may be increased.

[0144] A display device according to an embodiment of the present disclosure has been described such that a channel of a first active region A1 in each pixel region PA may be formed by a second sub-gate 223b of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, a first active region A1 in each pixel region PA may be activated by a first sub-gate 223a of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, as Figures 13 to 16 shown, a first active region A1 in each pixel region PA may be disposed outside a second sub-gate 223b of the corresponding pixel region PA.

[0145] Only the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may be provided between the first active channel 221c1 and the first sub-gate 223a in each pixel region PA, without the second sub-gate 223b being interposed therebetween. The second active channel 221c2 of each pixel region PA may include a first sub-channel SC1, a second sub-channel SC2, and a third sub-channel SC3. The first sub-channel SC1 of each pixel region PA may overlap with the second sub-gate 223b of the corresponding pixel region PA. The second sub-channel SC2 and the third sub-channel SC3 of each pixel region PA may be provided outside the second sub-gate 223b of the corresponding pixel region PA. For example, only the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may be provided between the second sub-channel SC2 and the first sub-gate 223a in each pixel region PA and between the third sub-channel SC3 and the first sub-gate 223a in each pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, a channel of the first active channel 221c1, a channel of the second sub-channel SC2, and a channel of the third sub-channel SC3 may be formed by a voltage applied to the first sub-gate 223a, and a channel of the first sub-channel SC1 may be formed by a voltage applied to the second sub-gate 223b.

[0146] The channels of the first active channel 221c1, the second sub-channel SC2, and the third sub-channel SC3 in each pixel region PA may be formed at a lower voltage than the channel of the first sub-channel SC1 in the corresponding pixel region PA. For example, the first active channel 221c1, the second sub-channel SC2, and the third sub-channel SC3 of each pixel region PA may be doped with conductive impurities. The first active channel 221c1, the second sub-channel SC2, and the third sub-channel SC3 of each pixel region PA may have a smaller resistance than the first sub-channel SC1 of the corresponding pixel region PA. The resistance of the first active channel 221c1, the second sub-channel SC2, and the third sub-channel SC3 in each pixel region PA may be greater than the resistance of the first active drain 221d1, the second active drain 221d2, the first active source 221s1, and the second active source 221s2 in the corresponding pixel region PA. For example, the first active drain 221d1, the second active drain 221d2, the first active source 221s1, and the second active source 221s2 in each pixel region PA may be doped with a higher concentration of conductive impurities than the first active channel 221c1, the second sub-channel SC2, and the third sub-channel SC3 of the corresponding pixel region PA. The second sub-channel SC2 disposed between the second active drain 221d2 and the first sub-channel SC1 in each pixel region PA and the third sub-channel SC3 disposed between the first sub-channel SC1 and the second active source 221s2 in each pixel region PA may be used as a lightly doped drain (LDD) region of the second active region A2 in the corresponding pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, the channel of the first sub-channel SC1 in each pixel region PA may be used as an effective channel of the second active channel 221c2 in the corresponding pixel region PA.

[0147] In a display device according to another embodiment of the present disclosure, when a relatively low voltage is applied to the first sub-gate 223a and the second sub-gate 223b of each pixel region PA, only the first active region A1 of each pixel region PA may be activated. Therefore, in a display device according to another embodiment of the present disclosure, the appearance of stains may be prevented or reduced, and the quality of low-gray-scale images may be improved without degrading the characteristics of the second thin-film transistor TR2 in each pixel region PA.

[0148] The distance between the first active channel 221c1 and the first sub-gate 223a in each pixel region PA may be greater than the distance between the first sub-channel SC1 and the second sub-gate 223b in the corresponding pixel region PA. Thus, in a display device according to another embodiment of the present disclosure, the first active region A1 of the second thin film transistor TR2 in each pixel may have a relatively large S factor. For example, in a display device according to another embodiment of the present disclosure, the deviation of the driving current generated by the second thin film transistor TR2 in each pixel region PA can be effectively reduced. Thus, in a display device according to another embodiment of the present disclosure, the efficiency and image quality of the second thin film transistor TR2 in each pixel region PA can be improved.

[0149] A display device according to an embodiment of the present disclosure is described such that the second active region A2 of each pixel region PA may include a first sub-channel SC1 disposed between the second sub-channel SC2 and the third sub-channel SC3 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the second active region A2 of each pixel region PA may have various structures. For example, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 may include a first active region A1 disposed outside the second sub-gate 223b and a second active region A2 disposed parallel to the first active region A1, wherein the second active region A2 may include a first sub-channel SC1 overlapping the second sub-gate 223b and a second sub-channel SC2 disposed outside the second sub-gate 223b, as Figure 17 and Figure 18 shown.

[0150] The first sub-channel SC1 may be disposed between the second active drain 221d2 and the second sub-channel SC2. The second sub-channel SC2 may be disposed between the first sub-channel SC1 and the second active source 221s2. The amount of oxygen contained in the first sub-channel SC1 may be different from the amount of oxygen contained in the second sub-channel SC2. For example, the second sub-channel SC2 may have a resistance between the second active source 221s2 and the first sub-channel SC1. The channel of the second sub-channel SC2 may be formed at a lower voltage than the channel of the first sub-channel SC1. Thus, in a display device according to another embodiment of the present disclosure, the first sub-channel SC1 may be used as an effective channel of the second active region A2. Thus, in a display device according to another embodiment of the present disclosure, the degree of freedom of the configuration of the second active region A2 in each pixel region PA can be improved.

[0151] In a display device according to another embodiment of the present disclosure, the length of the second sub-channel SC2 may be different from the length of the first sub-channel SC1. For example, in a display device according to another embodiment of the present disclosure, the length of the first sub-channel SC1 may be less than the length of the second sub-channel SC2, as Figure 17 and Figure 18 shown. Accordingly, in a display device according to another embodiment of the present disclosure, the effective channel region of the second active region A2 may be adjusted by the length of the first sub-channel SC1. Accordingly, in a display device according to another embodiment of the present disclosure, when both the first active region A1 and the second active region A2 of the corresponding pixel region PA are activated, the driving current generated by the second thin-film transistor TR2 of each pixel region PA can be effectively adjusted.

[0152] A display device according to an embodiment of the present disclosure has been described such that the second active region A2 of each pixel region PA may have the same size as the first active region A1 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the second active region A2 of each pixel region PA may have a different width and / or length from the first active region A1 of the corresponding pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, when only the first active region A1 of each pixel region PA is activated, the driving current generated by the second thin-film transistor TR2 of each pixel region PA can be effectively adjusted without degrading the characteristics of the second thin-film transistor TR2 in the corresponding pixel region PA.

[0153] A display device according to an embodiment of the present disclosure has been described such that the second active region A2 of each pixel region PA may be formed simultaneously with the first active region A1 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the second active region A2 of each pixel region PA may include a different material from the first active region A1 of the corresponding pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, when only the first active region A1 of each pixel region PA is activated, the driving current of the second thin-film transistor TR2 of each pixel region PA can be effectively adjusted. Accordingly, in a display device according to another embodiment of the present disclosure, the efficiency of the second thin-film transistor TR2 in each pixel region PA can be improved.

[0154] In a display device according to another embodiment of the present disclosure, the first sub-channel SC1 and the third sub-channel SC3 of the second active region A2 may be activated before the second sub-channel SC2 of the second active region A2. For example, in a display device according to another embodiment of the present disclosure, the second active region A2 may include a second sub-channel SC2 disposed between the first sub-channel SC1 and the third sub-channel SC3, and the resistance of the second sub-channel SC2 may be less than the resistance of the first sub-channel SC1 and the resistance of the third sub-channel SC3, as Figure 19 and Figure 20 shown. The second gate electrode 223 may include a second sub-gate 223b overlapping the first sub-channel SC1 and a third sub-gate 223d overlapping the third sub-channel SC3. The second sub-gate 223b and the third sub-gate 223d may be electrically connected to the first sub-gate 223a through a connection gate 223c. The second sub-channel SC2 may be disposed outside the second sub-gate 223b and the third sub-gate 223d. The second sub-channel SC2 may overlap the first sub-gate 223a. Accordingly, in a display device according to another embodiment of the present disclosure, the channels of the first sub-channel SC1 and the third sub-channel SC3 may be used as the effective channels of the second active region A2. Accordingly, in a display device according to another embodiment of the present disclosure, the effective channels of the second active region A2 may be effectively adjusted.

[0155] The display device according to an embodiment of the present disclosure has been described such that the second semiconductor pattern 221 of each pixel region PA may include a first active region A1 and a second active region A2, wherein the second active region A2 may be activated at a lower voltage than the first active region A1. However, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 of each pixel region PA may include a plurality of active regions A1 and A2. For example, in a display device according to another embodiment of the present disclosure, the second semiconductor pattern 221 may include a first active region A1 disposed between a second active region A2 and a third active region A3, as Figure 21 shown. Each of the first active region A1, the second active region A2, and the third active region A3 may include an active channel disposed between an active drain and an active source. The second drain electrode 225 may be electrically connected to the active drains of the first active region A1, the second active region A2, and the third active region A3. The second source electrode 227 may be electrically connected to the active sources of the first active region A1, the second active region A2, and the third active region A3.

[0156] The second gate electrode on the second semiconductor pattern 221 may include a first sub-gate 223a, a second sub-gate 223b, a first connection gate 223c, a third sub-gate 223f, and a second connection gate 223e. The first active region A1 may be activated before the second active region A2 and the third active region A3. For example, the second sub-gate 223b electrically connected to the first sub-gate 223a through the first connection gate 223c may partially overlap with the active channel of the second active region A2, the third sub-gate 223f electrically connected to the first sub-gate 223a through the second connection gate 223e may partially overlap with the active channel of the third active region A3, and the active channel of the first active region A1 may be disposed outside the second sub-gate 223b and the third sub-gate 223f. The active channel of the first active region A1 may have a conductivity corresponding to the voltage applied to the first sub-gate 223a. Therefore, in a display device according to another embodiment of the present disclosure, if a lower voltage is applied to the second gate electrode, only the first active region A1 may be activated. In addition, in a display device according to another embodiment of the present disclosure, if a higher voltage is applied to the second gate electrode, all of the first active region A1, the second active region A2, and the third active region A3 may be activated. Therefore, in a display device according to another embodiment of the present disclosure, the drive current generated by the second thin film transistor TR2 in each pixel region PA may be effectively adjusted according to the gray level of the implemented image. In addition, in a display device according to another embodiment of the present disclosure, the power consumption required to implement a low gray level image may be reduced without deteriorating the characteristics of the second thin film transistor TR2 in each pixel region PA.

[0157] In a display device according to another embodiment of the present disclosure, the channel of the active channel of the third active region A3 may be formed at a voltage different from that of the active channel of the second active region A2. For example, in a display device according to another embodiment of the present disclosure, the channel of the active channel of the first active region A1 may be formed at a first threshold voltage, the channel of the active channel of the second active region A2 may be formed at a second threshold voltage higher than the first threshold voltage, and the channel of the active channel of the third active region A3 may be formed at a third threshold voltage higher than the second threshold voltage. Therefore, in a display device according to another embodiment of the present disclosure, the width of the active region of the second semiconductor pattern 221 in each pixel region PA may be controlled according to the gray level of the image. Therefore, in a display device according to another embodiment of the present disclosure, the efficiency of the second thin film transistor TR2 in each pixel region may be effectively improved. For example, in a display device according to another embodiment of the present disclosure, the efficiency of the pixel driving circuit in each pixel region may be improved without degrading the characteristics of the second thin film transistor TR2 in the corresponding pixel region. In addition, in a display device according to another embodiment of the present disclosure, power consumption may be effectively reduced.

[0158] In a display device according to another embodiment of the present disclosure, the second sub-gate 223b and the third sub-gate 223f may be placed at various positions. For example, in a display device according to another embodiment of the present disclosure, the second sub-gate 223b may be disposed close to the second drain electrode 225, and the third sub-gate 223f may be disposed close to the second source electrode 227, as Figure 22 shown. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the second gate electrode in each pixel region may be increased.

[0159] As a result, a display device according to an embodiment of the present disclosure may include a pixel driving circuit electrically connected to a light emitting device, wherein the driving thin film transistor of the pixel driving circuit may include a semiconductor pattern, a first sub-gate, and a second sub-gate, wherein the second sub-gate may be disposed between the semiconductor pattern and the first sub-gate, and wherein at least a part of the channel region of the semiconductor pattern may not overlap with the second sub-gate. Therefore, in a display device according to an embodiment of the present disclosure, when a low gray level image is realized, only a part of the semiconductor pattern may be activated. For example, in a display device according to an embodiment of the present disclosure, when a low gray level image is realized, the occurrence of stains may be prevented or reduced without degrading the characteristics of the driving thin film transistor. Thus, in a display device according to an embodiment of the present disclosure, the quality of the image provided to the user may be improved. In addition, in a display device according to an embodiment of the present disclosure, lower power driving may be performed, and power consumption may be reduced.

[0160] Cross - Reference to Related Applications

[0161] This application claims the benefit and priority of Korean Patent Application No. 10 - 2023 - 0179958, filed in Korea on December 12, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a semiconductor pattern, the semiconductor pattern comprising a first active region and a second active region disposed parallel to the first active region; a first sub-gate, the first sub-gate being on the semiconductor pattern, the first sub-gate overlapping a first active channel of the first active region and a second active channel of the second active region; a second sub-gate, the second sub-gate being between the semiconductor pattern and the first sub-gate, and the second sub-gate being insulated from the semiconductor pattern; a drain electrode electrically connected to a drain region of the semiconductor pattern; as well as a source electrode electrically connected to a source region of the semiconductor pattern, The width of the second sub-gate on the second active channel is smaller than the width of the second sub-gate on the first active channel.

2. The display device according to claim 1, wherein: A width of the second sub-gate on the first active channel is greater than a width of the first sub-gate on the first active channel.

3. The display device according to claim 1, wherein: The second sub-gate is electrically connected to the first sub-gate, and Wherein, an insulating layer is interposed between the first sub-gate and the second sub-gate.

4. The display device according to claim 3, wherein: The first sub-gate is disposed on a different layer from the drain electrode and the source electrode.

5. The display device according to claim 4, wherein: The second sub-gate is electrically connected to the first sub-gate through a connection gate disposed outside the semiconductor pattern.

6. The display device according to claim 3, wherein: The first sub-gate is disposed on the same layer as the drain electrode and the source electrode and is spaced apart from the drain electrode and the source electrode.

7. The display device according to claim 3, wherein: The second active channel includes a first sub-channel overlapping the second sub-gate and a second sub-channel disposed outside the second sub-gate, and Wherein, the distance between the first sub-channel and the second sub-gate is smaller than the distance between the second sub-channel and the first sub-gate.

8. The display device according to claim 7, wherein: The resistance of the second sub-channel is the same as the resistance of the first sub-channel.

9. The display device according to claim 7, wherein: The second active channel includes a third sub-channel disposed outside the second sub-gate, The distance between the third sub-channel and the first sub-gate is greater than the distance between the first sub-channel and the second sub-gate, and The first sub-channel is arranged between the second sub-channel and the third sub-channel.

10. The display device according to claim 1, wherein: The semiconductor pattern includes an oxide semiconductor, and The amount of oxygen contained in the second active channel is the same as the amount of oxygen contained in the first active channel.

11. The display device according to claim 1, wherein: A width of the second sub-gate on the second active channel is smaller than a width of the first sub-gate on the second active channel.

12. The display device according to claim 1, wherein: The semiconductor pattern including the first active region and the second active region includes a single doping region, and the first active region and the second active region are doped with different impurities.

13. A display device, comprising: A first thin film transistor, the first thin film transistor is on a pixel region of the device substrate, the first thin film transistor comprising a first semiconductor pattern and a first gate electrode; a second thin film transistor, the second thin film transistor being on the pixel region of the device substrate, the second thin film transistor comprising a second semiconductor pattern and a second gate electrode; as well as a light emitting device, the light emitting device being on the pixel region of the device substrate, the light emitting device being electrically connected to the second thin film transistor, The second gate electrode includes a first sub-gate overlapping the channel region of the second semiconductor pattern and a second sub-gate disposed between the second semiconductor pattern and the first sub-gate. The channel region of the second semiconductor pattern includes a first active channel and a second active channel, the first active channel includes a portion overlapping with the second sub-gate, and the second active channel is disposed outside the second sub-gate. wherein the first active channel has a greater resistance than the second active channel, The first active channel includes a first sub-channel overlapping the second sub-gate and a second sub-channel arranged outside the second sub-gate.

14. The display device according to claim 13, wherein: The resistance of the second sub-channel is the same as the resistance of the second active channel.

15. The display device according to claim 13, wherein: The second sub-gate includes a material different from that of the first sub-gate.

16. The display device according to claim 15, wherein: The first gate electrode includes the same material as the second sub-gate.

17. The display device according to claim 15, further comprising: a first gate insulating layer between the second semiconductor pattern and the second sub-gate; and a second gate insulating layer, the second gate insulating layer being between the second sub-gate and the first sub-gate, The first gate electrode is disposed between the first gate insulating layer and the second gate insulating layer.

18. The display device according to claim 17, further comprising: an upper interlayer insulating layer, the upper interlayer insulating layer being on the second gate insulating layer and covering the first sub-gate; as well as a storage capacitor on the pixel region of the device substrate, The storage capacitor includes a first capacitor electrode disposed between the first gate insulating layer and the second gate insulating layer, a second capacitor electrode disposed between the second gate insulating layer and the upper interlayer insulating layer, and a third capacitor electrode disposed on the upper interlayer insulating layer.

19. The display device according to claim 13, wherein: A channel region of the first semiconductor pattern has a greater resistance than a drain region and a source region of the first semiconductor pattern, and The first sub-channel and the channel region of the first semiconductor pattern have the same resistance.

20. The display device according to claim 13, wherein: The second gate electrode further includes a third sub-gate disposed on the same layer as the second sub-gate. Wherein, the channel region of the second semiconductor pattern further includes a third active channel, the third active channel includes a portion overlapping with the third sub-gate, and Wherein, the second active channel is arranged between the first active channel and the third active channel.

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