GOA driving circuit and display panel

Abstract

According to the GOA driving circuit and the display panel provided by the invention, the GOA driving circuit comprises a driving input end, a driving scanning output end, a first capacitor element and a control unit, and the driving input end is used for receiving a first voltage in a sampling stage and receiving a second voltage in an output stage; the control unit is used for controlling the first end of the first capacitor element to receive the second voltage in the sampling stage, and the second end of the first capacitor element is electrically connected with the driving input end; the control unit is further used for controlling the first end of the first capacitor element to receive the first voltage in the output stage and controlling the second end of the first capacitor element to be electrically connected with the driving scanning output end, so that the absolute value of the output voltage of the driving scanning output end is larger than the absolute value of the first voltage. Under the condition of relatively low driving input voltage, higher gate driving working voltage is realized, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly relates to a GOA driving circuit and a display panel. Background Art

[0002] At present, with the improvement of people's living standards, various electronic products are becoming more and more popular in various fields such as office work, scientific research, medical treatment, vehicle-mounted, and aerospace. Among them, household electronic products such as laptop computers, monitors, televisions, and tablets are essential daily necessities for modern people. For a display panel, the obvious increase in the length of signal lines leads to voltage attenuation, and as the usage time increases, the TFT (Thin Film Transistor) has a positive drift in Vth (Threshold Voltage), etc., which may cause display problems such as "row missing" or "incomplete charging" (such as ghosting, dark lines). If a higher gate driving voltage is set, it will increase the load of the display chip, and also increase the power consumption of the display chip and the working temperature of the driving board. Therefore, how to achieve a higher gate driving working voltage under a relatively small gate driving input voltage while avoiding an increase in the chip load and improving display problems has become a technical problem to be solved. Summary of the Invention

[0003] The present application provides a GOA driving circuit and a display panel that can achieve a higher gate driving working voltage under a relatively small gate driving input voltage while avoiding an increase in the chip load, and improve the display effect.

[0004] In a first aspect, an embodiment of the present application provides a GOA driving circuit. The GOA driving circuit includes a plurality of cascaded GOA driving units. The working stages of the GOA driving unit include a sampling stage and an output stage. The GOA driving unit includes: A driving input terminal, configured to receive a first voltage in the sampling stage and a second voltage in the output stage; A driving scan output terminal, A first capacitive element, A control unit, where the control unit is electrically connected to the driving input terminal and the first capacitive element; The control unit is configured to control the first end of the first capacitive element to receive the second voltage in the sampling stage, and the second end of the first capacitive element is electrically connected to the driving input terminal; The control unit is further configured to control the first end of the first capacitive element to receive the first voltage in the output stage, and control the second end of the first capacitive element to be electrically connected to the driving scan output terminal, so that the absolute value of the output voltage of the driving scan output terminal is greater than the absolute value of the first voltage.

[0005] The GOA driving unit provided by this application, by designing that the GOA driving unit includes a driving input terminal, a driving scan output terminal, a first capacitive element, and a control unit, the driving input terminal is used to receive a first voltage during the sampling stage and a second voltage during the output stage; the control unit is electrically connected to the driving input terminal and the first capacitive element; the control unit is used to control the first end of the first capacitive element to receive the second voltage during the sampling stage, and the second end of the first capacitive element is electrically connected to the driving input terminal; the control unit is further used to control the first end of the first capacitive element to receive the first voltage during the output stage, and control the second end of the first capacitive element to be electrically connected to the driving scan output terminal, so that the absolute value of the output voltage of the driving scan output terminal is greater than the absolute value of the first voltage, realizing a higher gate driving operating voltage under the condition of a relatively low driving input voltage, forming a gate driving circuit with high thrust, and improving the problem of display defects caused by a long signal line length or a positive drift of Vth (threshold voltage) of the TFT, etc., without increasing the chip load, and improving the display effect.

[0006] In an optional implementation manner, during the output stage, the output voltage of the driving scan output terminal is (2×V1 - V2), where V1 is the first voltage and V2 is the second voltage, the absolute value of the second voltage is greater than the absolute value of the first voltage, and one of the first voltage and the second voltage is a high level and the other is a low level.

[0007] In an optional implementation manner, the control unit includes: A first switch unit, the first end of the first switch unit is electrically connected to the driving input terminal, the second end of the first switch unit is electrically connected to the second end of the first capacitive element, the first switch unit is in a conducting state during the sampling stage, and the first switch unit is in an off state during the output stage; A second switch unit, the first end of the second switch unit is electrically connected to the second end of the first switch unit, and the second end of the second switch unit is electrically connected to the driving scan output terminal; the second switch unit is in an off state during the sampling stage, and the second switch unit is in a conducting state during the output stage; A sixth switch unit, the first end of the sixth switch unit is electrically connected to the first end of the first capacitive element, and the other end of the sixth switch unit is loaded with the second voltage; the sixth switch unit is in a conducting state during the sampling stage, and the sixth switch unit is in an off state during the output stage; A seventh switching unit, a first end of the seventh switching unit is electrically connected to a first end of the first capacitive element, and the other end of the seventh switching unit is loaded with the first voltage; the seventh switching unit is in an off state during the sampling phase, and the seventh switching unit is in an on state during the output phase.

[0008] In an alternative embodiment, the GOA driving unit further includes: A driving transfer output terminal, the driving transfer output terminal is electrically connected to the control unit, The control unit is further configured to control the driving transfer output terminal to receive the second voltage during the sampling phase; The control unit is further configured to control the driving transfer output terminal to receive the first voltage during the output phase.

[0009] In an alternative embodiment, the control unit further includes: A fourth switching unit, a first end of the fourth switching unit is electrically connected to the driving transfer output terminal, and the other end of the fourth switching unit is loaded with the first voltage; the fourth switching unit is in an off state during the sampling phase, and the fourth switching unit is in an on state during the output phase; A ninth switching unit, a first end of the ninth switching unit is electrically connected to the driving transfer output terminal, and the other end of the ninth switching unit is loaded with the second voltage; the ninth switching unit is in an on state during the sampling phase, and the ninth switching unit is in an off state during the output phase.

[0010] In an alternative embodiment, the GOA driving unit further includes a first voltage terminal, a second voltage terminal, a first resistor, and a second capacitive element. The first voltage terminal is configured to output the first voltage, and the second voltage terminal is configured to output a second voltage; the control unit further includes a third switching unit and a fifth switching unit; A control end of the first switching unit is further electrically connected to the second voltage terminal through the first resistor, so that the first switching unit is in an on state during the sampling phase; The control end of the first switching unit is electrically connected to a first end of the second capacitive element through the fifth switching unit, and a second end of the second capacitive element is electrically connected to the first voltage terminal; the first end of the second capacitive element is further electrically connected to the driving input terminal through the third switching unit; During the sampling phase, the third switching unit is in an on state, the fifth switching unit is in an off state, and the second capacitive element stores the first voltage; In the output stage, the third switching unit is in an off state, the fifth switching unit is in an on state, and the second capacitive element controls the first switching unit to be in an off state through the fifth switching unit.

[0011] In an alternative embodiment, the control terminal of the ninth switching unit is electrically connected to the second voltage terminal through the first resistor and to the first terminal of the second capacitive element through the fifth switching unit, so that the ninth switching unit is in an on state in the sampling stage and in an off state in the output stage; And / or, the control terminal of the second switching unit is electrically connected to the first terminal of the first resistor, so that the second switching unit is in an off state in the sampling stage and in an on state in the output stage; And / or, the control terminal of the fourth switching unit is electrically connected to the second terminal of the second switching unit, so that the fourth switching unit is in an off state in the sampling stage and in an on state in the output stage; And / or, the control terminals of the sixth switching unit and the third switching unit are both electrically connected to the first clock signal, and the first clock signal outputs the first voltage in the sampling stage and outputs the second voltage in the output stage; And / or, the control terminals of the seventh switching unit and the fifth switching unit are both electrically connected to the second clock signal, and the second clock signal outputs the second voltage in the sampling stage and outputs the first voltage in the output stage.

[0012] In an alternative embodiment, the working stage of the GOA driving unit includes a holding stage. The driving input terminal receives the second voltage in the holding stage. The control unit is configured to control the third switching unit and the first switching unit to be in an on state in the holding stage, so that the first terminal of the second capacitive element is the second voltage; The control unit further includes an eighth switching unit. The first terminal of the eighth switching unit receives the second voltage. The second terminal of the eighth switching unit is electrically connected to the driving scan output terminal. The control terminal of the eighth switching unit is electrically connected between the third switching unit and the first terminal of the second capacitive element. The eighth switching unit is in an on state in the holding stage, so that the driving scan output terminal outputs the second voltage in the holding stage.

[0013] In an alternative embodiment, the ninth switching unit is in a conducting state during the holding phase, so that the driving transmission output terminal receives the second voltage during the holding phase, and the sixth switching unit is in a conducting state during the holding phase; the second switching unit, the fourth switching unit, the fifth switching unit, and the seventh switching unit are in an off state during the holding phase; A first clock signal is electrically connected to both the control terminal of the sixth switching unit and the control terminal of the third switching unit, a second clock signal is electrically connected to both the control terminal of the seventh switching unit and the control terminal of the fifth switching unit, the first clock signal and the second clock signal have opposite phases, the first clock signal has at least one period during the holding phase, and the second clock signal has at least one period during the holding phase.

[0014] In a second aspect, the present application further provides a display panel, including the GOA driving circuit described in the first aspect and multiple rows of pixel units. The driving scan output terminal of each stage of the GOA driving unit is electrically connected to at least one row of the pixel units, the driving transmission output terminal of the previous stage of the GOA driving unit is electrically connected to the driving input terminal of the current stage of the GOA driving unit; the driving transmission output terminal of the current stage of the GOA driving unit is electrically connected to the driving input terminal of the next group of GOA driving units. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below.

[0016] Figure 1 is a top view architecture schematic diagram of a display panel provided by an embodiment of the present application; Figure 2 is an architecture schematic diagram of a GOA driving unit provided by an embodiment of the present application Figure 1 ; Figure 3 is an architecture schematic diagram of a GOA driving unit provided by an embodiment of the present application Figure 2 ; Figure 4 is Figure 3 a schematic diagram of the GOA driving unit in the sampling stage in Figure 5 is Figure 4 a simplified schematic diagram of the GOA driving unit in the sampling stage in Figure 6 is Figure 3 a schematic diagram of the GOA driving unit in the output stage in Figure 7 is Figure 6 a simplified schematic diagram of the GOA driving unit in the output stage in Figure 8 Yes Figure 3 Schematic diagram of the circuit structure in the GOA driving unit when the first clock signal XCK is at a low level and the second clock signal CK is at a high level during the holding stage; Figure 9 Yes Figure 3 Schematic diagram of the circuit structure in the GOA driving unit when the first clock signal XCK is at a high level and the second clock signal CK is at a low level during the holding stage.

[0017] Explanation of the reference numerals in the drawings: Display panel 1000; GOA driving circuit 100; pixel unit 200; GOA driving unit 10; driving input terminal Pscan(n - 1); driving scan output terminal Pscan(n); first capacitive element C1; control unit 20; first switching unit T1; sixth switching unit T6; seventh switching unit T7; second switching unit T2; driving transfer output terminal Pscan(n + 1); fourth switching unit T4; ninth switching unit T9; first voltage terminal 11; second voltage terminal 12; first resistor R1; second capacitive element C2; third switching unit T3; fifth switching unit T5; first clock signal XCK; second clock signal CK; eighth switching unit T8; low level VGL; high level VGH. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. In addition, referring to "embodiment" or "embodiment manner" in the present application means that a specific feature, structure or characteristic described in conjunction with the embodiment or embodiment manner may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in the present application may be combined with other embodiments.

[0019] When describing some embodiments, the expressions "electrically connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components have physical contact or there is an electrical signal path, such as conduction between two components through a signal line, or there may be other electrical components or circuits between two components, but there is a signal path between the two components through other electrical components. However, the term "electrically connected" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0020] For a display panel, when the gate driving voltage is transmitted along the gate signal line, due to the influence of the internal resistance of the signal line, the TFT channel resistance, and the parasitic capacitance of the trace, the voltage transmitted by the gate signal line will gradually decay. Especially in the case of a large-size display, since the length of the gate signal line is relatively long, the voltage attenuation of the gate signal line will be more serious, which easily leads to display problems such as "incomplete charging" (such as ghosting, dark lines) or "row missing" of pixel units far from the gate driving module. At the same time, when the gate driving circuit works for a long time, the TFT in the gate driving circuit will have a positive threshold voltage shift (ΔVth≥5V) due to positive bias stress (PBS), resulting in an increase in the Vgs required for the TFT in the gate driving circuit to turn on. The number of GOA units in a large-size panel is large, and the problem of uneven aging is more prominent.

[0021] In this context, if the gate driving voltage in the gate driving circuit is set to a higher voltage, this higher voltage reserves a margin for the Vth shift to ensure that the TFT in the gate driving circuit can still be normally turned on after tens of thousands of hours of operation. At the same time, the higher gate driving voltage can compensate for the transmission loss of the gate signal line to ensure that the gate-source voltage (Vgs) of the remote TFT exceeds the threshold voltage (Vth), avoiding "row missing" or "incomplete charging" (such as ghosting, dark lines) caused by insufficient voltage.

[0022] However, by setting the gate driving voltage in the gate driving circuit to a higher voltage, the load on the display control chip is increased. For a large-size panel, usually a higher gate driving voltage is required, and the higher gate driving voltage will further increase the load on the display control chip, increasing the power consumption of the display control chip and the working temperature of the driving board.

[0023] Based on this, the present application provides a GOA driving circuit with high thrust, which can achieve a higher gate driving working voltage under a relatively small gate driving input voltage without increasing the chip load, realizing high thrust and improving the display effect.

[0024] Please refer to Figure 1 , the display panel 1000 includes a GOA driving circuit 100 and a plurality of pixel units 200.

[0025] The full name of GOA is Gate On Array or Gate Driver On Array, which means integrating the gate drive on the array substrate. The GOA circuit can also be called a gate driving circuit or a line scan driving circuit.

[0026] Please refer to Figure 1 , the GOA driving circuit 100 includes multiple stages of cascaded GOA driving units 10. Each stage of the GOA driving unit 10 includes a plurality of thin film transistors (TFTs), capacitors and auxiliary circuit elements, and forms a complete driving network in series.

[0027] The GOA driving circuit 100 is disposed in the non-display area (outer peripheral wiring area) of the display panel 1000.

[0028] A plurality of pixel units 200 are arranged in an array to form multiple rows of pixel units. Each row of pixel units is electrically connected to one or two GOA driving unit 10 circuits. When each row of pixel units is electrically connected to two GOA driving unit 10 circuits, the two GOA driving unit 10 circuits are connected to the opposite ends of each row of pixel units. The signal line of the GOA driving unit 10 circuit connected to a row of pixel units is a gate signal line or a gate line, which can also be called a scan line.

[0029] Each pixel unit 200 includes a TFT switch, a storage capacitor, a liquid crystal capacitor, etc. The TFT switch is controlled by the gate line signal and allows the data line voltage to be written into the pixel electrode when it is turned on. The storage capacitor maintains the stability of the pixel voltage and prevents the brightness change caused by the leakage of the liquid crystal capacitor. The liquid crystal capacitor is composed of liquid crystal molecules sandwiched between two glass substrates, and the turning of the liquid crystal molecules is controlled by an electric field to achieve the light transmittance corresponding to the written data line voltage.

[0030] The GOA circuit is directly integrated on the array substrate, and uses the same manufacturing process as the TFT in the pixel unit 200, without an external COF (Chip on Film) driving chip, to achieve the function of line-by-line scanning drive.

[0031] The working stages of the GOA driving unit 10 include a sampling stage and an output stage.

[0032] The output stage of the GOA driving unit 10 is the stage of outputting the gate driving voltage to a row of pixel units 200 connected thereto (i.e., the line scan time period). Among them, the sampling stage is the stage before outputting the gate driving voltage to the pixel unit 200 and preparing to boost the gate driving voltage.

[0033] Please refer to Figure 2 and Figure 3 The GOA driving unit 10 includes a driving input terminal Pscan(n - 1), a driving scan output terminal Pscan(n), a first capacitive element C1, and a control unit 20.

[0034] The driving input terminal Pscan(n - 1) of the current - stage GOA driving unit 10 is electrically connected to the driving transfer output terminal of the previous - stage GOA driving unit 10.

[0035] The driving scan output terminal Pscan(n) of the current - stage GOA driving unit 10 is electrically connected to a row of pixel units 200 for outputting a gate driving voltage.

[0036] Please refer to Figure 4 and Figure 5 The driving input terminal Pscan(n - 1) is used to receive a first voltage V1 during the sampling stage. The voltage received by the driving input terminal Pscan(n - 1) of the current - stage GOA driving unit 10 during the sampling stage comes from the output voltage of the driving transfer output terminal of the previous - stage GOA driving unit 10 during the output stage.

[0037] Please refer to Figure 6 and Figure 7 The driving input terminal Pscan(n - 1) is used to receive a second voltage V2 during the output stage. The voltage received by the driving input terminal Pscan(n - 1) of the current - stage GOA driving unit 10 during the output stage comes from the output voltage of the driving transfer output terminal of the previous - stage GOA driving unit 10 during the holding stage.

[0038] Wherein, one of the first voltage V1 and the second voltage V2 is a low level VGL, and the other of the first voltage V1 and the second voltage V2 is a high level VGH.

[0039] In this embodiment, taking the first voltage V1 as the low level VGL and the second voltage V2 as the high level VGH as an example. The voltage received by the driving input terminal Pscan(n - 1) of the current - stage GOA driving unit 10 during the sampling stage comes from the low level VGL of the driving transfer output terminal of the previous - stage GOA driving unit 10 during the output stage. The voltage received by the driving input terminal Pscan(n - 1) of the current - stage GOA driving unit 10 during the output stage comes from the high level VGH of the driving transfer output terminal of the previous - stage GOA driving unit 10 during the holding stage.

[0040] It should be noted that, without special instructions, the GOA driving unit 10 refers to the current - stage GOA driving unit 10. The sampling stage refers to the sampling stage of the current - stage GOA driving unit 10, and the output stage refers to the output stage of the current - stage GOA driving unit 10.

[0041] The control unit 20 is electrically connected to the driving input terminal Pscan(n - 1) and the first capacitive element C1. The control unit 20 includes a switching unit and the like.

[0042] Please refer to Figure 4 and Figure 5 , the control unit 20 is configured to control the first end of the first capacitive element C1 to receive the second voltage V2 during the sampling phase. The second end of the first capacitive element C1 is electrically connected to the driving input terminal Pscan(n - 1). For example, the control unit 20 is configured to control the first end of the first capacitive element C1 to receive the high level VGH during the sampling phase, and the second end of the first capacitive element C1 is electrically connected to the driving input terminal Pscan(n - 1). Specifically, the control unit 20 includes a first switching unit T1 and a sixth switching unit T6. The sixth switching unit T6 is electrically connected between the first end of the first capacitive element C1 and the second voltage V2 terminal. There is a first switching unit T1 electrically connected between the second end of the first capacitive element C1 and the driving input terminal Pscan(n - 1). The first switching unit T1 and the sixth switching unit T6 are in a conducting state during the sampling phase. In this way, the high level VGH is loaded at the first end of the first capacitive element C1, and the low level VGL is loaded at the second end of the first capacitive element C1. The potential difference across the first capacitive element C1 is (VGH - VGL).

[0043] Figure 4 In [the figure], the red line represents the high level. The blue line represents the low level. The gray represents the off state. Figure 5 is Figure 4 a simplified schematic diagram of

[0044] The control unit 20 is further configured to control the first end of the first capacitive element C1 to receive the first voltage V1 during the output phase, and control the second end of the first capacitive element C1 to be electrically connected to the driving scan output terminal Pscan(n), so that the absolute value of the output voltage of the driving scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1. For example, the control unit 20 is further configured to control the first end of the first capacitive element C1 to receive the high level VGH during the output phase, and control the second end of the first capacitive element C1 to be electrically connected to the driving scan output terminal Pscan(n), so that the absolute value of the output voltage of the driving scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1.

[0045] Specifically, please refer to Figure 6 and Figure 7, the control unit 20 includes a seventh switching unit T7, and the seventh switching unit T7 is electrically connected between the first end of the first capacitive element C1 and the first voltage V1 terminal. The control unit 20 includes a second switching unit T2, and the second switching unit T2 is electrically connected between the second end of the first capacitive element C1 and the driving scan output terminal Pscan(n). In this way, a low level VGL is applied to the first end of the first capacitive element C1. Since the potential difference across the first capacitive element C1 during the sampling phase is (VGH - VGL). According to the KVL formula, the potential of the driving scan output terminal Pscan(n) is VGL - (VGH - VGL), that is, 2×VGL - VGH. Among them, the voltage value of 2×VGL - VGH is less than VGL. The absolute value of 2×VGL - VGH is greater than the absolute value of VGL.

[0046] Figure 6 In the figure, the red line represents the high level. The blue line represents the low level. The gray represents the open state. Figure 7 is Figure 6 a simplified schematic diagram of.

[0047] In other words, in the output stage, the output voltage of the driving scan output terminal Pscan(n) is (2×V1 - V2), where V1 is the first voltage V1 and V2 is the second voltage V2. The absolute value of the second voltage V2 is greater than the absolute value of the first voltage V1, and one of the first voltage V1 and the second voltage V2 is the high level VGH and the other is the low level VGL. In this embodiment, the first voltage V1 is taken as the low level VGL and the second voltage V2 is taken as the high level VGH as an example.

[0048] For example, if VGL is -9v and VGH is 20v, then the potential of the driving scan output terminal Pscan(n) is -40v.

[0049] The GOA driving circuit 100 provided by the present application inputs VGL at the driving input terminal Pscan(n - 1), and the driving scan output terminal Pscan(n) can output 2×VGL - VGH. The absolute value of the voltage output by the driving scan output terminal Pscan(n) is greater than the voltage input at the driving input terminal Pscan(n - 1). Therefore, the GOA driving circuit 100 provided by the present application realizes a high-thrust effect, elevates the relatively low absolute value of the input VGL to the relatively high absolute value of 2×VGL - VGH, and improves the problem of poor display caused by a long signal line length or a positive drift of Vth (threshold voltage) of the TFT, etc., while avoiding an increase in chip load and improving the display effect.

[0050] In addition, since the row scanning of the positive-pressure driving pixel unit 200 causes a relatively large power consumption of the display control chip, in this embodiment, the row scanning of the pixel unit 200 is driven by negative pressure, which can reduce the absolute value of the input voltage, reduce the power consumption of the display control chip, and improve the heat generation problem of the driving board.

[0051] The GOA driving circuit 100 provided in this application is designed such that the GOA driving circuit 100 includes a driving input terminal Pscan(n-1), a driving scan output terminal Pscan(n), a first capacitor element C1, and a control unit 20. The driving input terminal Pscan(n-1) is configured to receive a first voltage V1 during the sampling phase and a second voltage V2 during the output phase; the control unit 20 is electrically connected to the driving input terminal Pscan(n-1) and the first capacitor element C1; the control unit 20 is configured to control the first end of the first capacitor element C1 to receive the second voltage V2 during the sampling phase, and the second end of the first capacitor element C1 is electrically connected to the driving input terminal Pscan(n-1); the control unit 20 is further configured to control the first end of the first capacitor element C1 to receive the first voltage V1 during the output phase, and control the second end of the first capacitor element C1 to be electrically connected to the driving scan output terminal Pscan(n), so that the absolute value of the output voltage of the driving scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1, achieving a higher gate driving operating voltage under a relatively low driving input voltage, forming a gate driving circuit with high driving force, and improving the problem of poor display caused by a long signal line length or a positive drift of Vth (threshold voltage) of the TFT, etc., without increasing the chip load, and enhancing the display effect.

[0052] The following takes the accompanying drawings as an example to illustrate the architecture of the control unit 20.

[0053] Optionally, please refer to Figures 4 - 7 , the control unit 20 includes a first switch unit T1.

[0054] The first end of the first switch unit T1 is electrically connected to the driving input terminal Pscan(n-1), the second end of the first switch unit T1 is electrically connected to the second end of the first capacitor element C1, the first switch unit T1 is in a conducting state during the sampling phase, and the first switch unit T1 is in an off state during the output phase.

[0055] Optionally, the first switch unit T1 is an NMOS transistor. Optionally, the control terminal of the first switch unit T1 is loaded with a high level VGH during the sampling phase. Optionally, the control terminal of the first switch unit T1 is loaded with a low level VGL during the output phase.

[0056] Further optionally, the first switching unit T1 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the first switching unit T1 is conducted to the second voltage V2 terminal during the sampling phase, and the control terminal of the first switching unit T1 is conducted to the first voltage V1 terminal during the output phase.

[0057] Alternatively, a clock signal is applied to the control terminal of the first switching unit T1. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0058] In other embodiments, the first switching unit T1 is a PMOS transistor. This embodiment can be designed with reference to the embodiment where the first switching unit T1 is an NMOS transistor.

[0059] Optionally, please refer to Figures 4 - 7 , the control unit 20 includes a second switching unit T2.

[0060] The first terminal of the second switching unit T2 is electrically connected to the second terminal of the first switching unit T1, and the second terminal of the second switching unit T2 is electrically connected to the driving scan output terminal Pscan(n). The second switching unit T2 is in an off state during the sampling phase and in an on state during the output phase.

[0061] Optionally, the second switching unit T2 is a PMOS transistor. Optionally, a high level VGH is applied to the control terminal of the second switching unit T2 during the sampling phase. Optionally, a low level VGL is applied to the control terminal of the second switching unit T2 during the output phase.

[0062] Further optionally, the second switching unit T2 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the second switching unit T2 is conducted to the second voltage V2 terminal during the sampling phase, and the control terminal of the second switching unit T2 is conducted to the first voltage V1 terminal during the output phase.

[0063] Alternatively, a clock signal is applied to the control terminal of the second switching unit T2. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0064] In other embodiments, the second switching unit T2 is an NMOS transistor. This embodiment can be designed with reference to the embodiment where the second switching unit T2 is a PMOS transistor.

[0065] Optionally, please refer to Figures 4 - 7 , the control unit 20 includes a sixth switching unit T6.

[0066] The first end of the sixth switching unit T6 is electrically connected to the first end of the first capacitive element C1, and the other end of the sixth switching unit T6 is loaded with the second voltage V2. The sixth switching unit T6 is in a conducting state during the sampling phase and in a non-conducting state during the output phase.

[0067] Optionally, the sixth switching unit T6 is a PMOS transistor. Optionally, the control terminal of the sixth switching unit T6 is loaded with a low level VGL during the sampling phase. Optionally, the control terminal of the sixth switching unit T6 is loaded with a high level VGH during the output phase.

[0068] Further optionally, the sixth switching unit T6 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the sixth switching unit T6 is in conduction with the first voltage V1 terminal during the sampling phase, and the control terminal of the sixth switching unit T6 is in conduction with the second voltage V2 terminal during the output phase.

[0069] Again optionally, the control terminal of the sixth switching unit T6 is loaded with a clock signal, the clock signal is at a low level VGL during the sampling phase, and the clock signal is at a high level VGH during the output phase.

[0070] In other embodiments, the sixth switching unit T6 is an NMOS transistor. This embodiment can be designed with reference to the embodiment where the sixth switching unit T6 is a PMOS transistor.

[0071] Optionally, please refer to Figures 4 - 7 , the control unit 20 includes a seventh switching unit T7.

[0072] The first end of the seventh switching unit T7 is electrically connected to the first end of the first capacitive element C1, and the other end of the seventh switching unit T7 is loaded with the first voltage V1. The seventh switching unit T7 is in a non-conducting state during the sampling phase and in a conducting state during the output phase.

[0073] Optionally, the seventh switching unit T7 is a PMOS transistor. Optionally, the control terminal of the seventh switching unit T7 is loaded with a high level VGH during the sampling phase. Optionally, the control terminal of the seventh switching unit T7 is loaded with a low level VGL during the output phase.

[0074] Further optionally, the seventh switching unit T7 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the seventh switching unit T7 is in conduction with the second voltage V2 terminal during the sampling phase, and the control terminal of the seventh switching unit T7 is in conduction with the first voltage V1 terminal during the output phase.

[0075] Optionally, a clock signal is applied to the control terminal of the seventh switching unit T7. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0076] In other embodiments, the seventh switching unit T7 is an NMOS transistor. This embodiment can be designed with reference to the embodiment where the seventh switching unit T7 is a PMOS transistor.

[0077] In an alternative embodiment, please refer to Figures 1 - 3 , the GOA driving unit 10 further includes a driving transfer output terminal Pscan(n + 1).

[0078] The driving transfer output terminal Pscan(n + 1) is electrically connected to the control unit 20. The driving transfer output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 is electrically connected to the driving input terminal Pscan(n - 1) of the next-stage GOA driving unit 10. The voltage signal output by the driving transfer output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 can trigger the operation of the next-stage GOA driving unit 10.

[0079] Please refer to Figures 4 - 7 , the control unit 20 is further configured to control the driving transfer output terminal Pscan(n + 1) to receive the second voltage V2 during the sampling phase. Taking the second voltage V2 as a high level VGH as an example. The control unit 20 is further configured to control the driving transfer output terminal Pscan(n + 1) to receive the first voltage V1 during the output phase. Taking the first voltage V1 as a low level VGL as an example.

[0080] That is, the control unit 20 is further configured to control the driving transfer output terminal Pscan(n + 1) to receive a high level VGH during the sampling phase and a low level VGL during the output phase. In other words, when the driving transfer output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 outputs a high level VGH during the sampling phase, the next-stage GOA driving unit 10 can be in the holding phase (i.e., the GOA driving unit 10 is in the waiting phase). When the driving transfer output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 outputs a low level VGL during the output phase, the next-stage GOA driving unit 10 can start to operate and enter the sampling phase.

[0081] In this embodiment, by designing the driving transmission output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 to output a high level VGH during the sampling stage, the next-stage GOA driving unit 10 is in the holding stage (i.e., the GOA driving unit 10 is in the waiting stage); by designing the driving transmission output terminal Pscan(n + 1) of the current-stage GOA driving unit 10 to output a low level VGL during the output stage, the next-stage GOA driving unit 10 can be made to start working and enter the sampling stage to prepare for the next-line scan.

[0082] In general display technologies, the voltage signals (sampling signals) transmitted from the previous stage to the next stage will be superimposed. For example, the sampling signal transmitted from the previous-stage GOA driving unit 10 to the current-stage GOA driving unit 10 is 5v, the sampling signal transmitted from the current-stage GOA driving unit 10 to the next-stage GOA driving unit 10 is 5v + 5v, and the sampling signal transmitted from the next-stage GOA driving unit 10 to the next-next-stage GOA driving unit 10 is 5v + 5v + 5v. Thus, the sampling signals are superimposed, which on the one hand increases the power consumption of the GOA driving circuit 100, and on the other hand, when the sampling signal of the GOA driving unit 10 is too large, it may cause problems such as device damage in the sampling signal of the GOA driving unit 10.

[0083] In this embodiment, the sampling signal transmitted from each stage of the GOA driving unit 10 to the next-stage GOA driving unit 10 is the first voltage V1 (VGL), and voltage superposition does not occur, effectively avoiding excessive power consumption of the GOA driving circuit 100 and effectively avoiding problems such as device damage in the sampling signal of the GOA driving unit 10 caused by too high a sampling signal.

[0084] In an alternative embodiment, please refer to Figures 4 - 7 , the control unit 20 further includes a fourth switch unit T4.

[0085] The first end of the fourth switch unit T4 is electrically connected to the driving transmission output terminal Pscan(n + 1), and the other end of the fourth switch unit T4 is loaded with the first voltage V1. The fourth switch unit T4 is in an open state during the sampling stage and in a conducting state during the output stage.

[0086] Optionally, the fourth switch unit T4 is a PMOS transistor. Optionally, the control end of the fourth switch unit T4 is loaded with a high level VGH during the sampling stage. Optionally, the control end of the fourth switch unit T4 is loaded with a low level VGL during the output stage.

[0087] Further optionally, the fourth switching unit T4 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the fourth switching unit T4 is turned on with the second voltage V2 terminal during the sampling phase, and the control terminal of the fourth switching unit T4 is turned on with the first voltage V1 terminal during the output phase.

[0088] Optionally again, a clock signal is applied to the control terminal of the fourth switching unit T4. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0089] In other embodiments, the fourth switching unit T4 is an NMOS transistor. This embodiment can be designed with reference to the embodiment where the fourth switching unit T4 is a PMOS transistor.

[0090] Please refer to Figures 4 - 7 , the control unit 20 further includes a ninth switching unit T9.

[0091] The first terminal of the ninth switching unit T9 is electrically connected to the drive transfer output terminal Pscan(n + 1), and the other terminal of the ninth switching unit T9 is applied with the second voltage V2. The ninth switching unit T9 is in a conducting state during the sampling phase and in a non-conducting state during the output phase.

[0092] Optionally, the ninth switching unit T9 is an NMOS transistor. Optionally, the control terminal of the ninth switching unit T9 is applied with a high level VGH during the sampling phase. Optionally, the control terminal of the ninth switching unit T9 is applied with a low level VGL during the output phase.

[0093] Further optionally, the ninth switching unit T9 is directly or indirectly electrically connected to the first voltage V1 terminal or the second voltage V2 terminal. The control terminal of the ninth switching unit T9 is turned on with the second voltage V2 terminal during the sampling phase, and the control terminal of the ninth switching unit T9 is turned on with the first voltage V1 terminal during the output phase.

[0094] Optionally again, a clock signal is applied to the control terminal of the ninth switching unit T9. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0095] In other embodiments, the ninth switching unit T9 is a PMOS transistor. This embodiment can be designed with reference to the embodiment where the ninth switching unit T9 is an NMOS transistor.

[0096] In an optional embodiment, please refer to Figures 4 - 7 , the GOA driving unit 10 further includes a first voltage terminal 11, a second voltage terminal 12, a first resistor R1, and a second capacitive element C2.

[0097] The first voltage terminal 11 is used to output the first voltage V1. The second voltage terminal 12 is used to output the second voltage V2. Taking the first voltage V1 as the low level VGL as an example, and taking the second voltage V2 as the high level VGH as an example.

[0098] Please refer to Figures 4 - 7 , the control unit 20 further includes a third switch unit T3 and a fifth switch unit T5.

[0099] The control terminal of the first switch unit T1 is also electrically connected to the second voltage terminal 12 through the first resistor R1. Both ends of the first resistor R1 are at the high level VGH, so that the first switch unit T1 is in the conducting state during the sampling stage.

[0100] The control terminal of the first switch unit T1 is electrically connected to the first end of the second capacitive element C2 through the fifth switch unit T5. The second end of the second capacitive element C2 is electrically connected to the first voltage terminal 11. The first end of the second capacitive element C2 is also electrically connected to the drive input terminal Pscan(n - 1) through the third switch unit T3.

[0101] During the sampling stage, the third switch unit T3 is in the conducting state. The fifth switch unit T5 is in the off state. The second capacitive element C2 stores the first voltage V1.

[0102] During the output stage, the third switch unit T3 is in the off state. The fifth switch unit T5 is in the conducting state. The second capacitive element C2 controls the first switch unit T1 to be in the off state through the fifth switch unit T5. Specifically, the second capacitive element C2 provides the low level VGL during the output stage, and the control terminal of the first switch unit T1 is loaded with the low level VGL. At this time, one end of the first resistor R1 connected to the control terminal of the first switch unit T1 is loaded with the low level VGL.

[0103] Optionally, the third switch unit T3 is a PMOS transistor. Optionally, the control terminal of the third switch unit T3 is loaded with the low level VGL during the sampling stage. Optionally, the control terminal of the third switch unit T3 is loaded with the high level VGH during the output stage.

[0104] Optionally, the third switch unit T3 is directly or indirectly electrically connected to the first voltage terminal 11 or the second voltage terminal 12. The control terminal of the third switch unit T3 is conducted with the first voltage terminal 11 during the sampling stage, and the control terminal of the third switch unit T3 is conducted with the second voltage terminal 12 during the output stage.

[0105] Optionally, the control terminal of the third switch unit T3 is loaded with a clock signal. The clock signal is at the low level VGL during the sampling stage and at the high level VGH during the output stage.

[0106] In other embodiments, the third switching unit T3 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the third switching unit T3 is a PMOS transistor.

[0107] Optionally, the fifth switching unit T5 is a PMOS transistor. Optionally, the control terminal of the fifth switching unit T5 is loaded with a high level VGH during the sampling phase. Optionally, the control terminal of the fifth switching unit T5 is loaded with a low level VGL during the output phase.

[0108] Further optionally, the fifth switching unit T5 is directly or indirectly electrically connected to the first voltage terminal 11 or the second voltage terminal 12. The control terminal of the fifth switching unit T5 is conducted with the second voltage terminal 12 during the sampling phase, and the control terminal of the fifth switching unit T5 is conducted with the first voltage terminal 11 during the output phase.

[0109] Alternatively, the control terminal of the fifth switching unit T5 is loaded with a clock signal. The clock signal is at a high level VGH during the sampling phase and at a low level VGL during the output phase.

[0110] In other embodiments, the fifth switching unit T5 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the fifth switching unit T5 is a PMOS transistor.

[0111] In this embodiment, please refer to Figures 4 - 7 , the control terminal of the third switching unit T3 can be loaded with a first clock signal XCK. The control terminal of the fifth switching unit T5 can be loaded with a second clock signal CK. The phase of the first clock signal XCK is opposite to that of the second clock signal CK.

[0112] In this embodiment, by designing the first capacitor element C1 and the second capacitor element C2 to store voltage during the sampling phase, the first capacitor element C1 boosts the gate drive voltage during the output phase, and the second capacitor element C2 provides the voltage for controlling the conduction of the second switching unit T2, etc. By designing the first resistor R1 to divide the voltage, the control terminal of the first switching unit T1 is at a low level VGL during the output phase, providing the voltage for controlling the conduction of the second switching unit T2, etc. This embodiment realizes the multiple functions and reuse of the devices through the design of the devices and the connection methods of each device, and realizes the function of boosting the drive voltage in this application with fewer devices.

[0113] In an alternative embodiment, please refer to Figures 4 - 7 , the control terminal of the ninth switching unit T9 is electrically connected to the second voltage terminal 12 through the first resistor R1 and to the first end of the second capacitor element C2 through the fifth switching unit T5, so that the ninth switching unit T9 is in a conducting state during the sampling phase and in a disconnected state during the output phase.

[0114] In this embodiment, by designing the architecture of the GOA driving unit 10, the on / off design of the ninth switching unit T9 at different stages can be realized, and further the output voltage of the driving transmission output terminal Pscan(n+1) can be controlled.

[0115] In an alternative embodiment, please refer to Figures 4 - 7 , the control end of the second switching unit T2 is electrically connected to the first end of the first resistor R1, so that the second switching unit T2 is in an off state during the sampling stage and in an on state during the output stage.

[0116] In this embodiment, by designing the architecture of the GOA driving unit 10, the on / off design of the second switching unit T2 at different stages can be realized, and further the output voltage of the driving scan output terminal Pscan(n) can be controlled.

[0117] In an alternative embodiment, please refer to Figures 4 - 7 , the control end of the fourth switching unit T4 is electrically connected to the second end of the second switching unit T2, so that the fourth switching unit T4 is in an off state during the sampling stage and in an on state during the output stage.

[0118] In this embodiment, by designing the architecture of the GOA driving unit 10, the on / off design of the fourth switching unit T4 at different stages can be realized, and further the output voltage of the driving transmission output terminal Pscan(n+1) can be controlled.

[0119] In an alternative embodiment, please refer to Figures 4 - 7 , the control ends of the sixth switching unit T6 and the third switching unit T3 are both electrically connected to the first clock signal XCK. The first clock signal XCK outputs the first voltage V1 during the sampling stage. The first clock signal XCK outputs the second voltage V2 during the output stage.

[0120] In this embodiment, by designing the architecture of the GOA driving unit 10, the on / off design of the sixth switching unit T6 at different stages can be realized, and further the voltage loaded on the first end of the first capacitor element C1 can be controlled, and further the first capacitor element C1 can store voltage during the sampling stage and amplify the gate driving voltage during the output stage; the on / off design of the third switching unit T3 at different stages can be realized, and further the second capacitor element C2 can be charged during the sampling stage.

[0121] In an alternative embodiment, the control ends of the seventh switching unit T7 and the fifth switching unit T5 are both electrically connected to the second clock signal CK. The second clock signal CK outputs the second voltage V2 during the sampling stage. The second clock signal CK outputs the first voltage V1 during the output stage.

[0122] In this embodiment, by designing the architecture of the GOA driving unit 10, the on / off design of the seventh switching unit T7 in different stages can be realized, thereby controlling the voltage applied to the first end of the first capacitive element C1, and further realizing the storage of voltage by the first capacitive element C1 in the sampling stage and the amplification of the gate driving voltage in the output stage; the on / off design of the fifth switching unit T5 in different stages can be realized, thereby discharging the second capacitive element C2 in the output stage of the second capacitive element C2, and further controlling the on / off state of the ninth switching unit T9.

[0123] The connection manners from the control terminal of the second switching unit T2 to the control terminal of the ninth switching unit T9 can be implemented independently of each other or simultaneously. In this embodiment, the connection manners from the control terminal of the second switching unit T2 to the control terminal of the ninth switching unit T9 above the present embodiment are taken as an example of simultaneous implementation.

[0124] In an alternative embodiment, please refer to Figure 8 and Figure 9 , the working stage of the GOA driving unit 10 includes a holding stage, and the driving input terminal Pscan(n - 1) receives the second voltage V2 in the holding stage. The control unit 20 is configured to control the third switching unit T3 and the first switching unit T1 to be in an on state in the holding stage, so that the first end of the second capacitive element C2 is the second voltage V2.

[0125] Please refer to Figure 8 and Figure 9 , the control unit 20 further includes an eighth switching unit T8. The first end of the eighth switching unit T8 receives the second voltage V2. The second end of the eighth switching unit T8 is electrically connected to the driving scan output terminal Pscan(n). The control terminal of the eighth switching unit T8 is electrically connected between the third switching unit T3 and the first end of the second capacitive element C2. The eighth switching unit T8 is in an on state in the holding stage, so that the driving scan output terminal Pscan(n) outputs the second voltage V2 in the holding stage. Taking the second voltage V2 as a high level VGH as an example.

[0126] When the driving scan output terminal Pscan(n) is the second voltage V2, the pixel unit 200 is in a non-scanning state.

[0127] The holding stage is the time period between the output stage and the next sampling stage, and the holding stage is also the stage where other GOA driving units 10 work. For example, when there are 1440 rows of pixel units 200, the holding stage of the first row of GOA driving units 10 is the scanning time period of the 2nd - 1440th row of pixel units 200.

[0128] Figure 8It is a schematic diagram of the circuit structure in the GOA driving unit 10 when the first clock signal XCK is at a low level and the second clock signal CK is at a high level during the holding stage. Figure 9 It is a schematic diagram of the circuit structure in the GOA driving unit 10 when the first clock signal XCK is at a high level and the second clock signal CK is at a low level during the holding stage.

[0129] In an optional implementation manner, the ninth switching unit T9 is in a conducting state during the holding stage, so that the driving transmission output terminal Pscan(n + 1) receives the second voltage V2 during the holding stage, thereby providing the second voltage V2 for the next-stage GOA driving unit 10 in the output stage or the holding stage. Taking the second voltage V2 as a high level VGH as an example.

[0130] The sixth switching unit T6 is in a conducting state during the holding stage. The second switching unit T2, the fourth switching unit T4, the fifth switching unit T5, and the seventh switching unit T7 are in a non-conducting state during the holding stage.

[0131] The control terminals of the sixth switching unit T6 and the third switching unit T3 are both electrically connected to the first clock signal XCK. The control terminals of the seventh switching unit T7 and the fifth switching unit T5 are both electrically connected to the second clock signal CK. The first clock signal XCK and the second clock signal CK have opposite phases. The first clock signal XCK has at least one period during the holding stage. The second clock signal CK has at least one period during the holding stage.

[0132] In the GOA driving unit 10 provided by the present application, during the holding stage, regardless of whether the levels of the first clock signal XCK and the second clock signal CK are high levels or low levels, the driving scan output terminal Pscan(n) outputs the second voltage V2 during the holding stage, and the driving transmission output terminal Pscan(n + 1) outputs the second voltage V2 during the holding stage, so that the pixel unit 200 electrically connected to the current GOA driving unit 10 is in a non-scanning state during the holding stage.

[0133] Please refer to Figures 1 - 3, the present application also provides a display panel 1000. The display panel 1000 includes the GOA driving circuit 100 and multiple rows of pixel units 200 described in any of the foregoing embodiments. The driving scan output terminal Pscan(n) of each stage of the GOA driving unit 10 is electrically connected to at least one row of the pixel units 200. The driving transfer output terminal Pscan(n + 1) of the previous stage of the GOA driving unit 10 is electrically connected to the driving input terminal Pscan(n - 1) of the current stage of the GOA driving unit 10. The driving transfer output terminal Pscan(n + 1) of the current stage of the GOA driving unit 10 is electrically connected to the driving input terminal Pscan(n - 1) of the next group of the GOA driving units 10 to drive line scanning.

[0134] The display panel 1000 includes, but is not limited to, an OLED or LCD display device.

[0135] For the display panel 1000 provided by the present application, by designing the GOA driving circuit 100 to include a driving input terminal Pscan(n - 1), a driving scan output terminal Pscan(n), a first capacitor element C1, and a control unit 20, the driving input terminal Pscan(n - 1) is used to receive a first voltage V1 during the sampling stage and a second voltage V2 during the output stage; the control unit 20 is electrically connected between the driving input terminal Pscan(n - 1) and the first capacitor element C1; the control unit 20 is used to control the first end of the first capacitor element C1 to receive the second voltage V2 during the sampling stage, and the second end of the first capacitor element C1 is electrically connected to the driving input terminal Pscan(n - 1); the control unit 20 is further used to control the first end of the first capacitor element C1 to receive the first voltage V1 during the output stage, and control the second end of the first capacitor element C1 to be electrically connected to the driving scan output terminal Pscan(n), so that the absolute value of the output voltage of the driving scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1, achieving a higher gate driving operating voltage under the condition of a relatively low driving input voltage, forming a gate driving circuit with high driving force, and improving the problem of display defects caused by a long signal line length or a positive drift of Vth (threshold voltage) of the TFT, etc., while avoiding an increase in chip load, and enhancing the display effect.

[0136] The GOA driving circuit 100 provided by the present application realizes high-voltage output under the premise of low-voltage input. The first switching unit T1, the eighth switching unit T8, and the ninth switching unit T9 are NMOS transistors, and the rest are PMOS transistors. The first clock signal XCK and the second clock signal CK are a group of clock signals with opposite phases. VGL is a low-level direct current, VGH is a high-level direct current, and the Pscan signal is a low-potential pulse signal with a normal high potential. It should be noted that in other designs, according to the characteristics of in-plane TFTs or different signals, the first switching unit T1, the eighth switching unit T8, and the ninth switching unit T9 can also be PMOS transistors, and the rest are NMOS transistors. The Scan signal can also be a high-potential pulse with a normal low potential. The schematic diagrams provided in the specification of this solution are only for illustration and do not serve as the sole reference for actual applications.

[0137] The following gives a simple description of the working cycle of the designed GOA driving circuit 100.

[0138] In the sampling stage, in this stage, the driving input terminal Pscan(n - 1) is at a low potential, the first clock signal XCK is at a low potential, and the second clock signal CK is at a high potential. At this time, the third switching unit T3 and the sixth switching unit T6 are turned on (conducted); the fifth switching unit T5 and the seventh switching unit T7 are cut off (disconnected). The connection end of the second capacitor element C2 and the third switching unit T3 is charged with a low potential. The eighth switching unit T8 is cut off. Due to the pull-up action of VGH and the first resistor R1, the second switching unit T2 is cut off and the fourth switching unit T4 is cut off. The first switching unit T1 and the ninth switching unit T9 are conducted. The driving transfer output terminal Pscan(n + 1) of the GOA driving circuit 100 outputs VGH to the next stage.

[0139] At this time, the first capacitor element C1 is charged with a low potential through the driving input terminal Pscan(n - 1) and the first switching unit T1, and the potential difference between the two ends is VGH - VGL. One end of the driving scan output terminal Pscan(n) is electrically connected to one end of the first capacitor element C1 through the second switching unit T2, and the second switching unit T2 is in an off state. The driving scan output terminal Pscan(n) is in a floating state.

[0140] In the output stage, the first clock signal XCK is at a high potential, and the second clock signal CK is at a low potential. At this time, the fifth switch unit T5 and the seventh switch unit T7 are turned on, the third switch unit T3 and the sixth switch unit T6 are turned off, the second capacitor element C2 outputs a low potential, the first switch unit T1 and the eighth switch unit T8 are turned off, and the second switch unit T2 is turned on. At this time, the circuit outputs through VGL → the first capacitor element C1 → the driving scan output terminal Pscan(n). According to the KVL formula, the potential of the driving scan output terminal Pscan(n) is 2×VGL - VGH, which is lower than VGL; at the same time, since the gate voltage of the fourth switch unit T4 is the driving scan output terminal Pscan(n), the fourth switch unit T4 is turned on and the ninth switch unit T9 is turned off. The driving transfer output terminal Pscan(n + 1) of the GOA driving circuit 100 outputs VGL to the next stage.

[0141] Two processes in the holding stage. During this process, since Pscan(n - 1) outputs a high level, the plates of the second capacitor element C2 are covered by the high level, the ninth switch unit T9 and the first switch unit T1 are continuously turned on, the second switch unit T2 is turned off. Regardless of the states of the second clock signal CK and the first clock signal XCK, the second switch unit T2 and the fourth switch unit T4 are both turned off, the eighth switch unit T8 is turned on, the driving scan output terminal Pscan(n) outputs VGH, and outputs VGH to the next stage through the ninth switch unit T9, achieving the design purpose.

[0142] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations on the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. A GOA driving circuit, characterized in that: The GOA driving circuit comprises a plurality of cascaded GOA driving units, and the working phases of the GOA driving units comprise a sampling phase and an output phase; The GOA driving unit comprises: a driving input terminal, for receiving a first voltage during the sampling phase and a second voltage during the output phase; Drive scan output terminal, The first capacitive element, a control unit, the control unit electrically connecting the driving input terminal and the first capacitive element; The control unit is used for controlling the first end of the first capacitive element to receive the second voltage during the sampling phase, and the second end of the first capacitive element is electrically connected to the driving input end; The control unit is also used to control the first end of the first capacitor element to receive the first voltage in the output stage, and control the second end of the first capacitor element to be electrically connected to the drive scan output end, so that the absolute value of the output voltage of the drive scan output end is greater than the absolute value of the first voltage.

2. The GOA driving circuit according to claim 1, characterized in that: In the output stage, the output voltage of the drive scan output terminal is (2×V1-V2), V1 is the first voltage, V2 is the second voltage, the absolute value of the second voltage is greater than the absolute value of the first voltage, and one of the first voltage and the second voltage is a high level, and the other is a low level.

3. The GOA driving circuit according to claim 1, characterized in that: The control unit comprises: a first switch unit, wherein a first end of the first switch unit is electrically connected to the driving input end, a second end of the first switch unit is electrically connected to the second end of the first capacitive element, the first switch unit is in an on state during the sampling phase, and the first switch unit is in an off state during the output phase; a second switch unit, wherein a first end of the second switch unit is electrically connected to a second end of the first switch unit, and a second end of the second switch unit is electrically connected to the drive scan output end; the second switch unit is in an off state in the sampling phase, and is in an on state in the output phase; a sixth switch unit, wherein a first end of the sixth switch unit is electrically connected to a first end of the first capacitor element, and the other end of the sixth switch unit is loaded with the second voltage; the sixth switch unit is in an on state during the sampling phase, and is in an off state during the output phase; A seventh switch unit, wherein a first end of the seventh switch unit is electrically connected to a first end of the first capacitor element, and the other end of the seventh switch unit is loaded with the first voltage; the seventh switch unit is in a disconnected state during the sampling phase, and is in a conductive state during the output phase.

4. The GOA driving circuit according to claim 3, characterized in that: The GOA driving unit also includes: a drive transmission output terminal, the drive transmission output terminal being electrically connected to the control unit, The control unit is further used to control the drive transfer output terminal to receive the second voltage during the sampling phase; The control unit is further configured to control the drive transfer output terminal to receive the first voltage during the output stage.

5. The GOA driving circuit according to claim 4, characterized in that: The control unit also includes: a fourth switch unit, wherein a first end of the fourth switch unit is electrically connected to the drive transmission output end, and the other end of the fourth switch unit is loaded with the first voltage; the fourth switch unit is in an off state during the sampling phase, and is in an on state during the output phase; A ninth switch unit, wherein a first end of the ninth switch unit is electrically connected to the drive transmission output end, and the other end of the ninth switch unit is loaded with the second voltage; the ninth switch unit is in an on state during the sampling phase, and the ninth switch unit is in an off state during the output phase.

6. The GOA driving circuit according to claim 5, characterized in that: The GOA driving unit further includes a first voltage terminal, a second voltage terminal, a first resistor, and a second capacitor element, wherein the first voltage terminal is used to output the first voltage, and the second voltage terminal is used to output the second voltage; the control unit further includes a third switch unit and a fifth switch unit; The control end of the first switch unit is also electrically connected to the second voltage end through the first resistor, so that the first switch unit is in a conducting state during the sampling phase; The control end of the first switch unit is electrically connected to the first end of the second capacitor element through the fifth switch unit, and the second end of the second capacitor element is electrically connected to the first voltage end; the first end of the second capacitor element is also electrically connected to the driving input end through the third switch unit; In the sampling phase, the third switch unit is in an on state, the fifth switch unit is in an off state, and the second capacitor element stores the first voltage; In the output stage, the third switch unit is in an off state, the fifth switch unit is in an on state, and the second capacitor element controls the first switch unit to be in an off state through the fifth switch unit.

7. The GOA driving circuit according to claim 6, characterized in that: The control end of the ninth switch unit is electrically connected to the second voltage end through the first resistor and to the first end of the second capacitor through the fifth switch unit, so that the ninth switch unit is in a conducting state during the sampling phase and in a disconnected state during the output phase; And / or, the control end of the second switch unit is electrically connected to the first end of the first resistor, so that the second switch unit is in an off state during the sampling phase and in an on state during the output phase; And / or, the control end of the fourth switch unit is electrically connected to the second end of the second switch unit, so that the fourth switch unit is in an off state during the sampling phase and in an on state during the output phase; And / or, the control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the first clock signal outputs the first voltage in the sampling phase, and the first clock signal outputs the second voltage in the output phase; And / or, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the second clock signal outputs the second voltage in the sampling phase, and the second clock signal outputs the first voltage in the output phase.

8. The GOA driving circuit according to claim 6, characterized in that: The working phase of the GOA driving unit includes a holding phase, the driving input end receives the second voltage in the holding phase, and the control unit is used to control the third switch unit and the first switch unit to be in a conducting state in the holding phase, so that the first end of the second capacitor element is the second voltage; The control unit also includes an eighth switch unit, a first end of the eighth switch unit receives the second voltage, a second end of the eighth switch unit is electrically connected to the drive scan output end, a control end of the eighth switch unit is electrically connected between the third switch unit and the first end of the second capacitor element, and the eighth switch unit is in an on state during the holding stage, so that the drive scan output end outputs the second voltage during the holding stage.

9. The GOA driving circuit according to claim 8, characterized in that: The ninth switch unit is in a conducting state during the holding phase, so that the drive transmission output terminal receives the second voltage during the holding phase. The sixth switch unit is in the on state during the holding phase; the second switch unit, the fourth switch unit, the fifth switch unit, and the seventh switch unit are in the off state during the holding phase; The control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the first clock signal and the second clock signal have opposite phases, the first clock signal has at least one cycle in the holding phase, and the second clock signal has at least one cycle in the holding phase.

10. A display panel, characterized in that: The method comprises the GOA driving circuit and a plurality of rows of pixel units according to any one of claims 1 to 9, wherein the driving scanning output terminal of each of the GOA driving units is electrically connected to at least one row of the pixel units, and the driving transfer output terminal of the GOA driving unit of the previous stage is electrically connected to the driving input terminal of the GOA driving unit of the current stage; The driving transmission output end of the GOA driving unit of the current stage is electrically connected to the driving input end of the next group of GOA driving units.

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