GOA driving circuit and display panel

Abstract

The GOA driving circuit and display panel provided in the present application are designed to include a driving input terminal, a driving scan output terminal, a first capacitor element, and a control unit. The driving input terminal is used to receive a first voltage in the sampling stage and a second voltage in the output stage; the control unit is used to control the first terminal of the first capacitor element to receive the second voltage in the sampling stage, and the second terminal of the first capacitor element is electrically connected to the driving input terminal; the control unit is also used to control the first terminal of the first capacitor element to receive the first voltage in the output stage, and control the second terminal of the first capacitor element to be electrically connected to the driving scan output terminal, so that the absolute value of the output voltage of the driving scan output terminal is greater than the absolute value of the first voltage, thereby achieving a higher gate driving operating voltage at a relatively low driving input voltage and improving the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA driving circuit and a display panel. Background Art

[0002] With the improvement of people's living standards, various electronic products are becoming increasingly popular in various fields such as office, scientific research, medical, automotive, and aerospace. Among them, home electronic products such as laptops, monitors, TVs, and tablets are indispensable daily necessities for modern people. For display panels, the significant increase in signal line length leads to voltage degradation. As well as the positive Vth (threshold voltage) drift of TFTs (thin-film transistors) over time, these factors can cause display issues such as "line dropouts" or "incomplete charging" (such as smearing and dark lines). Setting a higher gate drive voltage increases the load on the display chip, its power consumption, and the operating temperature of the driver board. Therefore, how to achieve a higher gate drive operating voltage at a relatively low gate drive input voltage while avoiding increased chip load and thus improving display issues has become a technical challenge that needs to be solved. Summary of the Invention

[0003] The present application provides a GOA driving circuit and a display panel that achieve a higher gate drive operating voltage with a relatively small gate drive input voltage while avoiding an increase in chip load, thereby improving the display effect.

[0004] In a first aspect, an embodiment of the present application provides a GOA driving circuit, the GOA driving circuit comprising a plurality of cascaded GOA driving units, wherein the working phases of the GOA driving units include a sampling phase and an output phase; the GOA driving units include:

[0005] a driving input terminal for receiving a first voltage during the sampling phase and a second voltage during the output phase;

[0006] Drive scan output terminal,

[0007] a first capacitive element,

[0008] a control unit electrically connecting the driving input terminal and the first capacitive element;

[0009] The control unit is used to control the first end of the first capacitive element to receive the second voltage during the sampling phase, and the second end of the first capacitive element to be electrically connected to the driving input end;

[0010] The control unit is also used to control the first end of the first capacitor element to receive the first voltage in the output stage, and control the second end of the first capacitor element to be electrically connected to the drive scan output end, so that the absolute value of the output voltage of the drive scan output end is greater than the absolute value of the first voltage.

[0011] The GOA driving unit provided in the present application is designed to include a driving input terminal, a driving scan output terminal, a first capacitor element, and a control unit. The driving input terminal is used to receive a first voltage in the sampling phase and a second voltage in the output phase; the control unit is electrically connected to the driving input terminal and the first capacitor element; the control unit is used to control the first terminal of the first capacitor element to receive the second voltage in the sampling phase, and the second terminal of the first capacitor element is electrically connected to the driving input terminal; the control unit is also used to control the first terminal of the first capacitor element to receive the first voltage and control the second terminal of the first capacitor element to be electrically connected to the driving scan output terminal in the output phase, so that the absolute value of the output voltage of the driving scan output terminal is greater than the absolute value of the first voltage, thereby achieving a higher gate driving operating voltage under a relatively low driving input voltage, forming a gate driving circuit with high thrust, and improving display defects caused by a long signal line length or a positive drift of the Vth (threshold voltage) of the TFT while avoiding an increase in chip load, thereby improving the display effect.

[0012] In an optional embodiment, in the output stage, the output voltage of the drive scan output end is (2×V1-V2), V1 is the first voltage, V2 is the second voltage, the absolute value of the second voltage is greater than the absolute value of the first voltage, and one of the first voltage and the second voltage is a high level and the other is a low level.

[0013] In an optional implementation, the control unit includes:

[0014] a first switch unit, wherein a first end of the first switch unit is electrically connected to the driving input end, a second end of the first switch unit is electrically connected to the second end of the first capacitive element, the first switch unit is in an on state during the sampling phase, and the first switch unit is in an off state during the output phase;

[0015] a second switch unit, wherein a first end of the second switch unit is electrically connected to a second end of the first switch unit, and a second end of the second switch unit is electrically connected to the drive scan output end; the second switch unit is in an off state during the sampling phase, and in an on state during the output phase;

[0016] a sixth switch unit, wherein a first end of the sixth switch unit is electrically connected to the first end of the first capacitor element, and the second voltage is applied to the other end of the sixth switch unit; the sixth switch unit is in an on state during the sampling phase and in an off state during the output phase;

[0017] A seventh switch unit, wherein a first end of the seventh switch unit is electrically connected to the first end of the first capacitor element, and the other end of the seventh switch unit is loaded with the first voltage; the seventh switch unit is in an off state during the sampling phase, and the seventh switch unit is in an on state during the output phase.

[0018] In an optional implementation, the GOA driving unit further includes:

[0019] a drive transmission output terminal, the drive transmission output terminal being electrically connected to the control unit,

[0020] The control unit is further configured to control the drive transfer output terminal to receive the second voltage during the sampling phase;

[0021] The control unit is further configured to control the drive transfer output terminal to receive the first voltage during the output stage.

[0022] In an optional implementation, the control unit further includes:

[0023] a fourth switch unit, wherein a first end of the fourth switch unit is electrically connected to the drive transmission output end, and the other end of the fourth switch unit is loaded with the first voltage; the fourth switch unit is in an off state during the sampling phase, and is in an on state during the output phase;

[0024] A ninth switch unit, wherein a first end of the ninth switch unit is electrically connected to the drive transmission output end, and the other end of the ninth switch unit is loaded with the second voltage; the ninth switch unit is in an on state during the sampling phase, and the ninth switch unit is in an off state during the output phase.

[0025] In an optional embodiment, the GOA driving unit further includes a first voltage terminal, a second voltage terminal, a first resistor, and a second capacitor element, wherein the first voltage terminal is used to output the first voltage, and the second voltage terminal is used to output the second voltage; the control unit further includes a third switch unit and a fifth switch unit;

[0026] The control end of the first switch unit is further electrically connected to the second voltage end via the first resistor, so that the first switch unit is in a conducting state during the sampling phase;

[0027] The control end of the first switch unit is electrically connected to the first end of the second capacitor element through the fifth switch unit, and the second end of the second capacitor element is electrically connected to the first voltage end; the first end of the second capacitor element is also electrically connected to the driving input end through the third switch unit;

[0028] During the sampling phase, the third switch unit is in an on state, the fifth switch unit is in an off state, and the second capacitor element stores the first voltage;

[0029] In the output stage, the third switch unit is in an off state, the fifth switch unit is in an on state, and the second capacitor element controls the first switch unit to be in an off state through the fifth switch unit.

[0030] In an optional embodiment, the control end of the ninth switch unit is electrically connected to the second voltage end through the first resistor and to the first end of the second capacitor element through the fifth switch unit, so that the ninth switch unit is in an on state during the sampling phase and in an off state during the output phase;

[0031] And / or, the control end of the second switch unit is electrically connected to the first end of the first resistor, so that the second switch unit is in an off state during the sampling phase and in an on state during the output phase;

[0032] And / or, the control end of the fourth switch unit is electrically connected to the second end of the second switch unit, so that the fourth switch unit is in an off state during the sampling phase and in an on state during the output phase;

[0033] And / or, the control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the first clock signal outputs the first voltage in the sampling phase, and the first clock signal outputs the second voltage in the output phase;

[0034] And / or, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the second clock signal outputs the second voltage in the sampling phase, and the second clock signal outputs the first voltage in the output phase.

[0035] In an optional embodiment, the working phase of the GOA driving unit includes a holding phase, the driving input end receives the second voltage during the holding phase, and the control unit is used to control the third switch unit and the first switch unit to be in an on state during the holding phase, so that the first end of the second capacitor element is the second voltage;

[0036] The control unit also includes an eighth switch unit, a first end of the eighth switch unit receives the second voltage, a second end of the eighth switch unit is electrically connected to the drive scan output end, a control end of the eighth switch unit is electrically connected between the third switch unit and the first end of the second capacitor element, and the eighth switch unit is in an on state during the holding stage, so that the drive scan output end outputs the second voltage during the holding stage.

[0037] In an optional embodiment, the ninth switch unit is in a conducting state during the holding phase, so that the drive transmission output terminal receives the second voltage during the holding phase, and the sixth switch unit is in a conducting state during the holding phase; the second switch unit, the fourth switch unit, the fifth switch unit, and the seventh switch unit are in a disconnected state during the holding phase;

[0038] The control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the first clock signal and the second clock signal have opposite phases, the first clock signal has at least one cycle in the holding phase, and the second clock signal has at least one cycle in the holding phase.

[0039] In the second aspect, the present application also provides a display panel, comprising the GOA driving circuit and multiple rows of pixel units described in the first aspect, wherein the driving scan output end of the GOA driving unit at each level is electrically connected to at least one row of pixel units, the driving transfer output end of the GOA driving unit at the previous level is electrically connected to the driving input end of the GOA driving unit at the current level; and the driving transfer output end of the GOA driving unit at the current level is electrically connected to the driving input end of the next group of GOA driving units. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments.

[0041] Figure 1 1 is a schematic diagram of a top view of a display panel provided in an embodiment of the present application;

[0042] Figure 2 This is a schematic diagram of the architecture of a GOA drive unit provided in an embodiment of the present application. Figure 1 ;

[0043] Figure 3 This is a schematic diagram of the architecture of a GOA drive unit provided in an embodiment of the present application. Figure 2 ;

[0044] Figure 4 yes Figure 3 Schematic diagram of the GOA driver unit in the sampling phase;

[0045] Figure 5 yes Figure 4 A simplified schematic diagram of the GOA driver unit in the sampling phase;

[0046] Figure 6 yes Figure 3 Schematic diagram of the GOA driver unit in the output stage;

[0047] Figure 7 yes Figure 6 A simplified schematic diagram of the GOA driver unit in the output stage;

[0048] Figure 8 yes Figure 3 Schematic diagram of the circuit architecture in the GOA driving unit when the first clock signal XCK is at a low level and the second clock signal CK is at a high level during the middle hold phase;

[0049] Figure 9 yes Figure 3 Schematic diagram of the circuit structure in the GOA driving unit when the first clock signal XCK is at a high level and the second clock signal CK is at a low level during the holding phase.

[0050] Description of Figure Numbers:

[0051] Display panel 1000; GOA driving circuit 100; pixel unit 200; GOA driving unit 10; driving input terminal Pscan(n-1); driving scan output terminal Pscan(n); first capacitor element C1; control unit 20; first switch unit T1; sixth switch unit T6; seventh switch unit T7; second switch unit T2; driving transfer output terminal Pscan(n+1); fourth switch unit T4; ninth switch unit T9; first voltage terminal 11; second voltage terminal 12; first resistor R1; second capacitor element C2; third switch unit T3; fifth switch unit T5; first clock signal XCK; second clock signal CK; eighth switch unit T8; low level VGL; high level VGH. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. In addition, the reference to "embodiment" or "implementation method" in this application means that the specific features, structures or characteristics described in conjunction with the embodiment or implementation method may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0053] When describing some embodiments, the expression "electrically connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in physical contact or there is an electrical signal path, for example, the two components are connected through a signal line, or there may be other electrical components or circuits between the two components, but there is a signal path between the two components through other electrical components. However, the term "electrically connected" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0054] For display panels, the gate drive voltage is susceptible to gradual attenuation as it travels along the gate signal line due to the internal resistance of the signal line, the TFT channel resistance, and the parasitic capacitance of the traces. This is particularly true for large-size displays, where the voltage attenuation is more severe due to the length of the gate signal line. This can easily lead to display issues such as "incomplete charging" (e.g., smearing, dark lines) or "row dropouts" in pixels farther from the gate drive module. Furthermore, when the gate drive circuit operates for extended periods, the TFTs in the gate drive circuit experience a positive Vth drift (ΔVth ≥ 5V) due to positive bias stress (PBS), increasing the Vgs required for the TFTs in the gate drive circuit to turn on. Large-size panels have a large number of GOA units, making the uneven aging problem more prominent.

[0055] In this context, if the gate drive voltage in the gate drive circuit is set to a higher voltage, the higher voltage is used as a reserve for Vth drift, ensuring that the TFT in the gate drive circuit can still be turned on normally after a lifespan of tens of thousands of hours. At the same time, the higher gate drive voltage can compensate for the transmission loss of the gate signal line, ensuring that the gate-source voltage (Vgs) of the remote TFT exceeds the threshold voltage (Vth), avoiding "row loss" or "incomplete charging" (such as smearing and dark lines) caused by insufficient voltage.

[0056] By setting the gate drive voltage in the gate drive circuit to a higher voltage, the load on the display control chip is increased. For large-size panels, a higher gate drive voltage is usually required, and a higher gate drive voltage will further increase the load on the display control chip, increasing the power consumption of the display control chip and the operating temperature of the driver board.

[0057] Based on this, the present application provides a GOA driving circuit with high thrust, which can achieve a higher gate drive operating voltage at a relatively small gate drive input voltage while avoiding an increase in chip load, thereby achieving high thrust and improving display effects.

[0058] See also Figure 1 The display panel 1000 includes a GOA driving circuit 100 and a plurality of pixel units 200 .

[0059] GOA stands for Gate On Array or Gate Driver On Array, which refers to the integration of gate drivers on the array substrate. GOA circuits can also be called gate driver circuits or row scan driver circuits.

[0060] See also Figure 1 The GOA driving circuit 100 includes multiple cascaded GOA driving units 10‌, each of which includes multiple thin film transistors (TFTs), capacitors, and auxiliary circuit elements, which are connected in series to form a complete driving network.

[0061] The GOA driving circuit 100 is disposed in a non-display area (peripheral wiring area) of the display panel 1000 .

[0062] Multiple pixel units 200 are arranged in an array to form multiple rows of pixel units, and each row of pixel units is electrically connected to one or two GOA driver unit 10 circuits. When each row of pixel units is electrically connected to two GOA driver unit 10 circuits, the two GOA driver unit 10 circuits connect opposite ends of each row of pixel units. The signal lines that electrically connect the GOA driver unit 10 circuit to a row of pixel units are gate signal lines or gate lines, which can also be called scan lines.

[0063] Each pixel unit 200 includes a TFT switch, a storage capacitor, and a liquid crystal capacitor. The TFT switch is controlled by a gate line signal, allowing the data line voltage to be written to the pixel electrode when it is on. The storage capacitor maintains pixel voltage stability and prevents brightness fluctuations caused by leakage from the liquid crystal capacitor. The liquid crystal capacitor is composed of liquid crystal molecules sandwiched between two glass substrates. The electric field controls the direction of the liquid crystal molecules to achieve a light transmittance corresponding to the written data line voltage.

[0064] The GOA circuit is directly integrated into the array substrate, using the same manufacturing process as the TFT in the pixel unit 200, and does not require an external COF (Chip on Film) driver chip to achieve a row-by-row scanning drive function.

[0065] The working phases of the GOA driving unit 10 include a sampling phase and an output phase.

[0066] The output phase of the GOA driver unit 10 is the phase in which the gate drive voltage is output to a row of electrically connected pixel units 200 (i.e., the row scanning period). The sampling phase is the phase before the gate drive voltage is output to the pixel units 200 and is the phase in which the gate drive voltage is prepared for increasing.

[0067] See also Figure 2 and Figure 3 The GOA driving unit 10 includes a driving input terminal Pscan(n−1), a driving scan output terminal Pscan(n), a first capacitive element C1 and a control unit 20 .

[0068] The driving input terminal Pscan(n-1) of the current stage GOA driving unit 10 is electrically connected to the driving transmission output terminal of the previous stage GOA driving unit 10 .

[0069] The drive scan output terminal Pscan(n) of the current-stage GOA driving unit 10 is electrically connected to a row of pixel units 200 for outputting a gate drive voltage.

[0070] See also Figure 4 and Figure 5 The driving input terminal Pscan(n-1) is used to receive the first voltage V1 during the sampling phase. The driving input terminal Pscan(n-1) of the current-stage GOA driving unit 10 is used to receive the voltage from the output voltage of the driving transfer output terminal of the previous-stage GOA driving unit 10 during the output phase during the sampling phase.

[0071] See also Figure 6 and Figure 7 The driving input terminal Pscan(n-1) is used to receive the second voltage V2 in the output phase. The driving input terminal Pscan(n-1) of the current-stage GOA driving unit 10 is used to receive the voltage in the output phase from the output voltage of the driving transfer output terminal of the previous-stage GOA driving unit 10 in the holding phase.

[0072] One of the first voltage V1 and the second voltage V2 is a low level VGL, and the other of the first voltage V1 and the second voltage V2 is a high level VGH.

[0073] In this embodiment, the first voltage V1 is a low level VGL and the second voltage V2 is a high level VGH. When the driving input terminal Pscan(n-1) of the current-stage GOA driving unit 10 is used to receive the voltage in the sampling phase from the low level VGL of the driving transfer output terminal of the previous-stage GOA driving unit 10 in the output phase. When the driving input terminal Pscan(n-1) of the current-stage GOA driving unit 10 is used to receive the voltage in the output phase from the high level VGH of the driving transfer output terminal of the previous-stage GOA driving unit 10 in the holding phase.

[0074] It should be noted that, unless otherwise specified, the GOA driving unit 10 refers to the current stage GOA driving unit 10. The sampling phase refers to the sampling phase of the current stage GOA driving unit 10, and the output phase refers to the output phase of the current stage GOA driving unit 10.

[0075] The control unit 20 is electrically connected to the driving input terminal Pscan(n-1) and the first capacitor element C1. The control unit 20 includes a switch unit and the like.

[0076] See also Figure 4 and Figure 5 The control unit 20 is configured to control the first end of the first capacitor C1 to receive the second voltage V2 during the sampling phase. The second end of the first capacitor C1 is electrically connected to the drive input terminal Pscan(n-1). For example, the control unit 20 is configured to control the first end of the first capacitor C1 to receive a high voltage VGH, and the second end of the first capacitor C1 to be electrically connected to the drive input terminal Pscan(n-1). Specifically, the control unit 20 includes a first switch unit T1 and a sixth switch unit T6. The sixth switch unit T6 is electrically connected between the first end of the first capacitor C1 and the second voltage V2 terminal. The first switch unit T1 is electrically connected between the second end of the first capacitor C1 and the drive input terminal Pscan(n-1). The first switch unit T1 and the sixth switch unit T6 are in an on state during the sampling phase. Thus, the first end of the first capacitor C1 is loaded with the high voltage VGH, and the second end of the first capacitor C1 is loaded with the low voltage VGL. The potential difference across the first capacitor C1 is (VGH-VGL).

[0077] Figure 4 The red line indicates a high level. The blue line indicates a low level. The gray line indicates a disconnected state. Figure 5 yes Figure 4 A simplified schematic diagram of .

[0078] The control unit 20 is further configured to control, during the output phase, the first end of the first capacitive element C1 to receive the first voltage V1, and to control the second end of the first capacitive element C1 to be electrically connected to the drive scan output terminal Pscan(n), such that the absolute value of the output voltage of the drive scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1. For example, the control unit 20 is further configured to control, during the output phase, the first end of the first capacitive element C1 to receive the high voltage VGH, and to control the second end of the first capacitive element C1 to be electrically connected to the drive scan output terminal Pscan(n), such that the absolute value of the output voltage of the drive scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1.

[0079] For details, please refer to Figure 6 and Figure 7 The control unit 20 includes a seventh switch unit T7, electrically connected between the first end of the first capacitor C1 and the first voltage V1 terminal. The control unit 20 includes a second switch unit T2, electrically connected between the second end of the first capacitor C1 and the drive scan output terminal Pscan(n). In this manner, the first end of the first capacitor C1 is loaded with a low voltage level VGL. Since the potential difference across the first capacitor C1 during the sampling phase is (VGH - VGL), according to the KVL formula, the potential of the drive scan output terminal Pscan(n) is VGL - (VGH - VGL), or 2×VGL - VGH. The voltage value of 2×VGL - VGH is less than VGL. The absolute value of 2×VGL - VGH is greater than the absolute value of VGL.

[0080] Figure 6 The red line indicates a high level. The blue line indicates a low level. The gray line indicates a disconnected state. Figure 7 yes Figure 6 A simplified schematic diagram of .

[0081] In other words, during the output phase, the output voltage of the drive scan output terminal Pscan(n) is (2×V1-V2), where V1 is the first voltage V1 and V2 is the second voltage V2. The absolute value of the second voltage V2 is greater than the absolute value of the first voltage V1. One of the first voltage V1 and the second voltage V2 is a high level VGH, and the other is a low level VGL. This embodiment assumes that the first voltage V1 is a low level VGL and the second voltage V2 is a high level VGH.

[0082] For example, if VGL is -9V and VGH is 20V, then the potential of the drive scan output terminal Pscan(n) is -40V.

[0083] The GOA driving circuit 100 provided in the present application can output 2×VGL-VGH at the driving scan output terminal Pscan(n) by inputting VGL at the driving input terminal Pscan(n-1). The absolute value of the voltage output by the driving scan output terminal Pscan(n) is greater than the voltage input at the driving input terminal Pscan(n-1). Therefore, the GOA driving circuit 100 provided in the present application achieves a high thrust effect, increasing the input VGL, which has a relatively low absolute value, to a relatively high absolute value of 2×VGL-VGH. While avoiding an increase in chip load, it improves display defects caused by a long signal line length or a positive drift of Vth (threshold voltage) in the TFT, thereby improving the display effect.

[0084] In addition, since the row scanning of the pixel unit 200 is driven by a positive voltage, the power consumption of the display control chip is relatively large. In this embodiment, the row scanning of the pixel unit 200 is driven by a negative voltage, which can reduce the absolute value of the input voltage, reduce the power consumption of the display control chip, and improve the heating problem of the driving board.

[0085] The GOA driving circuit 100 provided in the present application is designed to include a driving input terminal Pscan(n-1), a driving scan output terminal Pscan(n), a first capacitor element C1, and a control unit 20. The driving input terminal Pscan(n-1) is used to receive a first voltage V1 in the sampling phase and receive a second voltage V2 in the output phase; the control unit 20 is electrically connected to the driving input terminal Pscan(n-1) and the first capacitor element C1; the control unit 20 is used to control the first end of the first capacitor element C1 to receive the second voltage V2 in the sampling phase, and the second end of the first capacitor element C1 is electrically connected to the driving input terminal Pscan(n-1). n(n-1); the control unit 20 is further used to control the first end of the first capacitor element C1 to receive the first voltage V1 in the output stage, and control the second end of the first capacitor element C1 to be electrically connected to the drive scan output terminal Pscan(n), so that the absolute value of the output voltage of the drive scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1, and a higher gate drive operating voltage is achieved under a relatively low drive input voltage, thereby forming a gate drive circuit with high thrust, which improves the display poor problem caused by the long signal line length or the positive drift of Vth (threshold voltage) of the TFT while avoiding the increase of chip load, thereby improving the display effect.

[0086] The architecture of the control unit 20 is described below with reference to the accompanying drawings.

[0087] Optional, see Figure 4-Figure 7 , the control unit 20 includes a first switch unit T1.

[0088] The first end of the first switch unit T1 is electrically connected to the driving input end Pscan(n-1), the second end of the first switch unit T1 is electrically connected to the second end of the first capacitor element C1, the first switch unit T1 is in the on state during the sampling phase, and the first switch unit T1 is in the off state during the output phase.

[0089] Optionally, the first switch unit T1 is an NMOS transistor. Optionally, the control terminal of the first switch unit T1 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the first switch unit T1 is loaded with a low level VGL in the output phase.

[0090] Further optionally, the first switch unit T1 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the first switch unit T1 is connected to the second voltage V2 end in the sampling phase, and the control end of the first switch unit T1 is connected to the first voltage V1 end in the output phase.

[0091] Optionally, the control terminal of the first switch unit T1 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0092] In other embodiments, the first switch unit T1 is a PMOS transistor. This embodiment can be designed with reference to the embodiment in which the first switch unit T1 is an NMOS transistor.

[0093] Optional, see Figure 4-Figure 7 , the control unit 20 includes a second switch unit T2.

[0094] The first end of the second switch unit T2 is electrically connected to the second end of the first switch unit T1, and the second end of the second switch unit T2 is electrically connected to the drive scan output terminal Pscan(n). The second switch unit T2 is in an off state during the sampling phase and in an on state during the output phase.

[0095] Optionally, the second switch unit T2 is a PMOS transistor. Optionally, the control terminal of the second switch unit T2 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the second switch unit T2 is loaded with a low level VGL in the output phase.

[0096] Further optionally, the second switch unit T2 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the second switch unit T2 is connected to the second voltage V2 end in the sampling phase, and the control end of the second switch unit T2 is connected to the first voltage V1 end in the output phase.

[0097] Optionally, the control terminal of the second switch unit T2 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0098] In other embodiments, the second switch unit T2 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the second switch unit T2 is a PMOS transistor.

[0099] Optional, see Figure 4-Figure 7 , the control unit 20 includes a sixth switch unit T6.

[0100] The first end of the sixth switch unit T6 is electrically connected to the first end of the first capacitor C1, and the other end of the sixth switch unit T6 is loaded with the second voltage V2. The sixth switch unit T6 is in the on state during the sampling phase and in the off state during the output phase.

[0101] Optionally, the sixth switch unit T6 is a PMOS transistor. Optionally, the control terminal of the sixth switch unit T6 is loaded with a low level VGL in the sampling phase. Optionally, the control terminal of the sixth switch unit T6 is loaded with a high level VGH in the output phase.

[0102] Further optionally, the sixth switch unit T6 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the sixth switch unit T6 is connected to the first voltage V1 end in the sampling phase, and the control end of the sixth switch unit T6 is connected to the second voltage V2 end in the output phase.

[0103] Optionally, the control terminal of the sixth switch unit T6 is loaded with a clock signal, the clock signal is a low level VGL in the sampling phase, and the clock signal is a high level VGH in the output phase.

[0104] In other embodiments, the sixth switch unit T6 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the sixth switch unit T6 is a PMOS transistor.

[0105] Optional, see Figure 4-Figure 7 , the control unit 20 includes a seventh switch unit T7.

[0106] The first end of the seventh switch unit T7 is electrically connected to the first end of the first capacitor C1, and the other end of the seventh switch unit T7 is loaded with the first voltage V1. The seventh switch unit T7 is in an off state during the sampling phase and in an on state during the output phase.

[0107] Optionally, the seventh switch unit T7 is a PMOS transistor. Optionally, the control terminal of the seventh switch unit T7 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the seventh switch unit T7 is loaded with a low level VGL in the output phase.

[0108] Further optionally, the seventh switch unit T7 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the seventh switch unit T7 is connected to the second voltage V2 end in the sampling phase, and the control end of the seventh switch unit T7 is connected to the first voltage V1 end in the output phase.

[0109] Optionally, the control terminal of the seventh switch unit T7 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0110] In other embodiments, the seventh switch unit T7 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the seventh switch unit T7 is a PMOS transistor.

[0111] In an optional implementation, see Figure 1-Figure 3 The GOA driving unit 10 further includes a driving transmission output terminal Pscan(n+1).

[0112] The drive transfer output terminal Pscan(n+1) is electrically connected to the control unit 20. The drive transfer output terminal Pscan(n+1) of the current-stage GOA drive unit 10 is electrically connected to the drive input terminal Pscan(n-1) of the next-stage GOA drive unit 10. The voltage signal output by the drive transfer output terminal Pscan(n+1) of the current-stage GOA drive unit 10 can trigger the operation of the next-stage GOA drive unit 10.

[0113] See also Figure 4-Figure 7 The control unit 20 is further configured to control the drive transfer output terminal Pscan(n+1) to receive the second voltage V2 during the sampling phase. For example, the second voltage V2 is at a high level VGH. The control unit 20 is further configured to control the drive transfer output terminal Pscan(n+1) to receive the first voltage V1 during the output phase. For example, the first voltage V1 is at a low level VGL.

[0114] That is, the control unit 20 is further configured to control the drive transfer output terminal Pscan(n+1) to receive a high level VGH during the sampling phase, and to control the drive transfer output terminal Pscan(n+1) to receive a low level VGL during the output phase. In other words, the drive transfer output terminal Pscan(n+1) of the current-stage GOA driver unit 10 outputs a high level VGH during the sampling phase, which can cause the GOA driver unit 10 of the next stage to be in a holding phase (i.e., the GOA driver unit 10 is in a waiting phase). When the drive transfer output terminal Pscan(n+1) of the current-stage GOA driver unit 10 outputs a low level VGL during the output phase, the GOA driver unit 10 of the next stage can start working and enter the sampling phase.

[0115] In this embodiment, by designing the drive transfer output terminal Pscan(n+1) of the current-stage GOA driving unit 10 to output a high level VGH in the sampling phase, the GOA driving unit 10 of the next stage is in the holding phase (that is, the GOA driving unit 10 is in the waiting phase); by designing the drive transfer output terminal Pscan(n+1) of the current-stage GOA driving unit 10 to output a low level VGL in the output phase, the GOA driving unit 10 of the next stage can start working, enter the sampling phase, and prepare for the next row scan.

[0116] In general display technology, the voltage signals (sampling signals) transmitted from the previous level to the next level will be superimposed. For example, the sampling signal transmitted from the previous level GOA driving unit 10 to the current level GOA driving unit 10 is 5v, the sampling signal transmitted from the current level GOA driving unit 10 to the next level GOA driving unit 10 is 5v+5v, and the sampling signal transmitted from the next level GOA driving unit 10 to the next level GOA driving unit 10 is 5v+5v+5v. This causes the sampling signals to be superimposed, which on the one hand increases the power consumption of the GOA driving circuit 100, and on the other hand, when the sampling signal of the GOA driving unit 10 is too large, it may cause problems such as damage to the components in the sampling signal of the GOA driving unit 10.

[0117] In this embodiment, the sampling signal transmitted from each stage of the GOA driving unit 10 to the next stage of the GOA driving unit 10 is the first voltage V1 (VGL), and no voltage superposition occurs, thereby effectively avoiding excessive power consumption of the GOA driving circuit 100 and effectively avoiding problems such as damage to components in the sampling signal of the GOA driving unit 10 due to an excessively high sampling signal.

[0118] In an optional implementation, see Figure 4-Figure 7 , the control unit 20 further includes a fourth switch unit T4.

[0119] A first terminal of the fourth switch unit T4 is electrically connected to the drive transmission output terminal Pscan(n+1), and the other terminal of the fourth switch unit T4 is loaded with the first voltage V1. The fourth switch unit T4 is in an off state during the sampling phase and in an on state during the output phase.

[0120] Optionally, the fourth switch unit T4 is a PMOS transistor. Optionally, the control terminal of the fourth switch unit T4 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the fourth switch unit T4 is loaded with a low level VGL in the output phase.

[0121] Further optionally, the fourth switch unit T4 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the fourth switch unit T4 is connected to the second voltage V2 end in the sampling phase, and the control end of the fourth switch unit T4 is connected to the first voltage V1 end in the output phase.

[0122] Optionally, the control terminal of the fourth switch unit T4 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0123] In other embodiments, the fourth switch unit T4 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the fourth switch unit T4 is a PMOS transistor.

[0124] See also Figure 4-Figure 7 , the control unit 20 further includes a ninth switch unit T9.

[0125] A first terminal of the ninth switch unit T9 is electrically connected to the drive transmission output terminal Pscan(n+1), and the second voltage V2 is applied to the other terminal of the ninth switch unit T9. The ninth switch unit T9 is in an on state during the sampling phase and in an off state during the output phase.

[0126] Optionally, the ninth switch unit T9 is an NMOS transistor. Optionally, the control terminal of the ninth switch unit T9 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the ninth switch unit T9 is loaded with a low level VGL in the output phase.

[0127] Further optionally, the ninth switch unit T9 is directly or indirectly electrically connected to the first voltage V1 end or the second voltage V2 end, the control end of the ninth switch unit T9 is connected to the second voltage V2 end in the sampling phase, and the control end of the ninth switch unit T9 is connected to the first voltage V1 end in the output phase.

[0128] Optionally, the control terminal of the ninth switch unit T9 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0129] In other embodiments, the ninth switch unit T9 is a PMOS transistor. This embodiment can be designed with reference to the embodiment in which the ninth switch unit T9 is an NMOS transistor.

[0130] In an optional implementation, see Figure 4-Figure 7 The GOA driving unit 10 further includes a first voltage terminal 11, a second voltage terminal 12, a first resistor R1, and a second capacitor C2.

[0131] The first voltage terminal 11 is used to output the first voltage V1. The second voltage terminal 12 is used to output the second voltage V2. For example, the first voltage V1 is a low level VGL, and the second voltage V2 is a high level VGH.

[0132] See also Figure 4-Figure 7 The control unit 20 further includes a third switch unit T3 and a fifth switch unit T5.

[0133] The control end of the first switch unit T1 is also electrically connected to the second voltage end 12 through the first resistor R1. Both ends of the first resistor R1 are at a high level VGH, so that the first switch unit T1 is in a conducting state during the sampling phase.

[0134] The control terminal of the first switch unit T1 is electrically connected to the first terminal of the second capacitor C2 via the fifth switch unit T5. The second terminal of the second capacitor C2 is electrically connected to the first voltage terminal I1. The first terminal of the second capacitor C2 is also electrically connected to the driving input terminal Pscan(n-1) via the third switch unit T3.

[0135] During the sampling phase, the third switch unit T3 is in an on state, the fifth switch unit T5 is in an off state, and the second capacitor C2 stores the first voltage V1.

[0136] During the output phase, the third switch unit T3 is in the off state. The fifth switch unit T5 is in the on state. The second capacitor C2 controls the first switch unit T1 to be in the off state through the fifth switch unit T5. Specifically, the second capacitor C2 provides a low voltage level VGL during the output phase, and the control terminal of the first switch unit T1 is loaded with the low voltage level VGL. At this time, the first resistor R1 is connected to the control terminal of the first switch unit T1, and the low voltage level VGL is loaded.

[0137] Optionally, the third switch unit T3 is a PMOS transistor. Optionally, the control end of the third switch unit T3 is loaded with a low level VGL in the sampling phase. Optionally, the control end of the third switch unit T3 is loaded with a high level VGH in the output phase.

[0138] Optionally, the third switch unit T3 is directly or indirectly electrically connected to the first voltage terminal 11 or the second voltage terminal 12, and the control terminal of the third switch unit T3 is connected to the first voltage terminal 11 in the sampling phase, and the control terminal of the third switch unit T3 is connected to the second voltage terminal 12 in the output phase.

[0139] Optionally, the control terminal of the third switch unit T3 is loaded with a clock signal, the clock signal is a low level VGL in the sampling phase, and the clock signal is a high level VGH in the output phase.

[0140] In other embodiments, the third switch unit T3 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the third switch unit T3 is a PMOS transistor.

[0141] Optionally, the fifth switch unit T5 is a PMOS transistor. Optionally, the control terminal of the fifth switch unit T5 is loaded with a high level VGH in the sampling phase. Optionally, the control terminal of the fifth switch unit T5 is loaded with a low level VGL in the output phase.

[0142] Further optionally, the fifth switch unit T5 is directly or indirectly electrically connected to the first voltage terminal 11 or the second voltage terminal 12, the control terminal of the fifth switch unit T5 is connected to the second voltage terminal 12 in the sampling phase, and the control terminal of the fifth switch unit T5 is connected to the first voltage terminal 11 in the output phase.

[0143] Optionally, the control terminal of the fifth switch unit T5 is loaded with a clock signal, the clock signal is a high level VGH in the sampling phase, and the clock signal is a low level VGL in the output phase.

[0144] In other embodiments, the fifth switch unit T5 is an NMOS transistor. This embodiment can be designed with reference to the embodiment in which the fifth switch unit T5 is a PMOS transistor.

[0145] In this embodiment, please refer to Figure 4-Figure 7 The control terminal of the third switch unit T3 can be loaded with the first clock signal XCK. The control terminal of the fifth switch unit T5 can be loaded with the second clock signal CK, and the first clock signal XCK and the second clock signal CK have opposite phases.

[0146] This embodiment utilizes a first capacitor C1 and a second capacitor C2 to store voltage during the sampling phase. The first capacitor C1 boosts the gate drive voltage during the output phase, while the second capacitor C2 provides the voltage for the second switch unit T2 and other devices to control their conduction. A first resistor R1 is designed to divide the voltage, ensuring that the control terminal of the first switch unit T1 is at a low voltage level VGL during the output phase, providing the voltage for the second switch unit T2 and other devices to control their conduction. This embodiment achieves multiple functions and reuse through device design and connection, achieving the drive voltage boosting function described in this application with fewer devices.

[0147] In an optional implementation, see Figure 4-Figure 7 The control end of the ninth switch unit T9 is electrically connected to the second voltage end 12 through the first resistor R1 and is electrically connected to the first end of the second capacitor element C2 through the fifth switch unit T5, so that the ninth switch unit T9 is in the on state during the sampling phase and in the off state during the output phase.

[0148] In this embodiment, by designing the architecture of the GOA driving unit 10 , the on-off design of the ninth switch unit T9 at different stages can be realized, thereby controlling the output voltage of the driving transmission output terminal Pscan(n+1).

[0149] In an optional implementation, see Figure 4-Figure 7 The control end of the second switch unit T2 is electrically connected to the first end of the first resistor R1, so that the second switch unit T2 is in an off state during the sampling phase and in an on state during the output phase.

[0150] In this embodiment, by designing the architecture of the GOA driving unit 10 , the on-off design of the second switch unit T2 in different stages can be realized, thereby controlling the output voltage of the drive scan output terminal Pscan(n).

[0151] In an optional implementation, see Figure 4-Figure 7 The control end of the fourth switch unit T4 is electrically connected to the second end of the second switch unit T2, so that the fourth switch unit T4 is in a disconnected state during the sampling phase and in a conductive state during the output phase.

[0152] In this embodiment, by designing the architecture of the GOA driving unit 10 , the on-off design of the fourth switch unit T4 in different stages can be realized, thereby controlling the output voltage of the driving transmission output terminal Pscan(n+1).

[0153] In an optional implementation, see Figure 4-Figure 7The control end of the sixth switch unit T6 and the control end of the third switch unit T3 are both electrically connected to the first clock signal XCK. The first clock signal XCK outputs the first voltage V1 in the sampling phase. The first clock signal XCK outputs the second voltage V2 in the output phase.

[0154] By designing the architecture of the GOA driver unit 10, this embodiment can implement a design for switching the sixth switch unit T6 on and off at different stages, thereby controlling the voltage loaded on the first end of the first capacitor element C1, thereby enabling the first capacitor element C1 to store voltage during the sampling stage and amplify the gate drive voltage during the output stage; and can implement a design for switching the third switch unit T3 on and off at different stages, thereby charging the second capacitor element C2 during the sampling stage.

[0155] In an optional embodiment, the control end of the seventh switch unit T7 and the control end of the fifth switch unit T5 are both electrically connected to a second clock signal CK. The second clock signal CK outputs the second voltage V2 during the sampling phase. The second clock signal CK outputs the first voltage V1 during the output phase.

[0156] By designing the architecture of the GOA driving unit 10, this embodiment can implement the on-off design of the seventh switch unit T7 at different stages, thereby controlling the voltage loaded on the first end of the first capacitor element C1, thereby enabling the first capacitor element C1 to store the voltage in the sampling stage and amplify the gate drive voltage in the output stage; and can implement the on-off design of the fifth switch unit T5 at different stages, thereby discharging the second capacitor element C2 in the output stage, thereby controlling the on-off state of the ninth switch unit T9.

[0157] The connection between the control terminal of the second switch unit T2 and the control terminal of the ninth switch unit T9 can be implemented independently or simultaneously. In this embodiment, the connection between the control terminal of the second switch unit T2 and the control terminal of the ninth switch unit T9 is implemented simultaneously as an example.

[0158] In an optional implementation, see Figure 8 and Figure 9 The operating phase of the GOA driving unit 10 includes a holding phase, and the driving input terminal Pscan(n-1) receives the second voltage V2 during the holding phase. The control unit 20 is configured to control the third switch unit T3 and the first switch unit T1 to be in an on state during the holding phase, so that the first end of the second capacitor element C2 is at the second voltage V2.

[0159] See also Figure 8 and Figure 9The control unit 20 further includes an eighth switch unit T8. A first end of the eighth switch unit T8 receives the second voltage V2. A second end of the eighth switch unit T8 is electrically connected to the drive scan output terminal Pscan(n). A control end of the eighth switch unit T8 is electrically connected between the third switch unit T3 and the first end of the second capacitor C2. The eighth switch unit T8 is in an on state during the hold phase, causing the drive scan output terminal Pscan(n) to output the second voltage V2 during the hold phase. For example, the second voltage V2 is a high level VGH.

[0160] When the driving scan output terminal Pscan(n) is at the second voltage V2, the pixel unit 200 is in a non-scanning state.

[0161] The hold phase is the time period between the output phase and the next sampling phase, and is also the working phase of other GOA driver units 10. For example, when there are 1440 rows of pixel units 200, the hold phase of the first row of GOA driver units 10 is the scanning period of the pixel units 200 in rows 2 to 1440.

[0162] Figure 8 2 is a schematic diagram of the circuit structure of the GOA driving unit 10 when the first clock signal XCK is at a low level and the second clock signal CK is at a high level in the holding phase. Figure 9 2 is a schematic diagram of the circuit structure of the GOA driving unit 10 when the first clock signal XCK is at a high level and the second clock signal CK is at a low level in the holding phase.

[0163] In an optional embodiment, the ninth switch unit T9 is in an on state during the hold phase, so that the drive transfer output terminal Pscan(n+1) receives the second voltage V2 during the hold phase, thereby providing the second voltage V2 to the next-stage GOA driver unit 10 during the output phase or the hold phase. For example, the second voltage V2 is a high level VGH.

[0164] The sixth switch unit T6 is in the on state during the holding phase. The second switch unit T2, the fourth switch unit T4, the fifth switch unit T5, and the seventh switch unit T7 are in the off state during the holding phase.

[0165] The control terminal of the sixth switch unit T6 and the control terminal of the third switch unit T3 are both electrically connected to a first clock signal XCK. The control terminal of the seventh switch unit T7 and the control terminal of the fifth switch unit T5 are both electrically connected to a second clock signal CK. The first clock signal XCK and the second clock signal CK have opposite phases. The first clock signal XCK has at least one cycle during the hold phase. The second clock signal CK has at least one cycle during the hold phase.

[0166] The GOA driving unit 10 provided in the present application, in the holding phase, regardless of whether the levels of the first clock signal XCK and the second clock signal CK are high or low, drives the scanning output terminal Pscan(n) to output the second voltage V2 in the holding phase, and drives the transfer output terminal Pscan(n+1) to output the second voltage V2 in the holding phase, so that the pixel unit 200 electrically connected to the current GOA driving unit 10 is in a non-scanning state in the holding phase.

[0167] See also Figure 1-Figure 3 , the present application also provides a display panel 1000. The display panel 1000 includes the GOA driving circuit 100 and a plurality of rows of pixel units 200 described in any of the aforementioned embodiments. The drive scan output terminal Pscan(n) of the GOA driving unit 10 at each level is electrically connected to at least one row of pixel units 200. The drive transfer output terminal Pscan(n+1) of the GOA driving unit 10 at the previous level is electrically connected to the drive input terminal Pscan(n-1) of the GOA driving unit 10 at the current level. The drive transfer output terminal Pscan(n+1) of the GOA driving unit 10 at the current level is electrically connected to the drive input terminal Pscan(n-1) of the next group of GOA driving units 10 to drive row scanning.

[0168] The display panel 1000 includes, but is not limited to, an OLED or LCD display device.

[0169] The display panel 1000 provided in the present application includes a GOA driving circuit 100, which is designed to include a driving input terminal Pscan(n-1), a driving scan output terminal Pscan(n), a first capacitor element C1, and a control unit 20. The driving input terminal Pscan(n-1) is used to receive a first voltage V1 in the sampling phase and a second voltage V2 in the output phase; the control unit 20 is electrically connected to the driving input terminal Pscan(n-1) and the first capacitor element C1; the control unit 20 is used to control the first end of the first capacitor element C1 to receive the second voltage V2 in the sampling phase, and the second end of the first capacitor element C1 is electrically connected to the driving input terminal Pscan(n-1). (n-1); the control unit 20 is further used to control the first end of the first capacitor element C1 to receive the first voltage V1 in the output stage, and control the second end of the first capacitor element C1 to be electrically connected to the drive scan output terminal Pscan(n), so that the absolute value of the output voltage of the drive scan output terminal Pscan(n) is greater than the absolute value of the first voltage V1, and a higher gate drive operating voltage is achieved under a relatively low drive input voltage, thereby forming a gate drive circuit with high thrust, which improves the display poor problem caused by the long signal line length or the positive drift of Vth (threshold voltage) of the TFT while avoiding the increase of the chip load, thereby improving the display effect.

[0170] The GOA driving circuit 100 provided in the present application realizes high voltage output under the premise of low voltage input, with the first switch unit T1, the eighth switch unit T8, and the ninth switch unit T9 being NMOS tubes, and the rest being PMOS tubes. The first clock signal XCK and the second clock signal CK are a set of clock signals with opposite phases, VGL is a low-level DC, VGH is a high-level DC, and the Pscan signal is a low-potential pulse signal with a normal high potential. It should be noted that in other designs, according to the in-plane TFT characteristics or different signals, the first switch unit T1, the eighth switch unit T8, and the ninth switch unit T9 can also be PMOS tubes, and the rest are NMOS tubes, and the Scan signal can also be a high-potential pulse with a normal low potential. The schematic diagram provided in this solution specification is for illustration only and is not intended as the sole reference for actual application.

[0171] The following briefly describes the working cycle of the designed GOA driving circuit 100.

[0172] During the sampling phase, the drive input terminal Pscan(n-1) is at a low potential, the first clock signal XCK is at a low potential, and the second clock signal CK is at a high potential. At this time, the third switch unit T3 and the sixth switch unit T6 are open (conducting); the fifth switch unit T5 and the seventh switch unit T7 are closed (disconnected); the connection between the second capacitor element C2 and the third switch unit T3 is charged to a low potential, the eighth switch unit T8 is closed, and due to the pull-up effect of VGH and the first resistor R1, the second switch unit T2 and the fourth switch unit T4 are closed, while the first switch unit T1 and the ninth switch unit T9 are closed. The drive transfer output terminal Pscan(n+1) of the GOA driver circuit 100 outputs VGH to the next stage.

[0173] At this point, the first capacitive element C1 is charged to a low potential via the drive input terminal Pscan(n-1), and the first switch unit T1 is charged to a low potential, resulting in a potential difference of VGH-VGL across the first and second capacitive elements. One end of the drive scan output terminal Pscan(n) is electrically connected to one end of the first capacitive element C1 via the second switch unit T2, which is disconnected. The drive scan output terminal Pscan(n) is in a suspended state.

[0174] During the output phase, the first clock signal XCK is at a high level and the second clock signal CK is at a low level. At this point, the fifth and seventh switch units T5 and T7 are turned on, the third and sixth switch units T3 and T6 are turned off, the second capacitor C2 outputs a low level, the first and eighth switch units T1 and T8 are turned off, and the second switch unit T2 is turned on. The circuit then passes through VGL → first capacitor C1 → drive scan output terminal Pscan(n). According to the KVL formula, the potential at drive scan output terminal Pscan(n) is 2×VGL - VGH, which is lower than VGL. Simultaneously, because the gate voltage of the fourth switch unit T4 is at the drive scan output terminal Pscan(n), the fourth switch unit T4 is turned on, and the ninth switch unit T9 is turned off. The drive transfer output terminal Pscan(n+1) of the GOA drive circuit 100 outputs VGL to the next stage.

[0175] There are two processes in the holding phase. During this process, since Pscan(n-1) outputs a high level, the plate of the second capacitor element C2 is covered by the high level, the ninth switch unit T9 and the first switch unit T1 are continuously turned on, and the second switch unit T2 is turned off. Regardless of the states of the second clock signal CK and the first clock signal XCK, the second switch unit T2 and the fourth switch unit T4 are turned off, and the eighth switch unit T8 is turned on, driving the scan output terminal Pscan(n) to output VGH, and outputting VGH to the next stage through the ninth switch unit T9, thus achieving the design purpose.

[0176] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application, and these improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. A GOA driving circuit, characterized in that: The GOA driving circuit includes a plurality of cascaded GOA driving units, and the working phases of the GOA driving units include a sampling phase and an output phase; The GOA driving unit includes: a driving input terminal for receiving a first voltage during the sampling phase and a second voltage during the output phase; Drive scan output terminal, a first capacitive element, a control unit electrically connecting the driving input terminal and the first capacitive element; The control unit is used to control the first end of the first capacitive element to receive the second voltage during the sampling phase, and the second end of the first capacitive element to be electrically connected to the driving input end; The control unit is also used to control the first end of the first capacitor element to receive the first voltage in the output stage, and control the second end of the first capacitor element to be electrically connected to the drive scan output end, so that the absolute value of the output voltage of the drive scan output end is greater than the absolute value of the first voltage.

2. The GOA driving circuit according to claim 1, wherein: In the output stage, the output voltage of the drive scan output end is (2×V1-V2), V1 is the first voltage, V2 is the second voltage, the absolute value of the second voltage is greater than the absolute value of the first voltage, and one of the first voltage and the second voltage is a high level and the other is a low level.

3. The GOA driving circuit according to claim 1, wherein: The control unit comprises: a first switch unit, wherein a first end of the first switch unit is electrically connected to the driving input end, a second end of the first switch unit is electrically connected to the second end of the first capacitive element, the first switch unit is in an on state during the sampling phase, and the first switch unit is in an off state during the output phase; a second switch unit, wherein a first end of the second switch unit is electrically connected to a second end of the first switch unit, and a second end of the second switch unit is electrically connected to the drive scan output end; the second switch unit is in an off state during the sampling phase, and in an on state during the output phase; a sixth switch unit, wherein a first end of the sixth switch unit is electrically connected to the first end of the first capacitor element, and the second voltage is applied to the other end of the sixth switch unit; the sixth switch unit is in an on state during the sampling phase and in an off state during the output phase; A seventh switch unit, wherein a first end of the seventh switch unit is electrically connected to the first end of the first capacitor element, and the other end of the seventh switch unit is loaded with the first voltage; the seventh switch unit is in an off state during the sampling phase, and the seventh switch unit is in an on state during the output phase.

4. The GOA driving circuit according to claim 3, wherein: The GOA driving unit further includes: a drive transmission output terminal, the drive transmission output terminal being electrically connected to the control unit, The control unit is further configured to control the drive transfer output terminal to receive the second voltage during the sampling phase; The control unit is further configured to control the drive transfer output terminal to receive the first voltage during the output stage.

5. The GOA driving circuit according to claim 4, characterized in that: The control unit further comprises: a fourth switch unit, wherein a first end of the fourth switch unit is electrically connected to the drive transmission output end, and the other end of the fourth switch unit is loaded with the first voltage; the fourth switch unit is in an off state during the sampling phase, and is in an on state during the output phase; A ninth switch unit, wherein a first end of the ninth switch unit is electrically connected to the drive transmission output end, and the other end of the ninth switch unit is loaded with the second voltage; the ninth switch unit is in an on state during the sampling phase, and the ninth switch unit is in an off state during the output phase.

6. The GOA driving circuit according to claim 5, characterized in that: The GOA driving unit further includes a first voltage terminal, a second voltage terminal, a first resistor, and a second capacitor element, wherein the first voltage terminal is used to output the first voltage, and the second voltage terminal is used to output the second voltage; the control unit further includes a third switch unit and a fifth switch unit; The control end of the first switch unit is further electrically connected to the second voltage end via the first resistor, so that the first switch unit is in a conducting state during the sampling phase; The control end of the first switch unit is electrically connected to the first end of the second capacitor element through the fifth switch unit, and the second end of the second capacitor element is electrically connected to the first voltage end; the first end of the second capacitor element is also electrically connected to the driving input end through the third switch unit; During the sampling phase, the third switch unit is in an on state, the fifth switch unit is in an off state, and the second capacitor element stores the first voltage; In the output stage, the third switch unit is in an off state, the fifth switch unit is in an on state, and the second capacitor element controls the first switch unit to be in an off state through the fifth switch unit.

7. The GOA driving circuit according to claim 6, wherein: The control end of the ninth switch unit is electrically connected to the second voltage end through the first resistor and to the first end of the second capacitor through the fifth switch unit, so that the ninth switch unit is in an on state during the sampling phase and in an off state during the output phase; And / or, the control end of the second switch unit is electrically connected to the first end of the first resistor, so that the second switch unit is in an off state during the sampling phase and in an on state during the output phase; And / or, the control end of the fourth switch unit is electrically connected to the second end of the second switch unit, so that the fourth switch unit is in an off state during the sampling phase and in an on state during the output phase; And / or, the control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the first clock signal outputs the first voltage in the sampling phase, and the first clock signal outputs the second voltage in the output phase; And / or, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the second clock signal outputs the second voltage in the sampling phase, and the second clock signal outputs the first voltage in the output phase.

8. The GOA driving circuit according to claim 6, wherein: The working phase of the GOA driving unit includes a holding phase, the driving input end receives the second voltage during the holding phase, and the control unit is used to control the third switch unit and the first switch unit to be in an on state during the holding phase, so that the first end of the second capacitor element is the second voltage; The control unit also includes an eighth switch unit, a first end of the eighth switch unit receives the second voltage, a second end of the eighth switch unit is electrically connected to the drive scan output end, a control end of the eighth switch unit is electrically connected between the third switch unit and the first end of the second capacitor element, and the eighth switch unit is in an on state during the holding stage, so that the drive scan output end outputs the second voltage during the holding stage.

9. The GOA driving circuit according to claim 8, characterized in that: The ninth switch unit is in a conducting state during the holding phase, so that the driving transmission output terminal receives the second voltage during the holding phase. The sixth switch unit is in the on state during the holding phase; the second switch unit, the fourth switch unit, the fifth switch unit, and the seventh switch unit are in the off state during the holding phase; The control end of the sixth switch unit and the control end of the third switch unit are both electrically connected to a first clock signal, the control end of the seventh switch unit and the control end of the fifth switch unit are both electrically connected to a second clock signal, the first clock signal and the second clock signal have opposite phases, the first clock signal has at least one cycle in the holding phase, and the second clock signal has at least one cycle in the holding phase.

10. A display panel, characterized in that: The GOA driving circuit comprises the GOA driving circuit according to any one of claims 1 to 9 and a plurality of rows of pixel units, wherein the driving scanning output terminal of each GOA driving unit is electrically connected to at least one row of pixel units, and the driving transfer output terminal of the GOA driving unit of the previous stage is electrically connected to the driving input terminal of the GOA driving unit of the current stage; The driving transmission output end of the GOA driving unit of the current stage is electrically connected to the driving input end of the GOA driving unit of the next group.

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