Semiconductor memory device and control method thereof

Abstract

The invention provides a semiconductor memory device and a control method thereof, which can reduce leakage current generated in a sense amplifier in a data holding state. The semiconductor memory device includes: a sense amplifier connected to a pair of bit lines BLT, BLB including at least one transistor connected to a low voltage power supply side bit line BLB of the pair of bit lines BLT, BLB; in a state in which the predetermined operation is not performed and the sense amplifier holds data, the control unit sets the voltage of the low-voltage power supply side bit line BLB to a predetermined voltage VBLL that is higher than the low-voltage power supply voltage VSS.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a control method thereof. Background Art

[0002] A semiconductor memory device such as a dynamic random access memory (DRAM) is configured to generate a weak potential difference between a pair of bit lines based on data stored in a memory cell, and amplify this potential difference through a sense amplifier to read data. Common sense amplifiers include a known pair of N-type metal-oxide-semiconductor field effect transistors (nMOSFETs, n-Metal-Oxide-Semiconductor Field Effect Transistors) and a pair of P-type metal-oxide-semiconductor field effect transistors (pMOSFETs), for example, Japanese Patent Laid-Open No. 08-139290. Summary of the Invention

[0003] However, the operating voltage of the semiconductor memory device decreases with the low power consumption of the semiconductor memory device. As this operating voltage decreases, the threshold voltage of the transistors inside the sense amplifier also decreases. In addition, in a state where the sense amplifier holds data (the state after sensing data), if the voltage of the low-voltage power supply side bit line in a pair of bit lines is set to 0V, there is at least one transistor in which the gate-source voltage is 0V among the transistors connected to the low-voltage power supply side bit line. However, when the threshold voltage of the transistor decreases, in a state where the sense amplifier holds data, the leakage current generated in the transistor with a gate-source voltage of 0V may increase.

[0004] In view of the above problems, the present invention provides a semiconductor memory device and a control method thereof, which can reduce the leakage current generated in the sense amplifier in the data holding state.

[0005] To solve the above problems, the present invention provides a semiconductor memory device, including: a sense amplifier and a control unit. The sense amplifier is connected to a pair of bit lines and includes at least one transistor connected to the low-voltage power supply side bit line in the pair of bit lines. In a state where no predetermined operation is performed and the sense amplifier holds data, the control unit sets the voltage of the low-voltage power supply side bit line to a predetermined voltage higher than the low-voltage power supply voltage.

[0006] According to the present invention, in a state where no predetermined operation is performed and the sense amplifier holds data, since the voltage of the low-voltage power supply side bit line is set to a predetermined voltage higher than the low-voltage power supply voltage, for example, when the low-voltage power supply voltage is 0V, the back gate-source voltage of a transistor with a gate-source voltage of 0V becomes a negative voltage, and the threshold voltage of this transistor increases due to the reverse bias effect. Therefore, the leakage current generated by this transistor can be reduced, and thus the leakage current generated in the sense amplifier in the data holding state can be reduced.

[0007] In addition, the present application also provides a method for controlling a semiconductor memory device. The semiconductor memory device includes a sense amplifier, and the sense amplifier is connected to a pair of bit lines and includes at least one transistor connected to the low-voltage power supply side bit line of the pair of bit lines. In a state where no predetermined operation is performed and the sense amplifier holds data, the control unit of the semiconductor memory device executes a step of setting the voltage of the low-voltage power supply side bit line to a predetermined voltage higher than the low-voltage power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a semiconductor memory device in an embodiment of the present invention.

[0009] Figure 2 It is a diagram showing a configuration example of a control unit.

[0010] Figure 3 It is a diagram showing an example of changes in each control signal and the voltage of the low-voltage power supply side bit line.

[0011] Figure 4 It is a diagram showing another configuration example of a control unit.

[0012] DESCRIPTION OF REFERENCE NUMERALS:

[0013] 10: Sense amplifier

[0014] 10a, 10b: P-type metal oxide semiconductor field effect transistor (pMOSFET)

[0015] 10c, 10d, 10e, 10f, 11a: N-type metal oxide semiconductor field effect transistor (nMOSFET)

[0016] 11: Memory cell

[0017] 11b: Capacitor

[0018] 20: Control unit

[0019] 21: First supply unit

[0020] 21a: First switch unit

[0021] 21b: Second switch section

[0022] 21c: Third switch section

[0023] 21d: Fourth switch section

[0024] 22: Second supply section

[0025] 22a: Comparator

[0026] 22b: Switch section

[0027] 22c: NOT circuit

[0028] 22d: Switch section

[0029] BLT: High-voltage power supply side bit line

[0030] BLB: Low-voltage power supply side bit line

[0031] CSL: Column select signal

[0032] CSP: High-voltage power supply side node

[0033] CSN: Low-voltage power supply side node

[0034] LDQT, LDQB: Local data line

[0035] PD: First control signal

[0036] NSE: Second control signal

[0037] VBLL: Predetermined voltage

[0038] VSS: Low-voltage power supply voltage

[0039] VREF: Reference voltage

[0040] WL: Row select signal

[0041] t0, t1: Time Detailed implementation manners

[0042] As Figure 1 and Figure 2 shown, the semiconductor memory device includes at least one sense amplifier 10 connected to a pair of complementary bit lines BLT, BLB and a control section 20. Additionally, in this embodiment, for simplicity of explanation, other components known in the semiconductor memory device (e.g., power supply circuit, command decoder, address decoder, clock generator, etc.) are not described in detail.

[0043] In this embodiment, the semiconductor memory device is taken as an example of a DRAM, but the semiconductor memory device may also be other semiconductor memory devices (such as a Static Random Access Memory (SRAM), a flash memory, etc.).

[0044] The sense amplifier 10 is a cross couple latch type sense amplifier. As Figure 1 shown, it includes a pair of P-type metal oxide semiconductor field effect transistors (pMOSFETs) 10a, 10b and a pair of N-type metal oxide semiconductor field effect transistors (nMOSFETs) 10c, 10d. Here, the pMOSFETs 10a, 10b are an example of "a pair of first transistors" of the present invention, and the nMOSFETs 10c, 10d are an example of "a pair of second transistors" of the present invention.

[0045] In the pair of pMOSFETs 10a, 10b, the source terminal of one pMOSFET 10a is connected to the high voltage power supply side node CSP, the drain terminal is connected to the high voltage power supply side bit line BLT, and the gate terminal is connected to the low voltage power supply side bit line BLB. In addition, in the pair of pMOSFETs 10a, 10b, the source terminal of the other pMOSFET 10b is connected to the high voltage power supply side node CSP, the drain terminal is connected to the low voltage power supply side bit line BLB, and the gate terminal is connected to the high voltage power supply side bit line BLT. In addition, in this embodiment, the high voltage power supply voltage is taken as 1V and the low voltage power supply voltage VSS is taken as 0V for illustration.

[0046] In addition, in the pair of nMOSFETs 10c, 10d, the drain terminal of one nMOSFET 10c is connected to the high voltage power supply side bit line BLT, the source terminal is connected to the low voltage power supply side node CSN, and the gate terminal is connected to the low voltage power supply side bit line BLB. In addition, in the pair of nMOSFETs 10c, 10d, the drain terminal of the other nMOSFET 10d is connected to the low voltage power supply side bit line BLB, the source terminal is connected to the low voltage power supply side node CSN, and the gate terminal is connected to the high voltage power supply side bit line BLT.

[0047] In addition, the high-voltage power supply side bit line BLT is connected to one of a pair of complementary local data lines LDQT and LDQB, i.e., LDQT, via an nMOSFET 10e whose gate terminal inputs a column selection signal CSL corresponding to a column address input from the outside. In addition, the low-voltage power supply side bit line BLB is connected to the other local data line LDQB via an nMOSFET 10f whose gate terminal inputs the column selection signal CSL. In addition, a memory cell 11 is also connected to the low-voltage power supply side bit line BLB. The memory cell 11 may include, for example, a conventional configuration of an nMOSFET 11a to which a row selection signal WL is input to its gate terminal and a capacitor 11b.

[0048] In addition, Figure 1 the structure of the sense amplifier 10 shown in Figure 1 is only an example, and the sense amplifier 10 may include

[0049] other circuits not shown therein (such as an equalization circuit, etc.).

[0050] Referring to Figure 2 , a configuration example of the control unit 20 will be described. In a state where no predetermined operation is performed and the sense amplifier 10 holds data, the control unit 20 is configured to set the voltage of the low-voltage power supply side bit line BLB to a predetermined voltage VBLL higher than the low-voltage power supply voltage VSS.

[0051] In addition, when a predetermined operation is performed in a state where the voltage of the low-voltage power supply side bit line BLB is set to the predetermined voltage VBLL, the control unit 20 may set the voltage of the low-voltage power supply side bit line BLB to the low-voltage power supply voltage VSS. In this way, when a predetermined operation is performed, the voltage of the low-voltage power supply side bit line BLB is set to the low-voltage power supply voltage VSS, so that the predetermined operation can be normally performed.

[0052] Here, the predetermined operation may include at least one of the following: reading, writing data stored in the storage unit 11 connected to the sense amplifier 10, and precharging a pair of bit lines BLT and BLB. Thus, when at least one of reading, writing data stored in the storage unit 11, and precharging a pair of bit lines BLT and BLB is not performed, the voltage of the low-voltage power supply side bit line BLB can be set to a predetermined voltage VBLL.

[0053] In addition, the predetermined voltage VBLL may be lower than the voltage of the high-voltage power supply side bit line BLT in the pair of bit lines BLT and BLB (1V in this embodiment). Thus, a potential difference can be generated between the pair of bit lines BLT and BLB while the sense amplifier 10 holds data.

[0054] As Figure 2 shown, the control unit 20 includes: a first supply unit 21 and a second supply unit 22. The first supply unit 21 supplies the low-voltage power supply voltage VSS to the low-voltage power supply side bit line BLB; the second supply unit 22 supplies the predetermined voltage VBLL to the low-voltage power supply side bit line BLB in a state where the predetermined operation is not performed.

[0055] The first supply unit 21 includes a first switch unit 21a and a second switch unit 21b. When a first control signal PD indicating that the predetermined operation is not performed is input, the first switch unit 21a supplies the predetermined voltage VBLL supplied from the second supply unit 22 to the low-voltage power supply side bit line BLB; when a second control signal NSE indicating that the predetermined operation is performed is input, the second switch unit 21b supplies the low-voltage power supply voltage VSS to the low-voltage power supply side bit line BLB.

[0056] In this embodiment, the first switch unit 21a is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the low-voltage power supply side node CSN of each sense amplifier 10, and the source terminal is connected to the second supply unit 22. In addition, the first control signal PD is input to the gate terminal. When a high-level first control signal PD indicating that the predetermined operation is not performed is input to the gate terminal, the first switch unit 21a supplies the predetermined voltage VBLL supplied from the second supply unit 22 to the low-voltage power supply side node CSN of each sense amplifier 10. Then, the predetermined voltage VBLL is supplied to the low-voltage power supply side bit line BLB.

[0057] In the present embodiment, the second switching unit 21b is constituted by an nMOSFET. The drain terminal of this nMOSFET is connected to the low-voltage power supply side node CSN of each sense amplifier 10, and the source terminal is connected to the low-voltage power supply voltage VSS. In addition, a second control signal NSE is input to the gate terminal. When a high-level second control signal NSE indicating that a predetermined operation is to be performed is input to the gate terminal, the second switching unit 21b supplies the low-voltage power supply voltage VSS to the low-voltage power supply side node CSN of each sense amplifier 10. Then, the low-voltage power supply voltage VSS is supplied to the low-voltage power supply side bit line BLB.

[0058] In addition, the first control signal PD and the second control signal NSE may be complementary signals. In addition, the first control signal PD and the second control signal NSE may be generated in the control unit 20 or may be generated by other circuits provided in the semiconductor memory device.

[0059] The second supply unit 22 includes a comparator 22a and a switching unit 22b. The comparator 22a has a first terminal (+ terminal) and a second terminal (- terminal). The voltage of the low-voltage power supply side bit line BLB (connected to the low-voltage power supply side node CSN of each sense amplifier 10) is input to the first terminal, and a reference voltage VREF (= a predetermined voltage VBLL) is input to the second terminal. In addition, the output terminal of the comparator 22a is connected to the switching unit 22b. In the present embodiment, the switching unit 22b is constituted by an nMOSFET. The drain terminal of this nMOSFET is connected to the low-voltage power supply side node CSN of each sense amplifier 10 via the first switching unit 21a of the first supply unit 21, and the source terminal is connected to the low-voltage power supply voltage VSS. In addition, a signal output from the comparator 22a is input to the gate terminal. With such a configuration, the second supply unit 22 can output a predetermined voltage VBLL.

[0060] Reference Figure 3 , an example of the operation of the control unit 20 will be described. Here, first, it is assumed that a predetermined operation (at least one of the following: reading, writing data stored in the memory cell 11, and precharging a pair of bit lines BLT and BLB) is being performed in the semiconductor memory device. In this case, the first control signal PD is at a low level and the second control signal NSE is at a high level. At this time, the control unit 20 supplies the low-voltage power supply voltage VSS to the low-voltage power supply side node CSN of each sense amplifier 10. Thereby, the low-voltage power supply voltage VSS is supplied to the low-voltage power supply side bit line BLB.

[0061] Next, when the predetermined operation ends (when there is no more predetermined operation) and the sense amplifiers 10 hold data, at time t0, the first control signal PD goes high and the second control signal NSE goes low. At this time, the control unit 20 supplies the predetermined voltage VBLL to the low-voltage power supply side node CSN of each sense amplifier 10. Accordingly, the predetermined voltage VBLL is supplied to the low-voltage power supply side bit line BLB.

[0062] Here, in a state where no predetermined operation is performed and the sense amplifiers 10 hold data, by setting the voltage of the low-voltage power supply side bit line BLB to a predetermined voltage VBLL that is higher than the low-voltage power supply voltage VSS. For example, when the low-voltage power supply voltage VSS is 0V, the back gate-source voltage of a transistor ( Figure 1 the examples in are nMOSFET 10c, nMOSFET10f) with a gate-source voltage of 0V becomes a negative voltage, and the threshold voltage of this transistor 10c, 10f becomes higher due to the reverse bias effect. Therefore, the leakage current generated in this transistor 10c, 10f is reduced.

[0063] Next, when a predetermined operation (at least one of the following: reading, writing data stored in the memory cell 11, and precharging a pair of bit lines BLT, BLB) is performed at time t1, the first control signal PD goes low and the second control signal NSE goes high. At this time, the control unit 20 supplies the low-voltage power supply voltage VSS to the low-voltage power supply side node CSN of each sense amplifier 10. Thus, since the voltage of the low-voltage power supply side bit line BLB is set to the voltage VSS when the predetermined operation is performed, the predetermined operation can be performed normally.

[0064] As described above, according to the semiconductor memory device and its control method of the present embodiment, in a state where no predetermined operation is performed and the sense amplifiers 10 hold data, by setting the voltage of the low-voltage power supply side bit line BLB to a predetermined voltage VBLL that is higher than the low-voltage power supply voltage VSS. For example, when the low-voltage power supply voltage is 0V, the back gate-source voltage of a transistor ( Figure 1 the examples in are nMOSFET 10c, nMOSFET 10f) with a gate-source voltage of 0V becomes a negative voltage, and the threshold voltage of this transistor 10c, 10f becomes higher due to the reverse bias effect. Therefore, the leakage current generated in this transistor 10c, 10f is reduced. In addition, in nMOSFET 10f, since the gate-source voltage becomes a negative voltage, the leakage current generated in nMOSFET10f is reduced. Thereby, the leakage current generated in the sense amplifiers 10 in the data holding state can be reduced.

[0065] The above-described embodiments are only for explaining the present invention for easy understanding and are not for limiting the present invention. Therefore, each element disclosed in the above-described embodiments includes all design changes and equivalents within the technical scope of the present invention.

[0066] For example, in the above-described embodiment, the control unit 20 has the Figure 2 configuration shown as an example for explanation, but the present invention is not limited thereto. For example, the control unit 20 may have the Figure 4 another configuration shown. Referring to Figure 4 , the first supply unit 21 of the control unit 20 includes a first switch unit 21a, a second switch unit 21b, a third switch unit 21c, and a fourth switch unit 21d. Here, the configurations of the first switch unit 21a and the second switch unit 21b are the same as those in the above-described embodiment.

[0067] The third switch unit 21c is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the low-voltage power supply side node CSN of each sense amplifier 10, and the source terminal is connected to the drain terminal of the nMOSFET constituting the fourth switch unit 21d. In addition, a signal output from the comparator 22a of the second supply unit 22 is input to the gate terminal.

[0068] The fourth switch unit 21d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the source terminal of the fourth switch unit 21c, and the source terminal is connected to the low-voltage power supply voltage VSS. In addition, a first control signal PD is input to the gate terminal.

[0069] In addition, Figure 4 the second supply unit 22 of the control unit 20 shown in

[0070] includes a comparator 22a, a NOT circuit 22c, and a switch unit 22d. Here, the structure of the comparator 22a is the same as that in the above-described embodiment. The NOT circuit 22c inputs the first control signal PD. The switch unit 22d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the low-voltage power supply side node CSN of each sense amplifier 10 via the first switch unit 21a of the first supply unit 21, and the source terminal is connected to the low-voltage power supply voltage VSS. In addition, a signal output from the NOT circuit 22c is input to the gate terminal. Figure 4 As shown in

[0071] Figure 2 Figure 4 and Figure 4In the example, it is described by taking the switching units 21a, 21b, 21c, 21d, 22b, and 22d being composed of MOSFETs as an example, but the present invention is not limited thereto. For example, the switching units 21a, 21b, 21c, 21d, 22b, and 22d may be composed of other transistors other than MOSFETs, or may be composed of other elements or circuits other than transistors.

[0072] In addition, in Figure 2 and Figure 4 the example, it is described by taking the control unit 20 having one first supply unit 21 and one second supply unit 22 as an example, but the present invention is not limited thereto. For example, the control unit 20 may have a plurality of first supply units 21 and one second supply unit 22. In this case, each of the plurality of first supply units 21 is connected to each low-voltage power supply side node CSN of the plurality of sense amplifiers 10 in the same manner as in Figure 2 and Figure 4 the example, and one second supply unit 22 is connected to the plurality of first supply units 21. Thereby, one second supply unit 22 can supply a predetermined voltage VBLL to the low-voltage power supply side bit line BLB via each of the plurality of first supply units 21.

[0073] In addition, the structures of the sense amplifier 10 and the control unit 20 in the above-described embodiment are only examples, and can be appropriately changed, and various other structures can also be adopted.

Claims

1. A semiconductor storage device, characterized in that: include: a sense amplifier connected to a pair of bit lines, including at least one transistor connected to a low voltage power supply side bit line of the pair of bit lines; The control unit sets the voltage of the low voltage power supply side bit line to a predetermined voltage higher than the low voltage power supply voltage when a predetermined operation is not performed and the sense amplifier holds data.

2. The semiconductor memory device according to claim 1, wherein When the predetermined operation is performed in a state where the voltage of the low voltage power supply side bit line is set to the predetermined voltage, the control unit sets the voltage of the low voltage power supply side bit line to the low voltage power supply voltage.

3. The semiconductor memory device according to claim 1, wherein: The predetermined action includes at least one of: reading, writing data stored in a memory cell connected to the sense amplifier, and precharging the pair of bit lines.

4. The semiconductor memory device according to claim 1, wherein: The control unit includes: at least one first supply section, supplying the low voltage power supply voltage to the low voltage power supply side bit line; The second supply unit supplies the predetermined voltage to the low voltage power supply side bit line in a state where the predetermined operation is not performed.

5. The semiconductor memory device according to claim 4, wherein: The first supply unit includes: a first switch section that supplies the predetermined voltage supplied by the second supply section to the low voltage power supply side bit line when a first control signal indicating that the predetermined action is not performed is input; The second switch section supplies the low voltage power supply voltage to the low voltage power supply side bit line when a second control signal indicating that the predetermined operation is to be performed is input.

6. The semiconductor memory device according to claim 4 or 5, wherein: The second supply unit includes: The comparator has a first terminal and a second terminal. The voltage of the low voltage power supply side bit line is input to the first terminal, and the predetermined voltage is input to the second terminal.

7. The semiconductor memory device according to claim 1, wherein: The predetermined voltage is lower than a voltage of a high voltage power supply side bit line of the pair of bit lines.

8. The semiconductor memory device according to claim 1, wherein: The sense amplifier comprises: a pair of first transistors, wherein one first transistor is connected to the high voltage power supply side bit line, and the other first transistor is connected to the low voltage power supply side bit line; A pair of second transistors, one of the second transistors is connected to the high voltage power supply side bit line, and the other second transistor is connected to the low voltage power supply side bit line.

9. The semiconductor memory device according to claim 8, wherein: One of the pair of first transistors and the pair of second transistors is an N-type metal oxide semiconductor field effect transistor, and the other of the pair of first transistors and the pair of second transistors is a P-type metal oxide semiconductor field effect transistor.

10. The semiconductor memory device according to claim 1, wherein: The low voltage power supply voltage is 0V.

11. A control method for a semiconductor storage device, characterized in that: The semiconductor memory device includes a sense amplifier; The sense amplifier is connected to a pair of bit lines and includes at least one transistor connected to a low voltage power supply side bit line among the pair of bit lines; When the predetermined action is not performed and the sense amplifier holds data, the control unit of the semiconductor memory device sets the voltage of the low voltage power supply side bit line to a predetermined voltage higher than the low voltage power supply voltage.

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