Semiconductor memory device and control method thereof

Abstract

The present disclosure provides a semiconductor memory device and a method of controlling the same, the semiconductor memory device including: a memory cell array including memory cells; and a bit line sense amplifier having an open bit line structure and including a plurality of switching transistors, in which the bit line sense amplifier is connected to the memory cell via a bit line and a complementary bit line, and a plurality of switching transistors configured to control connections between the bit line, the complementary bit line, the readout bit line, and the complementary readout bit line based on a plurality of switching signals; a temperature measurement circuit configured to measure an operating temperature of the semiconductor memory device and generate a temperature code corresponding to the operating temperature; and a sense amplifier controller configured to control a timing of the plurality of switching signals based on the temperature code to reduce a sense noise of the bit line sense amplifier.

Description

Technical Field

[0001] The present disclosure relates to semiconductor integrated circuits, and more particularly, to a semiconductor memory device capable of effectively reducing read noise and a control method thereof. Background Art

[0002] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory (e.g., DRAM or SRAM) devices have fast read and write times, but the data stored therein is lost if the power supply is interrupted. On the other hand, non-volatile memory devices can retain data even if the power supply is interrupted.

[0003] A main example of a volatile memory device is a dynamic random access memory (DRAM) device. A memory cell in a DRAM can include an N-type metal oxide semiconductor (NMOS) transistor as a switch and a capacitor for storing charge (data). Depending on the presence or absence of charge on the capacitor stored in the memory cell (i.e., whether the terminal voltage of the cell capacitor is high or low), binary information "1" or "0" can be identified. The memory cell can be connected to a word line and a bit line. The bit line can be connected to a bit line sense amplifier. The bit line sense amplifier can read the data stored in the memory cell via the bit line based on the voltage applied to the word line.

[0004] The bit line sense amplifier can have an open bitline structure connected to the memory cell via a bit line and a complementary bit line. When a read operation or a refresh operation is performed in the volatile memory device, the bit line sense amplifier can detect and amplify the voltage difference between the bit line and the complementary bit line. A semiconductor device including a bit line sense amplifier may be affected by process, voltage, and temperature (PVT) variations, etc., which may cause offset noise due to characteristic differences between devices (such as threshold voltage differences). In addition, depending on the pattern of data stored in the memory cell, data pattern noise may occur due to interference or coupling between signal lines and / or voltage lines. Furthermore, charge leakage noise may occur due to charge leakage in the bit line sense amplifier. These read noises can vary with the operating temperature, which reduces the effective read margin of the bit line sense amplifier and degrades the performance of the semiconductor memory device. Summary of the Invention

[0005] The present disclosure provides a semiconductor memory device capable of effectively reducing read noise according to the operating temperature and a control method thereof.

[0006] According to one aspect of the present disclosure, a semiconductor memory device includes: a memory cell array including memory cells; a bit line sense amplifier having an open bit line structure and including a plurality of switching transistors, wherein the bit line sense amplifier is connected to the memory cells via a bit line and a complementary bit line, and the plurality of switching transistors are configured to control connections between the bit line, the complementary bit line, a sense bit line, and a complementary sense bit line based on a plurality of switching signals; a temperature measurement circuit configured to measure an operating temperature of the semiconductor memory device and generate a temperature code corresponding to the operating temperature; and a sense amplifier controller configured to control timings of the plurality of switching signals based on the temperature code to reduce read noise of the bit line sense amplifier.

[0007] According to one aspect of the present disclosure, a semiconductor memory device includes: a memory cell array including memory cells; a bit line sense amplifier having an open bit line structure, wherein the bit line sense amplifier is connected to the memory cells via a bit line and a complementary bit line, and the bit line sense amplifier includes: a first switching transistor configured to control a connection between the bit line and a complementary sense bit line based on a first switching signal; a second switching transistor configured to control a connection between the complementary bit line and a sense bit line based on the first switching signal; a third switching transistor configured to control a connection between the bit line and the sense bit line based on a second switching signal; a fourth switching transistor configured to control a connection between the complementary bit line and the complementary sense bit line based on the second switching signal; and a fifth switching transistor configured to control a connection between the sense bit line and the complementary sense bit line based on a third switching signal; a temperature measurement circuit configured to measure an operating temperature of the semiconductor memory device and generate a temperature code corresponding to the operating temperature; and a sense amplifier controller configured to control timings of the first switching signal, the second switching signal, and the third switching signal based on the operating temperature to reduce read noise of the bit line sense amplifier.

[0008] According to one aspect of the present disclosure, a method of controlling a semiconductor memory device includes: providing a bit line sense amplifier having an open bit line structure and including a plurality of switching transistors, wherein the bit line sense amplifier is connected to a memory cell via a bit line and a complementary bit line, and wherein the plurality of switching transistors are configured to control connections between the bit line, the complementary bit line, a sense bit line, and a complementary sense bit line based on a plurality of switching signals; measuring an operating temperature of the semiconductor memory device to generate a temperature code corresponding to the operating temperature; and controlling a timing of the plurality of switching signals based on the temperature code to reduce sense noise of the bit line sense amplifier.

[0009] A semiconductor memory device and a method of controlling a semiconductor memory device according to one or more embodiments can reduce sense noise, increase an effective sense margin of a bit line sense amplifier, and improve performance of the semiconductor memory device by controlling an operation timing of the bit line sense amplifier according to an operating temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the drawings, in which:

[0011] Figure 1 is a flowchart illustrating a method of controlling a semiconductor memory device according to one or more embodiments;

[0012] Figure 2 is a graph illustrating sense noise and an effective sense margin of a semiconductor memory device;

[0013] Figure 3 is a graph illustrating an example of a sense mode and characteristics of a semiconductor memory device according to an operating temperature according to one or more embodiments;

[0014] Figure 4 is a graph illustrating a sense mode of a semiconductor memory device depending on a temperature range according to one or more embodiments;

[0015] Figure 5 is a block diagram illustrating a memory system according to one or more embodiments;

[0016] Figure 6 is a block diagram illustrating a semiconductor memory device according to one or more embodiments;

[0017] Figure 7 is a block diagram illustrating a sense amplifier controller included in a semiconductor memory device according to one or more embodiments;

[0018] Figure 8 is a diagram illustrating a bank array included in a semiconductor memory device according to one or more embodiments;

[0019] Figure 9 and Figure 10 is a diagram illustrating a memory core circuit included in a semiconductor memory device according to one or more embodiments;

[0020] Figure 11 and Figure 12 is a diagram illustrating a bit line sense amplifier included in a semiconductor memory device according to one or more embodiments;

[0021] Figure 13 is a diagram illustrating Figure 12 the equivalent circuit of the bit line sense amplifier;

[0022] Figure 14 is a timing diagram illustrating the H-type read mode of the bit line sense amplifier included in a semiconductor memory device according to one or more embodiments;

[0023] Figure 15 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier in Figure 14 the first offset compensation period;

[0024] Figure 16 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier in Figure 14 the second offset compensation period;

[0025] Figure 17 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier after Figure 14 the second offset compensation period;

[0026] Figure 18 is a diagram illustrating the model of the bit line sense amplifier in the offset compensation operation;

[0027] Figure 19 is a diagram illustrating Figure 13 the read operation of the bit line sense amplifier in Figure 14 the first read period;

[0028] Figure 20 is a diagram illustrating Figure 13 the read operation of the bit line sense amplifier in Figure 14 the second read period;

[0029] Figure 21 is a diagram illustratingFigure 13 The bit line sense amplifier in Figure 14 The figure of the read operation in the third read period of

[0030] Figure 22 Is a timing diagram illustrating the D-type read mode of the bit line sense amplifier included in a semiconductor memory device according to one or more embodiments;

[0031] Figure 23 Is a timing diagram illustrating the C-type read mode of the bit line sense amplifier included in a semiconductor memory device according to one or more embodiments;

[0032] Figure 24 Is a diagram illustrating the floating time in the D-type read mode of a semiconductor memory device according to one or more embodiments;

[0033] Figure 25 Is a diagram illustrating the floating time in the C-type read mode of a semiconductor memory device according to one or more embodiments;

[0034] Figure 26 And Figure 27 Is a graph illustrating the control of the floating time in a semiconductor memory device according to one or more embodiments;

[0035] Figure 28 And Figure 29 Is a diagram illustrating a stacked memory device according to one or more embodiments;

[0036] Figure 30 And Figure 31 Is a diagram illustrating the package structure of a stacked memory device according to one or more embodiments;

[0037] Figure 32 Is a diagram illustrating a memory system according to one or more embodiments;

[0038] Figure 33 Is a block diagram illustrating a temperature measurement circuit included in a semiconductor memory device according to one or more embodiments;

[0039] Figure 34 Is an illustration of Figure 33 The circuit diagram of the temperature detector included in the temperature measurement circuit of

[0040] Figure 35 Is a diagram illustrating a semiconductor package including a stacked memory device according to one or more embodiments; and

[0041] Figure 36 Is a block diagram illustrating a mobile system according to one or more embodiments. Detailed Description

[0042] One or more embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which one or more example embodiments are shown. In the drawings, like reference numerals always refer to like elements.

[0043] Terms such as "unit", "module", "member", and "block" may be embodied as hardware or software. As used in this specification, multiple "units", "modules", "members", and "blocks" may be implemented as a single component, or a single "unit", "module", "member", and "block" may include multiple components.

[0044] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly or indirectly connected to the other element.

[0045] Likewise, when a component "comprises" or "includes" an element, unless there is a specific description to the contrary, the component may also include other elements, thus not excluding other elements.

[0046] Throughout the specification, when a member is "on" another member, this includes not only when the member is in contact with the other member, but also when there is another member between the two members.

[0047] In this specification, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" indicate "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0048] It should be understood that although the terms "first", "second", "third", etc. may be used in this specification to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0049] As used in this specification, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0050] Regarding any method or process described in this specification, code may be identified for ease of description, but is not intended to indicate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be implemented in an order different from the order shown. Unless the context of the present disclosure clearly indicates otherwise, one or more steps or operations may be omitted.

[0051] Figure 1 is a flowchart illustrating a method of controlling a semiconductor memory device according to one or more embodiments.

[0052] Reference Figure 1 , a bit line sense amplifier with an open bit line structure is provided. The open bit line structure enables the bit line sense amplifier to be connected to a memory cell via a bit line and a complementary bit line, and the bit line sense amplifier includes a plurality of switching transistors configured to control electrical connections between the bit line, the complementary bit line, the sense bit line, and the complementary sense bit line based on a plurality of switching signals (S100). This will be described below with reference to Figure 11 、 Figure 12 and Figure 13 one or more embodiments of the open bit line structure and the bit line sense amplifier will be described.

[0053] The operating temperature of the semiconductor memory device is measured, and a temperature code corresponding to the operating temperature is generated (S200). The temperature code can be generated using a temperature measurement circuit formed on a semiconductor die of the semiconductor memory device. This will be described below with reference to the attached Figure 33 and Figure 34 one or more embodiments of the temperature measurement circuit will be described.

[0054] Based on the temperature code, the timing of the plurality of switching signals is controlled such that the read noise of the plurality of bit line sense amplifiers decreases according to the operating temperature (S300). As will be described below with reference to Figure 2 The read noise of the bit line sense amplifier can be caused by various reasons. As will be referred to Figure 3 will be further described, the read noise characteristics can vary depending on the read mode and the operating temperature of the semiconductor memory device.

[0055] In an embodiment, as will be further described with reference to the attached Figure 3 and Figure 4 the operating temperature can be divided into a plurality of temperature ranges, and the timing of the plurality of switching signals can be controlled such that for each of the plurality of temperature ranges, the plurality of bit line sense amplifiers can operate in different read modes.

[0056] In an embodiment, as will be described below with reference to Figures 24 to 27 the timing of the plurality of switching signals can be controlled such that as the operating temperature increases, the floating time of the sense bit line and the complementary sense bit line can be reduced.

[0057] Therefore, according to one or more embodiments of the method for controlling a semiconductor memory device, the read noise can be reduced, the effective read margin of the bit line sense amplifier can be increased, and the performance of the semiconductor memory device can be improved by controlling the operation timing of the bit line sense amplifier according to the operating temperature.

[0058] Figure 2This is a diagram illustrating the read noise and effective read margin of a semiconductor memory device.

[0059] Based on the amount of charge on the capacitor included in the memory cell, the memory device can perform a read operation and a refresh operation. In this case, the bit line associated with the memory cell is precharged with a precharge voltage. Then, as the word line is activated, charge sharing occurs between the charge on the bit line charged with the precharge voltage and the charge on the capacitor of the memory cell. Due to the charge sharing, the voltage on the bit line will decrease or increase by an amount of voltage change ΔVBL.

[0060] Reference Figure 2 , the bit line sense amplifier can detect and amplify the voltage change ΔVBL. At this time, the effective read margin ESM of the bit line sense amplifier decreases as the read noise SNN (such as offset noise attributed to the threshold voltage difference of the transistors of the bit line sense amplifier, data pattern noise attributed to the pattern of the data stored in the memory cell, charge leakage noise attributed to the charge leakage on the read bit line and the complementary read bit line, etc.) increases. As the read noise SNN increases, the effective read margin ESM decreases, and when the effective read margin ESM is below a certain level, the bit line sense amplifier may not be able to detect the voltage change ΔVBL of the bit line.

[0061] A semiconductor memory device according to one or more embodiments can utilize multiple switch signals to reduce offset noise. In addition, a semiconductor memory device according to one or more embodiments can efficiently reduce data pattern noise and charge leakage noise that vary with the operating temperature by controlling the timing of the multiple switch signals according to the operating temperature.

[0062] Figure 3 This is a diagram illustrating an example of the read mode and characteristics according to the operating temperature of a semiconductor memory device according to one or more embodiments.

[0063] Figure 3 Illustrates the characteristics as a function of the operating temperature To for the D-type read mode DTP and the C-type read mode CTP. In Figure 3 , the horizontal axis represents the operating temperature To, and the vertical axis represents the minimum amount of voltage change ΔVBL that can be read by the bit line sense amplifier.

[0064] Reference Figure 3, as the operating temperature To increases, the minimum detectable voltage change ΔVBL increases. In other words, the readout ability of the bit line sense amplifier decreases as the operating temperature To increases. In the low temperature range RC below the boundary temperature Tb, data pattern noise due to the pattern of data stored in the memory cell dominates over charge leakage noise due to charge leakage from the read bit line and the complementary read bit line. In contrast, in the high temperature range RH above the boundary temperature Tb, charge leakage noise dominates over data pattern noise. Therefore, in the low temperature range RC, the D-type readout mode DTP, which is relatively more effective in reducing data pattern noise, is suitable, while in the high temperature range RH, the C-type readout mode CTP, which is relatively more effective in reducing charge leakage noise, is suitable. Figure 3 The boundary temperature Tb in Figure 3 can vary depending on the level of charge leakage due to the manufacturing process of the semiconductor memory device.

[0065] In Figure 3 Two readout modes are illustrated: the D-type readout mode DTP and the C-type readout mode CTP, but the present disclosure is not limited thereto. According to one or more embodiments, the operating temperature To can be divided into two or more temperature ranges, and the timing of the plurality of switch signals can be controlled such that for each temperature range, the plurality of bit line sense amplifiers operate in different readout modes that are most suitable for reducing readout noise.

[0066] Figure 4 is a diagram illustrating the readout mode of a semiconductor memory device depending on the temperature range according to one or more embodiments.

[0067] Referring to Figure 4 , the operating temperature To of the semiconductor memory device can be divided into a low temperature range RC between the minimum temperature TMIN and the first temperature T1, a normal temperature range RR between the first temperature T1 and the second temperature T2, and a high temperature range RH between the second temperature T2 and the maximum temperature TMAX. For example, the minimum temperature TMIN can be about 10°C, the first temperature T1 can be about 25°C, the second temperature T2 can be about 80°C, and the maximum temperature TMAX can be about 110°C.

[0068] As Figure 4 shown, the bit line sense amplifier can be controlled such that the bit line sense amplifier operates in the D-type readout mode DTP in the low temperature range RC, in the H-type readout mode HTP in the normal temperature range RR, and in the C-type readout mode CTP in the high temperature range RH. As will be described below with reference to Figure 14 The H-type readout mode HTP can effectively reduce both data pattern noise and charge leakage noise simultaneously. As will be described below with reference to Figure 22As described, the D-type readout mode DTP can more effectively reduce data pattern noise. As will be described below with reference to Figure 23 As described, the C-type readout mode CTP can more effectively reduce charge leakage noise.

[0069] Figure 5 is a block diagram illustrating a storage system according to one or more embodiments.

[0070] With reference to Figure 5 , the storage system 10 includes a memory controller 50 and a semiconductor storage device 400. Each of the memory controller 50 and the semiconductor storage device 400 includes an interface for communicating with each other.

[0071] These interfaces can be connected via a control bus 21 for transmitting commands CMD, access addresses ADDR, clock signals CLK, etc., and via a data bus 22 for transmitting data DATA.

[0072] Depending on the type of the semiconductor storage device, the command CMD may be considered to include an access address ADDR. The memory controller 50 generates a command signal for controlling the semiconductor storage device 400, and under the control of the memory controller 50, data can be written to the semiconductor storage device 400 or data can be read from the semiconductor storage device 400.

[0073] The semiconductor storage device 400 may include a temperature measurement circuit TMMS100 and a sense amplifier controller SACON200.

[0074] As will be described below with reference to Figure 33 and Figure 34 As described, the temperature measurement circuit TMMS100 can measure the operating temperature To of the semiconductor storage device 400 and generate a temperature code TCODE corresponding to the operating temperature To. The temperature measurement circuit TMMS100 may include an on-chip temperature sensor formed on the semiconductor die of the semiconductor storage device 400. The on-chip temperature sensor can be used to accurately reflect the actual operating temperature To of the semiconductor storage device 400 to control its operation.

[0075] As will be described below with reference to Figure 7 As described, the sense amplifier controller SACON 200 can control the timing of a plurality of switch signals based on the temperature code TCOD so that the read noise of the bit line sense amplifier can be reduced according to the operating temperature To.

[0076] Figure 6 is a block diagram illustrating a semiconductor storage device according to one or more embodiments.

[0077] With reference to Figure 6, the memory device 400 may include command control logic 410, an address register 420, bank control logic 430, a row selection circuit 460 (or row decoder), a column decoder 470, a memory cell array 480, a sense amplifier unit 485, an input / output (I / O) gating circuit 490, a data input / output (I / O) buffer 495, a refresh controller 497, a temperature measurement circuit TMMS100, and a sense amplifier controller SACON 200.

[0078] The memory cell array 480 may include a plurality of bank arrays 480a, …, 480h. The row selection circuit 460 may include a plurality of bank row selection circuits 460a, …, 460h respectively coupled to the bank arrays 480a, …, 480h. The column decoder 470 may include a plurality of bank column decoders 470a, …, 470h respectively coupled to the bank arrays 480a, …, 480h. The sense amplifier unit 485 may include a plurality of bank sense amplifiers 485a, …, 485h respectively coupled to the bank arrays 480a, …, 480h.

[0079] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller 50. The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 430, may provide the received row address ROW_ADDR to the row selection circuit 460, and may provide the received column address COL_ADDR to the column decoder 470.

[0080] The bank control logic 430 may generate bank control signals in response to the bank address BANK_ADDR. One of the bank row selection circuits 460a, …, 460h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the bank column decoders 470a, …, 470h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0081] The row address ROW_ADDR from the address register 420 may be applied to the bank row selection circuits 460a, …, 460h. One of the activated bank row selection circuits 460a, …, 460h may decode the row address ROW_ADDR and may activate a word line corresponding to the row address ROW_ADDR. For example, the activated bank row selection circuit 460 may apply a word line drive voltage to the word line corresponding to the row address ROW_ADDR.

[0082] The column decoder 470 may include a column address latch. The column address latch may receive a column address COL_ADDR from the address register 420 and may temporarily store the received column address COL_ADDR. In one or more embodiments, in burst mode, the column address latch may generate a column address incremented from the received column address COL_ADDR. The column address latch may apply the temporarily stored or generated column address to the bank column decoders 470a, …, 470h.

[0083] An activated one of the bank column decoders 470a, …, 470h may decode the column address COL_ADDR and may control the I / O gating circuit 490 to output data corresponding to the column address COL_ADDR.

[0084] The I / O gating circuit 490 may include circuitry for gating input / output data. The I / O gating circuit 490 may also include a read data latch for storing data output from the memory banks 480a, …, 480h, and a write driver for writing data to the memory banks 480a, …, 480h.

[0085] Data read from one of the memory banks 480a, …, 480h may be sensed by one of the memory sense amplifiers 485a, …, 485h coupled to the one memory bank from which the data is read and may be stored in the read data latch. The data stored in the read data latch may be provided to the memory controller 50 via the data I / O buffer 495. Data DQ to be written in one of the memory banks 480a, …, 480h may be provided from the memory controller 50 to the data I / O buffer 495. The write driver may write the data DQ in one of the memory banks 480a, …, 480h.

[0086] The command control logic 410 may control the operation of the memory device 400. For example, the command control logic 410 may generate control signals for the memory device 400 to perform a write operation, a read operation, or a refresh operation. The command control logic 410 may be based on Figure 3The command CMD transmitted by the memory controller 50 therein is used to generate internal command signals such as an activation signal IACT, a precharge signal IPRE, a refresh signal IREF, a read signal IRD, a write signal IWR, etc. The command control logic 410 may include a command decoder 411 that decodes the command CMD received from the memory controller 50, and a mode register 412 that sets the operation mode of the memory device 400.

[0087] Although Figure 6 the command control logic 410 and the address register 420 are illustrated as being different from each other, the command control logic 410 and the address register 420 may be implemented as a single integrated circuit. Additionally, although Figure 6 illustrated, the command CMD and the address ADDR are provided as different signals, the command CMD and the address ADDR may be provided as a combined signal specified by, for example, the DDR5, HBM, and LPDDR5 standards.

[0088] The temperature measurement circuit TMMS100 may measure the operating temperature To of the semiconductor memory device 400 to generate a temperature code TCODE corresponding to the operating temperature To.

[0089] The sense amplifier controller SACON 200 may control a plurality of bank sense amplifiers 485a,..., 485h included in the sense amplifier unit 485 based on the temperature code TCODE. In Figure 6 it, the command control logic 410 and the sense amplifier controller 200 are shown as separate components, but the command control logic 410 and the sense amplifier controller 200 may be implemented as inseparable components.

[0090] Figure 7 is a block diagram illustrating a sense amplifier controller included in a semiconductor memory device according to one or more embodiments.

[0091] Referring to Figure 7 it, the sense amplifier controller 200 may include a mode selector MSCON 210 and a signal generator SGGEN 220.

[0092] The mode selector 210 may generate a mode signal MD indicating a read mode based on the temperature code TCODE provided from the temperature measurement circuit TMMS100. As described above, the mode selector 210 may divide the range of the potential operating temperature To into multiple temperature ranges, and generate a mode signal MD for indicating a read mode corresponding to each temperature range. Information about the read mode corresponding to each temperature range may be provided in advance through a test process of the semiconductor memory device, and may be stored in the non-volatile memory of the semiconductor memory device.

[0093] The signal generator 220 can generate a plurality of switch signals P1, P2, and P3 and a voltage selection signal VSEL based on the pattern signal MD and the temperature code TCODE. The signal generator 220 can include a delay circuit DLY for controlling the timing of the plurality of switch signals P1, P2, and P3, etc. The number of the plurality of switch signals P1, P2, and P3 and the number of the voltage selection signal VSEL can vary depending on the configuration and operation of the bit line sense amplifier.

[0094] Figure 8 FIG. is a diagram illustrating a bank array included in a semiconductor memory device according to one or more embodiments.

[0095] Reference Figure 8 , the bank array 310 includes a plurality of word lines WL1 to WL2m (where m is a natural number greater than 2), a plurality of bit lines BTL1 to BTL2n (where n is a natural number greater than 2), and a plurality of memory cells MC disposed near the intersections between the word lines WL1 to WL2m and the bit lines BTL1 to BTL2n. In one or more embodiments, each of the plurality of memory cells MC may include a DRAM cell structure as Figure 8 illustrated. The memory cell MC may include a cell capacitor connected to the board voltage VP and a cell transistor connected between each bit line and the cell capacitor, and the gate electrode of the cell transistor is connected to each word line. The plurality of word lines WL1 to WL2m to which the plurality of memory cells MC are connected may be referred to as rows of the bank array 310, and the plurality of bit lines BL1 to BL3n to which the plurality of memory cells MC are connected may be referred to as columns of the bank array 310.

[0096] Figure 9 and Figure 10 FIG. is a diagram illustrating a memory core circuit included in a semiconductor memory device according to one or more embodiments.

[0097] Reference Figure 9 , a sub-cell array SCA, a sense amplifier region RSA, a word line driver region RWD, and a power supply and control region RPC may be provided in the memory core circuit. In Figure 9 , the decoder region is omitted.

[0098] The sub-cell array SCA includes a plurality of word lines WL0 to WL7 extending in the row direction and a plurality of bit lines BT0 to BT3 extending in the column direction, and memory cells MC are disposed at the points where the bit lines BT0 to BT3 and the word lines WL0 to WL7 intersect.

[0099] The word line driver region RWD includes a plurality of sub-word line drivers SWD respectively for driving the plurality of word lines WL0 to WL3.

[0100] The sense amplifier region RSA includes bit line sense amplifiers BLSA 560 and local sense amplifier circuits (LSA circuits) 570 that are connected to bit lines BT0 to BT3 of the sub-cell array SCA in an open bit line structure. The bit line sense amplifiers BLSA 560 can amplify the detected voltage level difference on the bit lines BT0 to BT3 and provide the amplified voltage level difference to the local input / output line pair LIO1 and LIOB1.

[0101] In the power supply and control region RPC, a power supply circuit for supplying power to each sub-peripheral circuit and a control circuit for controlling the operation of each sub-peripheral circuit are provided. Figure 9 A voltage driver VG that may be included in the power supply and control region RPC is shown, but the present disclosure is not limited thereto.

[0102] Reference Figure 10 , voltage selection transistors LS1 and LS2 can apply an internal voltage VINTA or a precharge voltage VBL to the control line LA based on selection signals SEL1 and SEL2. Additionally, voltage selection transistors LS3 and LS4 can apply a ground voltage VSS or a precharge voltage VBL to the complementary control line LAB based on selection signals SEL3 and SEL4. The selection signals SEL1 to SEL4 may be included in Figure 7 the voltage selection signal VSEL.

[0103] In a semiconductor memory device, when a word line WL selected by a row address is activated, data from a plurality of memory cells MC connected to the word line WL is transferred to the pair of bit lines BL and BLB, and a plurality of bits are transmitted. The bit line sense amplifier BLSA detects and amplifies the voltage difference between the pair of bit lines BL and BLB based on the voltage of the control line LA and the voltage of the complementary control line LAB. At this time, since a large number of bit line sense amplifiers BLSA operate simultaneously, interference occurs in the internal voltage VINTA applied to the memory cell and the plate voltage VP, and the data pattern noise can increase significantly according to the data pattern stored in the memory cell.

[0104] Figure 11 and Figure 12 are diagrams illustrating bit line sense amplifiers included in a semiconductor memory device according to one or more embodiments, and Figure 13 is a diagram illustrating Figure 12 the equivalent circuit of the bit line sense amplifier.

[0105] Reference is made to the appended Figure 11 and Figure 12, the bit line sense amplifier 350 includes a first control circuit CON1 351, a second control circuit CON2 352, and a sense amplifier circuit 353.

[0106] The first control circuit CON1 351 is coupled to the bit line BL, the sense bit line SBL, and the complementary sense bit line SBLB. The second control circuit CON2 352 is coupled to the complementary bit line BLB, the sense bit line SBL, and the complementary sense bit line SBLB. The first control circuit CON1 351 and the second control circuit CON2 352 receive a first switch signal P1 and a second switch signal P2, and operate based on the first switch signal P1 and the second switch signal P2.

[0107] For example, the first control circuit CON1 351 can control the electrical connection between the bit line BL and the sense bit line SBL in response to the second switch signal P2, and control the electrical connection between the bit line BL and the complementary sense bit line SBLB in response to the first switch signal P1. The second control circuit CON2 352 can control the electrical connection between the complementary bit line BL and the complementary sense bit line SBLB in response to the second switch signal P2, and can control the electrical connection between the complementary bit line BL and the sense bit line SBL in response to the first switch signal P1.

[0108] The sense amplifier 353 includes an equalization circuit EQ 354, a P-type sense amplifier PSA 355, and an N-type sense amplifier NSA 356. The sense amplifier 353 can detect and amplify the voltage difference between the bit line BL and the complementary bit line BLB based on the voltages of the control line LA and the complementary control line LAB.

[0109] The equalization circuit EQ 354 can equalize the bit line pair BL and BLB and the sense bit line pair SBL and SBLB to the precharge voltage VBL. For example, during the precharge operation of the bit line sense amplifier 350, the first switch signal P1, the second switch signal P2, and the third switch signal P3 can be enabled (e.g., enabled to a logic high level), such that the bit line pair BL and BLB and the sense bit line pair SBL and SBLB can be connected as a single node. At this time, the equalization circuits E_1 and E_2 can respond to the equalization signal PEQ, and the bit line pair BL and BLB and the sense bit line pair SBL and SBLB can be charged and equalized to the precharge voltage VBL.

[0110] Reference appendix Figure 12 and Figure 13, the bit line sense amplifier 350 may include an N-type sense amplifier and a P-type sense amplifier. For example, the N-type sense amplifier may include a first N-type transistor NM1 and a second N-type transistor NM2. The P-type sense amplifier may include a first P-type transistor PM1 and a second P-type transistor PM2. The N-type sense amplifier and the P-type sense amplifier may amplify the amount of voltage change of the bit line BL according to a specified ratio during the bit line sense operation.

[0111] According to an embodiment, the bit line sense amplifier 350 may include a plurality of switching transistors, such as a first switching transistor S1 to a fifth switching transistor S5. The first switching transistor S1 may be connected between the bit line BL and the complementary sense bit line SBLB. The first switching transistor S1 may electrically connect or disconnect the bit line BL and the complementary sense bit line SBLB based on a first switching signal P1. The second switching transistor S2 may be connected between the complementary bit line BLB and the sense bit line SBL. The second switching transistor S2 may electrically connect or disconnect the complementary bit line BLB and the sense bit line SBL based on the first switching signal P1. The third switching transistor S3 may be connected between the bit line BL and the sense bit line SBL. The third switching transistor S3 may electrically connect or disconnect the bit line BL and the sense bit line SBL based on a second switching signal P2. The fourth switching transistor S4 may be connected between the complementary bit line BLB and the complementary sense bit line SBLB. The fourth switching transistor S4 may electrically connect or disconnect the complementary bit line BLB and the complementary sense bit line SBLB based on the second switching signal P2. The fifth switching transistor S5 may be connected between the complementary sense bit line SBLB and the sense bit line SBL. The fifth switching transistor S5 may electrically connect or disconnect the sense bit line SBL and the complementary sense bit line SBLB based on a third switching signal P3.

[0112] According to an embodiment, an N-type sense amplifier and a P-type sense amplifier are connected between complementary sense bit lines SBLB and a sense bit line SBL, and can detect and amplify a voltage difference between a bit line BL and a complementary bit line BLB based on voltages of a control line LA and a complementary control line LAB. For example, one end of a first P-type transistor PM1 can be connected to the control line LA, the other end of the first P-type transistor PM1 can be connected to the complementary sense bit line SBLB, and a gate electrode of the first P-type transistor PM1 can be connected to the sense bit line SBL. One end of a second P-type transistor PM2 can be connected to the control line LA, the other end of the second P-type transistor PM2 can be connected to the sense bit line SBL, and a gate electrode of the second P-type transistor PM2 can be connected to the complementary sense bit line SBLB. One end of a first N-type transistor NM1 can be connected to the complementary sense bit line SBLB, the other end of the first N-type transistor NM1 can be connected to the complementary control line LAB, and a gate electrode of the first N-type transistor NM1 can be connected to the bit line BL. One end of a second N-type transistor NM2 can be connected to the sense bit line SBL, the other end of the second N-type transistor NM2 can be connected to the complementary control line LAB, and a gate electrode of the second N-type transistor NM2 can be connected to the complementary bit line BLB.

[0113] Figure 14 is a timing diagram illustrating an H-type readout mode of a bit line sense amplifier included in a semiconductor memory device according to one or more embodiments.

[0114] Refer to Figure 13 and Figure 14 , an operation period of the bit line sense amplifier 350 can sequentially include a precharge period PRC, an offset compensation period OC, a charge sharing period CS, and a read period SEN. The semiconductor memory device can compensate for an offset voltage between the bit line BL and the complementary bit line BLB by performing a bit line offset compensation operation, and can accurately read data stored in a memory cell by performing a bit line read operation.

[0115] In the precharge period PRC, a first switch signal P1, a second switch signal P2, and a third switch signal P3 are activated (e.g., activated to a logic high level), so that the bit line pair BL and BLB and the sense bit line pair SBL and SBLB can be connected as one node. At this time, the control line LA and the complementary control line LAB can have a precharge voltage VBL, so that the bit line pair BL and BLB and the sense bit line pair SBL and SBLB can be charged and equalized to the precharge voltage VBL.

[0116] In the offset compensation period OC, the bit line sense amplifier 350 can be based on as will be described below with reference to the attached Figures 15 to 18The described bit line offset compensation method is used to measure the offset voltage between the bit line BL and the complementary bit line BLB and compensate for it.

[0117] During the charge sharing period CS, the precharge voltage VBL can be applied to the control line LA and the complementary control line LAB. The third switch signal P3 can be changed to a logic high level, and the sense bit line SBL and the complementary sense bit line SBLB can be connected to each other. Thus, the sense bit line SBL and the complementary sense bit line SBLB can be changed to the precharge voltage VBL. At this time, the word line WL can be changed to a high level, and charge sharing can occur between the charge stored in the cell capacitor CC of the memory cell MC and the charge stored in the bit line BL.

[0118] During the sense period SEN, the bit line sense amplifier 350 can read the voltage on the bit line BL based on the bit line sensing method described below with reference to Figures 19 to 21 the description.

[0119] Figure 15 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier in Figure 14 the first offset compensation period, Figure 16 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier in Figure 14 the second offset compensation period, and Figure 17 is a diagram illustrating Figure 13 the offset compensation operation of the bit line sense amplifier after Figure 14 the second offset compensation period.

[0120] Referring to Figures 14 to 17 , in the first offset compensation period OC1, the bit line sense amplifier 350 can be used as a negative feedback offset compensation scheme. In the second offset compensation period OC2, the bit line sense amplifier 350 can be used as a diode offset compensation scheme. Although the negative feedback offset compensation scheme has a fast operation speed, the efficiency of offset compensation may be reduced due to the dispersion of the read characteristics caused by process, voltage, and temperature (PVT) variations. On the other hand, the diode offset compensation method can have good PVT characteristics but a slow operation speed. According to one or more embodiments of the semiconductor memory device, a hybrid offset method that combines the advantages of the negative feedback offset compensation method and the diode offset compensation method can be used to perform the offset compensation operation of the bit line sense amplifier 350.

[0121] In the first offset compensation period OC1 (see Figure 15),The bit line sense amplifier 350 may perform a first offset compensation operation. For example, the first switch signal P1 may be kept active at a logic high level. The second switch signal P2 and the third switch signal P3 may be deactivated to a logic low level. Thus, the sense bit line SBL and the complementary sense bit line SBLB may be electrically disconnected (or isolated) from each other. The bit line BL and the sense bit line SBL may be electrically disconnected from each other. The complementary bit line BLB and the complementary sense bit line SBLB may be electrically disconnected from each other. At this time, the control line LA may be applied with an internal voltage VINTA higher than the precharge voltage VBL, and the complementary control line LAB may be applied with a ground voltage VSS lower than the precharge voltage VBL.

[0122] During the first offset compensation period OC1, due to the offsets of the N-type sense amplifier and the P-type sense amplifier, the bit line BL and the complementary bit line BLB (or the sense bit line SBL and the complementary sense bit line SBLB) may have a predetermined voltage difference (hereinafter, referred to as an offset voltage difference). For example, the bit line BL and the complementary bit line BLB may have an N-type offset voltage Vofs_n through the offsets of the first N-type transistor NM1 and the second N-type transistor NM2. In addition, the bit line BL and the complementary bit line BLB may have a P-type offset voltage Vofs_p through the offsets of the first P-type transistor PM1 and the second P-type transistor PM2, that is, the bit line BL and the complementary bit line BLB may have an offset voltage difference 2Vdt_n,p which is the sum of the N-type offset voltage Vofs_n and the P-type offset voltage Vofs_p. The N-type offset voltage Vofs_n may account for a first offset compensation ratio Voc_n1 (e.g., 70%) of the offset voltage difference 2Vdt_n,p. The P-type offset voltage Vofs_p may account for a second offset compensation ratio Voc_p1 (e.g., 30%) less than the first offset compensation ratio Voc_n1 of the offset voltage difference 2Vdt_n,p.

[0123] During the second offset compensation period OC2 (see Figure 16 ), the bit line sense amplifier 350 may perform a second offset compensation operation. For example, the first switch signal P1 may be maintained at a logic high level. The second switch signal P2 and the third switch signal P3 may be maintained at a logic low level. Thus, the complementary sense bit line SBLB and the sense bit line SBL may be electrically disconnected from each other. The bit line BL and the sense bit line SBL may be electrically disconnected from each other. The complementary bit line BLB and the complementary sense bit line SBLB may be electrically disconnected from each other. At this time, the control line LA may be changed from the internal voltage VINTA to the precharge voltage VBL. The complementary control line LAB may be maintained at the ground voltage VSS. Thus, the first P-type transistor PM1 and the second P-type transistor PM2 may be turned off.

[0124] During the second offset compensation period OC2, as the first P-type transistor PM1 and the second P-type transistor PM2 are turned off, the ratio of the N-type offset voltage Vofs_n to the P-type offset voltage Vofs_p between the bit line BL and the complementary bit line BLB (or between the complementary sense bit line SBLB and the sense bit line SBL) can be changed. For example, the N-type offset voltage Vofs_n can account for a third offset compensation ratio Voc_n2 (e.g., 90%) greater than the first offset compensation ratio Voc_n1 of the offset voltage difference 2Vdt_n,p. The P-type offset voltage Vofs_p can account for a fourth offset compensation ratio Voc_p2 (e.g., 10%) less than the second offset compensation ratio Voc_p1 of the offset voltage difference 2Vdt_n,p. In one example, the fourth offset compensation ratio Voc_p2 can be set to 10% or less.

[0125] According to an embodiment, after the second offset compensation period OC2 (see Figure 17 ), the bit line sense amplifier 350 can perform a bit line offset detection operation between the bit line BL and the complementary bit line BLB. For example, the first switch signal P1 can be changed to a logic low level. Thus, the bit line BL and the sense bit line SBL can be electrically disconnected from each other. In addition, the complementary bit line BLB and the complementary sense bit line SBLB can be disconnected from each other. The third switch signal P3 can be changed to a logic high level. Thus, the sense bit line SBL and the complementary sense bit line SBLB can be electrically connected to each other. The complementary control line LAB can be changed to the precharge voltage VBL. Thus, the bit line BL and the complementary bit line BLB can maintain the offset voltage difference 2Vdt_n,p. In addition, the sense bit line SBL and the complementary sense bit line SBLB can have the precharge voltage VBL via the complementary control line LAB.

[0126] As described above, during the first offset compensation period OC1, the bit line sense amplifier 350 can quickly detect the offset voltage difference 2Vdt_n,p including the N-type offset voltage Vofs_n and the P-type offset voltage Vofs_p via a negative feedback offset compensation scheme. In addition, during the second offset compensation period OC2, the bit line sense amplifier 350 can improve the PVT characteristics through a diode offset compensation scheme to finally detect the offset voltage difference 2Vdt_n,p. The bit line sense amplifier 350 can change the ratio of the N-type offset voltage Vofs_n to the P-type offset voltage Vofs_p including the offset voltage difference 2Vdt_n,p through the first offset compensation period OC1 and the second offset compensation period OC2. By changing the ratio of the N-type offset voltage Vofs_n to the P-type offset voltage Vofs_p, the bit line sense amplifier 350 can improve the accuracy of the bit line sense operation.

[0127] Figure 18FIG. is a diagram illustrating a model of a bit line sense amplifier in an offset compensation operation. The modeled bit line sense amplifier 350 in the offset compensation operation may include an amplifier 350a and an offset voltage source Vofs.

[0128] The negative output terminal of the amplifier 350a is coupled to the negative voltage terminal of the offset voltage source Vofs. The positive input terminal of the offset voltage source Vofs is connected to the positive input terminal of the amplifier 350a. The positive output terminal of the amplifier 350a is connected to the negative input terminal of the amplifier 350a. In this case, the output terminal of the amplifier 350a may correspond to the sense bit line SBL and the complementary sense bit line SBLB, and the input terminal of the amplifier 350a may correspond to the bit line BL and the complementary bit line BLB. For example, the offset voltage Vos refers to the offset of the first P-type transistor PM1, the second P-type transistor PM2, the first N-type transistor NM1, and the second N-type transistor NM2. In this case, Figure 18 The behavior of the shown equivalent circuit may be as shown in Expression 1.

[0129] Expression 1:

[0130] V BL +V OS -V BLB =α(V SABL -V SABLB )

[0131] ∵(V BL =V SABLB ,V BLB =V SABL )

[0132]

[0133] Referring to Expression 1, V BL refers to the voltage on the bit line BL, Vos refers to the offset value of the bit line sense amplifier 350, V BLB refers to the voltage on the complementary bit line BLB, V SABL refers to the voltage on the sense bit line SBL, V SABLB refers to the voltage on the complementary sense bit line SBLB, and α refers to the voltage gain of the amplifier 350a. As shown in Expression 1, the voltage difference between the bit line BL and the complementary bit line SBL will be close to the offset voltage Vos. In other words, the offset of the bit line sense amplifier 350 can be compensated by the voltage level on the bit line BL compensated by the offset Vos.

[0134] Due to PVT variations, the threshold voltages of the first N-type transistor NM1 and the second N-type transistor NM2 can be different. In this case, it is assumed that the threshold voltage of the first N-type transistor NM1 is higher than the threshold voltage of the second N-type transistor NM2 by an offset voltage Vos. In this case, based on Figure 18 the aforementioned behavior of the modeled circuit in

[0135] Figure 2

[0136] Figure 19 Figure 13 Figure 14 is a diagram illustrating Figure 13 the bit-line sense amplifier in Figure 14 the first read period of Figure 20 is a diagram illustrating Figure 13 the bit-line sense amplifier in Figure 14 the second read period of Figure 21 is a diagram illustrating Figure 13 the bit-line sense amplifier in Figure 14 the third read period of

[0137] Refer to Figure 13 、 Figure 14 、 Figures 19 to 21 , the bit-line sense amplifier 350 can increase the read ratio of the N-type sense amplifier compared to the P-type sense amplifier to improve the read efficiency.

[0138] In the first read period SEN1 (refer to Figure 19) For example, the first switch signal P1 and the second switch signal P2 can be kept deactivated at a logic low level. Thus, the bit line BL can be electrically disconnected from the sense bit line SBL and the complementary sense bit line SBLB. The complementary bit line BLB can be electrically disconnected from the sense bit line SBL and the complementary sense bit line SBLB. The third switch signal P3 can be kept activated at a high level. Thus, the sense bit line SBL and the complementary sense bit line SBLB can be equalized to the same voltage. The control line LA can be applied with a first internal voltage VINTA higher than the pre-charge voltage VBL. Thus, the sense bit line SBL and the complementary sense bit line SBLB can rise to a predetermined voltage (e.g., VINTA - Vthp, where Vthp is the threshold voltage of the first P-type transistor PM1 or the second P-type transistor PM2). The word line WL can be kept at a high level during the bit line read operation.

[0139] In the second read period SEN2 (e.g., N-dominant read) (see Figure 20 ), the bit line sense amplifier 350 can perform a pre-read operation. For example, the third switch signal P3 can be deactivated to a logic low level. Thus, the complementary sense bit line SBLB and the sense bit line SBL can be electrically disconnected. The complementary control line LAB can be applied with a second internal voltage lower than the pre-charge voltage VBL (e.g., the ground voltage VSS). In this case, the voltage of the complementary sense bit line SBLB and the voltage of the sense bit line SBL can have different voltage values based on the N-type sense amplifier (e.g., the first N-type transistor NM1 or the second N-type transistor NM2). In this case, the read ratio of the N-type sense amplifier can account for a first read ratio Vs_n, such as 90%. The read ratio of the P-type sense amplifier can be a second read ratio Vs_p (e.g., 10%). In one example, the first read ratio Vs_n can be equal to the third offset compensation ratio Voc_n2 in the offset compensation operation described in reference Figures 15 to 17 . The second read ratio Vs_p can be equal to the fourth offset compensation ratio Voc_p2 in the offset compensation operation described in reference Figures 15 to 17 .

[0140] In the third read period SEN3 (see Figure 21 ), the bit line sense amplifier 350 can perform a recovery read operation. For example, the second switch signal P2 can be activated to a logic high level. Thus, the bit line BL and the sense bit line SBLB can be electrically connected. The complementary bit line BLB and the complementary sense bit line SBLB can be electrically connected. Thus, the bit line BL can be raised (or lowered) to the voltage level of the sense bit line SBL. The complementary bit line BLB can be raised (or lowered) to the voltage level of the complementary sense bit line SBLB. The bit line sense amplifier 350 can be connected to the data line after the first read period SEN1 and can output via the data line to the input / output circuit.

[0141] As described in reference Figure 14 、 Figures 19 to 21 , the sense amplifier controller 200 can control the timing of the second switch signal P2 and the third switch signal P3 such that within the normal temperature range RR of Figure 4 , the bit line sense amplifier operates in the H-type read mode HTP. The sense amplifier controller 200 can activate the third switch signal P3 such that the bit line SBL and the complementary bit line SBLB are electrically connected during the charge sharing period CS. Further, the sense amplifier controller 200 can activate the second switch signal P2 such that during the read period SEN after the charge sharing period CS, for example, during the third read period SEN3, the bit line BL and the sense bit line SBL are electrically connected and the complementary bit line SBL and the complementary sense bit line SBLB are electrically connected after the third switch signal P3 is deactivated.

[0142] Accordingly, in the H-type read mode HTP, the sense amplifier controller 200 can activate the third switch signal P3 to turn on the fifth switching transistor S5 after offset compensation is completed, deactivate the third switch signal P3 to turn off the fifth switching transistor S5 during the second read period SEN2, and activate the second switch signal P2 to turn on the third switching transistor S3 and the fourth switching transistor S4 during the third read period SEN3. By using this H-type read mode HTP, data pattern noise and charge leakage noise can be effectively reduced simultaneously.

[0143] Figure 22 is a timing diagram illustrating a D-type read mode of a bit line sense amplifier included in a semiconductor memory device according to one or more embodiments. Hereinafter, descriptions redundant with Figures 14 to 21 will be omitted, and the description will focus on the differences.

[0144] Referring to Figure 22 , the sense amplifier controller 200 can control the timing of the second switch signal P2 and the third switch signal P3 such that within Figure 4In the low-temperature range RC, the bit-line sense amplifier operates in the D-type read mode DTP. The sense amplifier controller 200 can deactivate the third switch signal P3 during the charge sharing period CS, causing the sense bit-line SBL and the complementary sense bit-line SBLB to be electrically disconnected. In addition, the sense amplifier controller 200 can switch the second switch signal P2 during the charge sharing period CS, such that, for example, during the time interval ta to tb, the bit-line BL and the sense bit-line SBL are temporarily electrically connected and the complementary bit-line BLB and the complementary sense bit-line SBLB are temporarily electrically connected. As used in this specification, "switching" a signal generally means alternating between an active (e.g., logic high) state and a deactivated (e.g., logic low) state. Further, the sense amplifier controller 200 can activate the second switch signal P2 in the sense period SEN after the charge sharing period CS, for example, in the third sense period SEN3, causing the bit-line BL and the sense bit-line SBL to be electrically connected and the complementary bit-line BLB and the complementary sense bit-line SBLB to be electrically connected.

[0145] Thus, in the D-type read mode DTP, the sense amplifier controller 200 switches the second switch signal P2 during the charge sharing period CS to transfer data information to the internal nodes of the bit-line sense amplifier, namely, the sense bit-line SBL and the complementary sense bit-line SBLB. At the start of the sense period SEN, for example, in the first sense period SEN1 and the second sense period SEN2, the second switch signal P2 can be deactivated to turn off the third switch transistor S3 and the fourth switch transistor S4, such that the readout by the voltages of the sense bit-line SBL and the complementary sense bit-line SBLB can be performed first. Then, in the third sense period SEN3, the second switch signal P2 can be activated to turn on the third switch transistor S3 and the fourth switch transistor S4. This D-type read mode DTP enables more effective reduction of data pattern noise dominant in the low-temperature range RC.

[0146] Figure 23 is a timing diagram illustrating a C-type read mode of a bit-line sense amplifier included in a semiconductor memory device according to one or more embodiments. Hereinafter, descriptions redundant with Figures 14 to 21 will be omitted, and the description will focus on the differences.

[0147] Refer to Figure 23 , the sense amplifier controller 200 can control the timing of the second switch signal P2 and the third switch signal P3 such that in Figure 4Within the high temperature range RH, the bit line sense amplifier operates in the C-type read mode. The sense amplifier controller 200 may deactivate the third switch signal P3 during the charge sharing period CS, causing the sense bit line SBL and the complementary sense bit line SBLB to be electrically disconnected. In addition, the sense amplifier controller 200 may activate the second switch signal P2 in advance before the read period SEN, for example, at the time point tc during the charge sharing cycle CS, such that the bit line BL and the sense bit line SBL are electrically connected and the complementary bit line SBL and the complementary sense bit line SBLB are electrically connected.

[0148] In this way, in the C-type read mode CTP, the second switch signal P2 can be activated before the read period SEN to turn on the third switch transistor S3 and the fourth switch transistor S4, operating the bit line sense amplifier as a cross-coupled latch. In this C-type read mode CTP, characteristic degradation due to charge leakage from the internal nodes SBL and SBLB through the N-type sense amplifiers NM1 and NM2 can be prevented or reduced.

[0149] Figure 24 is a diagram illustrating the floating time in the D-type read mode of a semiconductor memory device according to one or more embodiments, and Figure 25 is a diagram illustrating the floating time in the C-type read mode of a semiconductor memory device according to one or more embodiments. Figure 24 and Figure 25 illustrates Figure 22 and Figure 23 each part of the charge sharing period CS and the read period SEN of the second switch signal P2 shown in the timing diagram.

[0150] Referring to Figure 24 and Figure 25 , the floating time tFLT can be defined as the time interval when the sense bit line SBL and the complementary sense bit line SBLB are floating during the charge sharing period CS and the read period SEN.

[0151] For example, as Figure 24 shown, in the D-type read mode DTP, the floating time tFLT can be defined as the time interval between the time point tb when the second switch signal P2 is deactivated after switching in the charge sharing period CS and the time point td when the second switch signal P2 is reactivated in the read period SEN.

[0152] For example, in the C-type read mode CTP, as Figure 25 shown, the floating time tFLT can be defined as the time interval between the start time point t3 of the charge sharing period CS and the time point tc when the second switch signal P2 is activated in the charge sharing period CS.

[0153] Figure 26 and Figure 27 is a diagram illustrating the floating time in a semiconductor memory device according to one or more embodiments.

[0154] Referring to Figure 24 、 Figure 25 、 Figure 26 and Figure 27 , the timing of a switching signal (such as the second switching signal P2) can be controlled such that the floating time tFLT when the sense bit line SBL and the complementary sense bit line SBLB are floating decreases as the operating temperature To increases.

[0155] In an embodiment, the sense amplifier controller 200 can further delay the time point tb at which the second switching signal P2 is deactivated after switching in the charge sharing period CS as the operating temperature To increases, such that in Figure 24 's D-type read mode DTP, the floating time tFLT decreases as the operating temperature To increases.

[0156] In an embodiment, the sense amplifier controller 200 can further advance the time point tc at which the second switching signal P2 is activated in the charge sharing period CS as the operating temperature To increases, such that in Figure 25 's C-type read mode CTP, the floating time tFLT decreases as the operating temperature To increases.

[0157] In an embodiment, as Figure 27 shown, the sense amplifier controller 200 can divide the operating temperature To into multiple temperature ranges RC, RR, and RH, and control the timing of multiple switching signals such that the floating time tFLT changes according to the multiple temperature ranges RC, RR, and RH. For example, as described in reference Figure 4 , the operating temperature To of the semiconductor memory device can be divided into a low temperature range RC between the lowest temperature TMIN and the first temperature T1, a normal temperature range RR between the first temperature T1 and the second temperature T2, and a high temperature range RH between the second temperature T2 and the highest temperature TMAX.

[0158] Figure 28 and Figure 29 is a diagram illustrating a stacked memory device according to one or more embodiments.

[0159] Referring to Figure 28, the semiconductor memory device 900 may include a first semiconductor integrated circuit layer LA1 (910) to a k-th semiconductor integrated circuit layer LAk (920), where the lowest first semiconductor integrated circuit layer LA1 is assumed to be an interface or control chip, and the other semiconductor integrated circuit layers LA2 to LAk are assumed to be slave chips including core memory chips. The slave chips may form a plurality of memory banks.

[0160] The first semiconductor integrated circuit layer LA1 to the k-th semiconductor integrated circuit layer LAk may transmit and receive signals between the layers through through-substrate vias TSV (e.g., through-silicon vias). The lowest first semiconductor integrated circuit layer LA1, which is an interface or control chip, may communicate with an external memory controller through a conductive structure formed on an external surface.

[0161] Each of the first semiconductor integrated circuit layer LA1 910 to the k-th semiconductor integrated circuit layer LAk 920 may include a memory region 921 and a peripheral circuit 922 for driving the memory region 921. For example, the peripheral circuit 922 may include a row driver for driving word lines of the memory, a column driver for driving bit lines of the memory, a data input-output circuit for controlling input-output of data, a command buffer for receiving commands from an external source and buffering the commands, and an address buffer for receiving addresses from an external source and buffering the addresses.

[0162] The first semiconductor integrated circuit layer LA1 910 may further include a control circuit. The control circuit may control access to the memory region 921 based on commands and address signals from the memory controller, and may generate control signals for accessing the memory region 921.

[0163] The first semiconductor integrated circuit layer LA1 910 may include a temperature measurement circuit and a sense amplifier controller according to one or more embodiments. As described above, the sense amplifier controller may control the operation timing of bit line sense amplifiers based on a temperature code indicating the operating temperature to reduce sense noise according to the operating temperature.

[0164] Figure 29 An example of a high bandwidth memory (HBM) device 1100 is shown. Refer to Figure 29 , the HBM 1100 may have a stack of a plurality of DRAM semiconductor dies 1120, 1130, 1140, and 1150. The stacked HBM may be optimized by multiple independent interfaces (i.e., channels). According to the HBM standard, each DRAM stack may support up to 8 channels. Figure 29Shows an example stack including four DRAM semiconductor dies 1120, 1130, 1140, and 1150, and each DRAM semiconductor die supports two channels CHANNEL0 and CHANNEL1.

[0165] Each channel provides access to an independent set of DRAM banks. Requests from one channel may not access data attached to another different channel. The channels are timed independently and do not require synchronization.

[0166] The HBM 1100 may also include an interface die 1110 or a logic die located at the bottom of the stacked structure to provide signal routing and other functions. Some functions of the DRAM semiconductor dies 1120, 1130, 1140, and 1150 may be implemented in the interface die 1110.

[0167] According to one or more embodiments, the high bandwidth memory 1100 may include the temperature measurement circuit and the sense amplifier controller as described above. The sense amplifier controller may control the operation timing of the bit line sense amplifiers based on a temperature code indicating the operating temperature to reduce the sense noise according to the operating temperature.

[0168] Figure 30 and Figure 31 is a diagram illustrating a package structure of a stacked memory device according to one or more embodiments.

[0169] Refer to Figure 30 , the storage device 1000a may be a memory package and may include a substrate or an interposer layer ITP and a stacked memory device stacked on the interposer layer ITP. The stacked memory device may include a logic semiconductor die LSD (or a buffer semiconductor die) and a plurality of memory semiconductor dies MSD1, …, MSD4.

[0170] Refer to Figure 31 , the storage device 1000b may be a memory package and may include a substrate BSUB and a stacked memory device stacked on the substrate BSUB. The stacked memory device may include a logic semiconductor die LSD and a plurality of memory semiconductor dies MSD1, …, MSD4.

[0171] Figure 30 Illustrates a structure in which the memory semiconductor dies MSD1, …, MSD4 other than the logic semiconductor die LSD are vertically stacked and the logic semiconductor die LSD is electrically connected to the memory semiconductor dies MSD1, …, MSD4 through the interposer layer ITP or the substrate. In contrast, Figure 31 Illustrates a structure in which the logic semiconductor die LSD is vertically stacked with the memory semiconductor dies MSD1, …, MSD4.

[0172] The logic semiconductor die LSD may include the temperature measurement circuit TMMS100 and the sense amplifier controller SACON 200 as described above. According to one or more embodiments, the temperature measurement circuit TMMS100 may be integrated into at least one of the memory semiconductor dies MSD1 to MSD4.

[0173] The temperature measurement circuit TMMS100 may measure the operating temperature of the stacked memory device and generate a temperature code corresponding to the operating temperature. Based on the temperature code, the sense amplifier controller SACON 200 may control the timing of a plurality of switch signals to reduce the read noise of the plurality of bit line sense amplifiers according to the operating temperature.

[0174] The substrate base BSUB may be the same as or include the interposer layer ITP. The substrate base BSUB may be a printed circuit board (PCB). External connection elements such as conductive bumps BMP may be formed on the lower surface of the substrate base BSUB, and internal connection elements such as conductive bumps may be formed on the upper surface of the substrate base BSUB. In one or more embodiments, the semiconductor die LSD and MSD1, …, MSD4 may be electrically connected through through-silicon vias. In other example embodiments, the semiconductor die LSD and MSD1, …, MSD4 may be electrically connected through bonding wires. In other example embodiments, the semiconductor die LSD and MSD1, …, MSD4 may be electrically connected through a combination of through-silicon vias and bonding wires. In Figure 31 example embodiments, the logic semiconductor die LSD may be electrically connected to the memory semiconductor dies MSD1, …, MSD4 through conductive line patterns formed in the interposer layer ITP. The stacked semiconductor dies LSD and MSD1, …, MSD4 may be encapsulated using a sealant such as resin RSN.

[0175] Figure 32 is a diagram illustrating a memory system according to one or more embodiments.

[0176] As Figure 32 illustrated, the memory system 70 may include a memory module 1200 and a memory controller 50. The memory module 1200 may include a module substrate and a plurality of memory chips 401a, 401b, 401c, 401d, 401e, 401f, 401g, 401h and a module sensor TSOD 1250 mounted on the module substrate. Figure 32 Illustrated is a non-limiting example of eight memory chips 401a, …, 401h, however, the number of memory chips included in the memory module 1200 may be determined in different ways.

[0177] Referring toFigure 32 , the storage module 1200 can be connected to the memory controller 50 via a data bus 1210 and a control bus 1220. The storage module 1200 can be inserted into a socket connector of a larger storage system or computing system. The electrical connectors (or pins) of the storage module 1200 can be connected to the electrical contacts of the socket connector. The electrical connectors connected to the electrical contacts and the buses 1210 and 1220 allow direct access to the memory buffer or buffer chips 1270 and allow indirect access to the memory chips 401a, …, 401h of the storage module 1200. The data bus 1210 can include signal lines (conductive wirings) to transmit data signals DQ and data strobe signals DQS, and the control bus 1220 includes at least one of command (CMD) lines and / or address (ADD) lines.

[0178] The data bus 1210 and the control bus 1220 are directly connected to the buffer chips 1270 via respective socket / pin and bus signal line arrangements. Further, the buffer chips 1270 are respectively connected to the memory chips 401a, …, 401h via at least one common connection first bus 1230, and via separately connected second buses 1240a, 1240b, 1240c, 1240d, 1240e, 1240f, 1240g, 1240h from designated ports of the buffer chips 1270 to corresponding ports of the memory chips 401a, …, 401h. The buffer chips 1270 can be used to transmit received commands and / or addresses received from the memory controller 50 via the control bus 1220 to the corresponding memory chips 401a, …, 401h via the first bus 1230.

[0179] The buffer chips 1270 can transmit write data DQ (i.e., data to be written to one or more of the memory chips 400a, …, 400h) and data strobe signals DQS received from the memory controller 50 via the data bus 1210 to the memory chips 401a, …, 401h via the respective second buses 1240a, …, 1240h. Alternatively, the buffer chips 1270 can transmit read data DQ (data obtained from one or more of the memory chips 401a, …, 401h) obtained from one or more of the memory chips 401a, …, 401h via the second buses 1240a, …, 1240h to the memory controller 50 via the data bus 1210.

[0180] Each of the memory chips 401a to 401h may include the temperature measurement circuit TMMS100 and the sense amplifier controller SACON 200 as described above. The temperature measurement circuit TMMS100 may measure the operating temperature of the stacked memory device and generate a temperature code corresponding to the operating temperature. Based on the temperature code, the sense amplifier controller SACON 200 may control the timing of a plurality of switch signals to reduce the read noise of the plurality of bit line sense amplifiers according to the operating temperature.

[0181] Figure 33 is a block diagram illustrating an example embodiment of a temperature measurement circuit included in a semiconductor memory device according to one or more embodiments, and Figure 34 is illustrative of Figure 33 a circuit diagram of an example embodiment of a temperature detector included in the temperature measurement circuit of Figure 33 and Figure 34 The temperature measurement circuits of

[0182] are merely examples, and the configuration of the temperature measurement circuit may be changed in various ways.

[0182] Referring to Figure 33 , the temperature measurement circuit 100 may include a temperature detector DET 110 and an analog-to-digital converter CNV 120. The temperature detector 110 may output at least one of a voltage signal VPTAT and a current signal IPTAT that is proportional to the operating temperature To. The analog-to-digital converter 120 may convert the output of the temperature detector 110 into a digital signal to generate a temperature code TCODE of multiple bits.

[0183] In one or more embodiments, the temperature detector 110 may be implemented using a first PMOS transistor M1 (with current I1), a second PMOS transistor M2 (with current I2), a feedback amplifier AMP, a resistor R, and a first bipolar transistor B1 and a second bipolar transistor B2 connected between a power supply voltage VDD and a ground voltage VSS as shown in Figure 34 . The voltage dVBE across the resistor R can be obtained by Equation 2.

[0184] Equation 2:

[0185] dVBE = VBE1 - VBE2

[0186] = VT * Ln(Ic1 / Is1) - VT * Ln(n * Ic2 / Is2)

[0187] = VT * Ln(n)

[0188] In Expression 2, Is1 and Is2 indicate the reverse saturation currents of bipolar transistors B1 and B2. Similarly, Ic1 and Ic2 indicate the currents flowing through bipolar transistors B1 and B2. Additionally, n is the gain ratio of bipolar transistors B1 and B2, and VT indicates the temperature voltage proportional to the absolute temperature of temperature detector 110. Ln(n) is a constant value, and thus the voltage dVBE across resistor R and the current I2 flowing through resistor R are proportional to the temperature change. Voltage signal VPTAT and current signal IPTAT can be generated as outputs based on the voltage dVBE and current I2 proportional to the operating temperature.

[0189] Reference Figure 33 and Figure 34 The on-chip temperature sensor described can be integrated in the same semiconductor die of a semiconductor memory device, and the on-chip temperature sensor is different from an external temperature sensor such as TSOD provided at a memory module. Using temperature measurement circuit 100, the operating temperature To of the semiconductor memory device can be accurately measured.

[0190] Figure 35 is a diagram illustrating a semiconductor package including a stacked memory device according to one or more embodiments.

[0191] Reference Figure 35 , semiconductor package 1700 may include one or more stacked memory devices 1710 and a graphics processing unit (GPU) 1720.

[0192] Stacked memory device 1710 and GPU 1720 may be mounted on an interposer 1730, and the interposer 1730 on which stacked memory device 1710 and GPU 1720 are mounted may be mounted on package substrate 1740. Package substrate 1740 is mounted on solder balls 1750. GPU 1720 may perform the same operations as the memory controller described above, or may include a memory controller. GPU 1720 may store data generated or used in graphics processing in stacked memory device 1710.

[0193] Stacked memory device 1710 may be implemented in various forms, and stacked memory device 1710 may be a memory device in the form of a high bandwidth memory (HBM) stacking multiple layers. Stacked memory device 1710 may include buffer dies and multiple memory dies.

[0194] Figure 36 is a block diagram illustrating a mobile system according to one or more embodiments.

[0195] Reference Figure 36, the mobile system 2000 may include an application processor (AP) 2100, a connection unit 2200, a volatile storage device (VM) 2300, a non-volatile storage device (NVM) 2400, a user interface 2500, and a power supply 2600. In one or more embodiments, the mobile system 2000 may be, for example, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, or another type of electronic device.

[0196] The application processor 2100 may run applications such as a web browser, a game application, a video player, etc. The connection unit 2200 may perform wired or wireless communication with an external device. The volatile storage device 2300 may store data processed by the application processor 2100 or may operate as a working memory. The non-volatile storage device 2400 may store a boot image for booting the mobile system 2000. The user interface 2500 may include at least one input device such as a keypad, a touch screen, etc., and at least one output device such as a speaker, a display device, etc.

[0197] The semiconductor storage device 2300 may include the temperature measurement circuit TMMS100 and the sense amplifier controller SACON 200 as described above. The temperature measurement circuit TMMS100 may measure the operating temperature of the semiconductor storage device 2300 and generate a temperature code corresponding to the operating temperature. Based on the temperature code, the sense amplifier controller SACON 200 may control the timing of a plurality of switch signals to reduce the read noise of a plurality of bit line sense amplifiers according to the operating temperature.

[0198] As described above, according to one or more embodiments of the semiconductor storage device and the method of controlling the semiconductor storage device, the effective read margin of the bit line sense amplifier can be increased by controlling the operation timing of the bit line sense amplifier to reduce the read noise according to the operating temperature, and the performance of the semiconductor storage device can be improved.

[0199] The embodiments described in this specification may be applicable to any storage device and a system including a storage device. For example, the embodiments may be applicable to systems such as a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a video camera, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a server system, an automotive device, etc.

[0200] The foregoing describes example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the present disclosure.

Claims

1. A semiconductor memory device, comprising: A memory cell array, the memory cell array comprising memory cells; a bit line sense amplifier having an open bit line structure and comprising a plurality of switch transistors, wherein the bit line sense amplifier is connected to the memory cell via a bit line and a complementary bit line, and the plurality of switch transistors are configured to control connections between the bit line, the complementary bit line, a sense bit line, and a complementary sense bit line based on a plurality of switch signals; a temperature measurement circuit configured to measure an operating temperature of the semiconductor memory device and generate a temperature code corresponding to the operating temperature; and A sense amplifier controller is configured to reduce a sense noise of the bit line sense amplifier by controlling a timing of the plurality of switching signals based on the temperature code.

2. The semiconductor memory device according to claim 1, wherein: The sense amplifier controller is further configured to control the bit line sense amplifier to operate in a sense mode among a plurality of sense modes by controlling the timings of the plurality of switch signals based on a temperature range within which the operating temperature falls.

3. The semiconductor memory device according to claim 1, wherein: The sense amplifier controller is further configured to control the timing of the plurality of switch signals so that a floating time during which the sense bit line and the complementary sense bit line are floated decreases as the operating temperature increases.

4. The semiconductor memory device according to claim 3, wherein: The sense amplifier controller is further configured to control the timing of the plurality of switch signals so that the floating time changes based on a temperature range within which the operating temperature falls among a plurality of temperature ranges.

5. The semiconductor memory device according to claim 1, wherein The plurality of switch transistors include: a first switch transistor configured to control a connection between the bit line and the complementary read bit line based on a first switch signal; a second switch transistor configured to control a connection between the complementary bit line and the readout bit line based on the first switch signal; a third switch transistor configured to control a connection between the bit line and the readout bit line based on a second switch signal; a fourth switch transistor configured to control a connection between the complementary bit line and the complementary readout bit line based on the second switch signal; and A fifth switch transistor is configured to control the connection between the read bit line and the complementary read bit line based on a third switch signal.

6. The semiconductor memory device according to claim 5, in, The operating temperature falls within a temperature range of a plurality of temperature ranges, the plurality of temperature ranges comprising a normal temperature range, a high temperature range higher than the normal temperature range, and a low temperature range lower than the normal temperature range, and The sense amplifier controller is further configured to: control the timing of the second switch signal and the third switch signal based on the temperature range, so that the bit line sense amplifier operates in a sense mode among multiple sense modes.

7. The semiconductor memory device according to claim 6, wherein: The sense amplifier controller is further configured to: based on the temperature range being the normal temperature range, enable the bit line sense amplifier to operate in the H-type sense mode by the following operations: During a charge sharing period, connecting the sense bit line and the complementary sense bit line by activating the third switch signal; and During a readout period after the charge sharing period, the bit line and the readout bit line are connected and the complementary bit line and the complementary readout bit line are connected by activating the second switch signal after the third switch signal is deactivated.

8. The semiconductor memory device according to claim 6, wherein: The sense amplifier controller is further configured to: based on the temperature range being the low temperature range, operate the bit line sense amplifier in the D-type sense mode by: During a charge sharing period, disconnecting the sense bit line and the complementary sense bit line by deactivating the third switch signal; During the charge sharing period, the bit line and the read bit line are temporarily connected, and the complementary bit line and the complementary read bit line are temporarily connected by switching the second switch signal between an activated state and a deactivated state; as well as During a readout period after the charge sharing period, the bit line and the readout bit line are connected and the complementary bit line and the complementary readout bit line are connected by activating the second switch signal.

9. The semiconductor memory device according to claim 6, wherein: The sense amplifier controller is further configured to: based on the temperature range being the high temperature range, enable the bit line sense amplifier to operate in the C-type sense mode by the following operations: During a charge sharing period, disconnecting the sense bit line and the complementary sense bit line by deactivating the third switch signal; During the charge sharing period, the bit line and the read bit line are temporarily connected, and the complementary bit line and the complementary read bit line are temporarily connected by switching the second switch signal; as well as The bit line and the read bit line are connected, and the complementary bit line and the complementary read bit line are connected by activating the second switch signal before the read period after the charge sharing period.

10. The semiconductor memory device according to claim 6, wherein: The read-out amplifier controller is further configured to: control the timing of the second switch signal and the third switch signal based on the temperature range being the low temperature range so that the bit line read-out amplifier operates in a D-type read-out mode; control the timing of the second switch signal and the third switch signal based on the temperature range being the high temperature range so that the bit line read-out amplifier operates in a C-type read-out mode; and control the timing of the second switch signal and the third switch signal based on the temperature range being the normal temperature range so that the bit line read-out amplifier operates in an H-type read-out mode.

11. The semiconductor memory device according to claim 5, wherein: The sense amplifier controller is further configured to operate the bit line sense amplifier in the D-type sense mode by: During a charge sharing period, disconnecting the sense bit line and the complementary sense bit line by deactivating the third switch signal; During the charge sharing period, the bit line and the read bit line are temporarily connected, and the complementary bit line and the complementary read bit line are temporarily connected by switching the second switch signal; During a readout period after the charge sharing period, the bit line and the readout bit line are connected, and the complementary bit line and the complementary readout bit line are connected by activating the second switch signal; and Based on the increase in the operating temperature, by delaying a time point at which the second switch signal is deactivated after switching of the second switch signal, the floating time during which the sense bit line and the complementary sense bit line are floated is reduced.

12. The semiconductor memory device according to claim 5, wherein: The sense amplifier controller is further configured to operate the bit line sense amplifier in the C-type sense mode by: During a charge sharing period, disconnecting the sense bit line and the complementary sense bit line by deactivating the third switch signal; After the charge sharing period starts and before the read period, the bit line is connected to the read bit line and the complementary bit line is connected to the complementary read bit line by activating the second switch signal; and Based on the increase in the operating temperature, the floating time during which the read bit line and the complementary read bit line are floated is reduced by adjusting the time point at which the second switch signal is activated to an earlier time point in the charge sharing period.

13. The semiconductor memory device according to claim 1, wherein: The bit line sense amplifier comprises: a first P-type transistor connected between the control line and the complementary read bit line, the first P-type transistor including a gate electrode connected to the read bit line; a second P-type transistor connected between the control line and the read bit line, the second P-type transistor including a gate electrode connected to the complementary read bit line; a first N-type transistor connected between a complementary control line and the complementary read bit line, the first N-type transistor including a gate electrode connected to the bit line; and A second N-type transistor is connected between the complementary control line and the readout bit line, the second N-type transistor including a gate electrode connected to the complementary bit line.

14. A semiconductor memory device, comprising: A memory cell array, the memory cell array comprising memory cells; a bit line sense amplifier, the bit line sense amplifier having an open bit line structure, wherein the bit line sense amplifier is connected to the memory cell via a bit line and a complementary bit line, the bit line sense amplifier comprising: a first switch transistor, the first switch transistor being configured to control a connection between the bit line and the complementary sense bit line based on a first switch signal; a second switch transistor, the second switch transistor being configured to control a connection between the complementary bit line and the sense bit line based on the first switch signal; a third switch transistor, the third switch transistor being configured to control a connection between the bit line and the sense bit line based on a second switch signal; a fourth switch transistor, the fourth switch transistor being configured to control a connection between the complementary bit line and the complementary sense bit line based on the second switch signal; and a fifth switch transistor, the fifth switch transistor being configured to control a connection between the sense bit line and the complementary sense bit line based on the third switch signal; a temperature measurement circuit configured to measure an operating temperature of the semiconductor memory device and generate a temperature code corresponding to the operating temperature; and A sense amplifier controller is configured to reduce a sense noise of the bit line sense amplifier by controlling a timing of the first switching signal, the second switching signal, and the third switching signal based on the operating temperature.

15. The semiconductor memory device according to claim 14, wherein: The sense amplifier controller is further configured to control the bit line sense amplifier to operate in a sense mode among multiple sense modes by controlling the timing of the first switch signal, the second switch signal, and the third switch signal based on a temperature range into which the operating temperature falls among multiple temperature ranges.

16. The semiconductor memory device according to claim 14, wherein: The sense amplifier controller is further configured to control the timing of the first switch signal, the second switch signal, and the third switch signal so that a floating time during which the sense bit line and the complementary sense bit line float decreases as the operating temperature increases.

17. A method for controlling a semiconductor memory device, the method comprising: Providing a bit line sense amplifier having an open bit line structure and comprising a plurality of switch transistors, wherein the bit line sense amplifier is connected to a memory cell via a bit line and a complementary bit line, and wherein the plurality of switch transistors are configured to control connections between the bit line, the complementary bit line, a sense bit line, and a complementary sense bit line based on a plurality of switch signals; measuring an operating temperature of the semiconductor memory device to generate a temperature code corresponding to the operating temperature; and Based on the temperature code, timing of the plurality of switching signals is controlled to reduce read noise of the bit line sense amplifier.

18. The method according to claim 17, wherein: Controlling the timing of the plurality of switch signals comprises: The bit line sense amplifier is controlled to operate in a sense mode among a plurality of sense modes by controlling the timings of the plurality of switch signals based on a temperature range within which the operating temperature falls among a plurality of temperature ranges.

19. The method according to claim 17, wherein: Controlling the timing of the plurality of switch signals comprises: The timing of the plurality of switch signals is controlled so that the floating time of the floating of the sense bit line and the complementary sense bit line decreases as the operating temperature increases.

20. The method according to claim 17, further comprising: performing a precharge operation, the precharge operation comprising charging the bit line, the complementary bit line, the sense bit line, and the complementary sense bit line using a precharge voltage; performing a first offset compensation operation, the first offset compensation operation comprising: connecting the bit line and the complementary sense bit line; connecting the complementary bit line and the sense bit line; applying a first internal voltage higher than the precharge voltage to a P-type sense amplifier of the bit line sense amplifier; and applying a second internal voltage lower than the precharge voltage to an N-type sense amplifier of the bit line sense amplifier; and A second offset compensation operation is performed, the second offset compensation operation including: applying the precharge voltage to the P-type sense amplifier; and applying the second internal voltage to the N-type sense amplifier.

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