A NAND flash memory, storage device and electronic device

Abstract

A NAND flash memory, a memory and an electronic device. The NAND flash memory reads data of multiple pages at the same time on the same surface, and makes the saturation current of each page different and / or the time of reading data of each page different, so that the data recorded by each page is different, the total current of the reading circuit is different, and the speed of voltage drop of the discharge capacitor C SO is different. When the NAND flash memory reads data of multiple pages, the relationship between the voltage of the discharge capacitor C SO and the comparison voltage is detected by using a voltage comparison unit, so that the data recorded by each page is accurately read, and confusion between the read data and the pages is avoided.

Description

Technical Field

[0001] This invention relates to the field of memory chip technology, and more particularly to a NAND flash memory, a memory, and an electronic device. Background Technology

[0002] NAND flash memory is a non-volatile storage device that uses NAND gate circuits to store data. NAND flash memory has advantages such as high storage density, fast data read and write speed, low power consumption, and long lifespan, and can be widely used in various electronic devices, such as solid-state disks (SSDs), universal serial bus (USB) flash drives, memory cards, and mobile devices.

[0003] Data reading and writing are the most typical scenarios in NAND flash memory applications. Among them, data reading (read operation) is the most important user scenario, so improving the read performance and power consumption of NAND memory is of great significance. The read operation of NAND memory can be divided into a pre-charge process, an evaluation process, and a discharge process. The latency of each process is continuously reduced with the improvement of manufacturers' process technology, circuit design, and manufacturing capabilities until it reaches an extreme value. As the media of NAND memory is iterated and updated, the reduction of read latency gradually slows down, causing NAND memory to be unable to meet the requirements of future storage scenarios for low power consumption and high performance. Summary of the Invention

[0004] To address the aforementioned problems, embodiments of this application provide a NAND flash memory, a memory, and an electronic device. When simultaneously reading data from multiple pages on the same plane, ensuring that the saturation current of each page is different and / or the data reading time for each page is different allows for accurate reading of the data recorded on each page, avoiding confusion between read data and pages. Furthermore, this application also provides a memory and an electronic device corresponding to this NAND flash memory.

[0005] Therefore, the following technical solutions are adopted in the embodiments of this application:

[0006] In a first aspect, this application provides a NAND flash memory, comprising: a voltage control unit including a plurality of first output ports and a plurality of second output ports, wherein the plurality of first output ports are all used to output a first electrical signal, and the plurality of second output ports are all used to output a second electrical signal; a NAND array including a plurality of sub-blocks, each sub-block including a plurality of pages, the plurality of pages being electrically connected to the plurality of first output ports respectively, for reading or writing data when receiving the first electrical signal; an asynchronous unit electrically connected between the plurality of first output ports and the plurality of sub-blocks, or electrically connected to the gate of a sub-block select transistor in the plurality of pages of the plurality of sub-blocks and the gate of a dual-gate MOS transistor in the plurality of pages of the plurality of sub-blocks, for making the saturation current of the target dual-gate MOS transistors of the simultaneous reading of multiple pages different, and / or making the conduction time of each page of the simultaneous reading of multiple pages different; and a plurality of discharge capacitors C. SO The first terminals of the plurality of discharge capacitors are electrically connected to the plurality of second output ports, and the second terminals of the plurality of discharge capacitors are grounded; the voltage comparison unit includes a plurality of input ports, which are electrically connected to the plurality of second output ports, for comparing the magnitude of the voltage received by the plurality of input ports with the comparison voltage, and outputting the comparison result.

[0007] In this implementation, the NAND memory reads data from multiple pages simultaneously on the same side, which can make the saturation current of each page different and / or the time for reading data from each page different. This results in different data recorded on each page, different total current in the read circuit, and thus different discharge capacitor C. SO The voltage drops at different rates. When NAND flash memory reads data from multiple pages, a voltage comparison unit can be used to detect the discharge capacitor C. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page.

[0008] In one embodiment, the discharge capacitor is in a discharging state when the data recorded by the target dual-gate MOS transistor on the page it is electrically connected to is "1"; the discharge capacitor is in a charging state when the data recorded by the target dual-gate MOS transistor on the page it is electrically connected to is "0".

[0009] In this embodiment, when the data recorded by the target dual-gate MOSFET is "1", the circuit containing the target dual-gate MOSFET and the discharge capacitor is turned on, allowing the discharge capacitor to discharge and thus lowering its voltage. When the data recorded by the target dual-gate MOSFET is "0", the circuit containing the target dual-gate MOSFET and the discharge capacitor is turned off, allowing the discharge capacitor to charge and thus maintaining its voltage. The voltage comparison unit can accurately read the data recorded on each page based on the voltage of multiple discharge capacitors at different times, avoiding confusion between the read data and the page data.

[0010] In one embodiment, the voltage comparison unit is specifically used to compare the voltage received at the plurality of input ports at multiple latch time points with the magnitude of the comparison voltage to obtain multiple sub-output results; the NAND flash memory further includes: a decoding unit, used to compare the multiple sub-output results with a preset result to determine whether the data recorded by the target dual-gate MOS transistors of each page of the simultaneous reading of multiple pages is "0" or "1"; the preset result records that the sub-output results at different latch time points correspond to the data recorded by the multiple target dual-gate MOS transistors read simultaneously.

[0011] In this embodiment, because the saturation currents of the target dual-gate MOS transistors reading multiple pages simultaneously are different, or the time for reading the data of each page is different, the voltages of the multiple discharge capacitors in the voltage comparison unit are different at different times. The decoding unit can compare the data recorded by each target dual-gate MOS transistor corresponding to the voltages of the multiple discharge capacitors at different times according to its own pre-stored table, thereby accurately reading the data recorded in each page and avoiding confusion between the read data and the page.

[0012] In one implementation, the relationship between the number M of the plurality of latching time points and the number N of pages read simultaneously is: M ≥ (2 N -1); M and N are positive integers greater than or equal to 2.

[0013] In this embodiment, the number M of latching time points set in the voltage comparison unit shall not be less than (2 N -1) to avoid insufficient latch time, which would prevent the inability to distinguish the voltages of multiple discharge capacitors when the data recorded by the target dual-gate MOS transistor is not the same when multiple pages are read simultaneously.

[0014] In one implementation, there is at least one latching time point between different discharge durations; the discharge duration refers to the time it takes for the voltage of the discharge capacitor electrically connected to the target dual-gate MOS transistor of multiple pages read simultaneously to drop to the comparison voltage.

[0015] In one implementation, when the conduction times of the various pages being read simultaneously are different, the time difference between the conduction times of two adjacent pages is less than or equal to the duration during which the voltage of the discharge capacitor drops to the comparison voltage.

[0016] In this implementation, when the time for reading data from each page is different, the asynchronous unit ensures that the delay time is less than or equal to the time it takes for the voltage of the discharge capacitor to drop to the comparison voltage, thus avoiding completely asynchronous reading of the two pages.

[0017] In one embodiment, the voltage control unit is further configured to electrically connect the plurality of first output ports to the plurality of second output ports respectively when the output of the first electrical signal and the second electrical signal is stopped.

[0018] In this embodiment, after the voltage control unit stops outputting the first and second electrical signals, each first output port can be electrically connected to a second output port to form a reading circuit, allowing the discharge capacitor C to... SO Discharge is used to read data.

[0019] In one embodiment, the voltage control unit is further configured to convert the current at the second output port from a first value to a second value.

[0020] In this embodiment, after the voltage control unit is electrically connected to the multiple first output ports and the multiple second output ports respectively, it can change the current value of the second output ports to reduce the current flowing into the NAND array 420 and thus protect the NAND array.

[0021] Secondly, this application provides a memory comprising: a circuit board, at least one NAND flash memory as may be implemented in the first aspect, the NAND flash memory being fixed and electrically connected to the circuit board for storing data.

[0022] Thirdly, an electronic device is provided in the embodiments of this application, including: at least one memory as may be implemented as in the second aspect, at least one processor, the processor being electrically connected to the at least one memory for writing data to the at least one memory and / or reading data from the at least one memory. Attached Figure Description

[0023] The accompanying drawings used in the description of the embodiments or prior art are briefly introduced below.

[0024] Figure 1 This is a schematic diagram of the structure of a dual-gate MOS transistor in a NAND memory module in the related technology.

[0025] Figure 2This is a schematic diagram of the structure of a NAND memory in related technologies;

[0026] Figure 3 A schematic diagram illustrating the path for reading data from page 1 of sub-block 0 of NAND memory in related technologies;

[0027] Figure 4 This is a schematic diagram of the structure of the first type of NAND memory provided in the embodiments of this application;

[0028] Figure 5 The discharge capacitor C in the reading circuit provided in this application embodiment SO A schematic diagram showing the relationship between the rate of voltage drop and the current;

[0029] Figure 6 This is a schematic diagram of the structure of the second type of NAND memory provided in the embodiments of this application;

[0030] Figure 7 The discharge capacitor C in the reading circuit provided in this application embodiment SO A schematic diagram showing the relationship between the rate of voltage drop and the current;

[0031] Figure 8 This is a schematic diagram of the structure of the third type of NAND memory provided in the embodiments of this application. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0033] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0034] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0035] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0036] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0037] NAND flash memory employs a dual-gate transistor design. A traditional metal-oxide-semiconductor field-effect transistor (MOSFET) consists of a source, drain, gate, and base. The memory cell within a NAND flash memory adds a floating gate within the insulating layer of a traditional MOSFET to store charge. By applying a large voltage difference between the gate and base, electrons or holes can be injected into the floating gate, enabling write and erase operations. The amount of stored charge changes the transistor's threshold voltage V. TH Different threshold voltages V TH Each memory cell stores one or more bits of data, representing different information states. When the voltage applied to the gate exceeds the threshold voltage V... TH When the voltage difference between the source and drain is low, the channel will invert. If a voltage difference exists between the source and drain at this time, a current path will be formed. Conversely, no current path will be formed. Based on this, the threshold voltage V of the transistor can be determined. TH The size can be used to read the stored data.

[0038] Figure 1 This is a schematic diagram of a dual-gate MOS transistor structure for NAND memory in related technologies. Figure 1 As shown, NAND memory can change the threshold voltage V of a dual-gate MOSFET by utilizing the amount of charge stored on the floating gate. TH NAND memory has a read voltage V applied to its gate. read Then, if the voltage V is read... read The threshold voltage V formed by the charge in the floating gate is greater than TH When this occurs, it will trigger a controllable transconductance effect in the dual-gate MOSFET, causing the channel between the source and drain to conduct, allowing current to flow through the channel. When the read voltage V... read Greater than the threshold voltage V TH When the dual-gate MOS transistor of the memory cell is in the ON state, it indicates that the data recorded in the memory cell is "1". Conversely, when the read voltage V... read Less than the threshold voltage V TH When the dual-gate MOS transistor of the memory cell is in the off state, it indicates that the data recorded in the memory cell is "0".

[0039] In NAND memory, read operations are performed at the "page" level. A page typically contains multiple storage cells. When performing a read operation, NAND memory first selects the word line (WL) of the target page and connects the WL to the source output (SO) node via a bit line (BL).

[0040] like Figure 2 As shown, the NAND memory includes a read circuit, and the voltage control unit of the read circuit applies a suitable read voltage V at BL. read When a voltage is applied to BL, the charge state of the memory cell affects the voltage on BL. If the charge state of the memory cell forms a threshold voltage V... TH Greater than the read voltage V on BL read At that time, the read voltage V on BL read It will change. The reading circuit is based on the reading voltage V on BL. read The NAND memory detects changes in the discharge capacitor C, amplifies and encodes these changes, and outputs data information in a detected manner. SO The voltage changes allow for rapid reading and transmission of data from the storage unit.

[0041] The process of reading a single page from NAND memory can be divided into a precharge phase, an evaluation phase, and a discharge phase.

[0042] During the pre-charging process, the voltage control unit charges WL and BL, causing the discharge capacitor C at the BL and SO nodes to discharge. SO The voltage formed is V BL and V SO And V BL <V SO .

[0043] During the evaluation process, due to the discharge capacitance C at the SO node... SO voltage V SO Voltage V greater than BL BL If the memory cell is in the ON state (data is "1"), the discharge capacitor C SO It will discharge, and discharge to the discharge capacitor C. SO voltage V SO Less than the comparison voltage V THSA If the memory cell is in the off state (data is "0"), the discharge capacitor C... SO It will not discharge; the discharge capacitor C SO voltage V SOIt will always be greater than the comparison voltage V. THSA The voltage comparison unit inside the NAND memory can acquire the discharge capacitor C at the SO node at a "latch" time point. SO voltage V SO And through voltage V SO Comparison voltage V THSA The voltage comparison unit determines whether the read data is "1" or "0" by comparing the values ​​between the two values. The voltage comparison unit saves the read data and stores it in the data buffer area.

[0044] During the discharge process, the voltage control unit discharges WL and BL to complete the reading operation.

[0045] On the same plane, reading data from multiple pages of NAND memory requires sequential execution. For example... Figure 3 As shown, taking reading data from page 1 of sub-block (string) 0 as an example, when the NAND memory needs to read the target memory cell, the row address decoder processes the voltage output from the boost and control circuits and applies it to each WL. The sub-block select transistor is turned on by applying a positive voltage Vpass, allowing BL to access the memory cell under sub-block 0. At the same time, other non-selected sub-block select transistors are set to a low voltage (e.g., 0V) to prevent them from turning on and interfering with the reading result.

[0046] The target memory cell is located at the WL2 voltage, which is then applied with a read voltage V. read Then, the memory cell on WL2 can be activated and selected for reading. The gates of other memory cells are set to a high voltage V. pass This causes the transistors connected in series on other sub-blocks to conduct, ensuring that the conduction state of the entire sub-block is determined by the conduction state of the read memory cell. If the data written to the target memory cell is "0", it indicates that the threshold voltage V of the target memory cell has been reached. TH Greater than the reading voltage V read The target memory cell is in a turned-off state, and the memory cell string has virtually no current flowing through it. If the target memory cell is written with data "1", it indicates that the threshold voltage V of the target memory cell is... TH Greater than the reading voltage V read The target memory cell is in the ON state, and a current flows through the memory cell in series. Let the current be I. cell After the NAND memory completes reading page 1, it discharges the WL and BL. If the NAND memory needs to read a page on sub-block 1, the above process is repeated, only requiring the sub-block select transistor 0 to be turned off and the sub-block select transistor 1 to be turned on.

[0047] When performing a read operation on NAND memory, different faces and different logical unit numbers (LUNs) can be operated independently. This means that multiple faces and multiple LUNs can be read simultaneously within a single NAND memory chip. Within the same face, different pages can be read serially. Serial reading means reading pages one by one in sequence, rather than reading multiple pages simultaneously. When reading a page, NAND memory needs to recharge and discharge the BL (Block Buffer) to read the data. However, this repeated charging and discharging process limits read performance and increases read power consumption. If two sub-blocks are opened simultaneously, the current flowing through the two sub-blocks is approximately the same, and the voltage V of node SO... SO If the downward slopes are nearly identical, there may be two cases, "01" and "10", that cannot be distinguished, leading to confusion between the read data and the page.

[0048] To address the shortcomings of related technologies, this application provides a novel NAND memory, storage device, and electronic device. To improve data read speed, an asynchronous unit can be added to the NAND memory. This asynchronous unit allows for different saturation currents and different data read times for each page. When the NAND memory simultaneously reads data from multiple pages on the same side, the different saturation currents and / or different data read times for each page result in different data recorded on each page, leading to different total currents in the read circuit and affecting the discharge capacitor C. SO The voltage drops at different rates. When NAND flash memory reads data from multiple pages, a voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page. The asynchronous unit below can also be called "current limiting unit", "time control unit" and "current limiting and time control unit" depending on its function.

[0049] Figure 4 This is a schematic diagram of the structure of the first type of NAND memory provided in the embodiments of this application. Figure 4 As shown, the NAND memory 400 includes a read circuit 410, a NAND array 420, and a current limiting unit 430. The CMOS circuit 410 includes a voltage control unit 411, a voltage comparison unit 412, a data cache unit 413, a decoding unit 414, and multiple discharge capacitors C. SO The NAND array 420 comprises multiple sub-blocks.

[0050] The voltage control unit 411 includes multiple first output ports and multiple second output ports. The multiple first output ports are respectively connected to various sub-blocks of the NAND array 420 via lines, with the lines between the voltage control unit 411 and the multiple sub-blocks designated as "BL". Each sub-block includes multiple sub-block select transistors, the drain of each sub-block select transistor is connected to one BL, and the source of each sub-block select transistor is connected in series with multiple dual-gate MOS transistors of the memory cells. The gate of each memory cell's dual-gate MOS transistor is connected to an external read unit via a line, with the lines between the gate of each memory cell's dual-gate MOS transistor and the external read unit designated as "WL".

[0051] Multiple second output ports of the voltage control unit 411 are respectively connected to multiple input ports of the voltage comparison unit 412. Multiple discharge capacitors C SO One end of each capacitor is connected to the line between the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412, and multiple discharge capacitors C SO The other end is grounded. Let the discharge capacitor C... SO The node of the line connecting the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412 is the SO node.

[0052] The voltage control unit 411 is used to convert the electrical energy supplied by the power source into a suitable voltage and to finely regulate the voltage applied to WL, such as reading the voltage V. read Through voltage V pass etc., for BL, WL and discharge capacitor C SO Provide voltage. During the data reading process of the NAND memory 400, the voltage control unit 411 supplies voltage to the discharge capacitor C during the pre-charge phase. SO It can charge and control the voltage of SO nodes, and can stop power supply during the evaluation phase, and connect the line where an SO node is located to a BL to form a read loop, and can clamp the voltage of the SO node to prevent it from being too low.

[0053] In this embodiment, the voltage control unit 411 applies a voltage VBL to each BL of the NAND array 420, and applies a voltage VSO to each input port of the voltage comparison unit 412 of the read circuit 410, where VSO > VBL. After the multiple first output ports are electrically connected to the multiple second output ports, the voltage control unit 411 can change the current value of the second output ports, converting the current of the second output ports from a first value to a second value. The voltage control unit 411 changes the discharge capacitor C. SO The discharge current is reduced, thereby reducing the current flowing into the NAND array 420 and protecting the NAND array 420.

[0054] The read circuit 410 may further include a read unit, which parses the input address signal to determine the index, page, block, or other location information of the target memory cell to be operated on. The read unit transmits the parsed location information to the NAND array 420, causing the sub-block select transistor inside the corresponding sub-block in the NAND array 420 to conduct, thus enabling the circuit containing the target memory cell to conduct. Additionally, the address decoding unit 413 is also used to generate appropriate operation signals based on the parsed location information and the selection result of the target memory cell, to control the charging, discharging, erasing, or other related operations of the target memory cell.

[0055] In this embodiment of the application, when the NAND array 420 performs read operations on more than one sub-block managed memory cell at the same time, the read cell can simultaneously parse more than one input address information and transmit more than one parsed location to the NAND array 420 to control the selection gate of more than one target memory cell.

[0056] The current limiting unit 430 can be configured between each BL and each sub-block, or within each sub-block, on the gate of the sub-block select transistor and the gate of the dual-gate MOS transistor of each memory cell. It is used to limit the saturation current of each page by adjusting the gate voltage, threshold voltage, series resistance, and equivalent resistance of the dual-gate MOS transistor of each page's memory cell, thus ensuring that the saturation current of each page is different. The saturation current refers to the current of the dual-gate MOS transistor of each memory cell in the page, the sub-block select transistor of the page, the BL, and the discharge capacitor C. SO The current in the circuit being read.

[0057] Taking the simultaneous reading of data from two pages of NAND flash memory 400 as an example, let the two pages be page 0 and page 1. Assume that the memory cell of page 0 is connected to sub-block select transistors 0 and BL0, and the memory cell of page 1 is connected to sub-block select transistors 1 and BL1, and the saturation current I of the dual-gate MOSFET of the memory cell of page 0 is... cell0 The saturation current I of the dual-gate MOSFET in memory cells larger than page 1 cell1 .

[0058] During the evaluation process, if the data in the memory cell of page 0 is "1" and the data in the memory cell of page 1 is "1", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 And the dual-gate MOS transistor in the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell1 Therefore, the total current in the reading circuit when the data is "11" is I.cell0 +I cell1 .

[0059] If the data in the memory cell of page 0 is "1" and the data in the memory cell of page 1 is "0", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 Furthermore, the dual-gate MOS transistor in the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "10" is I. cell0 .

[0060] If the data in the memory cell of page 0 is "0" and the data in the memory cell of page 1 is "1", the dual-gate MOSFET in the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Conversely, the dual-gate MOSFET in the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell1 Therefore, the total current in the reading circuit when the data is "01" is I. cell1 .

[0061] If the data in the memory cell of page 0 is "0" and the data in the memory cell of page 1 is "0", the dual-gate MOSFET in the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Similarly, the dual-gate MOSFET in the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, the total current in the read circuit when the data is "00" is 0.

[0062] In this embodiment, the total current in the reading circuit is different, and the discharge capacitor C... SO The voltage from voltage V SO Drop to comparison voltage V THSA The slopes are not the same. For example, Figure 5 As shown, the total current in the reading circuit is I. cell0 +I cell1 I cell0 I cell1 There are four cases: 0, 1, and 0. When the data is "11", the total current in the reading circuit is I. cell0 +I cell1 Discharge capacitor C SO The voltage drop rate is the fastest and the slope is the steepest. This is due to the saturation current I... cell0 Greater than the saturation current I cell1 Therefore, the discharge capacitor C when the data is "10" is...SO The voltage drop rate is greater than that of the discharge capacitor C when the data is "01". SO The rate of voltage drop, i.e., the discharge capacitance C when the data is "10". SO The slope of the voltage change is greater than that of the discharge capacitor C when the data is "01". SO The slope of the voltage change. When the data is "00", the total current in the reading circuit is 0, and the discharge capacitor C... SO The voltage remains constant.

[0063] Voltage comparator unit 412 is used to receive discharge capacitor C SO Discharge capacitor voltage V SO And compare the discharge capacitor voltage V SO Comparison voltage V THSA The size between them. In this embodiment, the voltage comparison unit 412 can be set with M latch time points. The relationship between the number of multiple latch time points M and the number of pages read simultaneously N is: M ≥ (2 N -1); M and N are positive integers greater than or equal to 2.

[0064] NAND flash memory can be classified into single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) based on the number of bits stored in the storage cell.

[0065] SLC is a type of flash memory where each storage cell can only store one bit (0 or 1). When reading data from a page using SLC, a read voltage V is applied to the storage cell. read Therefore, the relationship between the number of latching time points M set in the voltage comparison unit 412 and the number of pages read simultaneously N is: M ≥ (2 N -1).

[0066] Each memory cell in an MLC can store multiple bits, typically 2 bits. When an MLC reads a page of data, it applies a read voltage V1 to the memory cell. read Therefore, the relationship between the number of latching time points M set in the voltage comparison unit 412 and the number of pages read simultaneously N is: M ≥ (2 N -1)×X1. Where X1 is 1 or 2. The value of X1 depends on the type of page being read.

[0067] Each memory cell of a TLC can store more bits, typically 3 bits. When a TLC reads a page of data, a read voltage V of X2 is applied to the memory cell.read Therefore, the relationship between the number of latching time points M set in the voltage comparison unit 412 and the number of pages read simultaneously N is: M ≥ (2 N -1)×X2. Where X2 is 1, 2, 3 or 4. The value of X2 depends on the type of page being read.

[0068] Each cell in a QLC can store more bits, typically 4 bits. When a QLC reads a page of data, a read voltage V of X3 is applied to the cell. read Therefore, the relationship between the number of latching time points M set in the voltage comparison unit 412 and the number of pages read simultaneously N is: M ≥ (2 N -1)×X3. Where X3 is 1, 2, 3, 4, 5, 6, 7 or 8. The value of X3 is related to the type of page being read.

[0069] Voltage comparator 412 is used to compare the voltage V of node SO within a specific time period. SO and a specific comparison voltage V THSA The comparison is performed, and the results are digitized and latched. In this embodiment, the voltage comparison unit 412 can detect the comparison result at each latch time point and input the comparison result into the data buffer unit 413. In one case, the voltage comparison unit 412 determines the discharge capacitor voltage V at a latch time point. SO Greater than the comparison voltage V THSA In the first case, the output is "fail". In the second case, the voltage comparison unit 412 determines the voltage V of the discharge capacitor at a latch time point. SO Equal to or less than the comparison voltage V THSA When the time comes, output "pass".

[0070] There is at least one latch time point between different discharge durations. Discharge duration refers to the time it takes for the voltage of the discharge capacitor electrically connected to the target dual-gate MOS transistor, which is simultaneously reading multiple pages, to drop to the comparison voltage. Preferably, the first latch time point among the M latch time points can be set to the discharge capacitor C when the data is "11". SO The voltage drops to the comparison voltage V THSA The time point. The Mth latch time point among the M latch time points can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA The time points. The 2nd to N-1th latch time points out of the M latch time points are between the first latch time point and the Mth latch time point.

[0071] like Figure 5As shown, the voltage comparison unit 412 is configured with three latch time points. The first latch time point can be set to the discharge capacitor C when the data is "11". SO The voltage drops to the comparison voltage V THSA The second latch time point can be set to the discharge capacitor C when the data is "10". SO The voltage drops to the comparison voltage V THSA The third latch time point can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA The point in time.

[0072] The output results of voltage comparator unit 412 are shown in Table 1. When the data is "11", voltage comparator unit 412 outputs "pass" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "10", voltage comparator unit 412 outputs "fail" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "01", voltage comparator unit 412 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "pass" at the third latch time point. When the data is "00", voltage comparator unit 412 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "fail" at the third latch time point.

[0073] Table 1 shows the output results of the voltage comparison unit at the three latch time points for different data.

[0074] Page 0 Page 1 The first latch The second latch The third latch 1 1 pass pass pass 1 0 fail pass pass 0 1 fail fail pass 0 0 fail fail fail

[0075] The data cache unit 413 is coupled to the voltage comparison unit 412 and is used to store the results of multiple latches by the voltage comparison unit 412, and to transmit data with the decoding unit 414. In this embodiment, the data cache unit 413 temporarily caches the data read by the NAND flash memory 400 from the NAND array 420 so that the read data can be subsequently transmitted to the host or processor. The decoding unit 414 is coupled to the data cache unit 413 and is used to read the comparison results of the voltage comparison unit 412 cached by the data cache unit 413, and to analyze whether the data of each page is "0" or "1" based on the comparison results.

[0076] The decoding unit 414 is used to perform calculations and processing on the results of multiple latches in the data storage unit 413, thereby obtaining the original data from the read storage unit. In this embodiment, the decoding unit 414 pre-stores the preset results of Table 1. It can be defined that when the comparison results of the three latch time points are all "pass", the data on page 0 is "1" and the data on page 1 is "1". The NAND flash memory 400 can define that when the comparison result of the first latch time point is "fail" and the comparison results of the second and third latch time points are "pass", the data on page 0 is "1" and the data on page 1 is "0". The NAND flash memory 400 can define that when the comparison results of the first and second latch time points are "fail" and the comparison result of the third latch time point is "pass", the data on page 0 is "0" and the data on page 1 is "1". The NAND flash memory 400 can define that when the comparison results of the three latch time points are all "fail", the data on page 0 is "0" and the data on page 1 is "0".

[0077] Decoding unit 414 receives three results all being "pass" and outputs "11". Decoding unit 414 receives the first result as "fail", the second and third results as "pass", and outputs "10". Decoding unit 414 receives the first and second results as "fail", the third result as "pass", and outputs "01". Decoding unit 414 receives three results all being "fail" and outputs "00". Alternatively, if "pass" is considered logical "1" and "fail" is considered logical "0", then the result of the first page is the logical OR operation of the first and second latch results, and the result of the second page is the logical OR operation of the first and third latch results.

[0078] In this embodiment, when the NAND flash memory 400 accesses multiple pages on the same side simultaneously, the saturation current of the dual-gate MOS transistor in the memory cell of each page can be changed, making the saturation current of each page different. This results in different data recorded on each page, different total current in the read circuit, and thus different discharge capacitor C. SO The voltage drops at different rates. When NAND flash memory 400 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page.

[0079] Figure 6This is a schematic diagram of the structure of the second type of NAND memory provided in the embodiments of this application. Figure 6 As shown, compared to the structure of NAND memory 400, the structure of NAND memory 600 is that the current limiting unit 430 is replaced with the timing unit 630.

[0080] The timing unit 630 is used to stagger the discharge times of each page, such as by changing the read voltage V. read By adjusting the application time and adding additional switches to adjust the start time of different pages entering the evaluation phase, the storage units of each page can be made to enter the evaluation phase and read data at different times. In this embodiment, the timing unit 630 can be connected to each sub-block selection transistor. By sending control signals to the sub-block selection transistors, the sub-block selection transistors are turned on, so that the storage units of the pages corresponding to different sub-blocks can read data at different times. Optionally, the NAND memory 600 can be equipped with a switching transistor on each WL. The timing unit 630 is connected to each switching transistor respectively. By sending control signals to the switching transistors, the switching transistors are turned on, so that the storage units of different pages can read data at different times.

[0081] Taking the simultaneous reading of data from two pages of NAND flash memory 400 as an example, let the two pages be page 0 and page 1. Assume that the memory cell of page 0 is connected to sub-block select transistors 0 and BL0, and the memory cell of page 1 is connected to sub-block select transistors 1 and BL1. The saturation current I of the dual-gate MOSFETs of the memory cells in both pages... cell The two pages of memory cells have the same dual-gate MOS transistors with a read voltage V applied. read The time difference is a set time T. The duration of the set time T is equal to or less than the time it takes for the storage unit of page 0 to read data.

[0082] During the evaluation process, the timing unit 630 prioritizes turning on the selection transistor for the sub-block containing page 0, and after waiting for a set time T, turns on the selection transistor for the sub-block containing page 1. If the data in the memory cell of page 0 is "1" and the data in the memory cell of page 1 is "1", the dual-gate MOS transistor of the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell And the dual-gate MOS transistor in the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell Therefore, when the data is "11", the total current in the read circuit changes from I... cell After time T, it becomes 2I. cell .

[0083] If the data in the memory cell of page 0 is "1" and the data in the memory cell of page 1 is "0", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell Furthermore, the dual-gate MOS transistor in the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. Therefore, the total current in the read circuit when the data is "10" is always I. cell .

[0084] If the data in the memory cell of page 0 is "0" and the data in the memory cell of page 1 is "1", the dual-gate MOSFET in the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Conversely, the dual-gate MOSFET in the memory cell of page 1 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell Therefore, when the data is "01", the total current in the reading circuit changes from 0 to I after time T. cell .

[0085] If the data in the memory cell of page 0 is "0" and the data in the memory cell of page 1 is "0", the dual-gate MOSFET in the memory cell of page 0 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Similarly, the dual-gate MOSFET in the memory cell of page 1 is in the off state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, the total current in the read circuit is always 0 when the data is "00".

[0086] The total current in the reading circuit is different, and the discharge capacitor C SO The voltage from voltage V SO Drop to comparison voltage V THSA The slopes are not the same. For example, Figure 7 As shown, the total current in the reading circuit when the data is "11" is I. cell At that time, the discharge capacitor C SO The voltage drops relatively quickly and with a large slope. When the data is "11", the total current in the reading circuit becomes 2I. cell At that time, the discharge capacitor C SO The voltage drop rate increases, and the slope increases from its original value. When the data is "10", the total current in the reading circuit remains I. cell Therefore, the discharge capacitor C SO The voltage drop rate and slope remain constant. When the total current in the reading circuit is 0 when the data is "01", the discharge capacitor C... SOThe voltage remains constant. When the data is "01", the total current in the read circuit becomes I. cell At that time, the discharge capacitor C SO The voltage begins to drop, and the rate of drop is similar to the rate at which the discharge capacitor C is at a value of "10". SO The voltage drops at the same rate and with the same slope. When the data is "00", the total current in the reading circuit is 0, and the discharge capacitor C... SO The voltage remains constant.

[0087] The voltage comparator unit 612 is configured with three latch time points. The first latch time point can be set to the discharge capacitor C when the data is "11". SO The voltage drops to the comparison voltage V THSA The second latch time point can be set to the discharge capacitor C when the data is "10". SO The voltage drops to the comparison voltage V THSA The third latch time point can be set to the discharge capacitor C when the data is "01". SO The voltage drops to the comparison voltage V THSA The point in time.

[0088] The output results of voltage comparator unit 612 are shown in Table 2. When the data is "11", voltage comparator unit 612 outputs "pass" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "10", voltage comparator unit 612 outputs "fail" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "01", voltage comparator unit 612 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "pass" at the third latch time point. When the data is "00", voltage comparator unit 612 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "fail" at the third latch time point.

[0089] Table 2 shows the output results of the voltage comparison unit at the three latch time points for different data.

[0090] Page 0 Page 1 The first latch The second latch The third latch 1 1 pass pass pass 1 0 fail pass pass 0 1 fail fail pass 0 0 fail fail fail

[0091] The decoding unit 614 pre-stores the preset results of table 2. It can be defined that when the comparison results of the three latch time points are all "pass", the data on page 0 is "1" and the data on page 1 is "1". The NAND flash memory 600 can also define that when the comparison result of the first latch time point is "fail", and the comparison results of the second and third latch time points are "pass", the data on page 0 is "1" and the data on page 1 is "0". The NAND flash memory 600 can also define that when the comparison results of the first and second latch time points are "fail", and the comparison result of the third latch time point is "pass", the data on page 0 is "0" and the data on page 1 is "1". The NAND flash memory 600 can also define that when the comparison results of the three latch time points are all "fail", the data on page 0 is "0" and the data on page 1 is "0".

[0092] Decoding unit 614 receives three results all being "pass" and outputs "11". Decoding unit 614 receives the first result as "fail", the second and third results as "pass", and outputs "10". Decoding unit 614 receives the first and second results as "fail", the third result as "pass", and outputs "01". Decoding unit 614 receives three results all being "fail" and outputs "00".

[0093] In this embodiment, the NAND flash memory 600 can simultaneously access multiple pages on the same side, changing the time it takes to read the data recorded in the storage cells of each page. This results in different data recorded on each page, leading to different total currents in the read circuit and allowing the discharge capacitor C to discharge differently. SO The voltage drops at different rates. When NAND flash memory 600 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page.

[0094] Figure 8 This is a schematic diagram of the structure of the third type of NAND memory provided in the embodiments of this application. For example... Figure 8 As shown, compared to the structure of NAND memory 400, the structure of NAND memory 800 is that the current limiting unit 430 is replaced with the current limiting timing unit 830.

[0095] The current limiting and timing control unit 830 has the functions of the current limiting unit 430 and the timing control unit 630. It is used to limit the saturation current of each page, so that the saturation current of each page is different, and to stagger the discharge time of each page, so that the storage unit of each page can read data at different times.

[0096] Taking the NAND flash memory 800 reading data from four pages of storage cells simultaneously as an example, let the four pages be page 0, page 1, page 2 and page 3.

[0097] The current-limiting timing unit 830 can make all or part of the saturation current of the dual-gate MOSFETs of the four page memory cells different, and can also make all or part of the time for applying the read voltage to the dual-gate MOSFETs of the four page memory cells different. For example, the current-limiting timing unit 830 can make the saturation current of the dual-gate MOSFET of the memory cell of page 0 the same as that of the memory cell of page 1, and make the saturation current of the dual-gate MOSFET of the memory cell of page 2 the same as that of the memory cell of page 3, and can also make the saturation current of the dual-gate MOSFET of the memory cell of page 0 different from that of the memory cell of page 2. The current-limiting timing unit 830 ensures that the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 0 is the same as the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 2, the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 1 is the same as the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 3, and the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 0 is different from the time for applying the read voltage to the dual-gate MOS transistor of the memory cell in page 1. Other cases exist, but will not be listed here.

[0098] Assume that the saturation currents of the dual-gate MOS transistors in the four memory cells are related by I. cell0 >I cell1 >I cell2 >I cell3 The time when the read voltage is applied to the dual-gate MOS transistors of the four memory cells is sequentially separated by a set time T.

[0099] During the evaluation process, the flow limiting and timing unit 830 prioritizes turning on the selection transistor for the sub-block containing page 0, and after waiting for a set time T, turns on the selection transistor for the sub-block containing page 1. This process continues until the selection transistor for the sub-block containing page 1 is turned on.

[0100] If the data in the memory cells of all four pages is "1111", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 In the memory cell of page 1, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "1111", the total current in the reading circuit changes sequentially to I. cell0 I cell0 +I cell1 I cell0 +I cell1 +I cell2 and I cell0 +I cell1 +I cell2 +I cell3 .

[0101] If the data in the memory cells of all four pages is "1110", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 In the memory cell of page 1, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 In the memory cell on page 3, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, when the data is "1110", the total current in the read circuit changes sequentially to I. cell0 I cell0 +I cell1 and I cell0 +I cell1 +I cell2 .

[0102] If the data in the memory cells of all four pages is "1101", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0In the memory cell of page 1, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell1 On page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "1101", the total current in the reading circuit changes sequentially to I. cell0 I cell0 +I cell1 and I cell0 +I cell1 +I cell3 .

[0103] If the data in the memory cells of all four pages is "1100", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 In the memory cell of page 1, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 3, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, the total current in the read circuit when the data is "1100" changes sequentially by I. cell0 and I cell0 +I cell1 .

[0104] If the data in the memory cells of all four pages is "1011", the dual-gate MOSFET in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell0 On page 1, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "1011", the total current in the reading circuit changes sequentially to I. cell0I cell0 +I cell2 and I cell0 +I cell2 +I cell3 .

[0105] If the data in the memory cells of all four pages is "1010", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 On page 1, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 In the memory cell on page 3, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, when the data is "1010", the total current in the read circuit changes sequentially to I. cell0 and I cell0 +I cell2 .

[0106] If the data in the memory cells of all four pages is "1001", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0 On page 1, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "1001", the total current in the reading circuit changes sequentially to I. cell0 and I cell0 +I cell3 .

[0107] If the data in the four memory cells is "1000", the dual-gate MOS transistor in the memory cell of page 0 is in the on state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell0In page 1, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Similarly, in page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, when the data is "1000", the total current in the read circuit is always I. cell0 .

[0108] If the data in the memory cells of all four pages is "0111", the dual-gate MOS transistor in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "0111", the total current in the reading circuit changes sequentially to I. cell1 I cell1 +I cell2 and I cell1 +I cell2 +I cell3 .

[0109] If the data in the memory cells of all four pages is "0110", the dual-gate MOS transistor in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 In the memory cell on page 3, the dual-gate MOSFET is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, when the data is "0110", the total current in the read circuit changes sequentially to I. cell1 , and I cell1 +I cell2 .

[0110] If the data in the memory cells of all four pages is "0101", the dual-gate MOS transistor in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell1 On page 2, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "0101", the total current in the reading circuit changes sequentially to I. cell1 and I cell1 +I cell3 .

[0111] If the data in the memory cells of all four pages is "0100", the dual-gate MOS transistor in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOS transistor is the saturation current I. cell1 On page 2, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. On page 3, the dual-gate MOSFET in the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, when the data is "0100", the total current in the read circuit changes sequentially to I. cell2 .

[0112] If the data in the memory cells of all four pages is "0011", the dual-gate MOSFET in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFET in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFET in the memory cell of page 2 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell2 On page 3, the dual-gate MOSFET of the memory cell is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "0011", the total current in the reading circuit changes sequentially to I. cell2 and I cell2 +I cell3 .

[0113] If the data in the memory cells of all four pages is "0001", the dual-gate MOSFET in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFET in the memory cell of page 1 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFET in the memory cell of page 2 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFET in the memory cell of page 3 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is the saturation current I. cell3 Therefore, when the data is "0001", the total current in the read circuit is always I. cell3 .

[0114] If the data in the memory cells of all four pages is "0000", the dual-gate MOSFET in the memory cell of page 0 is in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. The dual-gate MOSFETs in the memory cells of page 1, 2, and 3 are also in the ON state, and the current flowing through the channel between the source and drain of the dual-gate MOSFET is 0. Therefore, the total current in the read circuit is always 0 when the data is "0000".

[0115] The total current in the reading circuit is different, and the discharge capacitor C SO The voltage from voltage V SO Drop to comparison voltage V THSA The slopes are not the same. Among them, the larger the total current, the larger the discharge capacitance C. SO The steeper the slope of the voltage change, the better. The voltage comparison unit 812 can detect the comparison results at multiple latch time points and input the multiple comparison results into the data cache unit 813. The data cache unit 813 temporarily caches the data read by the NAND flash memory 800 from the NAND array 820 so that the read data can be transferred to the host or processor later. The decoding unit 814 can read the comparison results of the voltage comparison unit 812 cached in the data cache unit 813, and analyze whether the data of each page is "0" or "1" based on the comparison results.

[0116] In this embodiment, the NAND flash memory 800 can simultaneously access multiple pages on the same side, changing the saturation current of the dual-gate MOS transistor in each page's memory cell to make the saturation current of each page different, and changing the time for reading the data recorded in the memory cell of each page, so that the data recorded in each page is different, the total current of the read circuit is different, and the discharge capacitor C... SO The voltage drops at different rates. When NAND flash memory 800 reads data from multiple pages, the voltage comparison unit can be used to detect the discharge capacitor C at multiple latch time points. SO The relationship between the voltage and the comparison voltage is used to accurately read the data recorded on each page and avoid confusion between the read data and the page.

[0117] This application provides a memory comprising a circuit board and at least one NAND flash memory. The NAND flash memory is fixedly and electrically connected to the circuit board for storing data. The NAND flash memory can be, for example, Figures 4-8 The NAND flash memory shown. Because the memory includes, for example... Figures 4-8 The NAND flash memory shown has all or at least some of the advantages of NAND flash memory. This memory can be an SSD, USB flash drive, memory card, mobile device, etc.

[0118] This application provides an electronic device including at least one memory and at least one processor. The at least one processor is electrically connected to the at least one memory and is used to write data to and / or read data from the at least one memory. Since the memory includes, for example... Figures 4-8 The NAND flash memory shown indicates that electronic devices possess all or at least some of the advantages of NAND flash memory. These electronic devices can be smartphones, laptops, tablets, desktop computers, servers, storage systems, base stations, drones, outdoor cabinets, etc.

[0119] The number, positional relationship, type, and shape of the components of the memory provided in this application are not limited to the above embodiments. All technical solutions implemented under the principles of this application are within the protection scope of this application. Any one or more embodiments or illustrations in the specification, combined in a suitable manner, are within the protection scope of this application.

[0120] The number, positional relationship, type, and shape of the components of the electronic device provided in this application are not limited to the above embodiments. All technical solutions implemented under the principles of this application are within the protection scope of this application. Any one or more embodiments or illustrations in the specification, combined in a suitable manner, are within the protection scope of this application.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application. Those skilled in the art should understand that although this application has been described in detail with reference to the foregoing embodiments, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions in the embodiments of this application.

Claims

1. A NAND flash memory (400, 600, 800), characterized by, The application relates to a voltage control unit (411, 611, 811) comprising a plurality of first output ports, each of which is used for outputting a first electric signal, and a plurality of second output ports, each of which is used for outputting a second electric signal. A NAND array (420, 620, 820) comprising a plurality of sub-blocks, each of which comprises a plurality of pages, and each of the plurality of pages is electrically connected to the plurality of first output ports, and is used for reading or writing data when the first electric signal is received. An asynchronous unit (430, 630, 830) is electrically connected between the plurality of first output ports and the plurality of sub-blocks, or is electrically connected between the gate of a sub-block selection transistor in the plurality of pages and the gate of a double-gate MOS transistor in the plurality of pages, and is used for making the saturation current of a target double-gate MOS transistor of each of the plurality of pages different and / or making the on time of each of the plurality of pages different when data of the target double-gate MOS transistor of each of the plurality of pages is read simultaneously. A voltage comparison unit (412, 612, 812) comprising a plurality of input ports, each of which is electrically connected to the plurality of second output ports, and is used for comparing the voltage received by the plurality of input ports with a comparison voltage, and outputting a comparison result. a plurality of discharging capacitors (C SO ), first ends of the plurality of discharging capacitors are electrically connected to the plurality of second output ports respectively, and second ends of the plurality of discharging capacitors are grounded. The discharge capacitor is in a discharge state when the data recorded by the target double-gate MOS transistor of the page to which the discharge capacitor is electrically connected is "1", and is in a charging state when the data recorded by the target double-gate MOS transistor of the page to which the discharge capacitor is electrically connected is "0".

2. The NAND flash memory of claim 1, wherein, The voltage comparison unit is specifically used for comparing the voltage received by the plurality of input ports at a plurality of latch time points with the comparison voltage, and obtaining a plurality of sub-output results.

3. The NAND flash memory of claim 1 or 2, wherein, The NAND flash memory further comprises: A decoding unit (414, 614, 814) used for comparing the plurality of sub-output results with a preset result, and determining that the data recorded by the target double-gate MOS transistor of each of the plurality of pages is "0" or "1"; the preset result records the sub-output results of different latch time points corresponding to the data recorded by the plurality of target double-gate MOS transistors read simultaneously. M and N are positive integers greater than or equal to 2.

4. The NAND flash memory of claim 3, wherein, The relationship between the number M of the plurality of latching time points and the number N of the pages read simultaneously is: M≥(2 N -1); There is at least one latch time point between different discharge time lengths; the discharge time length refers to the time length during which the voltage of the discharge capacitor electrically connected to the target double-gate MOS transistor of each of the plurality of pages read simultaneously is reduced to the comparison voltage.

5. The NAND flash memory of claim 3 or 4, wherein, When the on time of each of the plurality of pages read simultaneously is different, the time difference between the on time of two adjacent pages is less than or equal to the time length during which the voltage of the discharge capacitor is reduced to the comparison voltage.

6. The NAND flash memory of any one of claims 1-5, wherein, The voltage control unit is further used for electrically connecting the plurality of first output ports to the plurality of second output ports when the voltage control unit stops outputting the first electric signal and the second electric signal.

7. The NAND flash memory of any one of claims 1-6, wherein, The voltage control unit is further used for converting the current of the second output port from a first value to a second value.

8. The NAND flash memory of claim 7, wherein, The application further relates to a circuit board.

9. A memory, comprising: ​ ​ At least one NAND flash memory as claimed in any one of claims 1-8, said NAND flash memory being fixed and electrically connected to said circuit board for storing data.

10. An electronic device, comprising: Comprising: At least one memory as claimed in claim 9, At least one processor, said processor being electrically connected to said at least one memory, for writing data to and / or reading data from said at least one memory.

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