Multi-step composite dielectric protection structure and preparation method thereof

Abstract

The application discloses a multi-step composite dielectric protection structure and a preparation method thereof. The method comprises the following steps: growing 2N-1 layers of composite dielectric layers on a semiconductor wafer finished product surface from bottom to top; wherein N is a natural number greater than 1; forming a mask pattern on the top of the composite dielectric layer; forming a multi-step dielectric layer by once dry etching of the composite dielectric layer according to the mask pattern; removing the mask pattern and the even number of dielectric layers exposed outside the window in the multi-step dielectric layer, and obtaining a multi-step composite dielectric protection structure with N layers. In the application, the multi-step composite dielectric structure can be completed by only once photolithography etching and additional large-area back etching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multi-step composite dielectric protection structure and its preparation method. Background Technology

[0002] The surface quality of semiconductor chips is a crucial factor limiting the breakdown voltage characteristics of semiconductor power devices. Dielectric passivation is of great significance for reducing reverse leakage current and improving the reliability of semiconductor devices. It not only provides mechanical protection for the device surface and prevents contamination by impurities, but also effectively passivates active surface states, thereby improving the blocking voltage of semiconductor power devices.

[0003] With the improvement of device withstand voltage and reliability, a single passivation dielectric is insufficient to adequately provide surface passivation protection. Therefore, composite dielectric structures are often used to protect the device surface. For example, a silicon oxide + silicon nitride composite dielectric structure: First, high-density, low-interface-state thermally oxidized silicon oxide is deposited as the first passivation layer, whose low interface-state density does not significantly affect the terminal electric field distribution. Second, high-dielectric-constant silicon nitride is deposited as the second passivation layer, which significantly reduces the surface electric field of the device while preventing contamination by moisture, impurities, etc.

[0004] However, due to the use of a multi-layer composite dielectric structure, different dielectrics require different etching or corrosion methods, often necessitating multiple etching or corrosion processes to form metal interconnect vias, making the process relatively complex. Secondly, because the multi-layer composite dielectric is quite thick, the resulting vertical dielectric vias have a high aspect ratio, leading to poor filling properties and high metal porosity during the thickening metal filling process. Summary of the Invention

[0005] Technical objective: To address the shortcomings of the aforementioned multilayer composite dielectric structures, this invention provides a multi-step composite dielectric protection structure and its preparation method, which can complete the multilayer step composite dielectric structure with only one photolithography etching and an additional large-area etch back.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0007] A method for preparing a multi-step composite dielectric protection structure includes the following steps:

[0008] Step 1: Grow 2N-1 composite dielectric layers sequentially from bottom to top on the surface of the semiconductor wafer; where N is a natural number greater than 1.

[0009] Step 2: Form a mask pattern on top of the composite dielectric layer;

[0010] Step 3: Based on the mask pattern, the composite dielectric layer is formed into a multi-step dielectric layer by a single dry etching process;

[0011] Step 4: Remove the even-numbered dielectric layers exposed outside the window in the mask pattern and multi-step dielectric layer to obtain an N-layer multi-step composite dielectric protection structure. The first step corresponds to one composite dielectric layer, the second to Nth steps each correspond to two composite dielectric layers, and the Nth step corresponds to 2N-1 and 2N composite dielectric layers.

[0012] A multi-step composite dielectric protection structure is located on a semiconductor wafer and is prepared by the above-described method for preparing a multi-step composite dielectric protection structure. It includes N-layer composite dielectric layers, where N is a natural number greater than 1. The first step corresponds to one layer of composite dielectric layer, the second to Nth steps each correspond to two layers of composite dielectric layer, and the Nth step corresponds to 2N-1 layers and 2N layers of composite dielectric layer.

[0013] Beneficial effects:

[0014] The process of this invention is simple. It only requires one photolithography etching in step 3 and a large-area back etching in step 4 to complete the multi-layered stepped composite dielectric structure. This method can not only achieve a large aspect ratio dielectric trench, but also, because it is a multi-layered stepped process, compared with an equivalent single-step trench, it can greatly improve the metal filling voids caused by high aspect ratio dielectric trenches, improve the metal filling performance, and thus improve the chip performance and reliability, while maintaining the same minimum linewidth. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a multi-step composite medium protection structure when N=2;

[0016] Figure 2 This is a schematic diagram of a multi-step composite medium protection structure when N=3;

[0017] Figures 3 to 8 This is a schematic diagram of the fabrication process for forming a multi-step composite dielectric protection structure on a SiC epitaxial wafer in Example 2;

[0018] Figure 9 This is a schematic diagram of the multi-step composite dielectric protection structure after a single dry etching process when N=3.

[0019] Explanation of reference numerals in the attached figures: 1. SiC substrate; 2. N-epitaxial layer; 3. P-well region; 4. N+ region; 5. P+ region; 6. JFET implantation region; 7. Oxygen dielectric layer; 8. Gate electrode; 9. Source ohmic metal; 10. Drain ohmic metal; 11. First passivation dielectric layer; 12. Second passivation dielectric layer; 13. Third passivation dielectric layer; 14. Front metal; 15. Back metal. Detailed Implementation

[0020] The following description, in conjunction with the accompanying drawings and embodiments, further explains and illustrates a multi-step composite dielectric protection structure and its preparation method according to the present invention.

[0021] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0022] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Example 1

[0023] As attached Figure 1 As shown, the preparation method of a multi-step composite dielectric protection structure in this embodiment includes the following steps:

[0024] Step 1: A 2N-1 layer composite dielectric layer is sequentially grown from bottom to top on the surface of the finished semiconductor wafer. The finished semiconductor wafer refers to a semiconductor wafer on which the gate dielectric, gate electrode, source electrode, and drain electrode have been fabricated. Semiconductor wafers include silicon, silicon carbide, gallium nitride, gallium oxide, and other semiconductor wafers. In the 2N-1 layer composite dielectric layer, the material of the composite dielectric layer is oxide, silicate, nitride, PSG (Phosphosilicate Glass), etc. The odd-numbered layers have the same material and a thickness ratio of 1:2 to 2:1; the even-numbered layers have the same material and a thickness ratio of 1:2 to 2:1; the odd-numbered and even-numbered layers have different materials and a thickness ratio of 1:5 to 1:20; the thickness range of the 2N-1 layer composite dielectric layer is 1µm to 10µm.

[0025] Step 2: Form a mask pattern on top of the composite dielectric layer; the mask pattern includes photoresist, metal, silicon nitride, silicon oxide, etc., and the width of the exposed etching window ranges from 0.3um to 2.0um;

[0026] Step 3: Based on the mask pattern, the composite dielectric layer is etched in a single dry process to form a multi-step dielectric layer; wherein, the ratio of the longitudinal etching rate to the lateral etching rate of even-numbered layers is 3:1 to 50:1, and the ratio of the longitudinal etching rate to the lateral etching rate of odd-numbered layers is 2:1 to 1:2, and the ratio of the longitudinal etching rate to the lateral etching rate of both odd-numbered and even-numbered composite dielectric layers increases with the increase of the number and thickness of the composite dielectric layers; as shown in the attached figure. Figure 9 As shown, attached Figure 9 This is a schematic diagram of the multi-step composite dielectric protection structure after a single dry etching process when N=3.

[0027] Step 4: Remove the even-numbered dielectric layers exposed outside the window in the mask pattern and multi-step dielectric layer to obtain an N-step multi-step composite dielectric protection structure. The first step corresponds to one composite dielectric layer, the second to Nth steps each correspond to two composite dielectric layers, and the Nth step corresponds to 2N-1 and 2N composite dielectric layers. When removing the even-numbered dielectric layers, the etching rate ratio of the even-numbered composite dielectric layers to the odd-numbered composite dielectric layers is greater than 10:1; where N=2, the resulting multi-step composite dielectric protection structure is shown in the attached figure. Figure 1 As shown; when N=3, the resulting multi-step composite dielectric protection structure is as shown in the attached figure. Figure 2 As shown.

[0028] In this embodiment of the multi-step composite dielectric protection structure with N steps, the opening width increases with the number of steps, and the bottommost step (the first step) has the smallest width. Compared to a single-layer composite dielectric protection structure with the same small width, metal filling is better. Furthermore, in this embodiment, the inclination angle α of the first step ranges from 40° to 80°, and the bottom angle of the smallest side is gentler, making it easier to fill.

[0029] This embodiment also discloses a multi-step composite dielectric protection structure located on a semiconductor wafer, comprising N composite dielectric layers, where N is a natural number greater than 1. The first step corresponds to one composite dielectric layer, the second to Nth steps each correspond to two composite dielectric layers, the Nth step corresponds to 2N-1 and 2N composite dielectric layers, and the materials of the two composite dielectric layers corresponding to each step from the second to the Nth step are different. Example 2

[0030] As attached Figure 2 As shown, the preparation method of a multi-step composite dielectric protection structure in this embodiment includes the following steps:

[0031] Step 1: A composite dielectric layer consisting of three layers grown sequentially from bottom to top on the surface of the semiconductor wafer: a first passivation dielectric layer 11, a second passivation dielectric layer 12, and a third passivation dielectric layer 13. The first and third passivation dielectric layers are made of the same material, but the material of the second passivation dielectric layer is different. The thickness ratio of the first to the third passivation dielectric layer is 1:2 to 2:1, the thickness ratio of the second to the first dielectric layer is 1:5 to 1:20, and the thickness ratio of the second to the third dielectric layer is 1:5 to 1:20. The total dielectric thickness is 1µm to 10µm.

[0032] The manufacturing process of semiconductor wafers includes:

[0033] A SiC epitaxial wafer is selected, which is formed by a SiC substrate 1 and an N-epitaxial layer 2, such as... Figure 3 As shown.

[0034] A dielectric mask is grown on the N-epitaxial layer 2, and a P-well region 3 is formed through photolithography, etching, ion implantation, and activated annealing processes. The implantation depth ranges from 0.5 μm to 1.1 μm, and the P-type implantation concentration ranges from 1e16 cm⁻¹. -3 ~1e18cm -3 Next, the same process steps are used to form N+ region 4, P+ region 5, and JFET implantation region 6. For example... Figure 4 As shown. The injection depth of region N+4 ranges from 0.2 μm to 0.5 μm, and the N-type injection concentration ranges from 1e18 cm⁻¹. -3 ~1e21cm -3 The injection depth of P+ region 5 ranges from 0.2 μm to 0.6 μm, and the P-type injection concentration ranges from 1e19 cm⁻¹. -3 ~1e21cm -3 The implantation depth of JFET implantation region 6 ranges from 1.0 μm to 2.0 μm, and the N-type implantation concentration ranges from 5e15 cm⁻¹. -3 ~5e17cm -3 The activation annealing time is 0.1h to 6h, and the annealing temperature is 1400℃ to 1800℃.

[0035] Next, a low-interface-state-density, high-mobility gate oxide dielectric layer 7 is grown through processes such as decarburization, sacrificial oxidation, wet etching, gate dielectric oxidation, and annealing. The gate electrode 8 is formed by LPCVD deposition of polycrystalline silicon, as shown below. Figure 5 As shown, the thickness of the gate oxide dielectric 7 ranges from 20 to 70 nm. The gate electrode 8 is a polycrystalline silicon gate electrode with a growth thickness of 200 nm to 800 nm.

[0036] Source ohmic metal 9 is formed through photolithography, metallization, and lift-off processes. Next, drain ohmic metal 10 is deposited on the back side. Finally, source and drain ohmic contacts are simultaneously formed on both sides using an annealing process, as shown below. Figure 6 As shown; the source and drain ohmic metals are Ni, Ti or Ti / Ni alloy, with a metal thickness ranging from 50 nm to 300 nm and an annealing temperature of 800℃ to 1200℃.

[0037] Step 2: Form a mask pattern on top of the composite dielectric layer using photolithography.

[0038] Step 3: Based on the mask pattern, the composite dielectric layer is formed into a multi-step dielectric layer by dry etching in one step; the etching rates of the second passivation dielectric layer and the first / third passivation dielectric layer are different. The ratio of the longitudinal etching rate to the transverse etching rate of the second passivation dielectric layer is 3:1 to 50:1, and the ratio of the longitudinal etching rate to the transverse etching rate of the first and third passivation dielectric layers is 2:1 to 1:2.

[0039] Step 4: Remove the mask pattern by applying and removing adhesive, and etch the exposed second passivation dielectric layer across the entire wafer to obtain a two-layer multi-step composite dielectric protection structure, such as... Figure 7 As shown. ICP or RIE etching is used. Etching gases include SF6, CF4, and BCl3. The exposed second passivation dielectric layer is removed by dry etching or wet etching, with an etching rate ratio greater than 10:1 between the second passivation layer and the first / third passivation layer.

[0040] After completion, the front metal 14 and back metal 15 can be thickened and filled using sputtering or evaporation processes to achieve electrode interconnection, such as... Figure 8 As shown. The front metal process uses a Ti / Al metal system, and the back metal process uses a Ti / Ni / Ag metal system.

[0041] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for preparing a multi-step composite dielectric protection structure, characterized in that, Includes the following steps: Step 1: Grow 2N-1 composite dielectric layers sequentially from bottom to top on the surface of the semiconductor wafer; where N is a natural number greater than 1. Step 2: Form a mask pattern on top of the composite dielectric layer; Step 3: Based on the mask pattern, the composite dielectric layer is formed into a multi-step dielectric layer by dry etching in one step; the ratio of the longitudinal etching rate to the transverse etching rate of even-numbered layers is 3:1 to 50:1, and the ratio of the longitudinal etching rate to the transverse etching rate of odd-numbered layers is 2:1 to 1:

2. The ratio of the longitudinal etching rate to the transverse etching rate of the composite dielectric layer with both odd and even-numbered layers increases with the increase of the number and thickness of the composite dielectric layer. Step 4: Remove the even-numbered dielectric layers exposed outside the window in the mask pattern and multi-step dielectric layer to obtain an N-step multi-step composite dielectric protection structure. The first step corresponds to one composite dielectric layer, the second to the Nth step each correspond to two composite dielectric layers, and the Nth step corresponds to 2N-2 and 2N-1 composite dielectric layers. When removing the even-numbered dielectric layers, the etching rate ratio of the even-numbered composite dielectric layers to the odd-numbered composite dielectric layers is greater than 10:

1.

2. The method for preparing a multi-step composite dielectric protection structure according to claim 1, characterized in that: The thickness of the composite dielectric layer of the 2N-1 layer ranges from 1µm to 10µm.

3. The method for preparing a multi-step composite dielectric protection structure according to claim 1, characterized in that: In the 2N-1 layer composite dielectric layer, the odd-numbered layers are made of the same material, with a thickness ratio of 1:2 to 2:

1.

4. The method for preparing a multi-step composite dielectric protection structure according to claim 1, characterized in that: In the 2N-1 layer composite dielectric layer, the even-numbered composite dielectric layers are made of the same material, and the thickness ratio is 1:2 to 2:

1.

5. The method for preparing a multi-step composite dielectric protection structure according to claim 1, characterized in that: In the 2N-1 layer composite dielectric layer, the materials of the odd-numbered and even-numbered composite dielectric layers are different, with a thickness ratio of 1:5 to 1:

20.

6. The method for preparing a multi-step composite dielectric protection structure according to claim 1, characterized in that: In a multi-step composite medium protection structure with N steps, the inclination angle α of the first step ranges from 40° to 80°.

7. A multi-step composite dielectric protection structure, located on a finished semiconductor wafer, prepared by the method for preparing a multi-step composite dielectric protection structure according to any one of claims 1-6, characterized in that, The composite dielectric layer includes N steps, where N is a natural number greater than 1. The first step corresponds to one composite dielectric layer, the second to Nth steps each correspond to two composite dielectric layers, and the Nth step corresponds to 2N-2 and 2N-1 composite dielectric layers.

8. The multi-step composite dielectric protection structure according to claim 7, characterized in that: From the second to the Nth step, the two composite medium layers corresponding to each step are made of different materials.

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