Semiconductor substrate, semiconductor package and method of forming same

Abstract

The present disclosure provides a semiconductor substrate comprising: a first patterned conductive layer; a dielectric structure on the first patterned conductive layer, wherein the dielectric structure has a side surface; a second patterned conductive layer on the dielectric structure and extending on the side surface; and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

Description

Semiconductor substrates, semiconductor packaging and their formation methods

[0001] Information related to divisional application

[0002] This is a divisional application. The parent application is a patent application filed on September 17, 2018, with application number "201811080361.6" and the invention title "Semiconductor Substrate, Semiconductor Package, and Method for Forming the Same". The aforementioned application claims priority to U.S. Patent Application Serial No. 16 / 038,037, filed on July 17, 2018. Technical Field

[0003] Some embodiments of this disclosure provide a semiconductor substrate structure, and more particularly with respect to a semiconductor substrate structure for enhancing heat dissipation. Background Technology

[0004] Electronic packages, such as electronic control modules, typically contain manufacturing circuitry that includes electronic components such as transistors and resistors. This circuitry conducts current, which in turn generates heat within the electronic package. Excessive heat buildup within specific electronic packages and other components of a module can lead to adverse effects, including circuit malfunctions. Therefore, heat needs to be dissipated from the electronic package.

[0005] Many electronic packages use semiconductor devices in the form of flip chips. Some conventional techniques for dissipating heat from electronic packages use thermally conductive heat sinks that are supported by clamps or directly mounted onto a printed circuit board.

[0006] While conventional methods are generally sufficient to dissipate some of the heat energy (heat) from semiconductor devices, many methods do not provide optimal heat dissipation. For example, many methods achieve substantial heat dissipation in a general direction primarily by placing a heat sink in thermal contact with one surface of the semiconductor device. While some additional heat dissipation can be achieved in other directions via air or other media exhibiting poor thermal conductivity, this dissipation is typically minimal. The resulting heat dissipation in many conventional semiconductor packages leads to size and power limitations.

[0007] Therefore, there is a need to provide semiconductor device and heat sink packages, as well as methods to dissipate heat energy (heat) from semiconductor devices in the most efficient way. Summary of the Invention

[0008] Some embodiments of this disclosure provide a semiconductor substrate comprising: a first patterned conductive layer; a dielectric structure on the first patterned conductive layer, wherein the dielectric structure has a side surface; a second patterned conductive layer on the dielectric structure and extending on the side surface; and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface.

[0009] Some embodiments of this disclosure provide a semiconductor package comprising: a dielectric structure having a bottom surface configured to be close to solder bumps and a side surface connected to the bottom surface; a first patterned conductive layer close to a top surface of the dielectric structure, the top surface being opposite to the bottom surface; a second patterned conductive layer extending on the side surface; a third patterned conductive layer being closer to the bottom surface than the first patterned conductive layer and extending on the side surface; and a semiconductor chip above the top surface.

[0010] Some embodiments of this disclosure provide a method for manufacturing a semiconductor package, comprising: providing a carrier; forming a first patterned conductive layer on the carrier; defining a dicing region in the dielectric structure by forming an opening in the dielectric structure; and simultaneously forming a second patterned conductive layer on the dielectric structure and extending into the opening. Attached Figure Description

[0011] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that different features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0012] Figures 1A and 1B are perspective views of a portion of a semiconductor substrate according to some embodiments of the present disclosure.

[0013] Figure 1C is a cross-sectional view along the cutting line AA marked in Figures 1A and 1B.

[0014] Figures 2A, 2B, and 2C are cross-sectional views illustrating semiconductor packages according to some embodiments of the present disclosure.

[0015] Figure 3A is a cross-sectional view illustrating a semiconductor substrate according to some embodiments of the present disclosure.

[0016] Figure 3B is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure.

[0017] Figures 4 to 8 are cross-sectional views illustrating various semiconductor substrates according to some embodiments of the present disclosure.

[0018] Figures 9 to 13 are cross-sectional views illustrating various semiconductor packages according to some embodiments of the present disclosure.

[0019] Figures 14A to 14F are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure.

[0020] Figures 15A to 15J are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure.

[0021] Figures 16A to 16L are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure.

[0022] Figures 17A to 17L are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure.

[0023] Figures 18A to 18L are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure.

[0024] Figures 19A to 19L are cross-sectional views illustrating semiconductor substrates at various manufacturing stages according to some embodiments of the present disclosure. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. In this disclosure, references to the formation of a first feature on or over a second feature in the following description may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0026] Embodiments of this disclosure are discussed in detail below. However, it should be understood that many applicable concepts provided in this disclosure can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0027] Additionally, spatial relative terms such as “down,” “below,” “lower,” “above,” “upper,” “lower,” “left,” and “right” may be used herein for ease of description to describe the relationship between one component or feature and another component(s) as illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It will be understood that when a component is referred to as “connected to” or “coupled to” another component, the component may be directly connected to or coupled to the other component, or there may be intervening components.

[0028] The numerical ranges and parameters set forth in this disclosure are approximate and are reported as precisely as possible to the specific examples described herein. However, some values ​​may contain certain errors necessarily caused by the standard deviation found in their respective test measurements. Moreover, as used herein, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. Alternatively, when considered by one of ordinary skill in the art, the term "about" means within an acceptable standard error of the mean. Except in operational / working examples, or unless expressly specified otherwise, all numerical ranges, quantities, values, and percentages (e.g., those used for the quantities of material, durations, temperatures, operating conditions, ratios of quantities, etc., disclosed herein) should be understood to be modified by the term "about" in all cases. Therefore, unless indicated to the contrary, the numerical parameters set forth in this disclosure and the appended claims are variable approximations. Each numerical parameter should be interpreted at least according to the number of significant figures reported and by applying general rounding techniques. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” may refer to two surfaces located within a few micrometers (μm) along the same plane, for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to the “substantially” same numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said value.

[0029] Some packages have significant heat dissipation requirements. In some embodiments, attaching additional heat sinks to the encapsulation, removing a portion of the encapsulation to expose the packaged chip, or using new encapsulation materials with better thermal conductivity have been used to meet package-level requirements. Nevertheless, these measures increase the overall cost of the package.

[0030] On the other hand, increasing the copper density, such as by thickening the copper wires or plating additional copper in the substrate, can also meet substrate-level requirements. However, this may increase the substrate thickness, and thus the overall package thickness.

[0031] This disclosure further provides a substrate cell surrounded by scribe lines. By plating copper into trenches positioned on the scribe lines simultaneously with copper plating to form conductive wiring in the substrate, the copper density in the substrate can be effectively increased. This operation enhances heat dissipation through the greater copper density without requiring additional fabrication operations. Due to the fact that the width of the scribe trench is greater than the width of the conductive wiring trench, it is contemplated that the conductive wiring trench is filled before the scribe trench. Such unfilled scribe trenches can further mitigate substrate warpage.

[0032] Referring to Figures 1A and 1B, which are perspective views of a portion of a semiconductor substrate according to some embodiments of the present disclosure, the semiconductor substrate is composed of a plurality of cells 101 defined by corresponding dicing regions 111. As shown in Figure 1A, each of the cells 101 is surrounded by dicing regions 111 at four sides, thus defining a quadrilateral cell 101. In some embodiments, the dicing regions 111 are in the form of filled or partially filled continuous trenches. Alternatively, the dicing regions 111 may be formed by filled or partially filled vias, such as those shown in Figure 1B.

[0033] Referring to Figure 1C, Figure 1C is a cross-sectional view cut from line AA in Figures 1A and 1B. Line AA cuts a cell on the substrate from its left boundary to its right boundary. Starting from the left boundary and moving laterally to the right, the cut line region 111 is first seen on the left, followed by multiple conductive layers 112 within the cell, and finally other cut line regions 111 are seen at the right boundary. In some embodiments, the conductive layers 112 may serve as power lines and redistribution lines (RDLs). The multiple conductive layers 112 are formed in a layer-based dielectric structure, i.e., each conductive layer is formed in a corresponding dielectric layer, and manufacturing traces, such as seed layers, set before the conductive layer is plated can be identified under a microscope with or without slight etching. Similarly, such manufacturing traces are also visible in the cut line region 111. Details of such manufacturing traces are described in Figures 3A and 3B of this disclosure.

[0034] Referring to Figures 2A, 2B, and 2C, these figures are cross-sectional views illustrating three different semiconductor packages according to some embodiments of the present disclosure. In Figure 2A, the semiconductor substrate shown in Figure 2C is integrated with solder bumps 201 at the bump side 201' and with a semiconductor chip 202 at the chip side 202' to form a semiconductor package 20A. In some embodiments, the chip 202 is bonded to the substrate via conductive bumps and a thermal interface material (TIM) 204. Alternatively, the TIM 204 may be applied close to the chip side 202' of the substrate over a diced region 111, and a heat sink 203 is bonded to the substrate via the TIM 204 over the diced region 111. The semiconductor package 20A provides better heat dissipation than conventional semiconductor packages because at least the diced region 111 has a higher density of conductive material, such as copper, so that heat generated at the chip 202 can be effectively dissipated via a more efficient thermal conduction path from the heat sink 203 to the conductive material at the diced region 111.

[0035] In Figure 2B, the semiconductor substrate shown in Figure 1C is integrated with solder bumps 201 at the bump side 201' and with a semiconductor chip 202 at the chip side 202' to form a semiconductor package 20B. In some embodiments, the chip 202 is bonded to the substrate via conductive bumps and an underfill material. Alternatively, an encapsulant 205 with suitable thermal conductivity covers the chip 202 and simultaneously contacts the conductive material at the dicing region 111. The semiconductor package 20B provides better heat dissipation than conventional semiconductor packages because at least the dicing region 111 has a higher density of conductive material, such as copper, so that heat generated at the chip 202 can be effectively dissipated via a more efficient heat conduction path from the encapsulant 205 to the conductive material at the dicing region 111.

[0036] In Figure 2C, the semiconductor substrate shown in Figure 1C is integrated with solder bumps 201 at the bump side 201' and with a semiconductor chip 202 at the chip side 202' to form a semiconductor package 20B. In some embodiments, the chip 202 is bonded to the substrate via conductive bumps and / or underfill material. Alternatively, an encapsulant 205 with suitable thermal conductivity covers the chip 202 and simultaneously contacts the conductive material at the dicing region 111. Furthermore, copper wires 206 further connect, for example, a conductive surface 204 at the back side of the chip 202 to the conductive material at the dicing region 111. The semiconductor package 20C provides better heat dissipation than conventional semiconductor packages because at least the dicing region 111 has a higher density of conductive material, such as copper, so that heat generated at the chip 202 can be effectively dissipated via a more efficient heat conduction path from the encapsulant 205 and the copper wires 206 to the conductive material at the dicing region 111.

[0037] Referring to FIG. 3A, FIG. 3A is a cross-sectional view illustrating a semiconductor substrate 10 according to some embodiments of the present disclosure. The semiconductor substrate 10 includes a first patterned conductive layer L1 and a first dielectric structure D1 on the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1 extends over a unit region 112' and the first patterned conductive layer L1' extends over a diced region 111. The unit region 112' is referred to herein as a conductive patterned region. Referring back to FIG. 1C, the first dielectric structure D1 has a side surface S1 over the diced region 111 of the substrate 10 but not over the unit region 112'. The first dielectric structure D1 includes a plurality of via trenches L21 in the unit region 112', wherein the plurality of via trenches L21 are filled with a conductive material and connected to a portion of the first patterned conductive layer L1. The first dielectric structure D1 includes at least one scribe trench M11 in the scribe line region 111, wherein the scribe trench M11 is filled or partially filled with conductive material and connected to the first patterned conductive layer L1' of the scribe line region 111. The scribe trench M11 is about 3 to 6 times wider than the via trench L21. In some embodiments, the width W2 of the via trench L21 is from about 50 to 70 μm, and the width W1 of the scribe trench M11 is from about 250 to 300 μm. The scribe line SC in FIG3A illustrates the dicing edge of the substrate 10 after chip mounting, molding encapsulation, and soldering, and after semiconductor packaging is completed. After each unit is separated along the scribe line SC to form an individual package, the side surface S1 of the first dielectric structure D1 is a sloped surface at the edge of the individual package.

[0038] As shown in Figure 3A, the conductive material filling the through-hole trench L21 and the scribing trench M11 comprises a second patterned conductive layer SE1, a third patterned conductive layer L2, and a metal structure M1. In some other embodiments where several metal structures are present, the metal structure M1 may be a first metal structure. In some embodiments, the third patterned conductive layer L2 and the metal structure M1 are formed in a single deposition operation. The third patterned conductive layer L2 and the metal structure M1 penetrate the first dielectric structure D1 and contact the first patterned conductive layer L1 and the first patterned conductive layer L1', respectively. In some embodiments, the first patterned conductive layer L1' is electrically coupled to the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1' is electrically coupled to the third patterned conductive layer L2 via the metal structure M1. In some embodiments, the conductive layer and the metal structure at the scribe line region 111 may or may not be electrically connected to the conductive layer at the cell inner region 112'.

[0039] The second patterned conductive layer SE1 may be a copper seed layer. The copper seed layer may be formed of copper or a copper alloy comprising silver, chromium, nickel, tin, gold, and combinations thereof. The thickness of the copper seed layer is in the range of approximately 2000 to approximately 8000 angstroms. The third patterned conductive layer L2 and the metal structure M1 may be made of the same material as the first patterned conductive layer L1. Since the scribe groove M11 is wider than the via groove L21, the conductive material may completely fill the via groove L21, but only partially fill the scribe groove M11. The degree to which the scribe groove M11 is filled can be determined by the relative width of the via groove L21 and the scribe groove M11. As previously discussed in Figures 1A and 1B, the cut-line region 111 may contain continuous trenches that are filled or partially filled, or vias that are filled or partially filled; therefore, in other embodiments, the scribe groove M11 represents a scribe via.

[0040] Referring to FIG. 3B, FIG. 3B is a cross-sectional view illustrating a semiconductor package 10' according to some embodiments of the present disclosure. The semiconductor package 10' includes a first dielectric structure D1 having a top surface T near the semiconductor chip 202 and a bottom surface B near the solder bump 201. The package 10' includes a first patterned conductive layer L1 near the top surface T. In some embodiments, the first patterned conductive layer L1 extends over a cell inner region 112' and over a dicing region 111. Referring back to FIG. 1C, the first dielectric structure D1 has a side surface S1' over the dicing region 111 of the package 10' but not over the cell inner region 112'. The first dielectric structure D1 includes a plurality of via trenches L21 in the cell inner region 112', which are filled with conductive material and connected to a portion of the first patterned conductive layer L1. The first dielectric structure D1 includes at least one scribe groove M11' in the scribe line region 111, which is filled or partially filled with conductive material and connected to a first patterned conductive layer L1' of the scribe line region 111. The scribe groove M11 is about 3 to 6 times wider than the via trench L21. In some embodiments, the width W2 of the via trench L21 is from about 50 to 70 μm, and the width W1 of the scribe groove M11' is from about 250 to 300 μm. The scribe line SC in FIG3B illustrates the cut edge of the package 10'. After each unit is separated along the scribe line SC to form an individual package, the side surface S1 of the first dielectric structure D1 is an inclined surface at the edge of the individual package.

[0041] As shown in Figure 3B, the conductive material filling the through-hole trench L21 and the scribing trench M11' comprises a second patterned conductive layer SE1', a third patterned conductive layer L2, and a metal structure M1'. In some embodiments, the third patterned conductive layer L2 and the metal structure M1' are formed in a single deposition operation. The third patterned conductive layer L2 and the metal structure M1' penetrate the first dielectric structure D1 and contact the first patterned conductive layer L1 and the first patterned conductive layer L1', respectively. In some embodiments, the first patterned conductive layer L1' is electrically coupled to the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1' is electrically coupled to the third patterned conductive layer L2 via the metal structure M1'. In some embodiments, the conductive layer and the metal structure at the scribe line region 111 may or may not be electrically connected to the conductive layer at the cell inner region 112'.

[0042] The second patterned conductive layer SE1' may be a copper seed layer. The copper seed layer may be formed of copper or a copper alloy comprising silver, chromium, nickel, tin, gold, and combinations thereof. The thickness of the copper seed layer is in the range of approximately 2000 to approximately 8000 angstroms. The third patterned conductive layer L2 and the metal structure M1' may be made of the same material as the first patterned conductive layer L1. Since the scribe groove M11' is wider than the via groove L21, the conductive material may completely fill the via groove L21, but only partially fill the scribe groove M11'. The degree to which the scribe groove M11' is filled can be determined by the relative width of the via groove L21 and the scribe groove M11'. As previously discussed in Figures 1A and 1B, the cut-line region 111 may contain a continuous trench or a via that is filled or partially filled; therefore, in other embodiments, the scribe groove M11 represents a scribe via.

[0043] In Figure 3B, the semiconductor chip 202 is disposed on the top surface T of the first dielectric structure D1 and is engaged with the bumps on the top surface T of the first dielectric structure D1. The semiconductor chip 202 is further encapsulated by an encapsulant 205 disposed on the top surface T.

[0044] Figures 4 through 8 are cross-sectional views illustrating various semiconductor substrates according to some embodiments of the present disclosure. Figure 4 illustrates a semiconductor substrate 40 based on the semiconductor structure 10 of Figure 3A. The same numerical designations in Figure 4 can be interpreted as substantially the same components or equivalents as those in Figure 3A, and their descriptions are omitted for brevity. In addition to the first patterned conductive layers L1, L1', the second patterned conductive layer SE1, the first dielectric layer D1, the first metal structure M1, and the third patterned conductive layer L2, the semiconductor substrate 40 further includes a second dielectric layer D2 covering a portion of the first metal structure M1 and the third patterned conductive layer L2, a fourth patterned conductive layer SE2 extending on the side surfaces of the first dielectric layer D1 and the second dielectric layer D2, a fifth patterned conductive layer L3, and a second metal structure M2 extending on the side surfaces of the first dielectric layer D1 and the second dielectric layer D2. In some embodiments, the second metal structure M2 may be made of the same material as constituting the first metal structure M1. In some embodiments, the fourth patterned conductive layer SE2 may be made of the same material as constituting the second patterned conductive layer SE1. In some embodiments, the fifth patterned conductive layer L3 may be made of the same material as the third patterned conductive layer L2.

[0045] Similar to the connection between the first metal structure M1 and the third patterned conductive layer L2, the second metal structure M2 at the cut line region 111 may or may not be electrically connected to the conductive layer at the inner region 112' of the cell.

[0046] In the semiconductor structure 40, the second metal structure M2 extends from the top surface T2 of the second dielectric layer D2 toward the side surface of the second dielectric layer D2, and overlaps with the portion of the first metal structure M1 extending downward above the side surface of the first dielectric layer D1 to the bottom of the scribe trench M11. In other words, the second metal structure M2 extends toward a layer below the top surface T1 of the first dielectric layer D1. After appropriate fine polishing and micro-etching, the fourth patterned conductive layer SE2 can be easily observed positioned between the first metal structure M1 and the second metal structure M2, and between the second metal structure M2 and the second dielectric layer D2.

[0047] Referring to Figure 5, which illustrates a semiconductor substrate 50 similar to semiconductor substrate 40 except for portions of the first metal structure M1 and the second metal structure M2. In Figure 5, the first metal structure M1 has a top surface T1' flush with the top surface of the third patterned conductive layer L2. Similarly, the second metal structure M2 has a top surface T2' flush with the top surface of the fifth patterned conductive layer L3. Note that the first metal structure M1 and the second metal structure M2 fill the dicing region 111 to the extent that the vertical sidewall V can be observed after chip separation. A portion of the vertical sidewall V is the dicing edge of the second metal structure M2, and a portion of the vertical sidewall V is the dicing edge of the first metal structure M1. The fourth patterned conductive layer SE2 is positioned on the top surface T1', side surface, and top surface of the second dielectric layer D2, thereby separating the second metal structure M2 from the first metal structure M1 and the second dielectric layer D2.

[0048] Referring to Figure 6, which illustrates a semiconductor substrate 60 similar to semiconductor substrate 40 except for portions of the first metal structure M1 and the second metal structure M2. In Figure 6, the second metal structure M2 has a top surface T2' flush with the top surface of the fifth patterned conductive layer L3. Note that the second metal structure M2 fills the dicing region 111 to the extent that the vertical sidewall V is visible after chip separation. The vertical sidewall V is the dicing edge of the second metal structure M2. The first metal structure M1 demarcates the side surface of the first dielectric layer D1 and is positioned on the first patterned conductive layer L1'. The fourth patterned conductive layer SE2 is positioned on the side and top surfaces of the second dielectric layer D2, thereby separating the second metal structure M2 from the first metal structure M1 and the second dielectric layer D2. The second metal structure M2 also extends below the top surface T1 of the first dielectric layer D1.

[0049] Referring to Figure 7, which illustrates a semiconductor substrate 70 similar to semiconductor substrate 40 except for portions of the first metal structure M1 and the second metal structure M2. In Figure 7, the first metal structure M1 has a top surface T1' flush with the top surface of the third patterned conductive layer L2. Note that the first metal structure M1 fills the dicing region 111 to the extent that the vertical sidewall V is visible after chip separation. The vertical sidewall V is the dicing edge of the first metal structure M1. The second metal structure M2 demarcates the side surface of the second dielectric layer D2 and is positioned on the top surface T1' of the first metal structure M1.

[0050] Referring to FIG8, FIG8 illustrates a semiconductor substrate 80, which is similar to semiconductor substrate 40 except for portions of the first metal structure M1 and the second metal structure M2. In FIG8, the first metal structure M1 is absent at the layer positions of the first dielectric layer D1 and the third patterned conductive layer L2. The second metal structure M2 demarcates the side surfaces of the first dielectric layer D1 and the second dielectric layer D2 down to the layer position of the first patterned conductive layer L1'. In an alternative embodiment not shown in FIG8, the second metal structure M2 fills the dicing region 111 to the extent that the vertical sidewall V is observable after chip separation. In such an alternative embodiment, the vertical sidewall V is the dicing edge of the second metal structure M2.

[0051] Figures 9 through 13 are cross-sectional views illustrating various semiconductor packages according to some embodiments of the present disclosure. Figures 9 through 13 show semiconductor packages 90, 100, 110, 120, and 130 fabricated on corresponding semiconductor substrates 40, 50, 60, 70, and 80 as described in Figures 4 through 8. Details of the corresponding semiconductor substrates 40, 50, 60, 70, and 80 are provided in Figures 4 through 8 of the present disclosure and are therefore omitted here for brevity. In addition to the semiconductor substrates 40, 50, 60, 70, and 80, each of the semiconductor packages 90, 100, 110, 120, and 130 includes a top surface T and a bottom surface B of a dielectric structure D. The bottom surface B is adjacent to the solder bump 901, and the top surface T is opposite to the bottom surface B and closer to the semiconductor chip 202 than the bottom surface B. Semiconductor chip 202 is bonded to corresponding semiconductor substrates 40, 50, 60, 70, and 80 via solder bumps 902 and bonding pads 903 on semiconductor chip 202. Encapsulant 205 encapsulates at least semiconductor chip 202 and bonding pads 903, and encapsulant 205 is positioned on the top surface T of dielectric structure D and in contact with the first patterned conductive layer L1.

[0052] Figures 9 through 13 provide examples of various semiconductor packages including corresponding semiconductor substrates 40, 50, 60, 70, and 80. Other package structures, such as those described in Figures 2A, 2B, and 2C, may also include corresponding semiconductor substrates 40, 50, 60, 70, and 80 and are within the scope of this disclosure.

[0053] Figures 14A to 14F are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 10 according to some embodiments of the present disclosure. In Figure 14A, a carrier 1401 includes a first patterned conductive layer L1. The first patterned conductive layer L1 can be formed by additive manufacturing or subtractive manufacturing. In additive manufacturing, a photoresist (PR) layer is formed before electroplating a conductive material. The conductive pattern is formed after the PR is removed. On the other hand, in subtractive manufacturing, a blanket electroplating of the conductive material is performed before the PR is formed. The conductive material portions not covered by the PR are then removed.

[0054] In Figure 14B, dielectric layer D1 is laminated on top of first patterned conductive layer L1. In Figure 14C, a plurality of openings O1 and O2 are formed in dielectric layer D1 by laser grooving, and openings O1 and O2 are wedge-shaped from the top to the bottom of dielectric layer D1, thereby exposing the top surface of the first patterned conductive layer L1. In some embodiments, at least one opening O1 is formed in dicing region 111, and one opening O2 is formed in conductive patterned region 112'. The opening O1 at dicing region 111 may be a partial via or a cross-section of a saw street extending between multiple units 101. The width W2 of opening O2 in conductive patterned region 112' is from about 50 to 70 μm, and the width W1 of opening O1 in dicing region 111 is from about 250 to 300 μm.

[0055] In Figure 14D, a second patterned conductive layer SE1, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of dielectric layer D1, the sidewalls of openings O1 and O2, and a portion of the first patterned conductive layers L1 and L1'. A third patterned conductive layer L2 is formed on the second patterned conductive layer SE1 by an additive manufacturing operation in both the dicing region 111 and the conductive pattern region 112'. After removing PR in the additive manufacturing operation, the desired pattern is obtained in the third patterned conductive layer L2. The portion of the conductive layer residing in the dicing region 111 is the metal structure M1, and the portion residing in the conductive pattern region 112' is referred to herein as the third patterned conductive layer L2. Due to the fact that width W1 is greater than width W2, when performed under the same plating conditions in a single plating operation, opening O2 is completely filled, while opening O1 is partially filled. In some embodiments, the electroplating operation performed in FIG14D is a pattern plating operation, which is configured to form finer conductive lines that delineate the contours of the openings O1 in the cut line region 111, compared to the panel plating operation described with respect to FIG16D of this disclosure.

[0056] Flash etching is performed to further remove the remaining second patterned conductive layer SE1 initially covered by PR, thereby exposing a portion of the top surface of dielectric layer D1 via the second patterned conductive layer SE1 and the third patterned conductive layer L2. In Figure 14E, solder resist SR is formed on the third patterned conductive layer L2, but the solder resist SR does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells separate at the scribe line region 111. Figure 14F illustrates the semiconductor substrate 10 with a unique metal structure M1 at the scribe line region 111 after separation. The metal structure M1 in the semiconductor substrate 10 enhances heat dissipation without additional fabrication operations through additional copper density, while the unfilled scribe trenches further alleviate substrate warpage issues.

[0057] Figures 15A to 15J are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 40 according to some embodiments of the present disclosure. The descriptions of Figures 15A to 15D can be found by referring to those provided for Figures 14A to 14D, and are not repeated here for brevity. In Figure 15E, a second dielectric layer D2 is laminated over a third patterned conductive layer L2 and filled with partially filled scribe trenches delimited by a first metal structure M1. In Figure 15F, a plurality of openings O3 and O4 are formed in the dielectric layer D2 by laser grooving, and the openings O3 and O4 are wedge-shaped from the top to the bottom of the dielectric layer D2, thereby exposing the top surface of the second patterned conductive layer L2. In some embodiments, at least one opening O3 is formed in a scribe line region 111, and an opening O2 is formed in a conductive pattern region 112'. In some embodiments, opening O3 is aligned with a first opening O1. The opening O1 at the cutting line region 111 may be a partial through hole or a cross-section of a saw cut extending between multiple units 101. The width W3 of the opening O3 in the conductive pattern region 112' is between about 50 and 70 μm, and the width W4 of the opening O4 in the cutting line region 111 is between about 250 and 300 μm.

[0058] In Figure 15G, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of the dielectric layer D2, the sidewalls of openings O3 and O4, and a portion of the first metal structure M1. A fifth patterned conductive layer L3 is formed on the fourth patterned conductive layer SE2 by an additive manufacturing operation in both the dicing region 111 and the conductive pattern region 112'. After removing PR in the additive manufacturing operation, the desired pattern is obtained in the fifth patterned conductive layer L2. The portion of the conductive layer residing in the dicing region 111 is the metal structure M2, and the portion residing in the conductive pattern region 112' is referred to herein as the fifth patterned conductive layer L3. Due to the fact that the width W3 is greater than the width W4, when performed under the same plating conditions in a single plating operation, opening O4 is completely filled, while opening O3 is partially filled. In some embodiments, the plating operation performed in Figure 15G is a patterning plating operation. Flash etching is performed to further remove the remaining fourth patterned conductive layer SE2 initially covered by PR, thereby exposing a portion of the top surface of dielectric layer D2 via the fourth patterned conductive layer SE2 and the fifth patterned conductive layer L3.

[0059] In Figures 15H to 15I, the carrier 1401 is removed from the second side S2 of dielectric layers D1 and D2. Solder resist SR is then formed on the first side S1 and the second side S2 of dielectric layers D1 and D2, but the solder resist SR does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells are separated at the scribe line region 111. Figure 15J illustrates a semiconductor substrate 40 with unique metal structures M1 and M2 at the scribe line region 111 after separation. The metal structures M1 and M2 in the semiconductor substrate 40 enhance heat dissipation through additional copper density without additional fabrication operations, while the unfilled scribe line trenches further alleviate substrate warpage issues.

[0060] Figures 16A to 16L are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 50 according to some embodiments of the present disclosure. The descriptions of Figures 16A to 16C can be found by referring to those provided for Figures 14A to 14C, and are not repeated here for brevity. In Figure 16D, a second patterned conductive layer SE1, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of the dielectric layer D1, the sidewalls of openings O1 and O2, and a portion of the first patterned conductive layers L1 and L1'. A third patterned conductive layer L2' is a panel plated on top of the second patterned conductive layer SE1 in both the dicing region 111 and the conductive pattern region 112'. Compared to the patterning plating operation, the panel plating operation performed in Figure 16D forms thicker conductive lines, thereby completely filling the openings O1 in the dicing region 111 and O2 in the conductive pattern region 112'. In some embodiments, the plating operation of Figure 16D can be performed by patterning plating followed by panel plating.

[0061] Comparing the patterned plating in Figure 14D with the panel plating in Figure 16D, panel plating allows the semiconductor substrate to have a larger volume of conductive material, such as a larger volume of copper, thereby enhancing the mechanical strength or rigidity of the semiconductor substrate. By employing both panel plating and patterned plating in a suitable manner, the volume of conductive material in the opening O1 can be controlled, thereby achieving the desired mechanical strength or rigidity of the semiconductor substrate to prevent foreseeable warping problems.

[0062] In Figure 16E, a reduction operation is performed to remove excess conductive material from above the top surface of dielectric layer D1. In Figure 16F, the third patterned conductive layer L2 is completed by, for example, a subtractive manufacturing process. Following Figure 16E, a conductive layer is deposited on the top surface of dielectric layer D1, followed by the formation of a patterned PR. As shown in Figure 16F, the portion of the conductive layer exposed via the patterned PR is removed, thereby revealing the third patterned conductive layer L2 in the conductive pattern region 112' and the first metal structure M1 in the cut-line region 111. In Figure 16G, a second dielectric layer D2 is laminated on the third patterned conductive layer L2 and covers the first metal structure M1. In Figure 16H, a plurality of openings O3 and O4 are formed in dielectric layer D2 by laser grooving, and the openings O3 and O4 are wedge-shaped from the top to the bottom of dielectric layer D2, thereby exposing the top surface of the second patterned conductive layer L2 and the first metal structure M1. In some embodiments, at least one opening O3 is formed in the cutting line region 111, and an opening O4 is formed in the conductive pattern region 112'. In some embodiments, the opening O3 is aligned with the first opening O1. The opening O1 at the cutting line region 111 may be a partial through-hole or a cross-section of a saw track extending between a plurality of units 101. The width W4 of the opening O4 in the conductive pattern region 112' is between about 50 and 70 μm, and the width W3 of the opening O3 in the cutting line region 111 is between about 250 and 300 μm.

[0063] In Figure 16I, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of dielectric layer D2, the sidewalls of openings O3 and O4, and a portion of the first metal structure M1. A fifth patterned conductive layer L3 and a second metal structure M2 are formed on the fourth patterned conductive layer SE2 in the conductive pattern region 112' and the dicing region 111, respectively. In some embodiments, the formation of the fifth patterned conductive layer L3 and the second metal structure M2 may follow the description of the formation of the third patterned conductive layer L2 and the first metal structure M1 in the current embodiment, and the description therein will not be repeated for the sake of brevity.

[0064] In Figures 16J to 16K, the carrier 1401 is removed from the second side S2 of dielectric layers D1 and D2. Solder resist SR is then formed on the first side S1 and the second side S2 of dielectric layers D1 and D2, but the solder resist SR does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells separate at the scribe line region 111. Figure 16L illustrates a semiconductor substrate 50 with unique metal structures M1 and M2 at the scribe line region 111 after separation. The metal structures M1 and M2 in the semiconductor substrate 50 enhance heat dissipation via additional copper density without additional fabrication operations. Although the scribe trench is filled with conductive material, it better mitigates substrate warpage issues compared to a configuration where only dielectric layers D1 and D2 reside in the scribe line region 111.

[0065] Figures 17A to 17L are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 60 according to some embodiments of the present disclosure. The descriptions of Figures 17A to 17F can be found by referring to the description of Figures 15A to 15F, and are not repeated here for brevity. In Figure 17G, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of the dielectric layer D2, the sidewalls of openings O3 and O4, and portions of the third patterned conductive layer L2 and the first metal structure M1. The fifth patterned conductive layer L3' is a panel plated on top of the fourth patterned conductive layer SE2 in both the dicing region 111 and the conductive pattern region 112'. Compared to the patterning plating operation, the panel plating operation performed in Figure 17G forms thicker conductive lines, thereby completely filling the openings O3 in the dicing region 111 and O4 in the conductive pattern region 112'. In some embodiments, the electroplating operation of Figure 17G can be performed by patterning plating followed by panel plating.

[0066] In Figure 17H, a reduction operation is performed to remove excess conductive material from above the top surface of dielectric layer D2. In Figure 17I, the fifth patterned conductive layer L3 is completed via, for example, a subtractive manufacturing process. Following Figure 17H, a conductive layer is deposited over the top surface of dielectric layer D2, followed by the formation of a patterned PR. As shown in Figure 17I, the portion of the conductive layer exposed via the patterned PR is removed, thereby revealing the fifth patterned conductive layer L3 in the conductive pattern region 112' and the second metal structure M2 in the dicing region 111. Due to the panel plating performed in Figure 17G, the third opening is completely filled with a conductive material such as copper. As previously discussed, this can further enhance the mechanical strength or rigidity of the semiconductor substrate to prevent warping effects.

[0067] In Figures 17J to 17K, the carrier 1401 is removed from the second side S2 of dielectric layers D1 and D2. Solder resist SR is then formed on the first side S1 and the second side S2 of dielectric layers D1 and D2, but the solder resist SR does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells separate at the scribe line region 111. Figure 17L illustrates a semiconductor substrate 60 with unique metal structures M1 and M2 at the scribe line region 111 after separation. The metal structures M1 and M2 in the semiconductor substrate 60 enhance heat dissipation via additional copper density without additional fabrication operations. Although the scribe trench is filled with conductive material, it better mitigates substrate warpage issues compared to a configuration where only dielectric layers D1 and D2 reside in the scribe line region 111.

[0068] Figures 18A to 18L are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 70 according to some embodiments of the present disclosure. The descriptions of Figures 18A to 18H can be found by referring to the descriptions of Figures 16A to 16H, and are not repeated here for brevity. In Figure 18I, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electrodeless plating operation to non-selectively cover the top surface of dielectric layer D2, the sidewalls of openings O3 and O4, a portion of the third patterned conductive layer L2, and the first metal structure M1. A fifth patterned conductive layer L3 is formed on the fourth patterned conductive layer SE2 by an additive manufacturing operation in both the dicing region 111 and the conductive pattern region 112'. After the PR is removed in the additive manufacturing operation, the desired pattern is obtained in the fifth patterned conductive layer L3. The portion of the conductive layer residing in the dicing region 111 is the metal structure M2, and the portion residing in the conductive pattern region 112' is referred to herein as the fifth patterned conductive layer L3. Because width W3 is greater than width W4, when an electroplating operation is performed under the same electroplating conditions, opening O4 is completely filled, while opening O3 is partially filled. In some embodiments, the electroplating operation performed in FIG18I is a patterning operation.

[0069] In Figures 18J to 18K, the carrier 1401 is removed from the second side S2 of dielectric layers D1 and D2. Solder resist SR is then formed on the first side S1 and the second side S2 of dielectric layers D1 and D2, but the solder resist does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells are separated at the scribe line region 111. Figure 18L illustrates a semiconductor substrate 70 with unique metal structures M1 and M2 at the scribe line region 111 after separation. The metal structures M1 and M2 in the semiconductor substrate 70 enhance heat dissipation through additional copper density without additional fabrication operations, while the unfilled scribe line trenches further alleviate substrate warpage issues.

[0070] Figures 19A to 19L are cross-sectional views illustrating various manufacturing stages of a semiconductor substrate 80 according to some embodiments of the present disclosure. The descriptions of Figures 19A to 19B can be found by addressing the descriptions of Figures 14A to 14B, and are not repeated here for brevity. In Figure 19C, a plurality of openings O2 are formed in the dielectric layer D1 by laser grooving, and the openings O2 are wedge-shaped from the top to the bottom of the dielectric layer D1, thereby exposing the top surface of the first patterned conductive layer L1. In some embodiments, the openings O2 are formed only in the conductive patterned region 112' with a width W2 of about 50 to 70 μm. The descriptions of Figures 19D to 19G can be found by addressing the descriptions of Figures 18D to 18G, and are not repeated here for brevity. In Figure 19H, a plurality of openings O3' and O4 are formed in dielectric layer D2 by laser grooving, and the openings O3' and O4 are wedge-shaped from the top to the bottom of dielectric layer D2, thereby exposing the top surface of the first patterned conductive layer L1' and the top surface of the second patterned conductive layer L2, respectively. In some embodiments, at least one opening O3' is formed in the dicing region 111. In some embodiments, the opening O3' is aligned with the first patterned conductive layer L1'. The opening O3' at the dicing region 111 may be a partial via or a cross-section of a sawtooth extending between a plurality of units 101. The width W3 of the opening O3' in the conductive patterned region 112' is between about 250 and 300 μm, and the width W4 of the opening O4 in the dicing region 111 is between about 50 and 70 μm.

[0071] In Figure 19I, a fourth patterned conductive layer SE2, such as a seed layer, is formed non-selectively over the top surface of dielectric layer D2, the sidewalls of openings O3' and O4, a portion of the second patterned conductive layer L2, and the first patterned conductive layer L1' by an electrodeless plating operation. A fifth patterned conductive layer L3 is formed on the fourth patterned conductive layer SE2 by an additive manufacturing operation in both the cut-line region 111 and the conductive pattern region 112'. After removing PR in the additive manufacturing operation, the desired pattern is obtained in the fifth patterned conductive layer L3. The portion of the conductive layer residing in the cut-line region 111 is the metal structure M2, and the portion residing in the conductive pattern region 112' is referred to herein as the fifth patterned conductive layer L3. Due to the fact that the width W3 is greater than the width W4, when performed under the same plating conditions in a single plating operation, opening O4 is completely filled, while opening O3 is partially filled. In some embodiments, the plating operation performed in Figure 19I is a patterning plating operation.

[0072] Alternatively, in FIG19I, the fifth patterned conductive layer L3 can be formed on the fourth patterned conductive layer SE2 by a subtractive manufacturing operation, for example, as described in FIG17G to FIG17I, wherein the opening O3' is completely filled with conductive material, thereby enhancing the rigidity of the semiconductor substrate 80. It should be noted that in FIG19I, the second metal structure M2 is in direct contact with the first patterned conductive layer L1' in the diced area 111, and the first metal structure M1 is not present.

[0073] In Figures 19J to 19K, the carrier 1401 is removed from the second side S2 of dielectric layers D1 and D2. Solder resist SR is then formed on the first side S1 and the second side S2 of dielectric layers D1 and D2, but does not cover the scribe line region 111. After chip bonding and molding operations (not shown), individual cells are separated at the scribe line region 111. Figure 19L illustrates a semiconductor substrate 80 with unique metal structures M1 and M2 at the scribe line region 111 after separation. The metal structures M1 and M2 in the semiconductor substrate 80 enhance heat dissipation through additional copper density without additional fabrication operations, while the unfilled scribe line trenches further alleviate substrate warpage issues.

[0074] The foregoing outlines several embodiments and detailed features of this disclosure. The embodiments described herein can be readily used as a basis for designing or modifying other processes and for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor substrate comprising: First dielectric layer; A second dielectric layer is placed on top of the first dielectric layer; a first metal structure is placed on the top surface of the first dielectric layer. And a second metal structure, which is on the top surface of the second dielectric layer and outside the side surface of the second dielectric layer, the second metal structure extending to a layer below the top surface of the first dielectric layer, and the side surface of the second metal structure being exposed, wherein the first metal structure and the second metal structure partially overlap and partially do not overlap in the horizontal direction.

2. The semiconductor substrate according to claim 1, wherein the first metal structure has a stepped structure and the stepped structure is outside the side surface of the first dielectric layer.

3. The semiconductor substrate of claim 2, further comprising a first patterned conductive layer disposed in the first dielectric layer, wherein the first patterned conductive layer partially overlaps the first metal structure in the vertical direction.

4. The semiconductor substrate of claim 1, further comprising a second patterned conductive layer disposed in the second dielectric layer, wherein the second patterned conductive layer partially overlaps the second metal structure in the horizontal direction.

5. The semiconductor substrate of claim 1, wherein the side surface of the first dielectric layer and the side surface of the second dielectric layer are offset.

6. The semiconductor substrate of claim 3, wherein the second dielectric layer is above and covers the first patterned conductive layer, wherein the second metal structure extends outside the side surface of the second dielectric layer and outside the first patterned conductive layer.

7. The semiconductor substrate of claim 6, wherein the first patterned conductive layer is substantially aligned with the second patterned conductive layer disposed in the second dielectric layer.

8. The semiconductor device substrate of claim 3, wherein the second metal structure partially overlaps with both the first dielectric layer and the second dielectric layer in the horizontal direction.

9. The semiconductor substrate of claim 2, wherein the side surface of the first metal structure is substantially aligned with the side surface of the second metal structure.

10. The semiconductor substrate of claim 3, wherein the second metal structure covers a portion of the side surface of the first metal structure.

11. A semiconductor package comprising: First dielectric layer; The second dielectric layer is located below the first dielectric layer; A semiconductor chip, located above the top surface of the first dielectric layer; A first metallic structure is located adjacent to the first dielectric layer; And a second metal structure adjacent to the second dielectric layer, the second metal structure extending on the side surface of the second dielectric layer to a layer beyond the bottom surface of the second dielectric layer, and the side surface of the second metal structure being exposed, wherein the first metal structure and the second metal structure partially overlap and partially do not overlap in the horizontal direction.

12. The semiconductor package of claim 11, wherein the side surface of the first dielectric layer is a sloped surface.

13. The semiconductor package of claim 12, wherein the side surface of the first dielectric layer tapers toward the second dielectric layer.

14. The semiconductor package of claim 11, wherein the side surface of the second dielectric layer is a sloped surface.

15. The semiconductor package of claim 14, wherein the side surface of the second dielectric layer tapers toward the solder bump, the solder bump being disposed beneath the second dielectric layer.

16. The semiconductor package of claim 15, wherein the solder bump is directly below the solder bump of the semiconductor chip.

17. The semiconductor package of claim 11, wherein the first metal structure has a stepped structure adjacent to the second metal structure.

18. The semiconductor package of claim 11, further comprising an encapsulant for encapsulating the semiconductor chip and the first dielectric layer.

19. The semiconductor package of claim 11, wherein the first metal structure is disposed on the second dielectric layer, and the outer portion of the first metal structure is on the second metal structure.

20. A method for manufacturing a semiconductor package, comprising: Provide a carrier; form a first patterned conductive layer on the carrier; A dielectric structure is formed on the first patterned conductive layer; A cut-line region is defined in the dielectric structure by forming an opening in the dielectric structure; and a second patterned conductive layer is simultaneously formed on the dielectric structure and enters the opening.

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