A 48-pulse rectifier

Abstract

This invention provides a 48-pulse rectifier, belonging to the field of power electronics technology. Addressing the weakness of traditional DC-side pulse multiplication methods in multi-pulse rectifiers, this invention proposes a novel passive pulse quadruple multiplication method. Compared to existing pulse multiplication methods, this method improves the harmonic suppression performance of the multi-pulse rectifier without increasing the total capacity of magnetic components or diode losses. The multi-pulse rectifier described in this invention combines transformer rectification technology with a DC-side pulse multiplication method, significantly reducing input current harmonics and output voltage ripple without using active components.

Description

Technical Field

[0001] This invention belongs to the field of power electronics, and specifically relates to a parallel 48-pulse rectifier using a passive pulse quadruple amplification method. Background Technology

[0002] Multi-pulse rectifiers, with their advantages of simple structure and high reliability, are often used as the front-end rectifier interface for high-power industrial equipment connecting to the power grid. The power quality of the AC and DC sides of a multi-pulse rectifier depends on its pulse count. Currently, there are two main methods to increase the system's pulse count: increasing the number of output phases of the phase-shifting transformer and using a passive pulse multiplication method on the DC side. However, excessively increasing the number of phases of the phase-shifting transformer increases its winding complexity, significantly increasing its manufacturing difficulty and cost. While the passive pulse multiplication method on the DC side is simple to implement and low in cost, existing methods can only achieve a two- or three-fold increase in the pulse count, limiting its multiplication capability. Without increasing the winding complexity of the phase-shifting transformer, using existing passive pulse multiplication methods may result in a high total harmonic distortion (THD) of the rectifier's input current and an excessively large output voltage ripple factor. Therefore, in order to reduce the manufacturing cost of multi-pulse rectifier systems and improve their power quality, it is urgent to develop a DC-side passive pulse multiplication method that has strong pulse multiplication capability, simple structure and low cost. Summary of the Invention

[0003] The purpose of this invention is to provide a novel passive pulse quadruple multiplier circuit to address the performance limitations of existing pulse multiplication methods. A star-connected autotransformer is used as the phase-shifting transformer, combined with the proposed passive pulse quadruple multiplier circuit, to construct a novel 48-pulse rectifier. The proposed rectifier has a simple structure and is easy to implement, effectively improving the AC and DC power quality of the rectifier without increasing the capacitance of magnetic components or diode losses.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] This invention discloses a 48-pulse rectifier, comprising: a phase-shifting transformer, two sets of diode rectifier bridges, a zero-sequence current suppressor, a pulse quadruple multiplier circuit, and a load. The pulse quadruple multiplier circuit consists of a pulse multiplier circuit one and a pulse multiplier circuit two. The input terminal of the phase-shifting transformer is connected to a three-phase power grid, and the two sets of three-phase voltages output from the phase-shifting transformer are respectively input to the three-phase input terminals of the two sets of three-phase diode rectifier bridges. On the output side of the first three-phase diode rectifier bridge, the common cathode of the upper arm diode and the common anode of the lower arm diode are respectively connected to terminals m1 and m3 of the zero-sequence current suppressor; on the output side of the second three-phase diode rectifier bridge, the common cathode of the upper arm diode and the common anode of the lower arm diode are respectively connected to terminals m2 and m4 of the zero-sequence current suppressor. Terminals n1 and n2 of the zero-sequence current suppressor are respectively connected to the two ends of the primary winding of the first pulse multiplier circuit, and terminals n3 and n4 of the zero-sequence current suppressor are respectively connected to the two ends of the primary winding of the second pulse multiplier circuit. The common cathode of the two auxiliary diodes on the primary side of pulse multiplier circuit one is connected to the positive terminal of the load. The center tap of the primary winding of pulse multiplier circuit two is connected to the negative terminal of the load. The common cathode of the two auxiliary diodes on the secondary side of pulse multiplier circuit one and pulse multiplier circuit two are respectively connected to the positive terminal of the load. The center tap of the secondary winding of pulse multiplier circuit one and pulse multiplier circuit two is respectively connected to the negative terminal of the load.

[0006] The present invention discloses a 48-pulse rectifier, wherein the phase-shifting transformer is a star-type autotransformer, and its windings are connected in a phase-shifting multiple manner to convert the input three-phase AC voltage into two sets of three-phase AC voltage outputs with a phase difference of 30°.

[0007] The present invention discloses a 48-pulse rectifier, wherein the input side of the two sets of three-phase rectifier bridges of the main circuit is connected to the two sets of three-phase voltage output terminals of the main transformer, and the output terminal is connected to the pulse four-fold multiplier circuit through a zero-sequence current suppressor.

[0008] The present invention discloses a 48-pulse rectifier, wherein the zero-sequence current suppressor consists of four windings, and the zero-sequence impedance in the circuit is increased according to the differential mode connection method to suppress the zero-sequence current.

[0009] The present invention discloses a 48-pulse rectifier, wherein the pulse multiplier circuit consists of a double-tapped balancing reactor with a secondary winding and four auxiliary diodes.

[0010] The present invention provides a 48-pulse rectifier, wherein the pulse multiplier circuit II consists of a center-tapped balancing reactor II with a secondary winding and two auxiliary diodes.

[0011] By adopting the above technical solution, the present invention has the following advantages over the prior art:

[0012] 1) Compared with the current source input series type multi-pulse rectifier, the 48-pulse rectifier of this invention does not require a large inductor in series on the input side, nor does it require an electrolytic capacitor in parallel on the DC side. The load is directly connected to two sets of pulse multiplier circuits. The output voltage ripple coefficient can be reduced to below 1% by relying solely on the modulation effect of the pulse quadruple circuit, thereby improving the input power factor and reducing hardware costs.

[0013] 2) Compared to the 36-pulse rectifier using the traditional dual passive harmonic suppression method, the 48-pulse rectifier of this invention improves the system's harmonic suppression performance by 1 / 3 simply by adding a pulse multiplier circuit. Although the proposed pulse quadruple multiplier circuit uses an additional set of balancing reactors compared to the dual passive harmonic suppression circuit, the total capacity of the magnetic components does not increase.

[0014] 3) The passive pulse quadruple booster circuit proposed in this invention has only two auxiliary diodes connected in series with the load, while the remaining four auxiliary diodes are connected in parallel with the load. Since the effective value of the current flowing through the auxiliary diodes connected in parallel with the load is extremely small when they are turned on, the total conduction loss of the auxiliary diodes in this method is low.

[0015] 4) The passive pulse quadruple-amplifier circuit proposed in this invention is highly versatile and can be applied to any phase-shifting transformer, not just the star-connected autotransformer in this example. By optimizing the turns ratio of the balancing reactor, the pulse number of any multi-pulse rectifier system can be increased to four times, and its input current harmonics can be reduced to about 1 / 4 of the original. The 48-pulse rectifier proposed in this invention has a simple structure, high reliability, and strong harmonic suppression capability, making it suitable for various high-power rectification applications. Attached Figure Description

[0016] The above and other objects, features and advantages of the invention will become clearer from the following description with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a topology diagram of a 48-pulse rectifier according to an embodiment of the present invention.

[0018] Figure 2 This is a topology diagram of a pulse quadruple circuit for a 48-pulse rectifier according to an embodiment of the present invention.

[0019] Figure 3 This is a winding structure diagram of the balancing reactor of a pulse multiplier circuit for a 48-pulse rectifier according to an embodiment of the present invention.

[0020] Figure 4 This is a winding structure diagram of the balancing reactor two in a pulse multiplier circuit two of a 48-pulse rectifier according to an embodiment of the present invention.

[0021] Figure 5The diagram shows the operating voltage waveform of a pulse quadruple booster circuit for a 48-pulse rectifier according to an embodiment of the present invention.

[0022] Figure 6 The diagram shows the operating current waveform of a pulse quadruple booster circuit for a 48-pulse rectifier according to an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the pulse quadruple booster circuit operating mode 1 of a 48-pulse rectifier according to an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the pulse quadruple booster circuit operating mode 2 of a 48-pulse rectifier according to an embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of the pulse quadruple booster circuit operating mode 3 of a 48-pulse rectifier according to an embodiment of the present invention.

[0026] Figure 10 This is a schematic diagram of the pulse quadruple multiplier circuit operating mode 4 of a 48-pulse rectifier according to an embodiment of the present invention.

[0027] Figure 11 This is a schematic diagram of the pulse quadruple booster circuit operating mode 5 of a 48-pulse rectifier according to an embodiment of the present invention.

[0028] Figure 12 This is a simulation diagram of the three-phase input current of a 48-pulse rectifier according to an embodiment of the present invention.

[0029] Figure 13 This is a schematic diagram of the input current spectrum of a 48-pulse rectifier according to an embodiment of the present invention.

[0030] Figure 14 This is a simulation diagram of the output voltage of a 48-pulse rectifier according to an embodiment of the present invention.

[0031] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 in i a i b i c For three-phase input current; i a1 i b1 i c1 i a2 i b2 i c2 These are the output winding currents of the phase-shifting transformer; i d1 i d2 The output currents of three-phase rectifier bridge one and three-phase rectifier bridge two are respectively, i m1to i m5 These represent the voltage levels in each mode; u d1 u d2 These are the output voltages of three-phase rectifier bridge one and three-phase rectifier bridge two, respectively; u d i d These represent the load voltage and current, respectively; i s1 i s2 These represent the output currents of the secondary single-phase full-wave rectifier circuits in pulse multiplier circuit one and pulse multiplier circuit two, respectively; D1 to D6 represent the auxiliary diodes, respectively; N p1 The number of turns (n1 to n2) between the two ends of the primary winding of the balancing reactor in the pulse multiplier circuit is 2N. p11 N is the number of turns between the two taps (P1 to Q1) of the primary winding of the balancing reactor. s1 N is the number of turns between the two ends of the secondary winding of the balancing reactor and the center tap (L1 to S1, M1 to S1); p2 N represents the number of turns (n3 to n4) between the two ends of the primary winding of the balancing reactor 2 in the pulse multiplier circuit 2. s2 This refers to the number of turns between the two ends of the secondary winding of the balancing reactor and the center tap (L2 to S2, M2 to S2); the n1 terminal of the primary winding of the balancing reactor and the L1 terminal of the secondary winding are the same name terminals; the n3 terminal of the primary winding of the balancing reactor and the L2 terminal of the secondary winding are the same name terminals; u p1 To balance the terminal voltage between terminals n1 and n2 of the primary winding of the reactor, u s1 The voltage u is the voltage between terminal L1 of the secondary winding and terminal S1 of the pulse multiplier circuit. p2 To balance the terminal voltage between terminals n3 and n4 of the primary winding of the reactor, u s2 This is the voltage between the L2 terminal of the secondary winding of the pulse multiplier circuit and the S2 terminal of the intermediate winding. Detailed Implementation

[0032] To better understand the technical solution of the present invention, the working principle and implementation methods of the present invention will be further described below with reference to the accompanying drawings. The following embodiments or drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0033] Example 1: As Figure 1 as well as Figure 2As shown, the 48-pulse rectifier involved in this embodiment consists of a phase-shifting transformer, a diode rectifier bridge one, a diode rectifier bridge two, a zero-sequence current suppressor, a pulse multiplier circuit one, and a pulse multiplier circuit two. The input terminal of the phase-shifting transformer is connected to the three-phase power grid, and the two sets of three-phase voltages output by the phase-shifting transformer are respectively input to the input sides of the two sets of three-phase diode rectifier bridges. The output side of the three-phase diode rectifier bridge one is connected to the m1 and m3 terminals of the zero-sequence current suppressor, and the output side of the three-phase diode rectifier bridge two is connected to the m2 and m4 terminals of the zero-sequence current suppressor, respectively. The n1 and n2 terminals of the zero-sequence current suppressor are respectively connected to the two ends of the primary winding of the pulse multiplier circuit one, and the n3 and n4 terminals of the zero-sequence current suppressor are respectively connected to the two ends of the primary winding of the pulse multiplier circuit two. The primary output terminal of pulse multiplier circuit one and the center tap of the primary side of pulse multiplier circuit two are connected to the positive and negative terminals of the load, respectively. The common cathodes of the two auxiliary diodes on the secondary side of pulse multiplier circuit one and pulse multiplier circuit two are connected to the positive terminal of the load, respectively. The center taps of the secondary windings of pulse multiplier circuit one and pulse multiplier circuit two are connected to the negative terminal of the load, respectively.

[0034] Using a star-connected autotransformer as a phase-shifting transformer reduces the capacity of the main transformer, thereby reducing its size and cost. Based on a 12-pulse rectifier constructed from a star-connected autotransformer, the proposed passive pulse quadruple amplification method can multiply the pulses from 12 to 48, reducing the theoretical THD of the input current from 15.2% to 3.8%. Compared to existing pulse multiplication methods, the proposed passive pulse quadruple amplification method exhibits stronger harmonic suppression without increasing the total capacity and losses of the magnetic components.

[0035] Example 2: Figure 3 as well as Figure 4 As shown, the 48-pulse rectifier involved in this embodiment has an auxiliary circuit composed of a pulse multiplier circuit one and a pulse multiplier circuit two. Pulse multiplier circuit one consists of a double-tapped balancing reactor with a secondary winding and four diodes. Pulse multiplier circuit two consists of a center-tapped balancing reactor with a secondary winding and two diodes. The turns ratio of each winding in balancing reactor one is N. p1 :N p11 :N s1 =20:5:288, the turns ratio of each winding in the second balancing reactor is N. p2 :N s2 =5:142.

[0036] Example 3: This example involves a 48-pulse rectifier. The pulse 4x4 multiplier circuit has five operating modes. The output current of the three-phase rectifier bridge in the main circuit is modulated into an 8-step wave with four non-zero levels through the five operating modes of the pulse 4x4 multiplier circuit. The five operating modes of the pulse 4x4 multiplier circuit are as follows: Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 As shown.

[0037] Working mode 1: such as Figure 5 As shown, when u p1 >0, u p2 <0, and u s1 >u d ,|u s2 |>u d When D1, D3, and D6 are turned on, the remaining auxiliary diodes are turned off, and the pulse quadruple multiplier circuit operates in mode 1. According to the ampere-turn balance theorem, the injected current i across the pulse quadruple multiplier circuit in mode 1 can be obtained. d1 with i d2 The level values ​​are respectively

[0038] (1)

[0039] Working mode 2: such as Figure 5 As shown, when u p1 Descending to u s1 d , and |u s2 |>u d At this time, the single-phase full-wave rectifier circuit on one side of the pulse multiplier circuit is turned off due to reverse voltage. D1 and D6 are turned on, while the remaining auxiliary diodes are turned off, and the pulse quadruple multiplier circuit operates in mode 2. According to the ampere-turn balance theorem, we can obtain...

[0040] (2)

[0041] Working mode 3: such as Figure 5 As shown, when u p1 Decrease and remain at zero, u p2 From less than zero to greater than zero and |u s2 | d At this time, the single-phase full-wave rectifier circuits on the two secondary sides of the pulse multiplier circuit are turned off due to reverse voltage. Only D1 and D2 are turned on and share the load current i. d The pulse quadruple amplifier circuit operates in mode 3. According to the ampere-turn balance theorem, we can obtain...

[0042] (3)

[0043] Working mode 4: such as Figure 5 As shown, when u p1 <0, u p2 >0, and |u s1 | d u s2 >u​​​d When D2 and D5 are turned on, the remaining auxiliary diodes are turned off, and the pulse 4x multiplier circuit operates in mode 4. Based on the mode symmetry, we can obtain...

[0044] (4)

[0045] Working mode 5: such as Figure 5 As shown, when u p1 Continue to descend to |u s1 |>u d , and u s2 >u d When D2, D4, and D5 are turned on, the remaining auxiliary diodes are turned off, and the pulse 4x multiplier circuit operates in mode 5. Based on the symmetry of the modes, we can obtain...

[0046] (5)

[0047] According to equations (1) to (5), the pulse quadruple amplifier circuit can increase the output current i of the two sets of three-phase rectifier bridges in the main circuit. d1 and i d2 Modulation as Figure 6 The two identical 8-step waves shown have a 30° phase difference and four non-zero level values. The pulse quadrupler circuit operates according to the mode sequence 3-4-5-4-3-2-1-2-3… within one power cycle, simultaneously increasing the input current step number and output voltage pulse number of the rectifier to four times their original values. Combined with the winding structure of the star autotransformer, 48-pulse rectification can be achieved, reducing the input current harmonics to one-quarter of that without the pulse quadrupler circuit.

[0048] Example 4: To verify the correctness of the topology and theory in the above examples, a simulation model was built using Simulink software. The input source was a three-phase voltage with an effective value of 220V and a frequency of 50Hz, and the output resistive load was 30Ω. Figure 12 As shown, the input current of this 48-pulse rectifier has 48 steps within one cycle, approaching a sine wave. Figure 13 As shown, the THD value of the input current is 3.65%, which is less than 5%, meeting the IEEE-519 standard. The lowest harmonic order is 47, conforming to the pattern of 48-pulse rectification. Since the THD value of the input current of the 12-pulse rectifier is 15.2% without the pulse quadrupler circuit, it is evident that the proposed pulse quadrupler circuit can reduce the input current harmonics to 1 / 4 of the original value. Compared to the dual passive harmonic suppression circuit, the harmonic suppression performance is improved by approximately 1 / 3. Figure 14 As shown, the output load voltage u d It has 48 wavefronts of equal width and height within one cycle, and the ripple factor is less than 1%.

[0049] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 48-pulse rectifier characterized by: The pulse multiplication circuit one (5) and the pulse multiplication circuit two (6) constitute a passive pulse four multiplication circuit; the phase-shifting transformer (1) performs phase-shifting on three-phase voltage input by a power grid, and outputs two groups of three-phase voltages with the same amplitude and a phase difference of 30°, and the two groups of three-phase voltages are input to the diode rectifier bridge one (2) and the diode rectifier bridge two (3) respectively; the common cathode of the upper bridge arm diode of the diode rectifier bridge one (2) and the common anode of the lower bridge arm diode are connected to the m1 and m3 terminals of the zero sequence current suppressor (4) respectively; the common cathode of the upper bridge arm diode of the diode rectifier bridge two (3) and the common anode of the lower bridge arm diode are connected to the m2 and m4 terminals of the zero sequence current suppressor (4) respectively; the n1 and n2 terminals of the zero sequence current suppressor (4) are connected to the two ends of the primary winding of the pulse multiplication circuit one (5) respectively, and the n3 and n4 terminals of the zero sequence current suppressor (4) are connected to the two ends of the primary winding of the pulse multiplication circuit two (6) respectively; the common cathode of the two auxiliary diodes D1 and D2 on the primary side of the pulse multiplication circuit one (5) is connected to the positive electrode of a load, and the center tap of the primary winding of the pulse multiplication circuit two (6) is connected to the negative electrode of the load, the common cathode of the two auxiliary diodes D3 and D4 on the secondary side of the pulse multiplication circuit one (5) and the two auxiliary diodes D5 and D6 on the secondary side of the pulse multiplication circuit two (6) are connected to the positive electrode of the load respectively, and the center taps of the secondary windings of the pulse multiplication circuit one (5) and the pulse multiplication circuit two (6) are connected to the negative electrode of the load respectively. The passive pulse four multiplication circuit has five working modes: Operating mode 1: when u p1 > 0, u p2 < 0, and u s1 = N s1 u p1 / N p1， u s1 > u d , D1, D3, D6 are on, the rest of the auxiliary diodes are off, wherein u s1 = N s1 u p1 / N p1 , |u s2 | = |N s2 u p2 / N p2 |; Working mode 2: when u p1 Down to u s1 < u d , and |u s2 |>u d , the pulse doubling circuit (5) secondary side single-phase full-wave rectifier circuit withstands reverse pressure off, at this time D1, D6 are turned on, the rest of the auxiliary diode is off; Working mode 3: when u p1 Down and keep zero, u p2 From less than zero to greater than zero and |u s2 | <u d At this time, the secondary side of the pulse doubling circuit two (6) single-phase full-wave rectifier circuit is closed under the reverse pressure, at this time only D1, D2 are turned on and share the load current i d ; Operating mode 4: when u p1 Continuing to decrease below zero and |u s1 | < u d , u p2 Continuing to increase and u s2 > u d , D2, D5 are on, the rest of the auxiliary diodes are off; Operating mode 5: when u p1 Continuing to decrease |u s1 |>u d , and u s2 >u d , D2, D4, D5 are on, and the rest of the auxiliary diodes are off; wherein, u p1 is the terminal voltage between the primary winding n1 and n2 of the balancing reactor, u s1 is the voltage between the terminal of the secondary winding L1 and the intermediate terminal S1 of the pulse multiplication circuit (5); u p2 is the terminal voltage between the primary winding n3 and n4 of the balancing reactor, u s2 is the voltage between the terminal of the secondary winding L2 and the intermediate terminal S2 of the pulse multiplication circuit (6); u d and i d are the load voltage and current, respectively; The passive pulse four multiplication circuit is switched in a time sequence of "3-4-5-4-3-2-1-2-3" according to the working modes in a power supply cycle.

2. A 48-pulse rectifier according to claim 1, characterized in that: The phase-shifting transformer (1) is a star autotransformer, consisting of three core columns, a three-phase structure is symmetrical, each core column contains 1 input winding and 2 output windings, wherein the number of turns of the 3 input windings is N1, the number of turns of the 6 output windings is N2, and the winding turn ratio is =1:(2 ).

3. A 48-pulse rectifier according to claim 1, characterized in that: The zero sequence current suppressor (4) is composed of four windings and connected in a differential mode.

4. A 48-pulse rectifier according to claim 1, characterized in that: The pulse multiplication circuit (5) is composed of a primary winding with double taps, a secondary winding with a center tap and four diodes, the number of turns between n1 and n2 of the primary winding of the first balanced reactor is N p1 , the number of turns between tap P1 and tap Q1 of the primary winding is 2N p11 ; the number of turns between L1 terminal and M1 terminal to the center tap S1 of the secondary winding of the first balanced reactor is N s1 ; the turn ratio of the first balanced reactor is N p1 :N p11 :N s1 =20:5:

288.

5. A 48-pulse rectifier according to claim 1, characterized in that: The pulse multiplication circuit two (6) is composed of a primary winding with center tap, a secondary winding with center tap and two diodes, the turns between n3 and n4 of the primary winding of the second balanced reactor are N p2 , the turns between L2 terminal and M2 terminal to the center tap S2 of the secondary winding of the second balanced reactor are N s2 ; the turns ratio of the second balanced reactor is N p2 :N s2 =5:142.

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