Pipeline analog-to-digital converter and error calibration method thereof

Abstract

The invention discloses a pipeline analog-to-digital converter and an error calibration method thereof, the pipeline analog-to-digital converter comprises a first sub-level ADC, a second sub-level ADC and a digital processing unit, the first sub-level ADC comprises a first capacitor array and a calibration control unit, the first capacitor array adjusts an array connection structure under the control of the calibration control unit, and the second capacitor array adjusts an array connection structure under the control of the calibration control unit. The second sub-stage ADC outputs a first digital signal and a second digital signal; the digital processing unit determines a calibration weight corresponding to the first sub-level ADC based on the first digital signal and the second digital signal; and calibrating the initial digital signal output by the first sub-level ADC according to the calibration weight to obtain a target digital signal. The digital signal for determining the calibration weight comprises the capacitor mismatch error information and the interstage gain error information, so that the two errors are calibrated at the same time through calibration of the calibration weight, the conversion precision of the analog-to-digital converter is improved, and the performance of the analog-to-digital converter is improved.

Description

Technical Field

[0001] The invention relates to the technical field of analog-to-digital conversion, and in particular to a pipeline analog-to-digital converter and an error calibration method thereof. Background Art

[0002] As the operating frequency and processing accuracy of hybrid digital-analog system chips continue to increase, the performance requirements for the analog-to-digital converter (ADC) inside the chip are also getting higher and higher. Pipelined-Successive Approximation Register ADC (Pipelined-SAR ADC) is an analog-to-digital converter that takes into account high sampling rate, high accuracy and low power consumption, and has become the mainstream architecture of analog-to-digital converter research in recent years.

[0003] In the related art, there are two errors in the pipelined successive approximation analog-to-digital converter, namely, the inter-stage gain error and the capacitance mismatch error of the sub-stage SAR ADC. The existence of the above two errors affects the conversion accuracy of the pipelined successive approximation analog-to-digital converter and reduces the performance of the pipelined successive approximation analog-to-digital converter.

[0004] Therefore, the calibration of inter-stage gain error and capacitor mismatch error of sub-stage SAR ADC is a technical problem that needs to be solved urgently in the design process of pipelined successive approximation analog-to-digital converter. Summary of the invention

[0005] The present invention provides a pipeline analog-to-digital converter and an error calibration method thereof, which are used to solve the problem of reduced conversion accuracy caused by the existence of inter-stage gain error and capacitor mismatch error in the existing pipeline successive approximation analog-to-digital converter.

[0006] In a first aspect, an embodiment of the present invention provides a pipeline analog-to-digital converter, comprising a first sub-stage ADC, a second sub-stage ADC and a digital processing unit electrically connected in sequence, wherein the first sub-stage ADC comprises a first capacitor array and a calibration control unit, wherein:

[0007] The first capacitor array adjusts its own array connection structure under the control of the calibration control unit so that the second sub-stage ADC outputs the first digital signal and the second digital signal;

[0008] Wherein, the first digital signal is determined according to a first residual voltage signal output by the first sub-ADC when the array connection structure of the first capacitor array is a first array connection structure, and the second digital signal is determined according to a second residual voltage signal output by the first sub-ADC when the array connection structure of the first capacitor array is a second array connection structure;

[0009] The digital processing unit determines a calibration weight corresponding to the first sub-ADC based on the first digital signal and the second digital signal;

[0010] The digital processing unit calibrates an initial digital signal output by the first sub-ADC according to the calibration weight to obtain a target digital signal.

[0011] In the pipelined analog-to-digital converter provided by the embodiment of the present invention, since the first digital signal and the second digital signal are generated by the first sub-ADC and the second sub-ADC, the first digital signal and the second digital signal include capacitance mismatch error information corresponding to the first sub-ADC, and inter-stage gain error information between the first sub-ADC and the second sub-ADC. By calibrating the initial digital signal output by the first sub-ADC with the calibration weight determined by the first digital signal and the second digital signal, simultaneous calibration of the inter-stage gain error and the capacitance mismatch error is achieved, the complexity of error calibration for the pipelined analog-to-digital converter is reduced, the conversion accuracy of the pipelined analog-to-digital converter is improved, and the performance of the pipelined analog-to-digital converter is improved.

[0012] In an optional embodiment, the first capacitor array includes a compensation capacitor group and a plurality of bit capacitor groups;

[0013] For any one of the plurality of bit capacitor groups, the calibration control unit is specifically configured to perform the following operations:

[0014] Control the first end of the bit capacitor group to be electrically connected to the reference voltage terminal, control the second end of the bit capacitor group to be grounded, and

[0015] Control the first ends of the other bit capacitor groups except the bit capacitor group among the plurality of bit capacitor groups, the second ends of the other bit capacitor groups, the first end of the compensation capacitor group, and the second end of the compensation capacitor group to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a first digital signal corresponding to the bit capacitor group.

[0016] In the above pipelined analog-to-digital converter, during the process of determining the calibration weight corresponding to any one of the multiple bit capacitor groups in the first capacitor array, the calibration control unit controls the first end of the bit capacitor group to be electrically connected to the reference voltage terminal, the second end of the bit capacitor group to be grounded, and controls all other capacitor groups in the first capacitor array to be electrically connected to the common-mode voltage terminal, so that the array structure of the first capacitor array is adjusted to the first array connection structure. At this time, the first sub-ADC outputs a first residual voltage corresponding to the bit capacitor group, and the second sub-ADC determines a first digital signal corresponding to the bit capacitor group according to the first residual voltage corresponding to the bit capacitor group. The first digital signal determined in the above manner contains capacitance error information corresponding to the bit capacitor group and inter-stage gain errors between different sub-ADCs.

[0017] In an alternative embodiment, for any one of the other bit capacitor groups among the multiple bit capacitor groups except the first bit capacitor group, the calibration control unit is specifically configured to perform the following operations:

[0018] Control the first ends of the first bit capacitor group to the first end of the bit capacitor group and the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal, control the second ends of the first bit capacitor group to the second end of the previous bit capacitor group and the second end of the compensation capacitor group to be grounded, and

[0019] Control the first ends of the bit capacitor group to the first end of the last bit capacitor group and the second ends of the bit capacitor group to the second end of the last bit capacitor group to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a second digital signal corresponding to the bit capacitor group.

[0020] In the above pipelined analog-to-digital converter, during the process of determining the calibration weight corresponding to any one of the other bit capacitor groups among the multiple bit capacitor groups except the first bit capacitor group, the calibration control unit controls the first ends of the first bit capacitor group to the first end of the bit capacitor group to be electrically connected to the reference voltage terminal, the second ends of the first bit capacitor group to the second end of the previous bit capacitor group to be grounded, and controls all other capacitor groups in the first capacitor array to be electrically connected to the common-mode voltage terminal, so that the array structure of the first capacitor array is adjusted to the second array connection structure. At this time, the first sub-ADC outputs a second residual voltage corresponding to the bit capacitor group, and the second sub-ADC determines a second digital signal corresponding to the bit capacitor group according to the second residual voltage corresponding to the bit capacitor group. The second digital signal determined in the above manner contains capacitance error information corresponding to the bit capacitor group and inter-stage gain errors between different sub-ADCs.

[0021] In an alternative embodiment, for the first bit capacitance group among the multiple bit capacitance groups, the calibration control unit is specifically configured to perform the following operations:

[0022] Control the first end of the first bit capacitance group to be grounded, control the second end of the first bit capacitance group to be electrically connected to the reference voltage terminal, and

[0023] Control the first end of the compensation capacitance group, the second end of the compensation capacitance group, the first ends of the other bit capacitance groups except the first bit capacitance group among the multiple bit capacitance groups, and the second ends of the other bit capacitance groups except the first bit capacitance group among the multiple bit capacitance groups to be all electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a second digital signal corresponding to the first bit capacitance group.

[0024] In the above pipelined analog-to-digital converter, during the process of determining the calibration weight corresponding to the first bit capacitance group among the multiple bit capacitance groups, the calibration control unit controls the first end of the first bit capacitance group to be grounded, the second end of the first bit capacitance group to be electrically connected to the reference voltage terminal, and controls all the other capacitance groups in the first capacitance array to be electrically connected to the common-mode voltage terminal, so that the array structure of the first capacitance array is adjusted to a second array connection structure. At this time, the first sub-ADC outputs a second residue voltage corresponding to the first bit capacitance group, and the second sub-ADC determines a second digital signal corresponding to the first bit capacitance group according to the second residue voltage corresponding to the first bit capacitance group. The second digital signal determined in the above manner contains capacitance error information corresponding to the first bit capacitance group and inter-stage gain errors between different sub-ADCs.

[0025] In an alternative embodiment, the digital processing unit is specifically configured to perform the following operations:

[0026] Calculate the ratio of the digital signal difference corresponding to the Nth bit capacitance group to the first coefficient to obtain the quantization difference corresponding to the Nth bit capacitance group;

[0027] Wherein, the Nth bit capacitance group belongs to the multiple bit capacitance groups, N is a positive integer, the difference between the first digital signal corresponding to the Nth bit capacitance group and the second digital signal corresponding to the Nth bit capacitance group is used as the digital signal difference corresponding to the Nth bit capacitance group, and the first coefficient is determined according to the effective number of bits of the second sub-ADC;

[0028] Use the quantization difference corresponding to the Nth bit capacitance group, the reference calibration weight, and the sum value of the calibration weights corresponding to the first bit capacitance group to the calibration weight corresponding to the N-1th bit capacitance group as the calibration weight corresponding to the Nth bit capacitance group;

[0029] Use the determined calibration weights corresponding to the multiple bit capacitor groups as the calibration weights corresponding to the first-stage ADC;

[0030] Wherein, the reference calibration weight is the calibration weight corresponding to the compensation capacitor group.

[0031] The above pipelined analog-to-digital converter determines the quantization difference corresponding to the bit capacitor group through the first coefficient and the difference between the first digital signal and the second digital signal corresponding to the same bit capacitor group; uses the sum of the quantization difference corresponding to the bit capacitor group, the reference calibration weight, and the calibration weights corresponding to all the bit capacitor groups before the bit capacitor group as the calibration weight corresponding to the bit capacitor group; and jointly uses the multiple calibration weights corresponding to the multiple bit capacitor groups as the calibration weights corresponding to the first-stage ADC, thereby realizing the determination of the calibration weights corresponding to the first-stage ADC.

[0032] In an alternative embodiment, during the process of determining the reference calibration weight:

[0033] The calibration control unit is specifically configured to perform the following operations:

[0034] Control the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal, control the second end of the compensation capacitor group to be grounded, and

[0035] Control the first ends and the second ends of the multiple bit capacitor groups to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a first digital signal corresponding to the compensation capacitor group;

[0036] Control the first end of the compensation capacitor group to be grounded, control the second end of the compensation capacitor group to be electrically connected to the reference voltage terminal, and

[0037] Control the first ends and the second ends of the multiple bit capacitor groups to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the compensation capacitor group.

[0038] In an alternative embodiment, the digital processing unit is specifically configured to perform the following operations:

[0039] Use the difference between the first digital signal corresponding to the compensation capacitor group and the second digital signal corresponding to the compensation capacitor group as the initial signal difference;

[0040] Use the ratio of the initial signal difference to the first coefficient as the reference calibration weight.

[0041] For the above pipeline analog-to-digital converter, the calibration control unit electrically connects the first end of the compensation capacitor bank to the reference voltage terminal and the second end of the compensation capacitor bank to ground to determine the first digital signal corresponding to the compensation capacitor bank, and electrically connects the first end of the compensation capacitor bank to ground and the second end of the compensation capacitor bank to the reference voltage terminal to determine the second digital signal corresponding to the compensation capacitor bank. By the difference between the first digital signal and the second digital signal corresponding to the compensation capacitor bank and the first coefficient, the determination of the reference calibration weight is achieved.

[0042] In an alternative embodiment, the digital processing unit is specifically configured to perform the following operations:

[0043] Multiply the calibration weights corresponding to the plurality of bit capacitor banks by the initial digital signal output by the first-stage ADC to obtain the target digital signal.

[0044] For the above pipeline analog-to-digital converter, since the effective number of bits of the stage ADC is the same as the number of bit capacitor banks in the first capacitor array, therefore, multiplying the plurality of calibration weights corresponding to the plurality of bit capacitor banks by the multi-bit initial digital signal output by the first-stage ADC one by one can obtain the calibrated multi-bit target digital signal, thereby achieving the calibration of the capacitor mismatch error and the inter-stage gain error in the pipeline analog-to-digital converter and improving the conversion accuracy of the pipeline analog-to-digital converter.

[0045] In an alternative embodiment, the pipeline analog-to-digital converter includes a plurality of cascaded stage ADCs;

[0046] The first-stage ADC is any one of the other stage ADCs except the last stage ADC among the plurality of cascaded stage ADCs, and the second-stage ADC is all the stage ADCs located after the first-stage ADC among the plurality of cascaded stage ADCs.

[0047] For the above pipeline analog-to-digital converter, which includes a plurality of cascaded stage ADCs, during the process of error calibration of the pipeline analog-to-digital converter, any one of the other stage ADCs except the last stage ADC is used as the first-stage ADC, and all the stage ADCs located after the first-stage ADC are used as the second-stage ADC to achieve the error calibration of the pipeline analog-to-digital converter and improve the performance of the pipeline analog-to-digital converter.

[0048] In a second aspect, an embodiment of the present invention provides a method for error calibration of a pipeline analog-to-digital converter, which is applied to the pipeline analog-to-digital converter described in any one of the embodiments in the first aspect above. The method includes:

[0049] Under the control of the calibration control unit of the first sub-ADC, the array connection structure of the first capacitor array in the first sub-ADC is adjusted so that the second sub-ADC outputs a first digital signal and a second digital signal;

[0050] Wherein, the first digital signal is determined according to the first residual voltage signal output by the first sub-ADC when the array connection structure of the first capacitor array is the first array connection structure, and the second digital signal is determined according to the second residual voltage signal output by the first sub-ADC when the array connection structure of the first capacitor array is the second array connection structure;

[0051] Through the digital processing unit, based on the first digital signal and the second digital signal, the calibration weight corresponding to the first sub-ADC is determined;

[0052] Through the digital processing unit, the initial digital signal output by the first sub-ADC is calibrated according to the calibration weight to obtain a target digital signal.

[0053] In an alternative embodiment, the first capacitor array includes a compensation capacitor group and a plurality of bit capacitor groups; for any one of the plurality of bit capacitor groups:

[0054] Under the control of the calibration control unit, adjusting the array connection structure of the first capacitor array includes:

[0055] Controlling the first end of the bit capacitor group to be electrically connected to the reference voltage terminal, controlling the second end of the bit capacitor group to be grounded, and

[0056] Controlling the first ends of the other bit capacitor groups except the bit capacitor group among the plurality of bit capacitor groups, the second ends of the other bit capacitor groups, the first end of the compensation capacitor group, and the second end of the compensation capacitor group to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a first digital signal corresponding to the bit capacitor group.

[0057] In an alternative embodiment, for any one of the other bit capacitor groups except the first bit capacitor group among the plurality of bit capacitor groups:

[0058] Under the control of the calibration control unit, adjusting the array connection structure of the first capacitor array includes:

[0059] Controlling the first ends of the first bit capacitor group to the bit capacitor group's previous bit capacitor group, and the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal, controlling the second ends of the first bit capacitor group to the previous bit capacitor group's second end, and the second end of the compensation capacitor group to be grounded, and

[0060] Control the first ends of the bit capacitor groups to the first ends of the last bit capacitor groups, and both the second ends of the bit capacitor groups to the second ends of the last bit capacitor groups are electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a second digital signal corresponding to the bit capacitor groups.

[0061] In an alternative embodiment, for the first bit capacitor group among the multiple bit capacitor groups:

[0062] Under the control of the calibration control unit, adjust the array connection structure of the first capacitor array, including:

[0063] Control the first end of the first bit capacitor group to be grounded, control the second end of the first bit capacitor group to be electrically connected to the reference voltage terminal, and

[0064] Control the first ends of the compensation capacitor group, the second ends of the compensation capacitor group, the first ends of the other bit capacitor groups except the first bit capacitor group among the multiple bit capacitor groups, and the second ends of the other bit capacitor groups except the first bit capacitor group among the multiple bit capacitor groups to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs a second digital signal corresponding to the first bit capacitor group.

[0065] In an alternative embodiment, the determining, by the digital processing unit, the calibration weights corresponding to the first sub-ADC based on the first digital signal and the second digital signal includes:

[0066] Calculate the ratio of the digital signal difference corresponding to the Nth bit capacitor group and the first coefficient to obtain the quantization difference corresponding to the Nth bit capacitor group;

[0067] Wherein, the Nth bit capacitor group belongs to the multiple bit capacitor groups, N is a positive integer, the difference between the first digital signal corresponding to the Nth bit capacitor group and the second digital signal corresponding to the Nth bit capacitor group is used as the digital signal difference corresponding to the Nth bit capacitor group, and the first coefficient is determined according to the effective number of bits of the second sub-ADC;

[0068] Take the quantization difference corresponding to the Nth bit capacitor group, the reference calibration weight, and the sum of the calibration weights corresponding to the first bit capacitor group to the calibration weights corresponding to the N-1th bit capacitor group as the calibration weight corresponding to the Nth bit capacitor group;

[0069] Take the determined calibration weights corresponding to the multiple bit capacitor groups as the calibration weights corresponding to the first sub-ADC;

[0070] Among them, the reference calibration weight is the calibration weight corresponding to the compensation capacitor bank.

[0071] In an alternative embodiment, during the process of determining the reference calibration weight:

[0072] Through the calibration control unit, control the first end of the compensation capacitor bank to be electrically connected to the reference voltage terminal, control the second end of the compensation capacitor bank to be grounded, and

[0073] Control the first ends and the second ends of the plurality of bit capacitor banks to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a first digital signal corresponding to the compensation capacitor bank;

[0074] Through the calibration control unit, control the first end of the compensation capacitor bank to be grounded, control the second end of the compensation capacitor bank to be electrically connected to the reference voltage terminal, and

[0075] Control the first ends and the second ends of the plurality of bit capacitor banks to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the compensation capacitor bank.

[0076] In an alternative embodiment, the reference calibration weight is determined by the following method:

[0077] Through the digital processing unit, take the difference between the first digital signal corresponding to the compensation capacitor bank and the second digital signal corresponding to the compensation capacitor bank as the initial signal difference;

[0078] Through the digital processing unit, take the ratio of the initial signal difference to the first coefficient as the reference calibration weight.

[0079] In an alternative embodiment, the digital processing unit calibrates the initial digital signal output by the first-stage ADC according to the calibration weight to obtain a target digital signal, including:

[0080] Multiply the calibration weights corresponding to the plurality of bit capacitor banks by the initial digital signal output by the first-stage ADC to obtain the target digital signal.

[0081] In an alternative embodiment, the pipelined analog-to-digital converter includes a plurality of cascaded sub-stage ADCs;

[0082] The first sub-ADC is any one of the sub-ADCs other than the last sub-ADC among the multiple cascaded sub-ADCs, and the second sub-ADC is all the sub-ADCs among the multiple cascaded sub-ADCs that are after the first sub-ADC.

[0083] In addition, for the technical effects brought by any implementation manner in the second aspect, reference may be made to the technical effects brought by different implementation manners in the first aspect, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0085] Figure 1 FIG. 12 is a schematic structural diagram of a pipelined successive approximation analog-to-digital converter provided by the related art;

[0086] Figure 2 FIG. 16 is a schematic timing diagram of the operation of a pipelined successive approximation analog-to-digital converter provided by the related art;

[0087] Figure 3 FIG. 20 is a schematic circuit structural diagram of a capacitor array of a pipelined successive approximation analog-to-digital converter provided by the related art;

[0088] Figure 4 FIG. 24 is a schematic module structural diagram of a pipelined analog-to-digital converter provided by an embodiment of the present invention;

[0089] Figure 5 FIG. 28 is a schematic circuit structural diagram of a pipelined analog-to-digital converter provided by an embodiment of the present invention;

[0090] Figure 6 FIG. 32 is a schematic working flow diagram of a pipelined analog-to-digital converter provided by an embodiment of the present invention;

[0091] Figure 7 FIG. 36 is a schematic array structural diagram of a first capacitor array during the sampling process provided by an embodiment of the present invention;

[0092] Figure 8 FIG. 40 is a schematic array structural diagram when the first capacitor array has a first array connection structure provided by an embodiment of the present invention;

[0093] Figure 9 FIG. 44 is a schematic array structural diagram when the first capacitor array has a second array connection structure provided by an embodiment of the present invention;

[0094] Figure 10 Schematic diagram of another array structure when the first capacitor array in the embodiment of the present invention is the first array connection structure;

[0095] Figure 11 Schematic diagram of another array structure when the first capacitor array in the embodiment of the present invention is the second array connection structure;

[0096] Figure 12 Schematic diagram of another array structure when the first capacitor array in the embodiment of the present invention is the first array connection structure;

[0097] Figure 13 Schematic diagram of another array structure when the first capacitor array in the embodiment of the present invention is the second array connection structure;

[0098] Figure 14 Schematic diagram of the working process for a digital processing unit to determine calibration weights provided by the embodiment of the present invention;

[0099] Figure 15 Schematic diagram of the module structure of another pipelined analog-to-digital converter provided by the embodiment of the present invention;

[0100] Figure 16 Schematic diagram of the complete working process of error calibration based on a pipelined analog-to-digital converter provided by the embodiment of the present invention;

[0101] Figure 17 Schematic diagram of the process of an error calibration method for a pipelined analog-to-digital converter provided by the embodiment of the present invention. Detailed implementation manners

[0102] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0103] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0104] With the continuous improvement of the operating frequency and processing accuracy of the digital-analog hybrid system-on-chip, the performance requirements for the analog-to-digital converter inside the chip are also getting higher and higher. For example, the analog-to-digital converter in a communication receiver needs to have a sampling rate of 100 MSPS and a sampling accuracy of 8 bits or more.

[0105] Currently, the commonly used high-speed and high-precision analog-to-digital converter is the pipeline analog-to-digital converter (Pipeline-ADC). However, its power consumption is relatively high, and it is difficult to exert its advantages in advanced nanoscale processes. The commonly used low-power analog-to-digital converter is the successive approximation register analog-to-digital converter (SAR ADC). However, it is difficult to achieve both high speed and high precision at the same time.

[0106] The pipelined successive approximation register analog-to-digital converter (Pipelined-SAR ADC) combines the high-speed and high-precision characteristics of the pipeline analog-to-digital converter with the low-power characteristics of the successive approximation register analog-to-digital converter. It is an analog-to-digital converter that takes into account high sampling rate, high precision, and low-power characteristics, and has become the mainstream architecture in the research of analog-to-digital converters in recent years.

[0107] First, an introduction to the pipelined successive approximation register analog-to-digital converter is given:

[0108] Figure 1 Fig. shows a schematic structural diagram of a pipelined successive approximation register analog-to-digital converter. As Figure 1 shown, the pipelined successive approximation register analog-to-digital converter 100 includes a SAR ADC1 110, a residual amplifier (RA) 120, a SAR ADC2 130, and a digital alignment logic circuit 140, where:

[0109] The SAR ADC1 110, the RA 120, and the SAR ADC2 130 are electrically connected in sequence. Both the SAR ADC1 110 and the SAR ADC2 130 are electrically connected to the digital alignment logic circuit 140, where:

[0110] The SAR ADC1 110 includes a sampling circuit 111, a capacitor digital-to-analog converter (CDAC) 112, a SAR logic circuit 113, and a comparer (CMP) 114, where:

[0111] The first input terminal of the sampling circuit 111 is used to receive the positive-phase input signal V IP , and the second input terminal of the sampling circuit 111 is used to receive the negative-phase input signal V IN , and the clock terminal of the sampling circuit 111 is used to receive the sampling clock signal clk S , and the output terminal of the sampling circuit 111 is electrically connected to the input terminal of the CDAC 112;

[0112] The output terminal of the CDAC 112 is electrically connected to the positive input terminal and the negative input terminal of the CMP 114 respectively, and is used to output the quantization residue voltage V RES1 to the input terminal of the RA120. The controlled terminal of the CDAC 112 is electrically connected to the control terminal of the SAR logic circuit 113;

[0113] The output terminal of the CMP 114 is electrically connected to the input terminal of the SAR logic circuit 113. The output terminal of the SAR logic circuit 113 serves as the output terminal of the SAR ADC1 110 and is used to output the quantization signal d 1 to the digital alignment logic circuit 140.

[0114] The clock terminal of the RA120 is used to receive the sampling clock signal clk A , and the inter-stage gain of the RA120 is A.

[0115] The SAR ADC2 130 includes a sampling circuit 131, a capacitor digital-to-analog converter (CDAC) 132, a SAR logic circuit 133, a variable capacitor array, and a comparer (CMP) 134, where:

[0116] The first input terminal of the sampling circuit 131 is electrically connected to the positive output terminal of the RA120, the second input terminal of the sampling circuit 131 is electrically connected to the negative output terminal of the RA120, and the clock terminal of the sampling circuit 131 is used to receive the sampling clock signal clk A , and the output terminal of the sampling circuit 131 is electrically connected to the input terminal of the CDAC 132;

[0117] The output terminal of the CDAC 132 is electrically connected to the positive input terminal and the negative input terminal of the CMP 134 respectively, and the controlled terminal of the CDAC 132 is electrically connected to the control terminal of the SAR logic circuit 133;

[0118] The output terminal of the CMP 134 is electrically connected to the input terminal of the SAR logic circuit 133. The output terminal of the SAR logic circuit 133 serves as the output terminal of the SAR ADC2 130 and is used to output the quantization signal d 2 to the digital alignment logic circuit 140.

[0119] The digital alignment logic circuit 140 performs alignment processing on the received quantized signal and outputs the final quantized digital signal d OUT .

[0120] Figure 2 Fig. shows a timing diagram of the operation of a pipelined successive approximation analog-to-digital converter. During the operation of the pipelined successive approximation analog-to-digital converter 100:

[0121] As Figure 2 shown, first, the SAR ADC1 110 samples the differential input signal (V S , V IP , V IN ) according to the sampling clock signal clk. After the sampling is completed, the sampled signal is quantized to obtain the quantized residue voltage V RES1 ;

[0122] Then, the RA120 amplifies the quantized residue voltage V A by A times according to the sampling clock signal clk RES1 . At the same time, the SAR ADC2 130 samples the amplified quantized residue voltage according to the sampling clock signal clk A , and after the sampling is completed, the amplified quantized residue voltage is quantized to obtain the quantized signal d 2 ;

[0123] Among them, the quantization process of the SAR ADC2 130 can be carried out simultaneously with the sampling process and the quantization process of the SAR ADC1 110.

[0124] Secondly, two types of errors existing in the pipelined successive approximation analog-to-digital converter, namely the inter-stage gain error and the capacitor mismatch error of the sub-stage SAR ADC, are introduced:

[0125] The capacitive digital-to-analog converter (CDAC) of the pipelined successive approximation analog-to-digital converter includes a capacitor array. Each capacitor array includes a first capacitor sub-array corresponding to the positive input terminal, a second capacitor sub-array corresponding to the negative input terminal, a first switch array and a second switch array, where:

[0126] Multiple switching switches in the first switch array are correspondingly connected to multiple capacitors in the first capacitor sub-array, and multiple switching switches in the second switch array are correspondingly connected to multiple capacitors in the second capacitor sub-array.

[0127] Figure 3 Fig. shows a schematic circuit diagram of the capacitor array in a pipelined successive approximation analog-to-digital converter with a closed-loop amplification structure. As Figure 3As shown, the effective number of bits of the SAR ADC1 110 is set to n1. Therefore, the digital signal output by the SAR ADC1 110 is d 1 <n1-1:0>, one capacitor sub-array in the capacitor array of the CDAC 112 includes n1 bit capacitors C arranged in parallel 01 <n1-1:0>, compensation capacitor C 01d and the parasitic capacitance C of the upper plate of the capacitor sub-array 01p , where the total capacitance of the capacitor sub-array is: C 01t = C 01d + ∑C 01 <n1-1:0>;

[0128] The feedback capacitor in the pipelined successive approximation analog-to-digital converter with a closed-loop amplification structure is C 0f , and the reference voltage of the pipelined successive approximation analog-to-digital converter is V REF ;

[0129] Set the effective number of bits of SAR ADC2 130 to n2. Therefore, the digital signal output by SAR ADC2 130 is d 2 <n2-1:0>, one capacitive sub-array in the capacitive array of CDAC 132 includes n2 bit capacitors C arranged in parallel 02 <n2-1:0>, compensating capacitor C 02d and the parasitic capacitance C of the upper plate of the capacitor sub-array 02p , where the total capacitance of the capacitor sub-array is: C 02t = C 02d + ∑C 02 <n2-1:0>;

[0130] In the circuit structure as shown in Figure 3 the inter-stage gain A is equal to the ratio of the total capacitance C 01t in the capacitance array of the SAR ADC1 110 to the feedback capacitance C 0f i.e., However, due to the mismatch between the total capacitance C 01t and the feedback capacitance C 0f there is an error between the actual inter-stage gain A and the ideal inter-stage gain, which is the inter-stage gain error;

[0131] In addition, due to the sampling method of sampling the upper plate by the SAR ADC2 130, therefore, the parasitic capacitance C 02p of the upper plate will also introduce an equivalent inter-stage gain error, and this equivalent inter-stage gain error is equal to the ratio of the parasitic capacitance C 02p of the upper plate to the total capacitance C 02t in the capacitance array of the SARADC2 130;

[0132] Furthermore, for each SAR ADC of the pipelined successive approximation analog-to-digital converter, the bit capacitances in the capacitance array of the SAR ADC are usually distributed in the form of binary exponents, such as 1, 2, 4, 8, …… Due to the influence of external factors such as process errors, there is a mismatch between the bit capacitances in the capacitance array, and the error caused by this mismatch is the capacitance mismatch error.

[0133] It can be seen from this that the existence of the inter-stage gain error and the capacitance mismatch error affects the conversion accuracy of the pipelined successive approximation analog-to-digital converter, making it difficult for the pipelined successive approximation analog-to-digital converter to achieve the accuracy requirement above 10 Bit and reducing the performance of the pipelined successive approximation analog-to-digital converter.

[0134] Currently, the mainstream calibration algorithm for the inter-stage gain error is the least mean square algorithm based on perturbation voltage injection. This calibration algorithm injects a pseudo-random perturbation voltage signal into the residual voltage output by the previous-stage SAR ADC, so that the subsequent-stage SAR ADC generates a digital code containing the information of the inter-stage gain error and the perturbation voltage signal, and eliminates the perturbation voltage signal information through relevant operations, retaining the information of the inter-stage gain error, thereby realizing the calibration of the inter-stage gain error. However, the above calibration algorithm needs to perform iterative convergence, with a long convergence time and a large hardware overhead;

[0135] The calibration algorithms for capacitor mismatch errors mainly include the algorithm based on the root mean square and the algorithm based on quantizing the low-order capacitance and weighting the high-order capacitance. However, the algorithm based on the root mean square also requires iterative convergence, which has a long convergence time and a large hardware overhead; the algorithm based on quantizing the low-order capacitance and weighting the high-order capacitance requires introducing an additional capacitance weight calibration circuit in the analog circuit, resulting in a large hardware overhead for the analog circuit;

[0136] Therefore, in the existing error calibration algorithms, the inter-stage gain error and the capacitor mismatch error need to be calibrated separately, which increases the complexity of error calibration and also increases the hardware overhead, and is not conducive to the design of the pipelined successive approximation analog-to-digital converter.

[0137] Based on this, the embodiments of the present invention provide a pipelined analog-to-digital converter and its error calibration method to achieve the calibration of the inter-stage gain error and the capacitor mismatch error in the pipelined analog-to-digital converter, improve the conversion accuracy of the pipelined analog-to-digital converter, and improve the performance of the pipelined analog-to-digital converter.

[0138] The pipelined analog-to-digital converter provided by the present invention will be specifically introduced below with reference to the accompanying drawings:

[0139] Figure 4 FIG. shows a schematic structural diagram of a pipelined analog-to-digital converter provided by an embodiment of the present invention, as Figure 4 shown, the pipelined analog-to-digital converter 400 includes a first-stage ADC 410, a residue amplifier (RA) 420, a second-stage ADC 430, and a digital processing unit 440 that are electrically connected in sequence, and the digital processing unit 440 is also electrically connected to the first-stage ADC 410;

[0140] Among them, the input of the first-stage ADC 410 can be a differential input signal (V IP , V IN ), or a residue amplified voltage signal output by the residue amplifier in the previous stage of the first-stage ADC 410. The embodiments of the present invention do not impose any restrictions on this.

[0141] It should be noted that the pipelined analog-to-digital converter in the embodiments of the present invention can be a pipelined successive approximation analog-to-digital converter or other pipelined analog-to-digital converters with a binary capacitor array. The embodiments of the present invention do not impose any restrictions on this.

[0142] Figure 5 FIG. shows a schematic circuit diagram of a pipelined analog-to-digital converter 400, as Figure 5 As shown, the first - stage ADC 410 includes a first capacitor array 4101 and a calibration control unit 4102. The first capacitor array 4101 includes a compensation capacitor bank 501, M bit - capacitor banks 502, a parasitic capacitor bank 503, a first switch array 504, and a second switch array 505, where:

[0143] The compensation capacitor bank 501 includes a P - terminal compensation capacitor and an N - terminal compensation capacitor, and the capacitance values of the P - terminal compensation capacitor and the N - terminal compensation capacitor are both C 1d ; for any one of the M bit - capacitor banks 502 in the bit - capacitor banks 502, the bit - capacitor bank includes a P - terminal bit - capacitor and an N - terminal bit - capacitor, and the capacitance values of the P - terminal bit - capacitor and the N - terminal bit - capacitor are the same; the capacitance values corresponding to the M bit - capacitor banks are respectively: C 1 <0>, C 1 <1>, …, C 1 <m-1>;

[0144] The upper plates of the P-terminal compensation capacitor and the upper plates of the M P-terminal bit capacitors are all connected to the common-mode voltage terminal V 01 through the control switch K CM electrically. The upper plates of the N-terminal compensation capacitor and the upper plates of the M N-terminal bit capacitors are all connected to the common-mode voltage terminal V 02 through the control switch K CM electrically;

[0145] The first switch array 504 includes M + 1 single-pole multi-throw switching switches (S 0p , S 1p , …, S Mp ). The first ends of the M + 1 switching switches (S 0p , S 1p , …, S Mp ) are respectively and electrically connected to the lower plates of the P-terminal compensation capacitor and the lower plates of the M P-terminal bit capacitors. The second ends of the M + 1 switching switches (S 0p , S 1p , …, S Mp ) are electrically connected to the reference voltage terminal V REF . The third ends of the M + 1 switching switches (S 0p , S 1p , …, S Mp ) are electrically connected to the common-mode voltage terminal V CM . The fourth ends of the M + 1 switching switches (S 0p , S 1p , …, S Mp ) are grounded;

[0146] The second switch array 505 includes M + 1 single-pole multi-throw switching switches (S 0n , S 1n , …, S Mn ). The first ends of the M + 1 switching switches (S 0n , S 1n , …, S Mn ) are respectively and electrically connected to the lower plates of the N-terminal compensation capacitor and the lower plates of the M N-terminal bit capacitors. The second ends of the M + 1 switching switches (S 0n , S 1n , …, S Mn ) are electrically connected to the reference voltage terminal V REF . The third ends of the M + 1 switching switches (S 0n , S 1n , …, S Mn ) are electrically connected to the common-mode voltage terminal V CM . The fourth ends of the M + 1 switching switches (S 0n , S 1n , …, S Mn The fourth terminal of () is grounded;

[0147] The switching switches (S 0p 、S 1p 、…、S Mp ) and the multiple controlled terminals of the switching switches (S 0n 、S 1n 、…、S Mn ) are all electrically connected to the control terminal of the calibration control unit 4102.

[0148] The parasitic capacitor bank 503 includes a P-terminal parasitic capacitor and an N-terminal parasitic capacitor. The capacitance values of the P-terminal parasitic capacitor and the N-terminal parasitic capacitor are both C 1p . The upper plate of the P-terminal parasitic capacitor is electrically connected to the common-mode voltage terminal V 01 through the control switch K CM . The upper plate of the N-terminal parasitic capacitor is electrically connected to the common-mode voltage terminal V 02 through the control switch K CM . The lower plates of the P-terminal parasitic capacitor and the N-terminal parasitic capacitor are both grounded;

[0149] As Figure 5 shown, there is a P-terminal feedback capacitor between the positive-phase output terminal (P-terminal) of the first-stage ADC 410 and the positive-phase input terminal (P-terminal) of the second-stage ADC 430, and there is an N-terminal feedback capacitor between the negative-phase output terminal (N-terminal) of the first-stage ADC 410 and the negative-phase input terminal (N-terminal) of the second-stage ADC 430. Among them, the capacitance values of the P-terminal feedback capacitor and the N-terminal feedback capacitor are both C f .

[0150] In one or more embodiments, the calibration control unit 403 can be integrated in the SAR logic circuit of the first-stage ADC 410.

[0151] Since the calibration control unit 403 can be integrated in the SAR logic circuit, the additional analog circuit overhead is small, which is beneficial to the realization of calibration.

[0152] Among them, as Figure 6 shown, the pipelined analog-to-digital converter 400 realizes the calibration of the inter-stage gain error and the capacitance mismatch error through steps S601 to S603:

[0153] Step S601, under the control of the calibration control unit 4102, the first capacitor array 4101 adjusts its own array connection structure so that the second-stage ADC 430 outputs a first digital signal and a second digital signal;

[0154] Among them, the first digital signal is determined according to the first residual voltage signal output by the first sub-ADC 410 when the array connection structure of the first capacitor array 4101 is the first array connection structure, and the second digital signal is determined according to the second residual voltage signal output by the first sub-ADC 410 when the array connection structure of the first capacitor array 4101 is the second array connection structure;

[0155] In a specific implementation, the first sub-ADC 410 first performs a sampling operation. During the sampling process, as Figure 7 shown, the control switch K 01 and the control switch K 02 are both closed, and the paths between the first ends and the third ends of each switching switch (S 0p , S 1p , …, S Mp , S 0n , S 1n , …, S Mn ) are conducted, so that the upper plates and the lower plates of each capacitor in the first capacitor array 4101 are both electrically connected to the common-mode voltage terminal V CM , that is, the upper plates and the lower plates of the P-terminal compensation capacitor, the upper plates and the lower plates of the N-terminal compensation capacitor, the upper plates and the lower plates of the M P-terminal bit capacitors, and the upper plates and the lower plates of the M N-terminal bit capacitors are all electrically connected to the common-mode voltage terminal V CM ;

[0156] After the sampling is completed, the calibration control unit 4102 generates a control signal to the controlled terminals of each switching switch to change the connection modes of some of the switching switches (S 0p , S 1p , …, S Mp ) and the switching switches (S 0n , S 1n , …, S Mn ), so that the array connection structure of the first capacitor array 4101 is changed. And after the adjustment of the array connection structure of the first capacitor array 4101 is completed, the first sub-ADC 410 performs a quantization operation.

[0157] Step S602, the digital processing unit 440 determines the calibration weight corresponding to the first sub-ADC 410 based on the first digital signal and the second digital signal;

[0158] In a specific implementation, after the second-stage ADC 430 completes a quantization operation, it outputs a first digital signal to the digital processing unit 440. After the second-stage ADC 430 completes the next quantization operation, it outputs a second digital signal to the digital processing unit 440. The digital processing unit 440 determines the calibration weight corresponding to the first-stage ADC 410 based on the received first digital signal and second digital signal.

[0159] Step S603: The digital processing unit 440 calibrates the initial digital signal output by the first-stage ADC 410 according to the calibration weight to obtain a target digital signal.

[0160] In the pipelined analog-to-digital converter provided by the embodiment of the present invention, since the first digital signal and the second digital signal are generated by the first-stage ADC and the second-stage ADC, the first digital signal and the second digital signal include the capacitor mismatch error information corresponding to the first-stage ADC, and the inter-stage gain error information between the first-stage ADC and the second-stage ADC. By using the calibration weight determined by the first digital signal and the second digital signal to calibrate the initial digital signal output by the first-stage ADC, simultaneous calibration of the inter-stage gain error and the capacitor mismatch error is achieved, the complexity of error calibration for the pipelined analog-to-digital converter is reduced, the conversion accuracy of the pipelined analog-to-digital converter is improved, and the performance of the pipelined analog-to-digital converter is improved.

[0161] In one or more embodiments, according to the compensation capacitor bank (C 1d ) and each bit capacitor bank (C 1 <0>, C 1 <1>, …, C 1 <m-1>) in sequence, measure the calibration weights corresponding to each capacitor bank; and use the calibration weight corresponding to the determined compensation capacitor bank (C 1d ) as the reference calibration weight, and based on this reference calibration weight, determine each bit capacitor bank (C 1 <0>, C 1 <1>, …, C 1 <m-1>)The corresponding calibration weight.

[0162] In an alternative embodiment, during the process of determining the reference calibration weight:

[0163] As Figure 8 shown, first, under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is made the first array connection structure 0, where:

[0164] The calibration control unit 4102 controls the first end of the compensation capacitor bank (C 1d ) to be electrically connected to the reference voltage terminal V REF , controls the second end of the compensation capacitor bank (C 1d ) to be grounded, and controls the first ends of the multiple bit capacitor banks C 1 <0:M-1>) and the second ends of the multiple bit capacitor banks (C 1 <0:M-1>) to be electrically connected to the common-mode voltage terminal V CM , so that the second-stage ADC 430 outputs the first digital signal d 1d corresponding to the compensation capacitor bank (C 2,0P ).

[0165] In one or more embodiments, the lower plate of the P-terminal compensation capacitor serves as the first end of the compensation capacitor bank, and the lower plate of the N-terminal compensation capacitor serves as the second end of the compensation capacitor bank; for any one of the multiple bit capacitor banks, the lower plate of the P-terminal bit capacitor serves as the first end of the bit capacitor bank, and the lower plate of the N-terminal bit capacitor serves as the second end of the bit capacitor bank.

[0166] In a specific implementation, when the array connection structure of the first capacitor array 4101 is the first array connection structure 0, the first-stage ADC 410 outputs the first residual voltage signal corresponding to the compensation capacitor bank (C 1d ), where, according to the law of conservation of charge, the first residual voltage signal V 1d corresponding to the compensation capacitor bank (C RES,0P ) can be expressed as:

[0167]

[0168] where C 1t is the total capacitance of the P-terminal in the first capacitor array 4101, that is, C 1t = C 1d + ∑C 1 <0:M-1>;

[0169] The first residual voltage signal V RES,0P after being amplified by RA420, the obtained first residual amplified voltage signal V ARES,0P can be expressed as:

[0170]

[0171] Among them, V OS,RA is the offset voltage of RA420, and V n1,RA is the noise voltage of RA420;

[0172] After the first residual amplified voltage signal V ARES,0P is quantized by the second-stage ADC 430, the first digital signal d 1d corresponding to the compensation capacitor bank (C 2,0P ) can be obtained. The first digital signal d 2,0P can be expressed as:

[0173]

[0174] Among them, V FS is the full-scale quantization range of the second-stage ADC 430, and V FS = 2V REF ; K is the effective number of bits of the second-stage ADC 430; C 2t is the total capacitance of the P-terminal in the second capacitor array of the second-stage ADC 430, that is, C 2t = C 2d + ∑C 2 <0:K-1>, C 2d is the capacitance value of the compensation capacitor in the second capacitor array, C 2 <0:K-1> are the capacitance values of each bit capacitor in the second capacitor array, and C 2p is the capacitance value of the parasitic capacitor in the second capacitor array; V RES2,0P is the residual voltage signal output by the second-stage ADC 430;

[0175] Therefore:

[0176]

[0177] As Figure 9 shown, after the second-stage ADC 430 outputs the first digital signal d 2,0P , under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is the second array connection structure 0, where:

[0178] The calibration control unit 4102 controls the first end of the compensation capacitor bank (C 1d ) to be grounded, controls the second end of the compensation capacitor bank (C 1d ) to be electrically connected to the reference voltage terminal V REF , and controls the multiple bit capacitor banks C 1 The first end of <0:M-1>) and the multiple bit capacitor groups C 1 The second end of <0:M-1>) are both electrically connected to the common mode voltage terminal V CM to enable the second sub-stage ADC to output the second digital signal d corresponding to the compensation capacitor group (C 1d ). 2,0N .

[0179] In a specific implementation, when the array connection structure of the first capacitor array 4101 is the second array connection structure 0, the first sub-stage ADC 410 outputs the second residue voltage signal corresponding to the compensation capacitor group (C 1d ), where, according to the law of conservation of charge, the second residue voltage signal V 1d corresponding to the compensation capacitor group (C RES,0N ) can be expressed as:

[0180]

[0181] where, C 1t is the total capacitance of the N terminals in the first capacitor array 4101, that is, C 1t = C 1d + ∑C 1 <0:M-1>;

[0182] The second residue voltage signal V RES,0N after being amplified by RA420, the obtained second residue amplified voltage signal V ARES,0N can be expressed as:

[0183]

[0184] where, V OS,RA is the offset voltage of RA420, and V n2,RA is the noise voltage of RA420;

[0185] The second residue amplified voltage signal V ARES,0N after being quantized by the second sub-stage ADC 430, the second digital signal d corresponding to the compensation capacitor group (C 1d ) can be obtained, and this second digital signal d 2,0N can be expressed as: 2,0N

[0186]

[0187] where, V FS is the full-scale quantization range of the second sub-stage ADC 430, and V FS = 2V REF ; K is the effective number of bits of the second sub-stage ADC 430; C 2t 2t is the total capacitance of the P terminal in the second capacitor array of the second-stage ADC 430, i.e., C 2t = C 2d + ∑C 2 <0:K-1>, C 2d is the capacitance value of the compensation capacitor in the second capacitor array, C 2 <0:K-1> are the capacitance values of the respective bit capacitors in the second capacitor array, C 2p is the capacitance value of the parasitic capacitance in the second capacitor array; V RES2,0N is the residual voltage signal output by the second-stage ADC 430;

[0188] Therefore:

[0189]

[0190] In an alternative embodiment, during the process of determining the reference calibration weight: The digital processing unit 440 is specifically configured to perform the following operations:

[0191] Take the difference between the first digital signal corresponding to the compensation capacitor group and the second digital signal corresponding to the compensation capacitor group as the initial signal difference; take the ratio of the initial signal difference to the first coefficient as the reference calibration weight.

[0192] In one or more embodiments, the first coefficient is determined according to the effective number of bits of the second-stage ADC 430.

[0193] In a specific implementation, take the product of the effective number of bits of the second-stage ADC 430 preset values as the first coefficient. For example, set the preset value to 2 and the effective number of bits of the second-stage ADC 430 to K, then the first coefficient is: 2 K .

[0194] In a specific implementation, calculate the difference between the first digital signal d 1d corresponding to the compensation capacitor group (C 2,0P ) and the second digital signal d 1d corresponding to the compensation capacitor group (C 2,0N ) to obtain the initial signal difference Δd 2,0 , where the initial signal difference Δd 2,0 can be expressed as:

[0195]

[0196] where ΔV RES2,0 is the difference of the residual voltage signal output by the second-stage ADC 430; ΔV n,RA is the difference of the noise voltage of RA420;

[0197] That is:

[0198]

[0199] By taking the average value through multiple measurements, the difference ΔV of the residual voltage signal output by the second-stage ADC 430 in the above formula RES2,0 approaches 0, and the difference ΔV of the noise voltage of RA420 n,RA also approaches 0. Therefore, the initial signal difference Δd 2,0 can be expressed as:

[0200]

[0201] Also, since V FS = 2V REF , therefore, the initial signal difference Δd 2,0 can also be expressed as:

[0202]

[0203] Since the first coefficient is 2 K , therefore, the ratio of the initial signal difference to the first coefficient, that is, the reference calibration weight W cal,0 can be expressed as:

[0204]

[0205] Among them, represents the actual weight ratio of the compensation capacitor C 1d ; represents the actual inter-stage gain including the inter-stage gain error information; represents the equivalent inter-stage gain error introduced due to the parasitic capacitor C 2p .

[0206] The calibration control unit determines the first digital signal corresponding to the compensation capacitor bank by controlling the first end of the compensation capacitor bank to be electrically connected to the reference voltage terminal and the second end of the compensation capacitor bank to be grounded, and determines the second digital signal corresponding to the compensation capacitor bank by controlling the first end of the compensation capacitor bank to be grounded and the second end of the compensation capacitor bank to be electrically connected to the reference voltage terminal. Through the difference between the first digital signal and the second digital signal corresponding to the compensation capacitor bank, and the first coefficient, the determination of the reference calibration weight is realized.

[0207] In the above embodiment, since the calibration weight corresponding to the capacitor bank is determined by taking the average value through multiple measurements, there is no need for iterative convergence, which shortens the time for determining the calibration weight and improves the calibration efficiency of the pipelined analog-to-digital converter.

[0208] In a specific implementation, when realizing the compensation capacitor bank (C 1d )After the corresponding reference calibration weights are determined, the calibration weights corresponding to multiple bit capacitor groups are measured sequentially. For example, the specific measurement order can be: bit capacitor group C 1 <0>, bit capacitor group C 1 <1>, …, bit capacitor group C 1 <m-1>。

[0209] In an alternative embodiment, for any one of the multiple bit capacitor groups, in the process of determining the calibration weight corresponding to the bit capacitor group:

[0210] The calibration control unit 4102 controls the first end of the bit capacitor group to be electrically connected to the reference voltage terminal V REF The second end of the bit capacitor group is controlled to be grounded, and the first ends of the other bit capacitor groups except the bit capacitor group among the multiple bit capacitor groups, the second ends of the other bit capacitor groups, the first end of the compensation capacitor group, and the second end of the compensation capacitor group are all electrically connected to the common-mode voltage terminal V CM To enable the second-stage ADC 430 to output a first digital signal corresponding to the bit capacitor group.

[0211] In a specific implementation, taking the bit capacitor group C 1 <0> as an example:

[0212] As Figure 10 shown, after the first-stage ADC 410 finishes sampling, under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is the first array connection structure 1, where:

[0213] The first end of the bit capacitor group (C 1 <0>) is electrically connected to the reference voltage terminal V REF The second end of the bit capacitor group (C 1 <0>) is grounded, and the first ends of the other bit capacitor groups (C 1 <1:M - 1>), the second ends of the other bit capacitor groups (C 1 <1:M - 1>), the first end of the compensation capacitor group (C 1d ), and the second end of the compensation capacitor group (C 1d ) are all electrically connected to the common-mode voltage terminal V CM electrically connected.

[0214] In the case where the array connection structure of the first capacitor array 4101 is the first array connection structure 1, the second-stage ADC 430 outputs a first digital signal d 1 <0> corresponding to the bit capacitor group (C 2,1P );

[0215] Wherein, the specific implementation manner for the second-stage ADC 430 to obtain the first digital signal d 1 <0> corresponding to the bit capacitor group (C 2,1P ) is similar to the specific implementation manner for determining the first digital signal d 1d corresponding to the compensation capacitor group (C 2,0P ), and reference can be made to the foregoing first digital signal d 2,0P The determination method is not described in detail herein.

[0216] In an alternative embodiment, for the first bit capacitor bank among multiple bit capacitor banks, during the process of determining the calibration weight corresponding to the bit capacitor bank:

[0217] The calibration control unit 4102 controls the first end of the first bit capacitor bank to be grounded, controls the second end of the first bit capacitor bank to be electrically connected to the reference voltage terminal V REF electrically connected, and controls the first end of the compensation capacitor bank, the second end of the compensation capacitor bank, the first ends of the other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks, and the second ends of the other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks to be electrically connected to the common mode voltage terminal V CM electrically connected, so that the second-stage ADC 430 outputs a second digital signal corresponding to the first bit capacitor bank.

[0218] As Figure 11 shown, after the second-stage ADC 430 outputs the first digital signal d 2,1P , under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is the second array connection structure 1, where:

[0219] The first end of the bit capacitor bank (C 1 <0>) is grounded, the second end of the bit capacitor bank (C 1 <0>) is electrically connected to the reference voltage terminal V REF electrically connected, and the first ends of the other bit capacitor banks (C 1 <1:M - 1>), the second ends of the other bit capacitor banks (C 1 <1:M - 1>), the first end of the compensation capacitor bank (C 1d ) and the second end of the compensation capacitor bank (C 1d ) are all electrically connected to the common mode voltage terminal V CM electrically connected.

[0220] In the case where the array connection structure of the first capacitor array 4101 is the second array connection structure 1, the second-stage ADC 430 outputs a second digital signal d 1 <0> corresponding to the bit capacitor bank (C 2,1N );

[0221] wherein, the specific implementation manner for the second-stage ADC 430 to obtain the second digital signal d 1 <0> corresponding to the bit capacitor bank (C 2,1N <0>) is similar to the specific implementation manner for determining the second digital signal d 1d corresponding to the compensation capacitor bank (C 2,0N ), and reference can be made to the foregoing second digital signal d 2,0N The determination method is thus not elaborated further.

[0222] In a specific implementation, the first digital signal d corresponding to the bit capacitor group (C 1 <0>) is determined through the above embodiments, 2,1P , and the second digital signal d corresponding to the bit capacitor group (C 1 <0>) is determined. After that, the digital processing unit 440 determines the calibration weight corresponding to the bit capacitor group (C 2,1N based on the first digital signal d 2,1P and the second digital signal d 2,1N . 1 <0>).

[0223] In a specific implementation, taking the bit capacitor group C 1 <1> as an example:

[0224] As Figure 12 shown, after the first-stage ADC 410 finishes sampling, under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is the first array connection structure 2, where:

[0225] The first end of the bit capacitor group (C 1 <1>) is electrically connected to the reference voltage terminal V REF , the second end of the bit capacitor group (C 1 <1>) is grounded, and the first ends of the other bit capacitor groups (C 1 <0>, C 1 <2:M - 1>), the second ends of the other bit capacitor groups (C 1 <0>, C 1 <2:M - 1>), the first end of the compensation capacitor group (C 1d ) and the second end of the compensation capacitor group (C 1d ) are all electrically connected to the common-mode voltage terminal V CM .

[0226] In the case where the array connection structure of the first capacitor array 4101 is the first array connection structure 2, the second-stage ADC 430 outputs the first digital signal d corresponding to the bit capacitor group (C 1 <1>) 2,2P ;

[0227] Among them, the specific implementation of the second-stage ADC 430 obtaining the first digital signal d corresponding to the bit capacitor group (C 1 <1>) is similar to the specific implementation of determining the first digital signal d corresponding to the compensation capacitor group (C 2,2P 1d 2,0P ) described above, and reference can be made to the above first digital signal d 2,0P .​The determination method is not described in detail herein.

[0228] In an alternative embodiment, for any one of the bit capacitor groups other than the first bit capacitor group among the multiple bit capacitor groups, during the process of determining the calibration weight corresponding to the bit capacitor group:

[0229] The calibration control unit 4102 controls the first end of the first bit capacitor group to the first end of the previous bit capacitor group, and the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal V REF electrically connected, controls the second end of the first bit capacitor group to the second end of the previous bit capacitor group, and the second end of the compensation capacitor group to be grounded, and controls the first end of the bit capacitor group to the first end of the last bit capacitor group, and the second end of the bit capacitor group to the second end of the last bit capacitor group to be electrically connected to the common mode voltage terminal V CM electrically connected, so that the second-stage ADC 430 outputs a second digital signal corresponding to the bit capacitor group.

[0230] As Figure 13 shown, after the second-stage ADC 430 outputs the first digital signal d 2,2P , under the control of the calibration control unit 4102, the array connection structure of the first capacitor array 4101 is the second array connection structure 2, where:

[0231] The first end of the bit capacitor group (C 1 <0>) and the first end of the compensation capacitor group (C 1d ) are both electrically connected to the reference voltage terminal V REF electrically connected, the second end of the bit capacitor group (C 1 <0>) and the second end of the compensation capacitor group (C 1d ) are both grounded, and the first end of the bit capacitor group (C 1 <1:M-1>) and the second end of the bit capacitor group (C 1 <1:M-1>) are both electrically connected to the common mode voltage terminal V CM electrically connected.

[0232] In the case where the array connection structure of the first capacitor array 4101 is the second array connection structure 2, the second-stage ADC 430 outputs a second digital signal d 1 <1>) corresponding to the bit capacitor group (C 2,2N ;

[0233] wherein, the specific implementation manner for the second-stage ADC 430 to obtain the second digital signal d 1 <1>) corresponding to the bit capacitor group (C 2,2N is the same as the aforementioned method for determining the second digital signal d 1d ) corresponding to the compensation capacitor group (C 2,0N The specific implementation is similar to that of the second digital signal d 2,0N , and the determination method is the same, so it will not be elaborated here.

[0234] In a specific implementation, the first digital signal d corresponding to the bit capacitor bank (C 1 <1>) is determined through the above embodiments 2,2P , and the second digital signal d corresponding to the bit capacitor bank (C 1 <1>). After that, the digital processing unit 440 determines the calibration weight corresponding to the bit capacitor bank (C 2,2N <1>) according to the first digital signal d 2,2P and the second digital signal d 2,2N . 1 It should be noted that the determination methods of the first digital signal and the second digital signal corresponding to the bit capacitor bank (C

[0235] <2:M-1>) are all similar to those of the bit capacitor bank (C 1 <1>), and the embodiments corresponding to the bit capacitor bank (C 1 <1>) can be referred to, so they will not be elaborated here. 1 <1>) can be referred to, so they will not be elaborated here.

[0236] In an alternative embodiment, as Figure 14 shown, the digital processing unit 440 specifically determines the calibration weight corresponding to the Nth bit capacitor bank through steps S1401 to S1403:

[0237] Step S1401: Calculate the ratio of the digital signal difference corresponding to the Nth bit capacitor bank to the first coefficient to obtain the quantization difference corresponding to the Nth bit capacitor bank;

[0238] Among them, the Nth bit capacitor bank belongs to multiple bit capacitor banks, N is a positive integer, and the difference between the first digital signal corresponding to the Nth bit capacitor bank and the second digital signal corresponding to the Nth bit capacitor bank is used as the digital signal difference corresponding to the Nth bit capacitor bank. The first coefficient is determined according to the effective number of bits of the second sub-ADC 430;

[0239] Step S1402: Use the quantization difference corresponding to the Nth bit capacitor bank, the reference calibration weight, and the sum of the calibration weights corresponding to the first bit capacitor bank to the (N-1)th bit capacitor bank as the calibration weight corresponding to the Nth bit capacitor bank;

[0240] Step S1403: Use the determined calibration weights corresponding to multiple bit capacitor banks as the calibration weights corresponding to the first sub-ADC 410; among them, the reference calibration weight is the calibration weight corresponding to the compensation capacitor bank.

[0241] In a specific implementation, taking the bit capacitor bank C 1 <0>For example:

[0242] <0>As can be seen from the foregoing embodiments, the second sub-ADC 430 outputs the first digital signal d corresponding to the bit capacitor group (C 1 <0>) and 2,1P <0>, and the second digital signal d corresponding to the bit capacitor group (C 1 <0>) 2,1N <0>to the digital processing unit 440;

[0243] <0>The digital processing unit 440 is based on the first coefficient 2 K <0>, and according to the first digital signal d 2,1P <0>and the second digital signal d 2,1N <0>, determines the quantization difference corresponding to the bit capacitor group (C 1 <0>) as: <0>That is:

[0244]

[0245] <0>Since in the foregoing embodiments, the digital processing unit 440 has already determined the reference calibration weight W cal,0 <0>, then the calibration weight W corresponding to the bit capacitor group (C 1 <0>) is: cal,1 <0>That is:

[0246]

[0247] <0>In a specific implementation, taking the bit capacitor group C 1 <1> as an example:

[0248] <0>As can be seen from the foregoing embodiments, the second sub-ADC 430 outputs the first digital signal d corresponding to the bit capacitor group (C 1 <1>) and 2,2P <0>, and the second digital signal d corresponding to the bit capacitor group (C 1 <1>) 2,2N <0>to the digital processing unit 440;

[0249] <0>The digital processing unit 440 is based on the first coefficient 2 K <0>, and according to the first digital signal d 2,2P <0>and the second digital signal d 2，2N <0>, determines the quantization difference corresponding to the bit capacitor group (C 1 <0>) as: <0>That is:

[0250]

[0251] <0>Since in the foregoing embodiments, the digital processing unit 440 has already determined the reference calibration weight W cal,0 , and the calibration weight W corresponding to the bit capacitance group (C 1 <0>) is cal,1 , then the calibration weight W corresponding to the bit capacitance group (C 1 <1>) is cal,2 :

[0252]

[0253] And so on, the calibration weight W corresponding to the bit capacitance group (C 1 <2>) can be determined as cal,3 :

[0254]

[0255] The bit capacitance group (C 1 <m-1>The corresponding calibration weight W cal,M is as follows:

[0256]

[0257] In the above manner, M calibration weights corresponding one-to-one to M bit capacitor groups (C 1 <0: M - 1>) can be determined: W cal,1 , W cal,2 , …, W cal,M , and the M calibration weights (W cal,1 , W cal,2 , …, W cal,M ) are used as the calibration weights corresponding to the first - stage ADC 410.

[0258] Since the first digital signal and the second digital signal contain capacitance error information corresponding to the bit capacitor groups, as well as the inter - stage gain error between the first - stage ADC 410 and the second - stage ADC 430. Therefore, the calibration weights determined above contain the inter - stage gain error information caused by the feedback capacitance and the parasitic capacitance, as well as the capacitance mismatch error information between each bit capacitor. By performing error calibration operations with these calibration weights, simultaneous correction of the inter - stage gain error and the capacitance mismatch error can be achieved through one - time calibration, reducing the complexity of calibration;

[0259] In addition, the digital processing unit 440 can be integrated inside the pipelined analog - to - digital converter chip, ensuring the feasibility of mass production of the chip.

[0260] In one or more embodiments, the digital processing unit 440 stores the determined calibration weights corresponding to the first - stage ADC 410.

[0261] In an alternative embodiment, the digital processing unit 440 specifically implements the calibration operation in the following manner:

[0262] Multiply the calibration weights corresponding to multiple bit capacitor groups by the initial digital signal output by the first - stage ADC 410 to obtain a target digital signal.

[0263] In one or more embodiments, the initial digital signal output by the first - stage ADC 410 is: d 1 <M - 1: 0>, and the calibration weight corresponding to the first - stage ADC 410 is W cal <M: 1>. Therefore, by multiplying the corresponding bits of the initial digital signal d 1 <M - 1: 0> and the calibration weight W cal <M: 1>, the target digital signal d cal1 <M - 1: 0> can be obtained.

[0264] Exemplarily, d cal1 <0> = d 1 <0> × W cal,1 ; d cal1 <1> = d 1 <1> × W cal,2 ; …; d cal1 <m-1> ＝d 1 <m-1>×W cal,M 。

[0265] Since the effective number of bits of the sub-ADC is the same as the number of bit capacitor groups in the first capacitor array, therefore, multiplying the multiple calibration weights corresponding to the multiple bit capacitor groups by the multi-bit initial digital signal output by the first sub-ADC one by one can obtain the calibrated multi-bit target digital signal, thereby realizing the calibration of the capacitor mismatch error and the inter-stage gain error in the pipelined analog-to-digital converter and improving the conversion accuracy of the pipelined analog-to-digital converter.

[0266] In an alternative embodiment, the pipelined analog-to-digital converter includes a plurality of cascaded sub-ADCs;

[0267] The first sub-ADC is any one of the sub-ADCs other than the last sub-ADC among the plurality of cascaded sub-ADCs, and the second sub-ADC is all the sub-ADCs located after the first sub-ADC among the plurality of cascaded sub-ADCs.

[0268] As Figure 15 shown, the pipelined analog-to-digital converter includes Q cascaded sub-ADCs, namely ADC<1>, …, ADC <q-2>, ADC <q-1>, ADC <q>, each adjacent pair of sub-ADCs is connected by a residue amplifier, that is, the pipelined analog-to-digital converter further includes Q-1 residue amplifiers: RA<1>, …, RA <q-2>, RA <q-1>, each sub-ADC is also electrically connected to the digital processing unit;

[0269] In one or more embodiments, during the process of error calibration of a pipelined analog-to-digital converter in Q-stage series as shown in Figure 15 :

[0270] Starting from the penultimate sub-ADC, the calibration weight corresponding to each sub-ADC is determined level by level in reverse order, and the digital signal to be processed output by the sub-ADC is calibrated according to the calibration weight corresponding to a certain sub-ADC to obtain the target digital signal corresponding to the sub-ADC.

[0271] In a specific implementation, when determining the ADC <q-1>When corresponding calibration weights are used, the ADC <q-1>As a first-level sub ADC, the ADC <q>As a second-level ADC, and by using the method provided in the foregoing embodiments, the implementation of the ADC <q-1>Determination of the corresponding calibration weights, for example, for the ADC <q-1>The corresponding calibration weight is represented as W cal,Q(Q-1) ;

[0272] The digital processing unit completes the processing of the ADC <q-1>After determining the corresponding calibration weights, start performing the operation on the ADC <q-2>The determination process of the corresponding calibration weights, in which, as Figure 15 shown, the ADC <q-2>As a first-level sub-ADC, the ADC <q-1>and ADC <q>The whole composition serves as the second sub-ADC, and by using the method provided in the foregoing embodiments, the implementation is carried out for the ADC <q-2>Determination of the corresponding calibration weights, for example, for an ADC <q-2>The corresponding calibration weight is denoted as W cal,Q(Q-2) ;

[0273] And so on, until the determination of the calibration weights corresponding to ADC<1> is completed. For example, the calibration weights corresponding to ADC<1> are denoted as W cal,Q1 .

[0274] According to the calibration weights corresponding to each sub-ADC, the digital signals to be processed output by each sub-ADC are calibrated, and then the target digital signal output by the pipelined analog-to-digital converter can be obtained.

[0275] For example, ADC <q-1>The corresponding target digital signal is: d cal,Q-1 = d Q-1 × W cal,Q(Q-1) , where d Q-1 is the ADC <q-1>Output digital signal to be processed; ADC <q-2>The corresponding target digital signal is: d cal,Q-2 = d Q-2 × W cal,Q(Q-2) , where d Q-2 is the ADC <q-2>The digital signal to be processed output; and so on.

[0276] The above pipelined analog-to-digital converter includes a plurality of cascaded sub-ADC. During the error calibration of the pipelined analog-to-digital converter, any one of the sub-ADCs except the last sub-ADC is used as the first sub-ADC, and all the sub-ADCs located after the first sub-ADC are used as the second sub-ADC to achieve the error calibration of the pipelined analog-to-digital converter and improve the performance of the pipelined analog-to-digital converter.

[0277] Figure 16 Shows a schematic diagram of a complete process for error calibration based on a pipelined analog-to-digital converter, as Figure 16 shown, including the following steps:

[0278] Step S1601, power on the pipelined analog-to-digital converter;

[0279] Step S1602, after the first sub-ADC finishes sampling, the calibration control unit changes the array connection structure of the first capacitor array so that the second sub-ADC sequentially outputs a first digital signal and a second digital signal corresponding to the compensation capacitor group;

[0280] Step S1603, the digital processing unit determines the reference calibration weight corresponding to the compensation capacitor group according to the difference between the first digital signal and the second digital signal corresponding to the compensation capacitor group;

[0281] Step S1604, after the first sub-ADC finishes sampling, the calibration control unit changes the array connection structure of the first capacitor array so that the second sub-ADC outputs a first digital signal and a second digital signal corresponding to the i-th bit capacitor group;

[0282] where i is a positive integer, and the i-th bit capacitor group belongs to the first capacitor array.

[0283] Step S1605, the digital processing unit determines the calibration weight corresponding to the i-th bit capacitor group according to the difference between the first digital signal and the second digital signal corresponding to the i-th bit capacitor group and the reference calibration weight;

[0284] Step S1606, the digital processing unit uses all the determined calibration weights corresponding to the bit capacitor groups as the calibration weights corresponding to the first sub-ADC;

[0285] where the calibration weights corresponding to the first sub-ADC are:

[0286] W cal <M:1> = W cal,M ,..., W cal,2 、W cal,1 ;

[0287] Step S1607, the digital processing unit obtains the digital signal to be processed output by the first - stage ADC, and multiplies the initial digital signal by the corresponding bit of the calibration weight to obtain the target digital signal;

[0288] Among them, the digital signal d 1 <M - 1:0> to be processed output by the first - stage ADC, multiplies the initial digital signal d 1 <M - 1:0> by the corresponding bit of the calibration weight W cal <M:1> to obtain the target digital signal d cal1 <M - 1:0>.

[0289] Based on the same concept, an embodiment of the present invention further provides an error calibration method for a pipelined analog - to - digital converter. Since this method is the method executed by the pipelined analog - to - digital converter in the embodiment of the present invention, and the principle of solving problems by this method is similar to that of the pipelined analog - to - digital converter, the implementation of this method can refer to the implementation of the pipelined analog - to - digital converter, and the repeated parts will not be described again.

[0290] As Figure 17 shown, the above - mentioned method includes the following steps:

[0291] Step S1701, under the control of the calibration control unit of the first - stage ADC, adjust the array connection structure of the first capacitor array in the first - stage ADC so that the second - stage ADC outputs a first digital signal and a second digital signal;

[0292] Among them, the first digital signal is determined according to the first residue voltage signal output by the first - stage ADC when the array connection structure of the first capacitor array is the first array connection structure, and the second digital signal is determined according to the second residue voltage signal output by the first - stage ADC when the array connection structure of the first capacitor array is the second array connection structure;

[0293] Step S1702, through the digital processing unit, based on the first digital signal and the second digital signal, determine the calibration weight corresponding to the first - stage ADC;

[0294] Step S1703, through the digital processing unit, calibrate the initial digital signal output by the first - stage ADC according to the calibration weight to obtain the target digital signal.

[0295] In an optional embodiment, the first capacitor array includes a compensation capacitor group and a plurality of bit - capacitor groups; for any one of the plurality of bit - capacitor groups:

[0296] Under the control of the calibration control unit, adjusting the array connection structure of the first capacitor array includes:

[0297] The first end of the control bit capacitor bank is electrically connected to the reference voltage terminal, the second end of the control bit capacitor bank is grounded, and

[0298] the first ends of other bit capacitor banks except the bit capacitor bank among the multiple bit capacitor banks, the second ends of other bit capacitor banks, the first end of the compensation capacitor bank, and the second end of the compensation capacitor bank are all electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a first digital signal corresponding to the bit capacitor bank.

[0299] In an alternative embodiment, for any one of the other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks:

[0300] Under the control of the calibration control unit, adjusting the array connection structure of the first capacitor array, including:

[0301] controlling the first ends from the first end of the first bit capacitor bank to the previous bit capacitor bank of the bit capacitor bank, and the first end of the compensation capacitor bank to be all electrically connected to the reference voltage terminal, controlling the second ends from the second end of the first bit capacitor bank to the previous bit capacitor bank of the bit capacitor bank, and the second end of the compensation capacitor bank to be all grounded, and

[0302] controlling the first ends from the first end of the bit capacitor bank to the last bit capacitor bank of the bit capacitor bank, and the second ends from the second end of the bit capacitor bank to the last bit capacitor bank of the bit capacitor bank to be all electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the bit capacitor bank.

[0303] In an alternative embodiment, for the first bit capacitor bank among the multiple bit capacitor banks:

[0304] Under the control of the calibration control unit, adjusting the array connection structure of the first capacitor array, including:

[0305] controlling the first end of the first bit capacitor bank to be grounded, controlling the second end of the first bit capacitor bank to be electrically connected to the reference voltage terminal, and

[0306] controlling the first end of the compensation capacitor bank, the second end of the compensation capacitor bank, the first ends of other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks, and the second ends of other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks to be all electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the first bit capacitor bank.

[0307] In an alternative embodiment, through the digital processing unit, based on the first digital signal and the second digital signal, determining the calibration weight corresponding to the first-stage ADC, including:

[0308] calculating the ratio of the digital signal difference corresponding to the Nth bit capacitor bank to the first coefficient to obtain the quantization difference corresponding to the Nth bit capacitor bank;

[0309] Among them, the Nth bit capacitor group belongs to multiple bit capacitor groups, N is a positive integer, and the difference between the first digital signal corresponding to the Nth bit capacitor group and the second digital signal corresponding to the Nth bit capacitor group is used as the digital signal difference corresponding to the Nth bit capacitor group. The first coefficient is determined according to the effective number of bits of the second sub-ADC;

[0310] The quantization difference corresponding to the Nth bit capacitor group, the reference calibration weight, and the sum of the calibration weights corresponding to the first bit capacitor group to the calibration weights corresponding to the N-1th bit capacitor group are used as the calibration weight corresponding to the Nth bit capacitor group;

[0311] The determined calibration weights corresponding to multiple bit capacitor groups are used as the calibration weights corresponding to the first sub-ADC;

[0312] Among them, the reference calibration weight is the calibration weight corresponding to the compensation capacitor group.

[0313] In an alternative embodiment, during the process of determining the reference calibration weight:

[0314] Through the calibration control unit, control the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal, control the second end of the compensation capacitor group to be grounded, and

[0315] Control the first ends and the second ends of multiple bit capacitor groups to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs the first digital signal corresponding to the compensation capacitor group;

[0316] Through the calibration control unit, control the first end of the compensation capacitor group to be grounded, control the second end of the compensation capacitor group to be electrically connected to the reference voltage terminal, and

[0317] Control the first ends and the second ends of multiple bit capacitor groups to be electrically connected to the common-mode voltage terminal, so that the second sub-ADC outputs the second digital signal corresponding to the compensation capacitor group.

[0318] In an alternative embodiment, the reference calibration weight is determined by the following method:

[0319] Through the digital processing unit, the difference between the first digital signal corresponding to the compensation capacitor group and the second digital signal corresponding to the compensation capacitor group is used as the initial signal difference;

[0320] Through the digital processing unit, the ratio of the initial signal difference to the first coefficient is used as the reference calibration weight.

[0321] In an alternative embodiment, through the digital processing unit, the initial digital signal output by the first sub-ADC is calibrated according to the calibration weight to obtain the target digital signal, including:

[0322] Multiply the calibration weights corresponding to multiple bit capacitance groups by the initial digital signal output by the first-stage ADC to obtain a target digital signal.

[0323] In an alternative embodiment, the pipelined analog-to-digital converter includes multiple cascaded stage ADCs;

[0324] The first-stage ADC is any one of the stage ADCs other than the last stage ADC among the multiple cascaded stage ADCs, and the second-stage ADC is all the stage ADCs located after the first-stage ADC among the multiple cascaded stage ADCs.

[0325] Those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations. < / q> < / q> < / q> < / m-1>

Claims

1. A pipelined analog-to-digital converter, characterized in that, it includes a first-stage analog-to-digital converter ADC, a second-stage ADC and a digital processing unit which are electrically connected in sequence. The first-stage ADC includes a first capacitor array and a calibration control unit, where: The first capacitor array adjusts its own array connection structure under the control of the calibration control unit, so that the second-stage ADC outputs a first digital signal and a second digital signal; Wherein, the first digital signal is determined according to the first residual voltage signal output by the first-stage ADC when the array connection structure of the first capacitor array is the first array connection structure, and the second digital signal is determined according to the second residual voltage signal output by the first-stage ADC when the array connection structure of the first capacitor array is the second array connection structure; The digital processing unit determines a calibration weight corresponding to the first-stage ADC based on the first digital signal and the second digital signal; The digital processing unit calibrates the initial digital signal output by the first-stage ADC according to the calibration weight to obtain a target digital signal.

2. The analog-to-digital converter according to claim 1, characterized in that, The first capacitor array includes a compensation capacitor group and a plurality of bit capacitor groups; For any one of the plurality of bit capacitor groups, the calibration control unit is specifically used to perform the following operations: Control the first end of the bit capacitor group to be electrically connected to the reference voltage terminal, control the second end of the bit capacitor group to be grounded, and Control the first ends of the other bit capacitor groups except the bit capacitor group among the plurality of bit capacitor groups, the second ends of the other bit capacitor groups, the first end of the compensation capacitor group, and the second end of the compensation capacitor group to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a first digital signal corresponding to the bit capacitor group.

3. The analog-to-digital converter according to claim 2, characterized in that, For any one of the other bit capacitor groups except the first bit capacitor group among the plurality of bit capacitor groups, the calibration control unit is specifically used to perform the following operations: Control the first ends of the first bit capacitor group to the previous bit capacitor group of the bit capacitor group, and the first end of the compensation capacitor group to be electrically connected to the reference voltage terminal, control the second ends of the first bit capacitor group to the previous bit capacitor group of the bit capacitor group, and the second end of the compensation capacitor group to be grounded, and Control the first ends of the bit capacitor group to the last bit capacitor group, and the second ends of the bit capacitor group to the last bit capacitor group to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the bit capacitor group.

4. The analog-to-digital converter according to claim 2, characterized in that, For the first bit capacitor group among the plurality of bit capacitor groups, the calibration control unit is specifically used to perform the following operations: Control the first end of the first bit capacitor group to be grounded, control the second end of the first bit capacitor group to be electrically connected to the reference voltage terminal, and The first end of the compensation capacitor bank, the second end of the compensation capacitor bank, the first ends of the other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks, and the second ends of the other bit capacitor banks except the first bit capacitor bank among the multiple bit capacitor banks are all electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the first bit capacitor bank.

5. The analog-to-digital converter according to claim 2, wherein, the digital processing unit is specifically configured to perform the following operations: calculate the ratio of the digital signal difference corresponding to the Nth bit capacitor bank to the first coefficient to obtain a quantization difference corresponding to the Nth bit capacitor bank; wherein, the Nth bit capacitor bank belongs to the multiple bit capacitor banks, N is a positive integer, the difference between the first digital signal corresponding to the Nth bit capacitor bank and the second digital signal corresponding to the Nth bit capacitor bank is used as the digital signal difference corresponding to the Nth bit capacitor bank, and the first coefficient is determined according to the effective number of bits of the second-stage ADC; use the quantization difference corresponding to the Nth bit capacitor bank, the reference calibration weight, and the sum of the calibration weights corresponding to the first bit capacitor bank to the calibration weights corresponding to the N-1th bit capacitor bank as the calibration weight corresponding to the Nth bit capacitor bank; use the determined calibration weights corresponding to the multiple bit capacitor banks as the calibration weights corresponding to the first-stage ADC; wherein, the reference calibration weight is the calibration weight corresponding to the compensation capacitor bank.

6. The analog-to-digital converter according to claim 5, wherein, in the process of determining the reference calibration weight: the calibration control unit is specifically configured to perform the following operations: control the first end of the compensation capacitor bank to be electrically connected to the reference voltage terminal, control the second end of the compensation capacitor bank to be grounded, and control the first ends and the second ends of the multiple bit capacitor banks to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a first digital signal corresponding to the compensation capacitor bank; control the first end of the compensation capacitor bank to be grounded, control the second end of the compensation capacitor bank to be electrically connected to the reference voltage terminal, and control the first ends and the second ends of the multiple bit capacitor banks to be electrically connected to the common-mode voltage terminal, so that the second-stage ADC outputs a second digital signal corresponding to the compensation capacitor bank.

7. The analog-to-digital converter according to claim 6, wherein, the digital processing unit is specifically configured to perform the following operations: use the difference between the first digital signal corresponding to the compensation capacitor bank and the second digital signal corresponding to the compensation capacitor bank as the initial signal difference; use the ratio of the initial signal difference to the first coefficient as the reference calibration weight.

8. The analog-to-digital converter according to claim 5, wherein, the digital processing unit is specifically configured to perform the following operations: Multiply the calibration weights corresponding to the multiple bit capacitance groups by the initial digital signal output by the first - stage ADC to obtain the target digital signal.

9. The analog - to - digital converter according to any one of claims 1 to 8, characterized in that it includes a plurality of cascaded stage - level ADCs; The first - stage ADC is any one of the stage - level ADCs other than the last stage - level ADC among the plurality of cascaded stage - level ADCs, and the second - stage ADC is all the stage - level ADCs after the first - stage ADC among the plurality of cascaded stage - level ADCs.

10. An error calibration method for a pipelined analog - to - digital converter, characterized in that it is applied to the pipelined analog - to - digital converter according to any one of claims 1 to 9, and the method includes: Under the control of the calibration control unit of the first - stage ADC, adjust the array connection structure of the first capacitance array in the first - stage ADC so that the second - stage ADC outputs a first digital signal and a second digital signal; Wherein, the first digital signal is determined according to the first residue voltage signal output by the first - stage ADC when the array connection structure of the first capacitance array is the first array connection structure, and the second digital signal is determined according to the second residue voltage signal output by the first - stage ADC when the array connection structure of the first capacitance array is the second array connection structure; Based on the first digital signal and the second digital signal, determine the calibration weight corresponding to the first - stage ADC through a digital processing unit; Calibrate the initial digital signal output by the first - stage ADC according to the calibration weight through the digital processing unit to obtain the target digital signal.

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